Re: tlbi va, vaa vs. val, vaal

On Fri, Feb 27, 2015 at 01:15:57PM -0800, Mario Smarduch wrote: On 02/27/2015 02:24 AM, Will Deacon wrote: On Fri, Feb 27, 2015 at 12:12:32AM +, Mario Smarduch wrote: I noticed kernel tlbflush.h use tlbi va*, vaa* variants instead of val, vaal ones. Reading the manual D.5.7.2 it appears

Re: [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings

On Thu, Feb 19, 2015 at 10:54:43AM +, Ard Biesheuvel wrote: This is a 0th order approximation of how we could potentially force the guest to avoid uncached mappings, at least from the moment the MMU is on. (Before that, all of memory is implicitly classified as Device-nGnRnE) That's just

Re: [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings

On Wed, Mar 04, 2015 at 06:03:11PM +0100, Paolo Bonzini wrote: On 04/03/2015 15:29, Catalin Marinas wrote: I disagree it is 100% a host-side issue. It is a host-side issue _if_ the host tells the guest that the (virtual) device is non-coherent (or, more precisely, it does not explicitly

Re: [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings

On Thu, Mar 05, 2015 at 11:12:22AM +0100, Paolo Bonzini wrote: On 04/03/2015 18:28, Catalin Marinas wrote: Can you add that property to the device tree for PCI devices too? Yes but not with mainline yet: http://thread.gmane.org/gmane.linux.kernel.iommu/8935 We can add

Re: [RFC/RFT PATCH v2 1/3] arm/arm64: pageattr: add set_memory_nc

On Thu, May 14, 2015 at 02:46:44PM +0100, Andrew Jones wrote: On Thu, May 14, 2015 at 01:05:09PM +0200, Christoffer Dall wrote: On Wed, May 13, 2015 at 01:31:52PM +0200, Andrew Jones wrote: Provide a method to change normal, cacheable memory to non-cacheable. KVM will make use of this to

Re: [RFC/RFT PATCH v2 1/3] arm/arm64: pageattr: add set_memory_nc

On Tue, May 19, 2015 at 11:03:22AM +0100, Andrew Jones wrote: On Mon, May 18, 2015 at 04:53:03PM +0100, Catalin Marinas wrote: Another way would be to split the vma containing the non-cacheable memory so that you get a single vma with the vm_page_prot as Non-cacheable. This sounds

Re: [RFC/RFT PATCH v2 1/3] arm/arm64: pageattr: add set_memory_nc

On Wed, May 20, 2015 at 11:01:27AM +0100, Christoffer Dall wrote: On Tue, May 19, 2015 at 12:18:54PM +0100, Catalin Marinas wrote: On Tue, May 19, 2015 at 11:03:22AM +0100, Andrew Jones wrote: On Mon, May 18, 2015 at 04:53:03PM +0100, Catalin Marinas wrote: I didn't have time to follow

Re: [PATCH 0/2] arm64: KVM: Use instruction patching for GIC world switch

On Fri, Jun 12, 2015 at 12:06:35PM +0100, Marc Zyngier wrote: The current way we deal with the GIC world switch on arm64 is a bit convoluted. As we have two possible backends, we rely on a couple of indirections set at boot time. These indirection never change, so it would make more sense to

Re: [PATCH] arm64: Don't report clear pmds and puds as huge

On Wed, Jul 01, 2015 at 02:08:31PM +0200, Christoffer Dall wrote: The current pmd_huge() and pud_huge() functions simply check if the table bit is not set and reports the entries as huge in that case. This is counter-intuitive as a clear pmd/pud cannot also be a huge pmd/pud, and it is

Re: [PATCH 2/2] arm/arm64: KVM: fix two build failured under STRICT_MM_TYPECHECKS

@lists.cs.columbia.edu Signed-off-by: Ard Biesheuvel ard.biesheu...@linaro.org Acked-by: Catalin Marinas catalin.mari...@arm.com (I guess it will go via the kvm tree) ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman

Re: [PATCH 07/13] arm64: KVM: VHE: Patch out use of HVC

On Wed, Jul 08, 2015 at 05:19:10PM +0100, Marc Zyngier wrote: --- /dev/null +++ b/arch/arm64/kvm/vhe-macros.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2015 - ARM Ltd + * Author: Marc Zyngier marc.zyng...@arm.com + * + * This program is free software; you can redistribute it and/or modify +

Re: [PATCH 00/13] arm64: Virtualization Host Extension support

On Wed, Jul 08, 2015 at 05:19:03PM +0100, Marc Zyngier wrote: Marc Zyngier (13): arm/arm64: Add new is_kernel_in_hyp_mode predicate arm64: Allow the arch timer to use the HYP timer arm64: Add ARM64_HAS_VIRT_HOST_EXTN feature arm64: KVM: skip HYP setup when already running in HYP

Re: [PATCH 12/14] arm64: Check for selected granule support

On Thu, Aug 13, 2015 at 03:45:07PM +0100, Suzuki K. Poulose wrote: On 13/08/15 13:28, Steve Capper wrote: On 13 August 2015 at 12:34, Suzuki K. Poulose suzuki.poul...@arm.com wrote: __enable_mmu: + mrs x1, ID_AA64MMFR0_EL1 + ubfxx2, x1, #ID_AA64MMFR0_TGran_SHIFT, 4 +

Re: [PATCH 2/6] irqchip: GIC: Convert to EOImode == 1

On Wed, Aug 12, 2015 at 02:31:47PM +0100, Marc Zyngier wrote: On 11/08/15 10:15, Eric Auger wrote: On 07/09/2015 03:19 PM, Marc Zyngier wrote: static int gic_irq_set_irqchip_state(struct irq_data *d, @@ -272,11 +278,15 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs

Re: [PATCH 11/13] arm64: Panic when VHE and non VHE CPUs coexist

On Wed, Jul 08, 2015 at 05:19:14PM +0100, Marc Zyngier wrote: Having both VHE and non-VHE capable CPUs in the same system is likely to be a recipe for disaster. If the boot CPU has VHE, but a secondary is not, we won't be able to downgrade and run the kernel at EL1. Add CPU hotplug to the

Re: [PATCHv4 18/24] arm64/kvm: Make use of the system wide safe values

On Mon, Oct 19, 2015 at 03:39:36PM +0200, Christoffer Dall wrote: > On Mon, Oct 19, 2015 at 02:24:55PM +0100, Suzuki K. Poulose wrote: > > Use the system wide safe value from the new API for safer > > decisions > > > > Cc: Marc Zyngier > > Cc: Christoffer Dall

Re: [PATCH 0/3] arm64: Kill ESR_LNX_EXEC

On Tue, May 31, 2016 at 12:33:00PM +0100, Mark Rutland wrote: > Mark Rutland (3): > arm64: add macro to extract ESR_ELx.EC > arm64/kvm: use ESR_ELx_EC to extract EC > arm64: kill ESR_LNX_EXEC For the series: Reviewed-by: Catalin Marinas <catalin.

Re: [PATCH 0/3] arm64: Kill ESR_LNX_EXEC

On Tue, May 31, 2016 at 12:33:00PM +0100, Mark Rutland wrote: > Currently we (ab)use a reserved bit in ESR_ELx for our own purposes as > ESR_LNX_EXEC, which isn't ideal, especially as we're inconsistent with our > mnemonic usage. This series removes ESR_LNX_EXEC entirely, avoiding (ab)use of >

Re: [PATCH v3 22/23] arm64: VHE: Add support for running Linux in EL2 mode

dropping from EL2 to EL1, and setting up the HYP configuration. > > Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Acked-by: Catalin Marinas <catalin.mari...@arm.com> ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH v3 05/23] arm64: Add ARM64_HAS_VIRT_HOST_EXTN feature

@linaro.org> > Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Acked-by: Catalin Marinas <catalin.mari...@arm.com> ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH v3 03/23] arm/arm64: Add new is_kernel_in_hyp_mode predicate

c Zyngier <marc.zyng...@arm.com> Acked-by: Catalin Marinas <catalin.mari...@arm.com> ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH v3 20/23] arm64: perf: Count EL2 events if the kernel is running in HYP

On Wed, Feb 03, 2016 at 06:00:13PM +, Marc Zyngier wrote: > When the kernel is running in HYP (with VHE), it is necessary to > include EL2 events if the user requests counting kernel or > hypervisor events. > > Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Acke

Re: [PATCH v4 21/23] arm64: hw_breakpoint: Allow EL2 breakpoints if running in HYP

y simple. > > Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> To the best of my knowledge, this patch is fine ;) Reviewed-by: Catalin Marinas <catalin.mari...@arm.com> ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH v4 00/23] arm64: Virtualization Host Extension support

On Thu, Feb 11, 2016 at 07:10:50PM +, Marc Zyngier wrote: > On 11/02/16 19:07, Christoffer Dall wrote: > > On Thu, Feb 11, 2016 at 06:39:41PM +, Marc Zyngier wrote: > >> ARMv8.1 comes with the "Virtualization Host Extension" (VHE for > >> short), which enables simpler support of Type-2

Re: [PATCH] arm64: KVM: Turn kvm_ksym_ref into a NOP on VHE

On Sun, Mar 20, 2016 at 10:07:04PM +0100, Christoffer Dall wrote: > On Fri, Mar 18, 2016 at 06:07:09PM +0000, Catalin Marinas wrote: > > On Fri, Mar 18, 2016 at 05:25:59PM +, Marc Zyngier wrote: > > > When running with VHE, there is no need to translate kernel pointers >

Re: [PATCH] arm64: KVM: Move kvm_call_hyp back to its original localtion

On Tue, Mar 01, 2016 at 01:12:44PM +, Marc Zyngier wrote: > In order to reduce the risk of a bad merge, let's move the new > kvm_call_hyp back to its original location in the file. This has > zero impact from a code point of view. > > Signed-off-by: Marc Zyngier > --- >

[PATCH] kvm: arm64: Enable hardware updates of the Access Flag for Stage 2 page tables

re updates of the dirty status are not supported by KVM, so there is no possibility of losing such information. Signed-off-by: Catalin Marinas <catalin.mari...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Paolo

Re: [RFC PATCH] arm64: Fix EL1/EL2 early init inconsistencies with VHE

On Mon, Apr 18, 2016 at 06:57:26PM +0100, Dave P Martin wrote: > When using the Virtualisation Host Extensions, EL1 is not used in > the host and requires no separate configuration. > > In addition, with VHE enabled, non-hyp-specific EL2 configuration > that does not need to be done early will be

Re: [PATCH] kvm: arm64: Enable hardware updates of the Access Flag for Stage 2 page tables

On Mon, May 09, 2016 at 05:33:10PM +0200, Christoffer Dall wrote: > On Wed, Apr 13, 2016 at 05:57:37PM +0100, Catalin Marinas wrote: > > The ARMv8.1 architecture extensions introduce support for hardware > > updates of the access and dirty information in page table entries. With

Re: issues with emulated PCI MMIO backed by host memory under KVM

On Tue, Jun 28, 2016 at 03:19:14PM +0200, Ard Biesheuvel wrote: > On 28 June 2016 at 15:10, Catalin Marinas <catalin.mari...@arm.com> wrote: > > On Tue, Jun 28, 2016 at 02:20:43PM +0200, Christoffer Dall wrote: > >> On Tue, Jun 28, 2016 at 01:06:36PM +0200, Laszlo Ersek w

Re: issues with emulated PCI MMIO backed by host memory under KVM

On Tue, Jun 28, 2016 at 02:20:43PM +0200, Christoffer Dall wrote: > On Tue, Jun 28, 2016 at 01:06:36PM +0200, Laszlo Ersek wrote: > > On 06/28/16 12:04, Christoffer Dall wrote: > > > On Mon, Jun 27, 2016 at 03:57:28PM +0200, Ard Biesheuvel wrote: > > >> So if vga-pci.c is the only problematic

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote: > > On Wed, Feb 01, 2017 at 05:36:09PM +, Catalin Marinas wrote: > > > On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote: > > > &

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote: > On Wed, Feb 01, 2017 at 11:29:22AM -0500, Christopher Covington wrote: > > On 01/31/2017 12:56 PM, Marc Zyngier wrote: > > > Given that all ARMv8 CPUs can support SW_PAN, it is more likely to be > > > enabled than the ARMv8.1 PAN. I'd

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote: > On Wed, Feb 01, 2017 at 05:36:09PM +0000, Catalin Marinas wrote: > > On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote: > > > On Wed, Feb 01, 2017 at 11:29:22AM -0500, Christopher Covington wrote: > >

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Wed, Feb 01, 2017 at 06:34:01PM +, Will Deacon wrote: > On Wed, Feb 01, 2017 at 06:22:44PM +0000, Catalin Marinas wrote: > > On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote: > > > On Wed, Feb 01, 2017 at 05:49:34PM +0000, Catalin Marinas wrote: > > > &

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote: > On Wed, Feb 01, 2017 at 05:49:34PM +0000, Catalin Marinas wrote: > > On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote: > > > On Wed, Feb 01, 2017 at 05:36:09PM +0000, Catalin Marinas wrote: > > > &

Re: [PATCH v3 2/2] arm64: Support systems without FP/ASIMD

Hi Suzuki, On Tue, Nov 08, 2016 at 01:56:21PM +, Suzuki K. Poulose wrote: > diff --git a/arch/arm64/include/asm/cpucaps.h > b/arch/arm64/include/asm/cpucaps.h > index 87b4465..4174f09 100644 > --- a/arch/arm64/include/asm/cpucaps.h > +++ b/arch/arm64/include/asm/cpucaps.h > @@ -34,7 +34,8 @@

Re: [PATCH v3 0/2] arm64: Support systems without FP/ASIMD

On Tue, Nov 08, 2016 at 01:56:19PM +, Suzuki K. Poulose wrote: > This series adds supports to the kernel and KVM hyp to handle > systems without FP/ASIMD properly. At the moment the kernel > doesn't check if the FP unit is available before accessing > the registers (e.g during context switch).

Re: [PATCH v2] arm64: head.S: Fix CNTHCTL_EL2 access on VHE system

On Mon, Nov 28, 2016 at 09:13:02PM -0500, Jintack Lim wrote: > From: Jintack > > Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit. > EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is not set, but they > are 11th and 10th bits respectively when

Re: [PATCH] arm64: Work around Falkor erratum 1009

On Thu, Dec 08, 2016 at 11:45:12AM +, Mark Rutland wrote: > On Wed, Dec 07, 2016 at 03:04:31PM -0500, Christopher Covington wrote: > > + asm volatile(ALTERNATIVE( > > +"nop \n" > > +"nop \n", > > +"tlbi vmalle1is \n" > > +"dsb

Re: [PATCH 1/1] arm64: Correcting format specifier for printing 64 bit addresses

On Mon, Dec 05, 2016 at 11:24:21AM +, Will Deacon wrote: > On Mon, Dec 05, 2016 at 01:39:53PM +0530, Maninder Singh wrote: > > This patch corrects format specifier for printing 64 bit addresses. > > > > Signed-off-by: Maninder Singh > > Signed-off-by: Vaneet Narang

Re: [PATCH 1/2] ARM: hyp-stub: improve ABI

Hi Russell, Just a quick reply expressing my opinion on the ABI and KVM maintenance topics. Sorry I won't be able to follow up until the new year as I go on holiday soon. On Thu, Dec 15, 2016 at 06:57:18PM +, Russell King - ARM Linux wrote: > On Thu, Dec 15, 2016 at 03:37:15PM +, Marc

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

Some minor comments below, nothing fundamental (as long as you say the new sequence doesn't have the speculative TLB load problem I mentioned on a previous version). On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: > diff --git a/Documentation/arm64/silicon-errata.txt >

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Wed, Jan 11, 2017 at 06:37:39PM +, Mark Rutland wrote: > On Wed, Jan 11, 2017 at 12:35:55PM -0600, Timur Tabi wrote: > > On 01/11/2017 12:33 PM, Mark Rutland wrote: > > >It'll need to affect all lines since the kconfig column needs to expand > > >by at least one character to fit

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Wed, Jan 11, 2017 at 06:40:52PM +, Mark Rutland wrote: > On Wed, Jan 11, 2017 at 06:22:08PM +, Marc Zyngier wrote: > > On 11/01/17 18:06, Catalin Marinas wrote: > > > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: > > >> diff --git

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Wed, Jan 11, 2017 at 06:22:08PM +, Marc Zyngier wrote: > On 11/01/17 18:06, Catalin Marinas wrote: > > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: > >> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > >> index 32682be..9ee

Re: [PATCH 1/2] ARM: hyp-stub: improve ABI

On Mon, Jan 09, 2017 at 12:54:31PM +, Russell King - ARM Linux wrote: > So, we need KVM's stub to be (a) better documented so this stuff is > obvious, and (b) updated so that kdump stands a chance of working even > if the KVM stub is still in place at the point the host kernel panics. > >

Re: [PATCH v3 01/25] arm64: hyp-stub: Implement HVC_RESET_VECTORS stub hypercall

On Mon, Mar 06, 2017 at 02:24:34PM +, Marc Zyngier wrote: > Let's define a new stub hypercall that resets the HYP configuration > to its default: hyp-stub vectors, and MMU disabled. > > Of course, for the hyp-stub itself, this is a trivial no-op. > Hypervisors will have a bit more work to do.

Re: [PATCH v4 00/28] arm/arm64: KVM: Rework the hyp-stub API

kvm tree. For the whole series: Acked-by: Catalin Marinas <catalin.mari...@arm.com> -- Catalin ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH V13 10/10] arm/arm64: KVM: add guest SEA support

/include/asm/system_misc.h | 2 ++ > arch/arm64/mm/fault.c| 19 +++-- > drivers/acpi/apei/ghes.c | 13 ++-- > include/acpi/ghes.h | 2 +- > 8 files changed, 86 insertions(+), 16 deletions(-) For arm64: Acked-by: Catali

Re: [PATCH V13 05/10] acpi: apei: handle SEA notification type for ARMv8

> include/acpi/ghes.h | 7 + > 5 files changed, 101 insertions(+), 6 deletions(-) For the arch/arm64 part in here: Acked-by: Catalin Marinas <catalin.mari...@arm.com> ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH V13 04/10] arm64: exception: handle Synchronous External Abort

t; Reviewed-by: James Morse <james.mo...@arm.com> > --- > arch/arm64/include/asm/esr.h | 1 + > arch/arm64/mm/fault.c | 43 +++++-- Acked-by: Catalin Marinas <catalin.mari...@arm.com> _

Re: [PATCH 00/15] arm64/kvm: use common sysreg definitions

On Wed, Mar 29, 2017 at 09:41:47AM +0100, Will Deacon wrote: > On Tue, Mar 28, 2017 at 10:29:31PM +0200, Christoffer Dall wrote: > > On Tue, Mar 28, 2017 at 07:48:28PM +0100, Mark Rutland wrote: > > > On Wed, Mar 22, 2017 at 06:35:13PM +, Mark Rutland wrote: > > > > On Fri, Mar 10, 2017 at

Re: [PATCH V14 00/10] Add UEFI 2.6 and ACPI 6.1 updates for RAS on ARM64

Hi Rafael, On Tue, Mar 28, 2017 at 01:30:30PM -0600, Tyler Baicar wrote: > Tyler Baicar (9): > acpi: apei: read ack upon ghes record consumption > ras: acpi/apei: cper: generic error data entry v3 per ACPI 6.1 > efi: parse ARM processor error > arm64: exception: handle Synchronous

Re: [PATCH 01/11] arm64: docs: describe ELF hwcaps

On Wed, Jul 19, 2017 at 05:01:22PM +0100, Mark Rutland wrote: > +3. The hwcaps exposed in AT_HWCAP > +- > + > +HWCAP_FP > + > +Functionality implied by ID_AA64PFR0_EL1.FP == 0b. Aren't these too restrictive? Linux would still present HWCAP_FP even when

Re: [PATCH v2 06/16] arm64: entry.S: convert elX_sync

Hi James, On Fri, Jul 28, 2017 at 03:10:09PM +0100, James Morse wrote: > @@ -520,9 +514,16 @@ el1_preempt: > el0_sync: > kernel_entry 0 > mrs x25, esr_el1// read the syndrome register > + mrs x26, far_el1 Just checking, since we are going to access

Re: [PATCH] KVM: arm/arm64: vgic: Use READ_ONCE fo cmpxchg

d don't race > with other updates, guarantee that the cmpxchg operation compares > against the original value. > > Cc: Catalin Marinas <catalin.mari...@arm.com> > Signed-off-by: Christoffer Dall <cd...@linaro.org> FWIW: Acked-by: C

Re: [PATCH 08/31] arm64: Add a facility to turn an ESR syndrome into a sysreg encoding

kill, let's add a set of macros that convert an ESR value into > the corresponding sysreg encoding. > > We handle both AArch32 and AArch64, taking advantage of identical > encodings between system registers and CP15 accessors. > > Signed-off-by: Marc Zyngier <marc.zyng...

Re: [PATCH 25/31] arm64: Add workaround for Cavium Thunder erratum 30115

rapping in order to deal with it. > > [maz]: Adapted patch to the Group-0/1 trapping, reworked commit log > > Signed-off-by: David Daney <david.da...@cavium.com> > Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Acked-by: Catalin Marinas <catalin.mari...@arm.com&g

Re: [PATCH 24/31] arm64: Add MIDR values for Cavium cn83XX SoCs

On Wed, May 03, 2017 at 11:45:59AM +0100, Marc Zyngier wrote: > From: David Daney <david.da...@cavium.com> > > Signed-off-by: David Daney <david.da...@cavium.com> > Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Acked-by: Catalin Ma

Re: [PATCH 1/5] arm64: KVM: Do not use stack-protector to compile EL2 code

On Tue, May 02, 2017 at 02:30:37PM +0100, Marc Zyngier wrote: > We like living dangerously. Nothing explicitely forbids stack-protector > to be used in the EL2 code, while distributions routinely compile their > kernel with it. We're just lucky that no code actually triggers the > instrumentation.

Re: [PATCH v2 11/28] arm64/sve: Core task context handling

On Thu, Aug 31, 2017 at 06:00:43PM +0100, Dave P Martin wrote: > +el0_sve_acc: > + /* > + * Scalable Vector Extension access > + */ > + enable_dbg > + ct_user_exit > + mov x0, x25 > + mov x1, sp > + bl do_sve_acc > + b ret_to_user I think

Re: [PATCH v2 14/28] arm64/sve: Backend logic for setting the vector length

On Thu, Aug 31, 2017 at 06:00:46PM +0100, Dave P Martin wrote: > This patch implements the core logic for changing a task's vector > length on request from userspace. This will be used by the ptrace > and prctl frontends that are implemented in later patches. > > The SVE architecture permits,

Re: [PATCH v2 14/28] arm64/sve: Backend logic for setting the vector length

On Wed, Sep 13, 2017 at 08:06:12PM +0100, Dave P Martin wrote: > On Wed, Sep 13, 2017 at 10:29:11AM -0700, Catalin Marinas wrote: > > On Thu, Aug 31, 2017 at 06:00:46PM +0100, Dave P Martin wrote: > > > This patch implements the core logic for changing a task's vector > >

Re: [PATCH v2 11/28] arm64/sve: Core task context handling

On Wed, Sep 13, 2017 at 08:17:07PM +0100, Dave P Martin wrote: > On Wed, Sep 13, 2017 at 10:26:05AM -0700, Catalin Marinas wrote: > > On Thu, Aug 31, 2017 at 06:00:43PM +0100, Dave P Martin wrote: > > > +/* > > > + * Trapped SVE access > > > + */ > > &

Re: [PATCH v2 11/28] arm64/sve: Core task context handling

On Thu, Sep 14, 2017 at 08:40:41PM +0100, Dave P Martin wrote: > On Wed, Sep 13, 2017 at 03:21:29PM -0700, Catalin Marinas wrote: > > On Wed, Sep 13, 2017 at 08:17:07PM +0100, Dave P Martin wrote: > > > On Wed, Sep 13, 2017 at 10:26:05AM -0700, Catalin Marinas wrote: > >

Re: [PATCH v2 11/28] arm64/sve: Core task context handling

On Thu, Sep 14, 2017 at 08:55:56PM +0100, Dave P Martin wrote: > On Wed, Sep 13, 2017 at 07:33:25AM -0700, Catalin Marinas wrote: > > On Thu, Aug 31, 2017 at 06:00:43PM +0100, Dave P Martin wrote: > > > +/* > > > + * Handle SVE state across fork(): > > > + * &

Re: [PATCH v2 11/28] arm64/sve: Core task context handling

On Fri, Oct 06, 2017 at 02:10:09PM +0100, Dave P Martin wrote: > On Thu, Oct 05, 2017 at 12:28:35PM +0100, Catalin Marinas wrote: > > On Tue, Oct 03, 2017 at 12:33:03PM +0100, Dave P Martin wrote: > > > TIF_FOREIGN_FPSTATE's meaning is expanded to cover SVE, but otherwi

Re: [PATCH v2 11/28] arm64/sve: Core task context handling

On Fri, Oct 06, 2017 at 04:15:28PM +0100, Dave P Martin wrote: > On Fri, Oct 06, 2017 at 02:36:40PM +0100, Catalin Marinas wrote: > > On Fri, Oct 06, 2017 at 02:10:09PM +0100, Dave P Martin wrote: > > > On Thu, Oct 05, 2017 at 12:28:35PM +0100, Catalin Marinas wrote: > >

Re: [PATCH v2 11/28] arm64/sve: Core task context handling

On Tue, Oct 03, 2017 at 12:11:01PM +0100, Dave P Martin wrote: > On Wed, Sep 20, 2017 at 02:58:56PM +0100, Catalin Marinas wrote: > > On Thu, Sep 14, 2017 at 08:55:56PM +0100, Dave P Martin wrote: > > > On Wed, Sep 13, 2017 at 07:33:25AM -0700, Catalin Marinas wrote: > >

Re: [PATCH v3 13/28] arm64/sve: Signal handling support

On Thu, Oct 12, 2017 at 05:11:57PM +0100, Dave P Martin wrote: > On Wed, Oct 11, 2017 at 05:40:52PM +0100, Catalin Marinas wrote: > > On Tue, Oct 10, 2017 at 07:38:30PM +0100, Dave P Martin wrote: > > > diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c &

Re: [PATCH v3 04/13] arm64: alternatives: use tpidr_el2 on VHE hosts

On Fri, Oct 13, 2017 at 05:50:45PM +0100, James Morse wrote: > Hi Catalin, > > On 13/10/17 16:31, Catalin Marinas wrote: > > On Fri, Sep 22, 2017 at 07:26:05PM +0100, James Morse wrote: > >> diff --git a/arch/arm64/kernel/cpufeature.c > >> b/arch/arm64/kernel/cpu

Re: [PATCH v3 04/13] arm64: alternatives: use tpidr_el2 on VHE hosts

On Fri, Sep 22, 2017 at 07:26:05PM +0100, James Morse wrote: > diff --git a/arch/arm64/include/asm/processor.h > b/arch/arm64/include/asm/processor.h > index 29adab8138c3..8f2d0f7d193b 100644 > --- a/arch/arm64/include/asm/processor.h > +++ b/arch/arm64/include/asm/processor.h > @@ -193,5 +193,6

Re: [PATCH v2 11/28] arm64/sve: Core task context handling

On Tue, Oct 03, 2017 at 12:33:03PM +0100, Dave P Martin wrote: > On Wed, Sep 13, 2017 at 07:33:25AM -0700, Catalin Marinas wrote: > > On Thu, Aug 31, 2017 at 06:00:43PM +0100, Dave P Martin wrote: > > > +/* > > > + * Handle SVE state across fork(): > > > + * &

Re: [PATCH v2 14/28] arm64/sve: Backend logic for setting the vector length

On Thu, Oct 05, 2017 at 05:42:29PM +0100, Dave P Martin wrote: > On Wed, Sep 13, 2017 at 03:11:23PM -0700, Catalin Marinas wrote: > > On Wed, Sep 13, 2017 at 08:06:12PM +0100, Dave P Martin wrote: > > > On Wed, Sep 13, 2017 at 10:29:11AM -0700, Catalin Marinas wrote: > >

Re: [PATCH v3 11/28] arm64/sve: Core task context handling

On Thu, Oct 12, 2017 at 05:05:07PM +0100, Dave P Martin wrote: > On Wed, Oct 11, 2017 at 05:15:58PM +0100, Catalin Marinas wrote: > > On Tue, Oct 10, 2017 at 07:38:28PM +0100, Dave P Martin wrote: > > > diff --git a/arch/arm64/include/asm/processor.h > > > b/arch/ar

Re: [PATCH v3 26/28] arm64/sve: Add documentation

On Tue, Oct 10, 2017 at 07:38:43PM +0100, Dave P Martin wrote: > +4. Signal handling > +--- > + > +* A new signal frame record sve_context encodes the SVE registers on signal > + delivery. [1] > + > +* This record is supplementary to fpsimd_context. The FPSR and FPCR >

Re: [PATCH v3 04/13] arm64: alternatives: use tpidr_el2 on VHE hosts

if (cpu_have_const_cap(ARM64_HAS_VIRT_HOST_EXTN)) write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); At this point the capability bits should be set and the jump labels enabled. Otherwise: Reviewed-by: Catalin Marinas <catalin.mari...@arm.com> ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH v3 08/13] arm64: Add vmap_stack header file

On Fri, Sep 22, 2017 at 07:26:09PM +0100, James Morse wrote: > diff --git a/arch/arm64/include/asm/vmap_stack.h > b/arch/arm64/include/asm/vmap_stack.h > new file mode 100644 > index ..f41d043cac31 > --- /dev/null > +++ b/arch/arm64/include/asm/vmap_stack.h > @@ -0,0 +1,41 @@ > +/* >

Re: [PATCH v3 18/28] arm64/sve: Preserve SVE registers around EFI runtime service calls

d rather insane for EFI to change it, > and contemporary EFI implementations certainly won't. > > Signed-off-by: Dave Martin <dave.mar...@arm.com> > Reviewed-by: Alex Bennée <alex.ben...@linaro.org> > Cc: Ard Biesheuvel <ard.biesheu...@linaro.org> Reviewed-by: Catalin Mar

Re: [PATCH v3 09/13] arm64: kernel: Add arch-specific SDEI entry code and CPU masking

On Fri, Sep 22, 2017 at 07:26:10PM +0100, James Morse wrote: > diff --git a/arch/arm64/include/asm/sdei.h b/arch/arm64/include/asm/sdei.h > new file mode 100644 > index ..ed329e01a301 > --- /dev/null > +++ b/arch/arm64/include/asm/sdei.h > @@ -0,0 +1,63 @@ > +/* > + * Copyright (C)

Re: [PATCH v3 10/13] firmware: arm_sdei: Add support for CPU and system power states

On Fri, Sep 22, 2017 at 07:26:11PM +0100, James Morse wrote: > diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h > index f24bfb2b9a2d..466b949474df 100644 > --- a/include/linux/cpuhotplug.h > +++ b/include/linux/cpuhotplug.h > @@ -88,6 +88,7 @@ enum cpuhp_state { >

Re: [PATCH v2 10/28] arm64/sve: Low-level CPU setup

On Thu, Aug 31, 2017 at 06:00:42PM +0100, Dave P Martin wrote: > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > index 877d42f..dd22ef2 100644 > --- a/arch/arm64/mm/proc.S > +++ b/arch/arm64/mm/proc.S > @@ -27,6 +27,7 @@ > #include > #include > #include > +#include > > #ifdef

Re: [PATCH v2 09/28] arm64/sve: Signal frame and context structure definition

On Thu, Aug 31, 2017 at 06:00:41PM +0100, Dave P Martin wrote: > +/* > + * The SVE architecture leaves space for future expansion of the > + * vector length beyond its initial architectural limit of 2048 bits > + * (16 quadwords). > + */ > +#define SVE_VQ_BYTES 0x10/* number of bytes

Re: [PATCH v2 11/28] arm64/sve: Core task context handling

On Thu, Aug 31, 2017 at 06:00:43PM +0100, Dave P Martin wrote: > +/* > + * Handle SVE state across fork(): > + * > + * dst and src must not end up with aliases of the same sve_state. > + * Because a task cannot fork except in a syscall, we can discard SVE > + * state for dst here, so long as we

Re: [PATCH v3 08/28] arm64/sve: Kconfig update and conditional compilation support

orts_sve() just returns false for now: it will be > replaced with a non-trivial implementation in a later patch, once > SVE support is complete enough to be enabled safely. > > Signed-off-by: Dave Martin <dave.mar...@arm.com> > Reviewed-by: Alex Bennée <alex.ben...@li

Re: [PATCH v3 09/28] arm64/sve: Signal frame and context structure definition

gt; > Signed-off-by: Dave Martin <dave.mar...@arm.com> > Cc: Alex Bennée <alex.ben...@linaro.org> Reviewed-by: Catalin Marinas <catalin.mari...@arm.com> ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH v3 02/28] arm64: KVM: Hide unsupported AArch64 CPU features from guests

se could be handled in a similar way in future, as necessary. > > Signed-off-by: Dave Martin <dave.mar...@arm.com> > Cc: Marc Zyngier <marc.zyng...@arm.com> > --- > arch/arm64/include/asm/sysreg.h | 3 + > arch/arm64/kvm/hyp/switch.c | 6 + > arch/arm64/kvm/sys

Re: [PATCH v3 06/28] arm64/sve: System register and exception syndrome definitions

d-off-by: Dave Martin <dave.mar...@arm.com> > Reviewed-by: Alex Bennée <alex.ben...@linaro.org> Reviewed-by: Catalin Marinas <catalin.mari...@arm.com> ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH v3 07/28] arm64/sve: Low-level SVE architectural state manipulation functions

at generate > explicit opcodes in place of assembler mnemonics. > > Signed-off-by: Dave Martin <dave.mar...@arm.com> > Reviewed-by: Alex Bennée <alex.ben...@linaro.org> Acked-by: Catalin Marinas <catalin.mari...@arm.com> (not adding reviewed-by as I haven't check

Re: [PATCH v3 01/28] regset: Add support for dynamically sized regsets

o.org> > --- > fs/binfmt_elf.c| 6 ++--- > include/linux/regset.h | 67 > -- > 2 files changed, 63 insertions(+), 10 deletions(-) The patch looks fine to me: Reviewed-by: Catalin Marinas <catalin.mari...@arm.com> Ho

Re: [PATCH v3 04/28] arm64: Port deprecated instruction emulation to new sysctl interface

g interfaces over to register_sysctl(), though the > number of users of the new interface currently appears negligible. > --- > arch/arm64/kernel/armv8_deprecated.c | 15 +++ > 1 file changed, 3 insertions(+), 12 deletions(-) Reviewed-by: Catalin Marinas <catalin.mari.

Re: [PATCH v3 05/28] arm64: fpsimd: Simplify uses of {set, clear}_ti_thread_flag()

sheuvel <ard.biesheu...@linaro.org> Reviewed-by: Catalin Marinas <catalin.mari...@arm.com> ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH v3 10/28] arm64/sve: Low-level CPU setup

he primary and > secondary CPU initialisation code. > > Signed-off-by: Dave Martin <dave.mar...@arm.com> > Cc: Catalin Marinas <catalin.mari...@arm.com> > Cc: Alex Bennée <alex.ben...@linaro.org> Reviewed-by: Catalin Marinas <catalin.mari...@arm.com> _

Re: [PATCH v3 15/28] arm64: cpufeature: Move sys_caps_initialised declarations

t; be a more obvious place to put it. > > Signed-off-by: Dave Martin <dave.mar...@arm.com> > Reviewed-by: Alex Bennée <alex.ben...@linaro.org> > Reviewed-by: Suzuki K Poulose <suzuki.poul...@arm.com> Acked-by: Catalin Marinas <catalin.mari...@arm.com> _

Re: [PATCH v3 16/28] arm64/sve: Probe SVE capabilities and usable vector lengths

t, > so for now we just require it to be zero. > > Note that much of this code is dormant and SVE still won't be used > yet, since system_supports_sve() remains hardwired to false. > > Signed-off-by: Dave Martin <dave.mar...@arm.com> > Cc: Alex Bennée <alex.ben...@linaro

Re: [PATCH v3 12/28] arm64/sve: Support vector length resetting for new processes

ned-off-by: Dave Martin <dave.mar...@arm.com> > Reviewed-by: Alex Bennée <alex.ben...@linaro.org> Reviewed-by: Catalin Marinas <catalin.mari...@arm.com> ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH v3 14/28] arm64/sve: Backend logic for setting the vector length

can be chosen. > > Signed-off-by: Dave Martin <dave.mar...@arm.com> > Cc: Alex Bennée <alex.ben...@linaro.org> Reviewed-by: Catalin Marinas <catalin.mari...@arm.com> ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH v3 11/28] arm64/sve: Core task context handling

On Tue, Oct 10, 2017 at 07:38:28PM +0100, Dave P Martin wrote: > diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h > index 026a7c7..b1409de 100644 > --- a/arch/arm64/include/asm/fpsimd.h > +++ b/arch/arm64/include/asm/fpsimd.h > @@ -72,6 +75,20 @@ extern void

Re: [PATCH v3 13/28] arm64/sve: Signal handling support

sve_vq_from_vl(task->thread.sve_vl); > + for (i = 0; i < 32; ++i) > + memcpy(>vregs[i], ZREG(sst, vq, i), > +sizeof(fst->vregs[i])); > +} Nit: could we actually just do an assignment with some pointer casting? It looks l

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