The ISS field exposed by ESR_ELx contain two additional subfields
with FEAT_WFxT:
- RN, the register number containing the timeout
- RV, indicating if the register number is valid
Describe these two fields according to the arch spec.
No functional change.
Signed-off-by: Marc Zyngier
---
arch
Just like we have helpers for WFI and WFE, add the WFxT versions.
Note that the encoding is that reported by objdump, as no currrent
toolchain knows about these instructions yet.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/barrier.h | 4
1 file changed, 4 insertions(+)
diff
-off-by: Marc Zyngier
---
arch/arm64/include/asm/esr.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
index d52a0b269ee8..65c2201b11b2 100644
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
would be to remove the event
generation from the counters, and rely on the timeout where it
matters (spinlocks?). Feedback welcome.
Patches on top of 5.18-rc2, tested of the FVP AEM.
Marc Zyngier (10):
arm64: Expand ESR_ELx_WFx_ISS_TI to match its ARMv8.7 definition
arm64: Add RV and RN fields
Plumb in the capability, and expose WFxT to guests when available.
Signed-off-by: Marc Zyngier
---
arch/arm64/kernel/cpufeature.c | 12
arch/arm64/kvm/sys_regs.c | 2 ++
2 files changed, 14 insertions(+)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel
, but keep it around, as we are
going to make use of it soon.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/arch_timer.c | 10 ++
arch/arm64/kvm/arm.c | 5 -
include/kvm/arm_arch_timer.h | 2 --
3 files changed, 2 insertions(+), 15 deletions(-)
diff --git a/arch/arm64/kvm
On Mon, 11 Apr 2022 11:46:09 +0100,
Alexandru Elisei wrote:
>
> Hi Marc,
>
> On Fri, Apr 08, 2022 at 08:47:00AM +0100, Marc Zyngier wrote:
> > Hi Alex,
> >
> > On Thu, 07 Apr 2022 17:23:27 +0100,
> > Alexandru Elisei wrote:
> >
On Fri, 08 Apr 2022 21:03:25 +0100,
Kalesh Singh wrote:
>
> pkvm_hyp_alloc_private_va_range() can be used to reserve private VA ranges
> in the pKVM nVHE hypervisor. Allocations are aligned based on the order of
> the requested size.
>
> This will be used to implement stack guard pages for pKVM
On Fri, 08 Apr 2022 21:03:24 +0100,
Kalesh Singh wrote:
>
> hyp_alloc_private_va_range() can be used to reserve private VA ranges
> in the nVHE hypervisor. Allocations are aligned based on the order of
> the requested size.
>
> This will be used to implement stack guard pages for KVM nVHE
On Thu, 07 Apr 2022 18:24:14 +0100,
Raghavendra Rao Ananta wrote:
>
> Hi Marc,
>
> > > +#define KVM_REG_ARM_STD_BIT_TRNG_V1_0BIT(0)
> >
> > I'm really in two minds about this. Having one bit per service is easy
> > from an implementation perspective, but is also means that this
Hi Paolo,
Here's the first batches of fixes for 5.18 (most of it courtesy of
Oliver). The two important items here are a MMU rwlock fix when
splitting block mappings, and a debugfs registration issue resulting
in a potentially spectacular outcome.
Please pull,
M.
The following changes
Hi Alex,
On Thu, 07 Apr 2022 17:23:27 +0100,
Alexandru Elisei wrote:
>
> When userspace is debugging a VM, the kvm_debug_exit_arch part of the
> kvm_run struct contains arm64 specific debug information: the ESR_EL2
> value, encoded in the field "hsr", and the address of the instruction
> that
On Wed, 6 Apr 2022 23:56:12 +, Oliver Upton wrote:
> Funny enough, dirty_log_perf_test on arm64 highlights some issues around
> the use of debugfs in KVM. The test leaks a GIC FD across test
> iterations, and as such the associated VM is never destroyed.
> Nonetheless, the VM FD is reused for
On Wed, 16 Mar 2022 13:51:29 +0100, Andrew Jones wrote:
> When testing a kernel with commit a5905d6af492 ("KVM: arm64:
> Allow SMCCC_ARCH_WORKAROUND_3 to be discovered and migrated")
> get-reg-list output
>
> vregs: Number blessed registers: 234
> vregs: Number registers: 238
>
>
Hi Raghavendra,
On Thu, 07 Apr 2022 02:15:57 +0100,
Raghavendra Rao Ananta wrote:
>
> KVM regularly introduces new hypercall services to the guests without
> any consent from the userspace. This means, the guests can observe
> hypercall services in and out as they migrate across various host
>
On Fri, 01 Apr 2022 02:08:30 +0100,
Oliver Upton wrote:
>
> KVM currently does not trap ID register accesses from an AArch32 EL1.
> This is painful for a couple of reasons. Certain unimplemented features
> are visible to AArch32 EL1, as we limit PMU to version 3 and the debug
> architecture to
On Tue, 29 Mar 2022 03:20:59 -0700, Yu Zhe wrote:
> remove unnecessary casts.
Applied to fixes, thanks!
[1/1] KVM: arm64: vgic: remove unnecessary type castings
commit: c707663e81ef48d279719e97fd86acef835a2671
Cheers,
M.
--
Without deviation from the norm, progress is not
On Fri, 1 Apr 2022 19:46:52 +, Oliver Upton wrote:
> It is possible to take a stage-2 permission fault on a page larger than
> PAGE_SIZE. For example, when running a guest backed by 2M HugeTLB, KVM
> eagerly maps at the largest possible block size. When dirty logging is
> enabled on a memslot,
On Mon, 28 Mar 2022 20:19:22 -0700, Reiji Watanabe wrote:
> KVM allows userspace to configure either all EL1 32bit or 64bit vCPUs
> for a guest. At vCPU reset, vcpu_allowed_register_width() checks
> if the vcpu's register width is consistent with all other vCPUs'.
> Since the checking is done
Hi Oliver,
On Mon, 04 Apr 2022 19:21:17 +0100,
Oliver Upton wrote:
>
> Unfortunately, there is no guarantee that KVM was able to instantiate a
> debugfs directory for a particular VM. To that end, KVM shouldn't even
> attempt to create new debugfs files in this case. If the specified
> parent
-off-by: Marc Zyngier
---
arch/arm64/kvm/vgic/vgic-init.c| 7 ++-
arch/arm64/kvm/vgic/vgic-mmio-v2.c | 18 +++---
arch/arm64/kvm/vgic/vgic-mmio-v3.c | 23 +--
arch/arm64/kvm/vgic/vgic.h | 5 +
include/kvm/arm_vgic.h | 3 +++
5 files
).
Reviewed-by: Oliver Upton
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/vgic/vgic-its.c | 2 +-
arch/arm64/kvm/vgic/vgic-mmio-v3.c | 36 ++
arch/arm64/kvm/vgic/vgic.h | 1 +
include/kvm/arm_vgic.h | 4 ++--
4 files changed, 31 insertions
as a primitive to their ITS
counterpart. Note that we don't advertise them to the guest yet
(the architecture allows an implementation to do this).
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/vgic/vgic-its.c | 62 ++--
arch/arm64/kvm/vgic/vgic-mmio-v3.c | 66
bit numbers (shrug...)
- Plenty of small fixes all over the shop thanks to Oliver
- Rebased on top of 5.18-rc1
[1] https://lore.kernel.org/r/20220314164044.772709-1-...@kernel.org
Marc Zyngier (4):
irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES}
KVM: arm64: vgic-v3: Expose
As we're about to expose GICR_CTLR.{IR,CES} to guests, populate
the include file with the architectural values.
Signed-off-by: Marc Zyngier
---
include/linux/irqchip/arm-gic-v3.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/irqchip/arm-gic-v3.h
b/include/linux/irqchip
On Mon, 04 Apr 2022 18:02:02 +0100,
Jason Gunthorpe wrote:
>
> On Mon, Apr 04, 2022 at 03:47:11PM +0100, Marc Zyngier wrote:
> > > I'm guessing it will turn into a SBSA like thing where the ARM ARM is
> > > kind of vauge but a SOC has to implement No
On Mon, 04 Apr 2022 14:24:05 +0100,
Jason Gunthorpe wrote:
>
> On Fri, Apr 01, 2022 at 05:48:59PM +0100, Marc Zyngier wrote:
>
> > NAK. For a start, there is no such thing as 'write-combine' in the ARM
> > architecture, and I'm not convinced you can equate WC to Normal-NC.
Xieming,
This is the second time I fix email addresses for you. Next time, I
simply won't bother replying.
On Fri, 01 Apr 2022 10:08:28 +0100,
xieming wrote:
>
> when passthrough some pcie device, such as gpus(including
> Nvidia and AMD),kvm will report:"Unsupported FSC: EC=0x24
> xFSC=0x21
On Tue, 29 Mar 2022 07:14:16 +0100,
yuzhe wrote:
>
> >> @@ -229,7 +229,7 @@ static void print_irq_state(struct seq_file *s, struct
> >> vgic_irq *irq,
> >> static int vgic_debug_show(struct seq_file *s, void *v)
> >> {
> >> - struct kvm *kvm = (struct kvm *)s->private;
> >> + struct kvm
On Mon, 28 Mar 2022 11:38:36 +0100,
yuzhe wrote:
>
> remove unnecessary castings, from "void *" to "struct kvm *"
>
> Signed-off-by: yuzhe
> ---
> arch/arm64/kvm/vgic/vgic-debug.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git
On Fri, 25 Mar 2022 01:06:17 +,
谢明 wrote:
>
>thanks for your reply !
>you are right, 'If the device supports NORMAL_NC, this should
> be known by the host kernel and exposed to KVM'， accordding the kvm
> combining rules on arm64， stage1 is setting to NORMAL_NC， so can
> we add a
Please use my *working* email address (look in the MAINTAINERS file for
the up-to-date one).
On 2022-03-23 01:25, xieming wrote:
1) when passthrough some pcie device, such as AMD gpus,
kvm will report:"Unsupported FSC:" err.
Please detail this. What values of FSC? In what
On Tue, 22 Mar 2022 18:35:35 +, Oliver Upton wrote:
> This series addresses a couple of issues with how KVM exposes SMC64
> calls to its guest. It is currently possible for an AArch32 guest to
> discover the SMC64 SYSTEM_RESET2 function (via
> PSCI_1_0_FN_PSCI_FEATURES) and even make a call to
On Tue, 22 Mar 2022 05:49:29 +,
Oliver Upton wrote:
>
> On Mon, Mar 21, 2022 at 09:41:39PM -0700, Reiji Watanabe wrote:
> > On 3/18/22 12:38 PM, Oliver Upton wrote:
> > > The SMCCC does not allow the SMC64 calling convention to be used from
> > > AArch32. While KVM checks to see if the
Lawall (1):
KVM: arm64: fix typos in comments
Julien Grall (1):
KVM: arm64: Align the VMID allocation with the arm64 ASID
Keir Fraser (1):
KVM: arm64: pkvm: Implement CONFIG_DEBUG_LIST at EL2
Marc Zyngier (14):
Merge branch kvm-arm64/oslock into kvmarm-master/next
Merge
On Fri, 18 Mar 2022 11:37:19 +0100, Julia Lawall wrote:
> Various spelling mistakes in comments.
> Detected with the help of Coccinelle.
Applied to next, thanks!
[1/1] KVM: arm64: fix typos in comments
commit: 21ea457842759a236eefed2cfaa8cc7e5dc967a0
Cheers,
M.
--
Without
On Fri, 11 Mar 2022 17:39:46 +, Oliver Upton wrote:
> **NOTE** Patch 2 is a bugfix for commit d43583b890e7 ("KVM: arm64:
> Expose PSCI SYSTEM_RESET2 call to the guest") on kvmarm/next. Without
> this patch, it is possible for the guest to call
> PSCI_1_1_FN64_SYSTEM_RESET2 from AArch32.
>
>
Hi Jing,
On Thu, 17 Mar 2022 00:56:30 +,
Jing Zhang wrote:
>
> This tracepoint only provides a hook for poking vcpu exits information,
> not exported to tracefs.
> A timestamp is added for the last vcpu exit, which would be useful for
> analysis for vcpu exits.
The trace itself gives you a
Hi Jing,
On Thu, 17 Mar 2022 00:56:29 +,
Jing Zhang wrote:
>
> Arch specific exit reasons have been available for other architectures.
> Add arch specific exit reason support for ARM64, which would be used in
> KVM stats for monitoring VCPU status.
>
> Signed-off-by: Jing Zhang
> ---
>
gt; issue.
Yes, that's what should happen. I came up with the patch below. Please
give it a shot and let me know if that helps. If it does, I'll queue
it as a fix.
Thanks,
M.
From c23ccc9cfa603e30ac189d43af75f03b60d780bc Mon Sep 17 00:00:00 2001
From: Marc Zyngier
Date: Thu, 17 Mar
On 2022-03-17 06:44, Oliver Upton wrote:
On Wed, Mar 16, 2022 at 09:51:26PM -0700, Ricardo Koller wrote:
Add an arch_timer edge-cases selftest. For now, just add some basic
sanity checks, and some stress conditions (like waiting for the timers
while re-scheduling the vcpu). The next commit will
Hi Oliver,
On Tue, 15 Mar 2022 23:13:09 +,
Oliver Upton wrote:
>
> Hi Marc,
>
> On Mon, Mar 14, 2022 at 04:40:44PM +, Marc Zyngier wrote:
> > @@ -87,8 +91,16 @@ static int vgic_mmio_uaccess_write_v2_misc(struct
> > kvm_vcpu *vcpu,
> > * mig
),
> - KVM_REG_ARM_FW_REG(1),
> - KVM_REG_ARM_FW_REG(2),
> + KVM_REG_ARM_FW_REG(0), /* KVM_REG_ARM_PSCI_VERSION */
> + KVM_REG_ARM_FW_REG(1), /* KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1
> */
> + KVM_REG_ARM_FW_REG(2), /* KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2
> */
> + KV
On Wed, 16 Mar 2022 05:26:06 +,
Oliver Upton wrote:
>
> Hi Marc,
>
> On Mon, Mar 14, 2022 at 04:40:42PM +, Marc Zyngier wrote:
> > Since GICv4.1, it has become legal for an implementation to advertise
> > GICR_{INVLPIR,INVALLR,SYNCR} while having an
On Tue, 15 Mar 2022 23:16:05 +,
Oliver Upton wrote:
>
> Hi Marc,
>
> On Mon, Mar 14, 2022 at 04:40:41PM +, Marc Zyngier wrote:
> > As we're about to expose GICR_CTLR.{IR,CES} to guests, populate
> > the include file with the architectural values.
> >
&
On Tue, 15 Mar 2022 23:13:09 +,
Oliver Upton wrote:
>
> Hi Marc,
>
> On Mon, Mar 14, 2022 at 04:40:44PM +, Marc Zyngier wrote:
> > Since adversising GICR_CTLR.{IC,CES} is directly observable from
> > a guest, we need to make it selectable from userspace.
).
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/vgic/vgic-its.c | 2 +-
arch/arm64/kvm/vgic/vgic-mmio-v3.c | 44 --
arch/arm64/kvm/vgic/vgic.h | 1 +
include/kvm/arm_vgic.h | 4 +--
4 files changed, 34 insertions(+), 17 deletions(-)
diff --git
-off-by: Marc Zyngier
---
arch/arm64/kvm/vgic/vgic-init.c| 7 ++-
arch/arm64/kvm/vgic/vgic-mmio-v2.c | 18 +++---
arch/arm64/kvm/vgic/vgic-mmio-v3.c | 23 +--
include/kvm/arm_vgic.h | 3 +++
4 files changed, 45 insertions(+), 6 deletions(-)
diff
as a primitive to their ITS
counterpart. Note that we don't advertise them to the guest yet
(the architecture allows an implementation to do this).
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/vgic/vgic-its.c | 62 --
arch/arm64/kvm/vgic/vgic-mmio-v3.c | 62
on LPI disabling, and finally exposes these to
userspace and the guest with a new GICD_IIDR revision (and the ability
to save/restore it).
This series has been extremely useful to debug related GIC features,
and will be complemented by a few GIC patches.
Patches on top of 5.17-rc3.
M.
Marc
As we're about to expose GICR_CTLR.{IR,CES} to guests, populate
the include file with the architectural values.
Signed-off-by: Marc Zyngier
---
include/linux/irqchip/arm-gic-v3.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/irqchip/arm-gic-v3.h
b/include/linux/irqchip
On Wed, 9 Mar 2022 18:13:08 +, Will Deacon wrote:
> Commit d43583b890e7 ("KVM: arm64: Expose PSCI SYSTEM_RESET2 call to the
> guest") hooked up the SYSTEM_RESET2 PSCI call for guests but failed to
> preserve its arguments for userspace, instead overwriting them with
> zeroes via
On Tue, 8 Mar 2022 17:28:57 +, Oliver Upton wrote:
> KVM support for 32-bit ARM hosts (KVM/arm) has been removed from the
> kernel since commit 541ad0150ca4 ("arm: Remove 32bit KVM host
> support"). There still exists some remnants of the old architecture in
> the KVM documentation.
>
>
Hi Eugene,
On Tue, 08 Mar 2022 07:50:50 +,
Eugene Huang wrote:
>
> Hi Marc,
>
> Looks like to effectively troubleshoot, we need to upgrade our guest
> kernel to the latest version 5.17. I have these questions.
>
> 1. Can you please point out the kernel source that programs the arm
>
On Mon, 07 Mar 2022 16:28:44 +,
Alexandru Elisei wrote:
>
> Hi,
>
> On Mon, Mar 07, 2022 at 03:48:19PM +, Marc Zyngier wrote:
> > On 2022-03-07 14:52, Alexandru Elisei wrote:
> > > Hi,
> > >
> > > I was under the impression that KVM'
On Mon, 07 Mar 2022 16:24:58 +,
Alexandru Elisei wrote:
>
> Hi,
>
> On Mon, Mar 07, 2022 at 03:44:43PM +, Marc Zyngier wrote:
> > On 2022-03-07 15:23, Alexandru Elisei wrote:
> > > Hi,
> > >
> > > On Fri, Jan 28, 2022 at 12:18:51PM +,
On 2022-03-07 14:52, Alexandru Elisei wrote:
Hi,
I was under the impression that KVM's nested virtualization doesn't
support
AArch32 in the guest, why is the subject about hyp mode aarch32 timers?
Where did you see *ANY* mention of AArch32?
Or is that a very roundabout way to object to the
On 2022-03-07 15:23, Alexandru Elisei wrote:
Hi,
On Fri, Jan 28, 2022 at 12:18:51PM +, Marc Zyngier wrote:
From: Christoffer Dall
Emulating EL2 also means emulating the EL2 timers. To do so, we expand
our timer framework to deal with at most 4 timers. At any given time,
two timers
On Fri, 04 Mar 2022 08:00:20 +,
Reiji Watanabe wrote:
>
> > > +{
> > > + bool is32bit;
> > > + bool allowed = true;
> > > + struct kvm *kvm = vcpu->kvm;
> > > +
> > > + is32bit = vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT);
> > > +
> > > + mutex_lock(>lock);
> > > +
>
(such as a trap, for example).
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/arm.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index fefd5774ab55..f49ebdd9c990 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
On Wed, 02 Mar 2022 21:25:28 +,
Ricardo Koller wrote:
>
> Hi Oliver,
>
> On Wed, Mar 02, 2022 at 08:45:53PM +, Oliver Upton wrote:
> > Hi Ricardo,
> >
> > On Wed, Mar 02, 2022 at 09:21:43AM -0800, Ricardo Koller wrote:
> > > Add an arch_timer edge-cases selftest. For now, just add some
Hi Kalesh,
On Wed, 02 Mar 2022 17:24:53 +,
Kalesh Singh wrote:
>
> On Tue, Mar 1, 2022 at 11:46 PM Marc Zyngier wrote:
> >
> > On Fri, 25 Feb 2022 03:34:47 +,
> > Kalesh Singh wrote:
> > >
> > > pkvm_hyp_alloc_private_va_range(
Reiji,
Please add a cover letter to your patches. It actually is important to
track the changes as well as being an anchor in my email client.
On Thu, 03 Mar 2022 03:54:07 +,
Reiji Watanabe wrote:
>
> KVM allows userspace to configure either all EL1 32bit or 64bit vCPUs
> for a guest. At
On Thu, 03 Mar 2022 05:49:00 +,
Eugene Huang wrote:
>
> We have the following further 1-to-1 mappings:
> pcpu-20 - vcpu-0 is running your timer test, everything is fine
> pcpu-21 - vcpu-1 starts some other workload, and this affects the timer test
> on the other vcpu
>
> - Each vCPU thread
On Thu, 03 Mar 2022 01:01:40 +,
Oliver Upton wrote:
>
>
> I'm beginning to wonder if the VMM/KVM split implementation of
> system-scoped PSCI calls can ever be right. There exists a critical
> section in all system-wide PSCI calls that currently spans an exit to
> userspace. I cannot devise
On Wed, 02 Mar 2022 19:42:21 +,
Oliver Upton wrote:
>
> ARM64 is the only supported ARM archiecture for KVM now. Move all the
> documentation into a new directory, arm64, making the file structure
> consistent with this change.
>
> While we're at it, rename hyp-abi.rst to el2-abi.rst for
)
TBH, I'd drop the Fixes. Otherwise, it is going to be dragged into
-stable versions, and generate a number of pointless conflicts.
> Suggested-by: Marc Zyngier
> Signed-off-by: Oliver Upton
> ---
> Documentation/virt/kvm/api.rst | 83 -
> Documentation
On Fri, 25 Feb 2022 18:46:58 +, Mark Brown wrote:
> The recently added configuration option for Cortex A510 erratum 2077057 does
> not have a "default y" unlike other errata fixes. This appears to simply be
> an oversight since the help text suggests enabling the option if unsure and
> there's
On Wed, 02 Mar 2022 14:09:06 +,
Catalin Marinas wrote:
>
> On Fri, Feb 25, 2022 at 06:46:58PM +, Mark Brown wrote:
> > The recently added configuration option for Cortex A510 erratum 2077057 does
> > not have a "default y" unlike other errata fixes. This appears to simply be
> > an
Hi Sebastian,
On Wed, 02 Mar 2022 14:07:35 +,
Sebastian Ene wrote:
>
> This patch adds support for stolen time by sharing a memory region
> with the guest which will be used by the hypervisor to store the stolen
> time information. Reserve a 64kb MMIO memory region after the RTC peripheral
the vCPU is beeing initialised.
>
> Signed-off-by: Sebastian Ene
Reviewed-by: Marc Zyngier
M.
--
Without deviation from the norm, progress is not possible.
___
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kvmarm@lists.cs.columbia.edu
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On Tue, 01 Mar 2022 22:56:41 +,
Qian Cai wrote:
>
> On Mon, Feb 07, 2022 at 03:20:32PM +, Mark Brown wrote:
> > Since all the fields in the main ID registers are 4 bits wide we have up
> > until now not bothered specifying the width in the code. Since we now
> > wish to use this
On Sat, 26 Feb 2022 18:28:21 +,
Oliver Upton wrote:
>
> On Sat, Feb 26, 2022 at 3:29 AM Marc Zyngier wrote:
> >
> > On Thu, 24 Feb 2022 20:05:59 +,
> > Oliver Upton wrote:
> > >
> > > On Thu, Feb 24, 2022 at 03:40:15PM +, Marc Zyngier wr
On Fri, 25 Feb 2022 03:34:49 +,
Kalesh Singh wrote:
>
> Maps the stack pages in the flexible private VA range and allocates
> guard pages below the stack as unbacked VA space. The stack is aligned
> to twice its size to aid overflow detection (implemented in a subsequent
> patch in the
On Fri, 25 Feb 2022 03:34:48 +,
Kalesh Singh wrote:
>
> Maps the stack pages in the flexible private VA range and allocates
> guard pages below the stack as unbacked VA space. The stack is aligned
> to twice its size to aid overflow detection (implemented in a subsequent
> patch in the
On Fri, 25 Feb 2022 03:34:47 +,
Kalesh Singh wrote:
>
> pkvm_hyp_alloc_private_va_range() can be used to reserve private VA ranges
> in the pKVM nVHE hypervisor (). Also update __pkvm_create_private_mapping()
> to allow specifying an alignment for the private VA mapping.
>
> These will be
On Tue, 01 Mar 2022 19:03:33 +,
Eugene Huang wrote:
>
> > > * Does this timer rely on kvm timer irq injection?
> >
> > Yes. A timer interrupt is always injected in SW. But the timer interrupt can
> > either come from the HW timer itself (the VM was running while the timer
> >
[Please don't send HTML email and stick to plain text]
On 2022-02-28 18:02, Eugene Huang wrote:
Hi,
I am running qemu on an arm64 CentOS host. Inside a ubuntu VM, a
I assume that by this you mean QEMU as the VMM for a KVM guest, right?
process runs a timer created using timer_t:
On Thu, 24 Feb 2022 20:05:59 +,
Oliver Upton wrote:
>
> On Thu, Feb 24, 2022 at 03:40:15PM +, Marc Zyngier wrote:
> > > diff --git a/arch/arm64/kvm/psci.c b/arch/arm64/kvm/psci.c
> > > index 2bb8d047cde4..a7de84cec2e4 100644
> > > --- a/arch/arm64/kvm/
On Thu, 24 Feb 2022 19:35:33 +,
Oliver Upton wrote:
>
> Hi Marc,
>
> Thanks for reviewing the series. ACK to the nits and smaller comments
> you've made, I'll incorporate that feedback in the next series.
>
> On Thu, Feb 24, 2022 at 02:02:34PM +, Marc Zyngier wrot
On Thu, 24 Feb 2022 22:08:15 +,
Oliver Upton wrote:
>
> Hi Marc,
>
> On Thu, Feb 24, 2022 at 01:25:04PM +, Marc Zyngier wrote:
>
> [...]
>
> > > @@ -190,7 +190,7 @@ static void kvm_prepare_system_event(struct kvm_vcpu
> > > *vc
On Thu, 24 Feb 2022 19:21:50 +,
Oliver Upton wrote:
>
> Hi Marc,
>
> On Thu, Feb 24, 2022 at 12:30:49PM +, Marc Zyngier wrote:
> > On Wed, 23 Feb 2022 04:18:28 +,
> > Oliver Upton wrote:
> > >
> > > DEN0022D.b 5.6.2 "Caller responsibi
On Fri, 25 Feb 2022 02:12:32 +,
"Chen, Rong A" wrote:
>
> Hi Marc, Ard,
>
> We have ignored the warning related to asmlinkage according to the
> below advice:
>
> https://lore.kernel.org/lkml/CAMj1kXHrRYagSVniSetHdG15rkQS+fm4zVOtN=zda3w0qae...@mail.gmail.com/
Ah, I didn't realise it had
On 2022-02-23 09:27, cgel@gmail.com wrote:
From: Changcheng Deng
Fix the following coccicheck review:
./arch/arm64/kvm/psci.c: 379: 3-4: Unneeded semicolon
Reported-by: Zeal Robot
Signed-off-by: Changcheng Deng
---
arch/arm64/kvm/psci.c | 2 +-
1 file changed, 1 insertion(+), 1
On 2022-02-25 12:29, Will Deacon wrote:
On Fri, Feb 25, 2022 at 04:07:24AM +0800, kernel test robot wrote:
From: kernel test robot
arch/arm64/kvm/psci.c:372:3-4: Unneeded semicolon
Remove unneeded semicolon.
Generated by: scripts/coccinelle/misc/semicolon.cocci
Fixes: d43583b890e7 ("KVM:
Hi Paolo,
Only a couple of fixes this time around: one for the long standing
PSCI CPU_SUSPEND issue, and a selftest fix for systems that don't have
a GICv3.
Please pull,
M.
The following changes since commit 5bfa685e62e9ba93c303a9a8db646c7228b9b570:
KVM: arm64: vgic: Read HW
On Wed, 23 Feb 2022 04:18:38 +,
Oliver Upton wrote:
>
> Add a new system event type, KVM_SYSTEM_EVENT_SUSPEND, which indicates
> to userspace that the guest has requested the VM be suspended. Userspace
> can decide whether or not it wants to honor the guest's request by
> changing the MP
On Wed, 23 Feb 2022 04:18:37 +,
Oliver Upton wrote:
>
> Introduce a new MP state, KVM_MP_STATE_SUSPENDED, which indicates a vCPU
> is in a suspended state. In the suspended state the vCPU will block
> until a wakeup event (pending interrupt) is recognized.
>
> Add a new system event type,
On Wed, 23 Feb 2022 04:18:35 +,
Oliver Upton wrote:
> diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
> index f11039944c08..9085a1b1569a 100644
> --- a/include/linux/kvm_host.h
> +++ b/include/linux/kvm_host.h
> @@ -2202,6 +2202,13 @@ static inline void
On Wed, 23 Feb 2022 04:18:34 +,
Oliver Upton wrote:
>
> ARM DEN0022D.b 5.19 "SYSTEM_SUSPEND" describes a PSCI call that allows
> software to request that a system be placed in the deepest possible
> low-power state. Effectively, software can use this to suspend itself to
> RAM. Note that the
On Wed, 23 Feb 2022 04:18:31 +,
Oliver Upton wrote:
>
> A subsequent change to KVM will add support for additional power states.
> Store the MP state by value rather than keeping track of it as a
> boolean.
>
> No functional change intended.
>
> Signed-off-by: Oliver Upton
> ---
>
On Wed, 23 Feb 2022 04:18:28 +,
Oliver Upton wrote:
>
> DEN0022D.b 5.6.2 "Caller responsibilities" states that a PSCI
> implementation may return INVALID_ADDRESS for the CPU_ON call if the
> provided entry address is known to be invalid. There is an additional
> caveat to this rule. Prior to
On Wed, 23 Feb 2022 04:18:27 +,
Oliver Upton wrote:
>
> Create a helper that tests if a given IPA fits within the guest's
> address space.
>
> Signed-off-by: Oliver Upton
> ---
> arch/arm64/include/asm/kvm_mmu.h | 9 +
> arch/arm64/kvm/vgic/vgic-kvm-device.c | 2 +-
> 2 files
On 2022-02-23 12:56, Ard Biesheuvel wrote:
On Wed, 23 Feb 2022 at 13:54, Marc Zyngier wrote:
On 2022-02-23 12:34, Philip Li wrote:
> On Wed, Feb 23, 2022 at 09:16:59AM +0000, Marc Zyngier wrote:
>> On Wed, 23 Feb 2022 09:05:18 +,
>> kernel test robot wrote:
>
On 2022-02-23 12:34, Philip Li wrote:
On Wed, Feb 23, 2022 at 09:16:59AM +, Marc Zyngier wrote:
On Wed, 23 Feb 2022 09:05:18 +,
kernel test robot wrote:
>
> Hi Kalesh,
>
> Thank you for the patch! Perhaps something to improve:
>
> [auto
On Wed, 23 Feb 2022 09:05:18 +,
kernel test robot wrote:
>
> Hi Kalesh,
>
> Thank you for the patch! Perhaps something to improve:
>
> [auto build test WARNING on cfb92440ee71adcc2105b0890bb01ac3cddb8507]
>
> url:
>
On 2022-02-22 14:28, Alexandru Elisei wrote:
Hi,
On Tue, Feb 22, 2022 at 02:18:40PM +, Marc Zyngier wrote:
On 2022-02-22 13:58, Alexandru Elisei wrote:
> Hi,
>
> On Tue, Feb 22, 2022 at 10:08:30AM +, Sebastian Ene wrote:
> > This patch adds support for stolen time by s
On 2022-02-22 13:58, Alexandru Elisei wrote:
Hi,
On Tue, Feb 22, 2022 at 10:08:30AM +, Sebastian Ene wrote:
This patch adds support for stolen time by sharing a memory region
with the guest which will be used by the hypervisor to store the
stolen
time information. The exact format of the
On Mon, 21 Feb 2022 15:35:21 +, Will Deacon wrote:
> Here's version two of the patches I posted at the end of last week:
>
> https://lore.kernel.org/r/20220217184001.11753-1-w...@kernel.org
>
> The only change is to the comments and ABI documentation, so that we
> refer to the PSCI spec
Hi Reiji,
On 2022-02-19 04:50, Reiji Watanabe wrote:
Hi Marc,
On Thu, Feb 17, 2022 at 1:12 AM Marc Zyngier wrote:
On Thu, 17 Feb 2022 04:52:10 +,
Oliver Upton wrote:
> Would it make sense to test some opt-in capabilities that expose
> additional registers (PMU, SVE, etc.)?
I
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