Re: [PATCH v4 03/12] KVM: arm64: guest debug, define API headers

On Fri, May 15, 2015 at 03:27:06PM +0100, Alex Bennée wrote: This commit defines the API headers for guest debugging. There are two architecture specific debug structures: - kvm_guest_debug_arch, allows us to pass in HW debug registers - kvm_debug_exit_arch, signals exception and

Re: Advice on HYP interface for AsyncPF

On Thu, Apr 09, 2015 at 01:06:47PM +0100, Andrew Jones wrote: On Thu, Apr 09, 2015 at 08:57:23AM +0100, Marc Zyngier wrote: On Thu, 9 Apr 2015 02:46:54 +0100 Mario Smarduch m.smard...@samsung.com wrote: Hi Mario, I'm working with AsyncPF, and currently using hyp call to

Re: Advice on HYP interface for AsyncPF

For example, if Windows guests were taught to look for a particular ACPI table to learn about their HyperV features, then KVM could fake that table and also emulate the hypercalls. This requires KVM to provide those services and for the information to be in the appropriate

Re: [PATCH] KVM: arm64: add gic-400 compatible

Hi, On Thu, Apr 02, 2015 at 08:47:21AM +0100, AKASHI Takahiro wrote: Ping. This patch was acked but has never been merged? There's a more complete patch in the kvmarm tree, queued for 4.1 [1]. It adds both arm,gic-400 and arm,cortex-a7-gic. Mark. [1]

[PATCH] arm64/kvm: set {v,}TCR_EL2 RES1 bits

Currently we don't set the RES1 bits of TCR_EL2 and VTCR_EL2 when configuring them, which could lead to unexpected behaviour when an architectural meaning is defined for those bits. Set the RES1 bits to avoid issues. Signed-off-by: Mark Rutland mark.rutl...@arm.com Cc: Catalin Marinas

[PATCH] arm64: kvm: avoid %p in __kvm_hyp_panic

Currently __kvm_hyp_panic uses %p for values which are not pointers, such as the ESR value. This can confusingly lead to "(null)" being printed for the value. Use %x instead, and only use %p for host pointers. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Acked-by: Marc Zy

Re: [PATCH 15/21] arm64: KVM: Add panic handling

> diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c > index 06d3e20..cdc2a96 100644 > --- a/arch/arm64/kvm/hyp/switch.c > +++ b/arch/arm64/kvm/hyp/switch.c > @@ -140,3 +140,38 @@ int __hyp_text __guest_run(struct kvm_vcpu *vcpu) > > return exit_code; > } > + > +static

[PATCH] arm64: kvm: report original PAR_EL1 upon panic

to restoring host register values, enabling us to report the original values at the point of the panic. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm64/kvm/hyp.S | 6 +-

[PATCH] arm64: kvm: restore EL1N SP for panic

s in order to panic successfully. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Acked-by: Marc Zyngier <marc.zyng...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: <kvmarm@lists.cs.columbia.edu> --- arch/arm64/kvm/hyp.S | 8 1 file changed,

Re: [PATCH 01/13] arm/arm64: Add new is_kernel_in_hyp_mode predicate

Hi, +static inline bool is_kernel_in_hyp_mode(void) +{ + u64 el; + + asm(mrs %0, CurrentEL : =r (el)); + return el == CurrentEL_EL2; +} If you can include cputype.h, I think this can be: static inline bool is_kernel_in_hyp_mode(void) { return read_cpuid(CurrentEL) ==

Re: [PATCH 03/13] arm64: Add ARM64_HAS_VIRT_HOST_EXTN feature

On Wed, Jul 08, 2015 at 05:19:06PM +0100, Marc Zyngier wrote: Add a new ARM64_HAS_VIRT_HOST_EXTN features to indicate that the CPU has the ARMv8,1 VHE capability. Nit: s/,/./ It's probably worth mentioning somewhere that we have to check CurrentEL rather than a feature register in case some

Re: [PATCH 01/13] arm/arm64: Add new is_kernel_in_hyp_mode predicate

On Thu, Jul 09, 2015 at 11:05:34AM +0100, Marc Zyngier wrote: On 09/07/15 10:42, Mark Rutland wrote: Hi, +static inline bool is_kernel_in_hyp_mode(void) +{ + u64 el; + + asm(mrs %0, CurrentEL : =r (el)); + return el == CurrentEL_EL2; +} If you can include cputype.h, I

Re: [PATCH] KVM: arm/arm64: Fix PSCI affinity info return value for non valid cores

opensystems.com> > Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> This looks correct to me per the PSCI 0.2 spec: Acked-by: Mark Rutland <mark.rutl...@arm.com> Was this spotted by inspection, or do you have some client for which this is important? Thanks, Mark.

Re: [RFC PATCH v5 0/3] vfio: platform: return device properties for a platform device

On Mon, Oct 05, 2015 at 12:32:00PM +0200, Christoffer Dall wrote: > [cc'ing Mark R. and Shannon for their input on FDT and ACPI]. > > On Mon, Oct 05, 2015 at 11:07:35AM +0100, Peter Maydell wrote: > > On 5 October 2015 at 10:37, Christoffer Dall > > wrote: > > > On

Re: [PATCH v7 07/19] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

On Tue, Dec 15, 2015 at 04:49:27PM +0800, Shannon Zhao wrote: > From: Shannon Zhao > > When we use tools like perf on host, perf passes the event type and the > id of this event type category to kernel, then kernel will map them to > hardware event number and write this

Re: [PATCH 0/3] arm64: Kill ESR_LNX_EXEC

On Thu, Jun 02, 2016 at 07:21:47PM +0100, Will Deacon wrote: > On Tue, May 31, 2016 at 05:53:11PM +0100, Catalin Marinas wrote: > > On Tue, May 31, 2016 at 12:33:00PM +0100, Mark Rutland wrote: > > > Mark Rutland (3): > > > arm64: add macro to extract ESR_ELx.EC > &

Re: [kvm-unit-tests PATCH v2 03/10] arm/arm64: smp: support more than 8 cpus

On Mon, Jun 06, 2016 at 05:22:49PM +0100, Alex Bennée wrote: > Andrew Jones writes: > > +#define MPIDR_LEVEL_SHIFT(level) \ > > + (((1 << level) >> 1) << 3) > > +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ > > + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & 0xff) > > Doesn't

Re: [PATCH 4/5] arm/arm64: KVM: Map the HYP text as read-only

On Mon, Jun 13, 2016 at 03:00:48PM +0100, Marc Zyngier wrote: > There should be no reason for mapping the HYP text read/write. > > As such, let's have a new set of flags (PAGE_HYP_EXEC) that allows > execution, but makes the page as read-only, and update the two call > sites that deal with

Re: [PATCH 5/5] arm/arm64: KVM: Make default HYP mappings non-excutable

Hi, Nit: typo in subject "excutable" is missing an 'e'. Mark. On Mon, Jun 13, 2016 at 03:00:49PM +0100, Marc Zyngier wrote: > Structures that can be generally written to don't have any requirement > to be executable (quite the opposite). This includes the kvm and vcpu > structures, as well as

[PATCH 1/3] arm64: add macro to extract ESR_ELx.EC

value in a consistent fashion. Existing open-coded extractions in core arm64 code are moved over to the new helper. KVM code is left as-is for the moment. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Tested-by: Huang Shijie <shijie.hu...@arm.com> Cc: Catalin Marinas <catalin.

[PATCH 3/3] arm64: kill ESR_LNX_EXEC

, and the result is only used in another boolean expression. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Dave P Martin <dave.mar...@arm.com> Cc: Huang Shijie <shijie.hu...@arm.com> Cc: James Morse <james.mo...@arm.com&g

[PATCH 0/3] arm64: Kill ESR_LNX_EXEC

://git.kernel.org/cgit/linux/kernel/git/mark/linux.git/log/?h=arm64/entry-deasm Mark Rutland (3): arm64: add macro to extract ESR_ELx.EC arm64/kvm: use ESR_ELx_EC to extract EC arm64: kill ESR_LNX_EXEC arch/arm64/include/asm/esr.h | 1 + arch/arm64/include/asm/kvm_emulate.h | 2 +- arch

Re: [PATCH V12 3/7] dma: add Qualcomm Technologies HIDMA management driver

Hi, [adding KVM people, given this is meant for virtualization] On Mon, Jan 11, 2016 at 09:45:43AM -0500, Sinan Kaya wrote: > The Qualcomm Technologies HIDMA device has been designed to support > virtualization technology. The driver has been divided into two to follow > the hardware design. >

Re: [PATCH V12 3/7] dma: add Qualcomm Technologies HIDMA management driver

On Fri, Jan 15, 2016 at 10:12:00AM -0500, Sinan Kaya wrote: > Hi Mark, > > On 1/15/2016 9:56 AM, Mark Rutland wrote: > > Hi, > > > > [adding KVM people, given this is meant for virtualization] > > > > On Mon, Jan 11, 2016 at 09:45:43AM -0500, Sinan Kay

Re: [PATCH V12 3/7] dma: add Qualcomm Technologies HIDMA management driver

On Fri, Jan 15, 2016 at 03:14:28PM +, Marc Zyngier wrote: > On 15/01/16 14:56, Mark Rutland wrote: > > Hi, > > > > [adding KVM people, given this is meant for virtualization] > > > > On Mon, Jan 11, 2016 at 09:45:43AM -0500, Sinan Kaya wrote: > >>

Re: MPIDR Aff0 question

On Fri, Feb 05, 2016 at 10:23:53AM +0100, Andrew Jones wrote: > On Thu, Feb 04, 2016 at 06:51:06PM +, Marc Zyngier wrote: > What would the benefit of defining a "socket"? > > That's a good lead in for my next question. While I don't believe > there needs to be any relationship between socket

[PATCH] KVM: arm/arm64: vgic: ensure bitmaps are long enough

ing a multiple of sizeof(unsigned long), as we do elsewhere in the vgic code. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> --- virt/kvm/arm/vgic.c | 4 ++-- 1 file changed, 2 insertions(+),

Re: [PATCH v2 0/8] arm64: Support for systems without AArch32 state

On Wed, Mar 02, 2016 at 06:07:21PM +0300, Yury Norov wrote: > ubuntu@arm64:~$ uname -a > Linux arm64 4.5.0-rc5-00019-g3e330b9 #76 SMP PREEMPT Wed Mar 2 17:46:57 MSK > 2016 aarch64 aarch64 aarch64 GNU/Linux > > ubuntu@arm64:~$ cat /proc/cpuinfo > processor : 0-47 > BogoMIPS: 200.00

Re: [PATCH] arm/arm64: KVM: Enforce Break-Before-Make on Stage-2 page tables

he current code doesn't respect this, directly writing the new > entry and only then invalidating TLBs. Let's fix it up. > > Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> FWIW, this looks correct to me. Acked-by: Mark Rutland <mark.rutl...@arm.com> Mar

Re: issues with emulated PCI MMIO backed by host memory under KVM

On Mon, Jun 27, 2016 at 02:15:29PM +0100, Peter Maydell wrote: > On 27 June 2016 at 10:47, Ard Biesheuvel wrote: > > As for the USB case, I can't really figure out what is going on here, > > but I am fairly certain it is a different issue. If this is related to > > DMA,

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: > The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries > using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum > is triggered, page table entries using the new translation table base >

[RFC PATCH 00/13] arm64/kvm: use common sysreg definitions

lpers for sys_reg id") for the definition of SYS_DESC(). Thanks, Mark. Mark Rutland (13): arm64: sysreg: sort by encoding arm64: sysreg: add debug system registers arm64: sysreg: add performance monitor registers arm64: sysreg: subsume GICv3 sysreg definitions arm64: sysreg: ad

[RFC PATCH 05/13] arm64: sysreg: add register encodings used by KVM

are only made for regsiteres used today by KVM. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Suzuki K Poulose <suzuki.poul...@arm.com> Cc: Will Deacon <will.dea...@arm.com&g

[RFC PATCH 04/13] arm64: sysreg: subsume GICv3 sysreg definitions

moves the definitions to , adding a SYS_ prefix, and sorting the registers per their encoding. Existing users of the definitions are fixed up so that this change is not problematic. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc:

[RFC PATCH 13/13] arm64: kvm: Use common Set/Way sys definitions

Now that we have common definitions for the encoding of Set/Way cache maintenance operations, make the KVM code use these, simplifying the sys_reg_descs table. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Marc Zyngie

[RFC PATCH 09/13] arm64: kvm: Use common performance monitor sysreg definitions

is applied to bring these into line with the usual comment style. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: kvmarm@lists.cs.columbia.edu --- arch/arm64/k

[RFC PATCH 10/13] arm64: kvm: Use common GICv3 sysreg definitions

Now that we have common definitions for the GICv3 register encodings, make the KVM code use these, simplifying the sys_reg_descs table. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Marc Zyngier <marc.zyng...@arm.

[RFC PATCH 08/13] arm64: kvm: Use common debug sysreg definitions

-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: kvmarm@lists.cs.columbia.edu --- arch/arm64/kvm/sys_regs.c | 73 ++- 1 file changed, 21 insertion

[RFC PATCH 03/13] arm64: sysreg: add performance monitor registers

document. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Suzuki K Poulose <suzuki.poul...@arm.com> Cc: Will Deacon <will.dea...@arm.com> --- arch/arm64/include/asm/sysreg.h | 2

[RFC PATCH 02/13] arm64: sysreg: add debug system registers

This patch adds sysreg definitions for system registers in the debug and trace system register encoding space. Subsequent patches will make use of these definitions. The encodings were taken from ARM DDI 0487A.k_iss10775, Table C5-5. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: C

[RFC PATCH 11/13] arm64: kvm: use common invariant sysreg definitions

Now that we have common definitions for the register encodings used by KVM, make the KVM code uses thse for invariant sysreg definitions. This makes said definitions a reasonable amount shorter, especially as many comments are rendered redundant and can be removed. Signed-off-by: Mark Rutland

[RFC PATCH 12/13] arm64: kvm: Use common sysreg definitions

Now that we have common definitions for the remaining register encodings required by KVM, make the KVM code use these, simplifying the sys_reg_descs table and the genericv8_sys_regs table. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Christoffer Dall <christoffer.d...@linar

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: > The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries > using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum > is triggered, page table entries using the new translation table base >

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Fri, Jan 27, 2017 at 02:38:49PM +, Mark Rutland wrote: > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose > the con

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

Hi, On Fri, Jan 27, 2017 at 04:52:23PM -0500, Christopher Covington wrote: > On 01/27/2017 09:38 AM, Mark Rutland wrote: > > On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: > >> Replacing the above sequence with the one below will ensure that n

[PATCH 0/2] arm{,64}/kvm: survive unknown traps from guests

fallout to the guest, rather than allowing guests to potentially bring down the host. These patches try to make arm/arm64 KVM robust in these cases. Thanks, Mark. Mark Rutland (2): arm/kvm: survive unknown traps from guests arm64/kvm: survive unknown traps from guests arch/arm/include/asm

[PATCH 2/2] arm64/kvm: survive unknown traps from guests

userspace. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Dave Martin <dave.mar...@arm.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/kvm/handle_exit

Re: [PATCH 2/2] arm64/kvm: survive unknown traps from guests

On Mon, Feb 20, 2017 at 01:48:32PM +, Suzuki K Poulose wrote: > On 20/02/17 12:30, Mark Rutland wrote: > >The patch makes KVM handle any unknown EC by injecting an UNDEFINED > >exception into the guest, with a corresponding (ratelimited) warning in > >the host dmesg. W

Re: A question about TTBRs

On Fri, Feb 24, 2017 at 11:22:40AM +0100, Christoffer Dall wrote: > On Fri, Feb 24, 2017 at 09:55:09AM +, Raz wrote: > > Hello > > I am reading the arm8a book. According to the documentation the output > > address of each level 3 entry in TTBRx_EL1points to an address in the > > physical

Re: [RFC PATCH 00/13] arm64/kvm: use common sysreg definitions

On Fri, Feb 24, 2017 at 11:16:50AM +0100, Christoffer Dall wrote: > Hi Mark, > > On Tue, Jan 31, 2017 at 06:05:38PM +0000, Mark Rutland wrote: > > Whenever we add new functionality involving new system registers, we need to > > add sys_reg() definitions so that we can

Re: [PATCH v2 5/5] arm64: mmu: apply strict permissions to .init.text and .init.data

On Sat, Feb 11, 2017 at 08:23:06PM +, Ard Biesheuvel wrote: > To avoid having mappings that are writable and executable at the same > time, split the init region into a .init.text region that is mapped > read-only, and a .init.data region that is mapped non-executable. > > This is possible

Re: [PATCH v2 2/5] arm64: mmu: move TLB maintenance from callers to create_mapping_late()

ate*_mapping_late. Given the only users of this are changing permissions, perhaps we should rename this to change_mapping_prot(), or something like that? Otherwise, this looks fine to me, and boots fine. Either way: Reviewed-by: Mark Rutland <mark.rutl...@arm.com> Tested-by: Mark Rutland <mark

Re: [PATCH v2 4/5] arm64: mmu: map .text as read-only from the outset

On Sat, Feb 11, 2017 at 08:23:05PM +, Ard Biesheuvel wrote: > Now that alternatives patching code no longer relies on the primary > mapping of .text being writable, we can remove the code that removes > the writable permissions post-init time, and map it read-only from > the outset. > >

Re: [PATCH v2 3/5] arm64: alternatives: apply boot time fixups via the linear mapping

near alias of .text with RW- permissions > initially, and remove the write permissions as soon as alternative > patching has completed. > > Reviewed-by: Laura Abbott <labb...@redhat.com> > Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org> Reviewed-by: Mark

Re: [PATCH v2 4/5] arm64: mmu: map .text as read-only from the outset

On Tue, Feb 14, 2017 at 05:49:19PM +, Ard Biesheuvel wrote: > > > On 14 Feb 2017, at 17:40, Mark Rutland <mark.rutl...@arm.com> wrote: > > > >> On Tue, Feb 14, 2017 at 04:15:11PM +, Ard Biesheuvel wrote: > >> Having trivial 'off' switches for secu

Re: [PATCH v3 6/9] kvm: arm/arm64: Add host pmu to support VM introspection

On Wed, Jan 18, 2017 at 11:21:21AM +, Marc Zyngier wrote: > On 10/01/17 11:38, Punit Agrawal wrote: > > +#define VM_MASKGENMASK_ULL(31, 0) > > +#define EVENT_MASK GENMASK_ULL(32, 39) > > +#define EVENT_SHIFT(32) > > + > > +#define to_pid(cfg)((cfg) & VM_MASK) > > +#define

Re: [PATCH v3 6/9] kvm: arm/arm64: Add host pmu to support VM introspection

On Wed, Jan 18, 2017 at 02:51:31PM +, Punit Agrawal wrote: > I should've clarified in my reply that I wasn't looking to support the > third instance from Mark's examples above - "monitor all vCPUs on a > pCPU". I think it'll be quite expensive to figure out which threads from > a given pool

Re: [PATCH v3 6/9] kvm: arm/arm64: Add host pmu to support VM introspection

On Wed, Jan 18, 2017 at 04:17:18PM +, Punit Agrawal wrote: > Mark Rutland <mark.rutl...@arm.com> writes: > > > On Wed, Jan 18, 2017 at 02:51:31PM +, Punit Agrawal wrote: > >> I should've clarified in my reply that I wasn't looking to support the > >>

[PATCH 1/3] arm64: alternative: add auto-nop infrastructure

adds a new alternative_if, and updates alternative_else and alternative_endif to work with either alternative_if or alternative_endif. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com&g

[PATCH 3/3] arm64/kvm: use alternative auto-nop

NOPs executed. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: kvmarm@lists.cs.columbia.edu --- arch/arm64/include/asm/kvm_mmu.h | 10 +++--- arch/arm64/kvm/hyp.S |

Re: [PATCH 3/3] arm64/kvm: use alternative auto-nop

On Thu, Sep 08, 2016 at 01:16:48PM +0200, Christoffer Dall wrote: > On Wed, Sep 07, 2016 at 11:07:10AM +0100, Mark Rutland wrote: > > Make use of the new alternative_if and alternative_else_nop_endif and > > get rid of our homebew NOP sleds, making the code simpler to read. >

[PATCH 0/2] arm{,64}/kvm: excise redundant cache maintenance

a suitably configured ARMv7 board, I have not been able to test the patches myself, and any testing would be appreciated. Thanks, Mark. [1] https://groups.google.com/d/msg/jailhouse-dev/c9Ier7mUNoI/JWUJGyxfAQAJ [2] https://groups.google.com/d/msg/jailhouse-dev/c9Ier7mUNoI/qagpektgAQAJ Mark Rutland

[PATCH 2/2] arm64/kvm: remove unused stub functions

Now that 32-bit KVM no longer performs cache maintenance for page table updates, we no longer need empty stubs for arm64. Remove them. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Marc Zyngier <marc.zyng...@arm.

[PATCH 1/2] arm/kvm: excise redundant cache maintenance

t) that was otherwise implicit in the maintenance is folded into kvm_set_pmd() and kvm_set_pte(). Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: kvmarm@lists.cs.colum

Re: [PATCH 0/2] arm{,64}/kvm: excise redundant cache maintenance

On Tue, Aug 30, 2016 at 05:05:54PM +0100, Mark Rutland wrote: > As noted in a jailhouse thread a short while ago [1,2], the presence of the > virtualization extensions implies that page table walks are coherent, and do > not require that updates are cleaned to the PoU. > > These

Re: [PATCH 1/3] arm64: alternative: add auto-nop infrastructure

On Tue, Sep 13, 2016 at 09:36:14AM +0100, Ard Biesheuvel wrote: > On 7 September 2016 at 11:07, Mark Rutland <mark.rutl...@arm.com> wrote: > > In some cases, one side of an alternative sequence is simply a number of > > NOPs used to balance the other side. Keeping t

Re: [PATCH] arm64: KVM: Take S1 walks into account when determining S2 write faults

[Adding Julien, who seemed to be missing from the real Cc list] Mark. On Thu, Sep 29, 2016 at 12:37:01PM +0100, Will Deacon wrote: > The WnR bit in the HSR/ESR_EL2 indicates whether a data abort was > generated by a read or a write instruction. For stage 2 data aborts > generated by a stage 1

Re: [PATCH 1/2] arm64: perf: Move ARMv8 PMU perf event definitions to asm/perf_event.h

On Thu, Nov 10, 2016 at 09:12:35AM -0600, Wei Huang wrote: > On 11/10/2016 03:10 AM, Marc Zyngier wrote: > > On 09/11/16 19:57, Wei Huang wrote: > >> diff --git a/arch/arm64/include/asm/perf_event.h > >> b/arch/arm64/include/asm/perf_event.h > >> +/* > >> + * ARMv8 PMUv3 Performance Events

Re: [PATCH] arm/arm64: KVM: Perform local TLB invalidation when multiplexing vcpus on a single CPU

me. FWIW, with or without the other comments considered: Reviewed-by: Mark Rutland <mark.rutl...@arm.com> > --- > arch/arm/include/asm/kvm_host.h | 5 + > arch/arm/include/asm/kvm_hyp.h| 1 + > arch/arm/kvm/arm.c| 35 ++- &g

Re: [kvm-unit-tests PATCH] arm/arm64: introduce is_aarch32

On Thu, Nov 17, 2016 at 05:45:41PM +0100, Andrew Jones wrote: > Hi Mark, > > On Wed, Nov 16, 2016 at 05:45:44PM +0000, Mark Rutland wrote: > > So I don't think we should try to distinguish ARMv8-A AArch32 from > > ARMv7-A. We should test individual features, or if that's no

Re: [PATCH V3 02/10] ras: acpi/apei: cper: generic error data entry v3 per ACPI 6.1

On Fri, Oct 14, 2016 at 05:28:58PM +0100, Suzuki K Poulose wrote: > On 13/10/16 20:37, Baicar, Tyler wrote: > >On 10/13/2016 2:50 AM, Suzuki K Poulose wrote: > >>Is it always the same endianness as that of the CPU ? > > > >It is a fair assumption that the firmware populating this record will >

Re: [PATCH] arm64: Work around Falkor erratum 1009

On Wed, Dec 07, 2016 at 03:04:31PM -0500, Christopher Covington wrote: > From: Shanker Donthineni > > During a TLB invalidate sequence targeting the inner shareable > domain, Falkor may prematurely complete the DSB before all loads > and stores using the old translation

Re: [PATCH 1/2] ARM: hyp-stub: improve ABI

l King <rmk+ker...@armlinux.org.uk> This looks good to me, though I'd suggest s/ABI/calling convention/, as this isn't strictly speaking an ABI. So FWIW: Acked-by: Mark Rutland <mark.rutl...@arm.com> Thanks, Mark. > --- > arch/arm/kernel/hyp-stub.S | 27 ++-

Re: [PATCH] ARM: soft-reboot into same mode that we entered the kernel

Hi, On Fri, Dec 09, 2016 at 07:49:37PM +, Russell King wrote: > When we soft-reboot (eg, kexec) from one kernel into the next, we need > to ensure that we enter the new kernel in the same processor mode as > when we were entered, so that (eg) the new kernel can install its own > hypervisor -

Re: [PATCH] ARM: soft-reboot into same mode that we entered the kernel

On Tue, Dec 13, 2016 at 11:11:15AM +, Russell King - ARM Linux wrote: > On Tue, Dec 13, 2016 at 10:54:11AM +0000, Mark Rutland wrote: > > On Fri, Dec 09, 2016 at 07:49:37PM +, Russell King wrote: > > > ENTRY(__hyp_set_vectors) > > > + tst r0, #31 > &g

Re: [PATCH 2/3] KVM: arm64: Access CNTHCTL_EL2 bit fields correctly on VHE systems

Hi, On Fri, Jan 13, 2017 at 01:30:29PM +, Marc Zyngier wrote: > [+ Suzuki, who wrote the whole cpus_have_const_cap thing] > > On 13/01/17 12:36, Christoffer Dall wrote: > > On Fri, Jan 13, 2017 at 11:31:32AM +, Marc Zyngier wrote: > >> +static inline bool has_vhe(void) > >> +{ > >> +

Re: [PATCH 2/3] KVM: arm64: Access CNTHCTL_EL2 bit fields correctly on VHE systems

On Fri, Jan 13, 2017 at 01:36:12PM +0100, Christoffer Dall wrote: > On Fri, Jan 13, 2017 at 11:31:32AM +, Marc Zyngier wrote: > Further, are we guaranteed that the static branch gets compiled into > something that doesn't actually look at cpu_hwcap_keys, which is not > mapped in hyp mode?

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Wed, Jan 11, 2017 at 12:35:55PM -0600, Timur Tabi wrote: > On 01/11/2017 12:33 PM, Mark Rutland wrote: > >It'll need to affect all lines since the kconfig column needs to expand > >by at least one character to fit QCOM_FALKOR_ERRATUM_1003. > > Or we can make the mac

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Wed, Jan 11, 2017 at 06:22:08PM +, Marc Zyngier wrote: > On 11/01/17 18:06, Catalin Marinas wrote: > > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: > >> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > >> index 32682be..9ee46df 100644 > >> ---

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Wed, Jan 11, 2017 at 12:40:42PM -0600, Timur Tabi wrote: > On 01/11/2017 12:37 PM, Mark Rutland wrote: > >The name, as it is, is perfectly descriptive. > > > >Let's not sacrifice legibility over a non-issue. > > I don't want to kick a dead hors

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Thu, Jan 12, 2017 at 03:45:48PM +, Catalin Marinas wrote: > On Wed, Jan 11, 2017 at 06:40:52PM +0000, Mark Rutland wrote: > > Likewise, I beleive we may need to modify cpu_set_reserved_ttbr0(). > > This may be fine if my assumptions about this erra

Re: [PATCH 2/3] KVM: arm64: Access CNTHCTL_EL2 bit fields correctly on VHE systems

On Fri, Jan 13, 2017 at 02:42:04PM +, Mark Rutland wrote: > On Fri, Jan 13, 2017 at 01:30:29PM +, Marc Zyngier wrote: > > On 13/01/17 12:36, Christoffer Dall wrote: > > > Further, are we guaranteed that the static branch gets compiled into > > > something

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

Hi, On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote: > +config QCOM_FALKOR_E1003_RESERVED_ASID > + int > + default 1 > + depends on QCOM_FALKOR_ERRATUM_1003 > + I don't think this needs to be configurable, so let's drop this into a header, e.g. drop: #define

Re: [PATCH v2 4/5] arm64: Use __tlbi_dsb() macros in KVM code

On Fri, Jan 06, 2017 at 10:51:53AM -0500, Christopher Covington wrote: > On 01/03/2017 10:57 AM, Mark Rutland wrote: > > On Thu, Dec 29, 2016 at 05:43:34PM -0500, Christopher Covington wrote: > >> Refactor the KVM code to use the newly introduced __tlbi_dsb macros, which > &g

KVM/ARM: sleeping function called from invalid context

Hi, I'm seeing the splat below when running KVM on an arm64 host with CONFIG_DEBUG_ATOMIC_SLEEP and CONFIG_LOCKDEP enabled. I saw this on v4.11-rc1, and I can reproduce the problem on the current kvmarm master branch (563e2f5daa66fbc1). I've hacked noinlines into arch/arm/kvm/mmu.c in an

Re: KVM/ARM: sleeping function called from invalid context

On Thu, Mar 30, 2017 at 03:31:12PM +0100, Mark Rutland wrote: > Hi, > > I'm seeing the splat below when running KVM on an arm64 host with > CONFIG_DEBUG_ATOMIC_SLEEP and CONFIG_LOCKDEP enabled. > > I saw this on v4.11-rc1, and I can reproduce the problem on the current >

Re: [PATCH 00/15] arm64/kvm: use common sysreg definitions

Hi, On Fri, Mar 10, 2017 at 06:35:55PM +, Will Deacon wrote: > On Fri, Mar 10, 2017 at 08:17:22AM +, Marc Zyngier wrote: > > The next question is how do we merge this. Obviously, we can't split it > > between trees, and this is very likely to clash with anything that we > > will merge on

Re: [PATCH 00/15] arm64/kvm: use common sysreg definitions

On Wed, Mar 29, 2017 at 09:41:47AM +0100, Will Deacon wrote: > On Tue, Mar 28, 2017 at 10:29:31PM +0200, Christoffer Dall wrote: > > On Tue, Mar 28, 2017 at 07:48:28PM +0100, Mark Rutland wrote: > > > On Wed, Mar 22, 2017 at 06:35:13PM +, Mark Rutland wrote: > > >

Re: [PATCH 00/15] arm64/kvm: use common sysreg definitions

On Wed, Mar 22, 2017 at 06:35:13PM +, Mark Rutland wrote: > On Fri, Mar 10, 2017 at 06:35:55PM +, Will Deacon wrote: > > On Fri, Mar 10, 2017 at 08:17:22AM +, Marc Zyngier wrote: > > > > The next question is how do we merge this. Obviously, we can't split i

Re: [PATCH V8 1/3] irq: Add flags to request_percpu_irq function

Hi Daniel, On Thu, Mar 23, 2017 at 06:42:01PM +0100, Daniel Lezcano wrote: > In the next changes, we track the interrupts but we discard the timers as > that does not make sense. The next interrupt on a timer is predictable. Sorry, but I could not parse this. [...] > diff --git

Re: [PATCH RFC 6/7] ARM64: KVM: Support heterogeneous system

On Wed, Mar 15, 2017 at 03:06:33PM +0100, Andrew Jones wrote: > On Wed, Mar 15, 2017 at 02:36:45PM +0100, Christoffer Dall wrote: > > > If QEMU wants to know > > > whether or not the host it's running on is heterogeneous, then > > > it can just query sysfs, rather than ask KVM. > > > > > > > Can

Re: [PATCH v3] kvm: arm/arm64: Fix locking for kvm_free_stage2_pgd

.kernel.org # v3.10+ > Cc: Paolo Bonzini <pbon...@redhat.com> > Cc: Marc Zyngier <marc.zyng...@arm.com> > Cc: Christoffer Dall <christoffer.d...@linaro.org> > Cc: Mark Rutland <mark.rutl...@arm.com> > Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.c

[RFC 4/9] arm64/cpufeature: detect pointer authentication

So that we can dynamically handle the presence of pointer authentication functionality, wire up probing code in cpufeature.c. Currently, this only detects the presence of an architected algorithm. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@ar

[RFC 5/9] arm64: Don't trap host pointer auth use to EL2

HCR_EL2 itself. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: kvmarm@lists.cs.columbia.e

[RFC 1/9] asm-generic: mm_hooks: allow hooks to be overridden individually

, allow each hook to be overridden indiviually, by placing each under an #ifndef block. As architectures providing their own hooks can't include this file today, this shouldn't adversely affect any existing hooks. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Arnd Bergmann <a...@arnd

[RFC 0/9] ARMv8.3 pointer authentication userspace support

/linux/kernel/git/mark/boot-wrapper-aarch64.git pointer-auth Mark Rutland (9): asm-generic: mm_hooks: allow hooks to be overridden individually arm64: add pointer authentication register bits arm64/cpufeature: add ARMv8.3 id_aa64isar1 bits arm64/cpufeature: detect pointer authentication arm64

[RFC 2/9] arm64: add pointer authentication register bits

ESR_ELx.EC code used when the new instructions are affected by configurable traps This patch adds the relevant definitions to and for these, to be used by subsequent patches. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Suzu

[RFC 3/9] arm64/cpufeature: add ARMv8.3 id_aa64isar1 bits

ned-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Suzuki K Poulose <suzuki.poul...@arm.com> Cc: Will Deacon <will.dea...@arm.com> --- arch/arm64/kernel/cpufeature.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(

[RFC 8/9] arm64/kvm: context-switch PAC registers

will need to trap accesses to these to provide santized values. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: kvmarm@lists.cs.columbia.edu --- arch/arm64/include/asm/kvm_emulate.h | 15 +

[RFC 9/9] arm64: docs: document pointer authentication

available (e.g. as we expect for FP and other things today). I'm not sure quite what to say, and as it stands this isn't quite correct. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Will Deacon <will.dea...@arm.com> --- D

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