On Wed, Nov 28, 2018 at 02:45:15PM +, Steven Price wrote:
> This series add support for paravirtualized time for Arm64 guests and
> KVM hosts following the specification in Arm's document DEN 0057A:
>
> https://developer.arm.com/docs/den0057/a
>
> It implements support for Live Physical Time
On Fri, Jan 04, 2019 at 10:33:40AM +0100, Pavel Machek wrote:
> On Fri 2019-01-04 09:21:30, Marc Zyngier wrote:
> > On 03/01/2019 20:29, Pavel Machek wrote:
> > > On Fri 2018-12-07 18:39:25, Kristina Martsenko wrote:
> > >> From: Mark Rutland
> > >>
g
> Signed-off-by: Peter Maydell
>
> and as you would expect the system boots fine with -cpu cortex-a57
>
> On the kernel side it breaks at:
>
> commit 04ca3204fa09f5f55c8f113b0072004a7b364ff4
> Author: Mark Rutland
> Date: Fri Dec 7 18:39:30 2018 +
On Tue, Jan 29, 2019 at 11:54:13AM +, Peter Maydell wrote:
> On Tue, 29 Jan 2019 at 11:46, Mark Rutland wrote:
> > On Tue, Jan 29, 2019 at 11:08:19AM +, Alex Bennée wrote:
> > > The -cpu max enabled a cortex-a57 + whatever extra features we've
> > > enable
On Mon, Feb 18, 2019 at 07:52:18PM +, Dave Martin wrote:
> kvm_host.h uses DECLARE_BITMAP() to declare the features member of
> struct vcpu_arch, but the corresponding #include for this is
> missing.
>
> This patch adds a suitable #include for . Although
> the header builds without it today,
On Mon, Feb 18, 2019 at 07:52:25PM +, Dave Martin wrote:
> Some optional features of the Arm architecture add new system
> registers that are not present in the base architecture.
>
> Where these features are optional for the guest, the visibility of
> these registers may need to depend on som
On Mon, Feb 18, 2019 at 07:52:27PM +, Dave Martin wrote:
> -static bool __hyp_text __hyp_switch_fpsimd(struct kvm_vcpu *vcpu)
> +/* Check for an FPSIMD/SVE trap and handle as appropriate */
> +static bool __hyp_text __hyp_handle_fpsimd(struct kvm_vcpu *vcpu)
> {
> - struct user_fpsimd_stat
Hi,
On Tue, Feb 19, 2019 at 02:54:26PM +0530, Amit Daniel Kachhap wrote:
> From: Mark Rutland
>
> When restoring HCR_EL2 for the host, KVM uses HCR_HOST_VHE_FLAGS, which
> is a constant value. This works today, as the host HCR_EL2 value is
> always the same, but this will ge
tored in struct kvm_cpu_context as
> both host and guest can now use this field in a common way.
>
> Signed-off-by: Amit Daniel Kachhap
> Cc: Marc Zyngier
> Cc: Mark Rutland
> Cc: Christoffer Dall
> Cc: kvmarm@lists.cs.columbia.edu
> ---
> arch/arm/include/asm/kvm
On Tue, Feb 19, 2019 at 02:54:28PM +0530, Amit Daniel Kachhap wrote:
> From: Mark Rutland
>
> When pointer authentication is supported, a guest may wish to use it.
> This patch adds the necessary KVM infrastructure for this to work, with
> a semi-lazy context switch of the poi
eter instead of creating a new API.
>
> A new register is not created to pass this parameter via
> SET/GET_ONE_REG interface as just a flag (KVM_ARM_VCPU_PTRAUTH)
> supplied is enough to enable this feature.
>
> Signed-off-by: Amit Daniel Kachhap
> Cc: Mark Rutland
> Cc:
On Fri, Feb 22, 2019 at 04:23:23PM +0800, Leo Yan wrote:
> Use macro for ID_AA64MMFR1_EL1.VH bits shift instead of 8 directly.
>
> Signed-off-by: Leo Yan
It's always nice to get rid of magic numbers, and this is correct
AFAICT. FWIW:
Reviewed-by: Mark Rutland
Mark.
>
Reviewed-by: Mark Rutland
Mark.
> ---
> arch/arm64/include/asm/kvm_arm.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/kvm_arm.h
> b/arch/arm64/include/asm/kvm_arm.h
> index 6f602af5263c..d945a787f36e 100644
> --- a/arch
On Tue, Feb 26, 2019 at 12:06:16PM +, Dave Martin wrote:
> On Wed, Feb 20, 2019 at 03:23:50PM +0000, Mark Rutland wrote:
> > On Mon, Feb 18, 2019 at 07:52:18PM +, Dave Martin wrote:
> > > kvm_host.h uses DECLARE_BITMAP() to declare the features member of
> > >
On Tue, Feb 26, 2019 at 12:33:22PM +, Dave Martin wrote:
> On Tue, Feb 26, 2019 at 12:31:45PM +0000, Mark Rutland wrote:
> > On Tue, Feb 26, 2019 at 12:06:16PM +, Dave Martin wrote:
> > > On Wed, Feb 20, 2019 at 03:23:50PM +, Mark Rutland wrote:
>
> [
return -EINVAL;
> }
>
> +static u32 psci_get_version_0_1(void)
> +{
> + return PSCI_VERSION(0, 1);
> +}
Elsewhere in this file we've used a psci_${MAJOR}_${MINOR}_* naming
scheme.
To match that, I'd prefer we call this psci_0_1_get_version(), and
rename psci_get_ve
On Thu, Nov 26, 2020 at 03:54:00PM +, David Brazdil wrote:
> Function IDs used by PSCI are configurable for v0.1 via DT/APCI. If the
> host is using PSCI v0.1, KVM's host PSCI proxy needs to use the same IDs.
> Expose the array holding the information with a read-only accessor.
>
> Signed-off-
On Thu, Nov 26, 2020 at 03:54:01PM +, David Brazdil wrote:
> CPU index should never be negative. Change the signature of
> (set_)cpu_logical_map to take an unsigned int.
>
> Signed-off-by: David Brazdil
Is there a function problem here, or is this just cleanup from
inspection?
Core code inc
On Thu, Nov 26, 2020 at 03:54:02PM +, David Brazdil wrote:
> KVM currently initializes MAIR_EL2 to the value of MAIR_EL1. In
> preparation for initializing MAIR_EL2 before MAIR_EL1, move the constant
> into a shared header file. Since it is used for EL1 and EL2, rename to
> MAIR_ELx_SET.
>
> S
On Thu, Nov 26, 2020 at 03:54:03PM +, David Brazdil wrote:
> When the a CPU is booted in EL2, the kernel checks for VHE support and
> initializes the CPU core accordingly. For nVHE it also installs the stub
> vectors and drops down to EL1.
>
> Once KVM gains the ability to boot cores without g
On Tue, Dec 01, 2020 at 01:19:13PM +, David Brazdil wrote:
> Hey Sudeep,
>
> > > diff --git a/Documentation/admin-guide/kernel-parameters.txt
> > > b/Documentation/admin-guide/kernel-parameters.txt
> > > index 526d65d8573a..06c89975c29c 100644
> > > --- a/Documentation/admin-guide/kernel-para
On Thu, Nov 26, 2020 at 03:54:18PM +, David Brazdil wrote:
> Add a handler of CPU_SUSPEND host PSCI SMCs. The SMC can either enter
> a sleep state indistinguishable from a WFI or a deeper sleep state that
> behaves like a CPU_OFF+CPU_ON except that the core is still considered
> online when asl
On Tue, Dec 01, 2020 at 02:43:49PM +, David Brazdil wrote:
> > > > be just me, but if you agree please update so that it doesn't give
> > > > remote
> > > > idea that it is not valid on VHE enabled hardware.
> > > >
> > > > I was trying to run this on the hardware and was trying to understand
mall cleanup so that the function ID array is only used for
> v0.1 configurations.
>
> Signed-off-by: David Brazdil
Acked-by: Mark Rutland
Mark.
> ---
> drivers/firmware/psci/psci.c | 94 +++-
> 1 file changed, 60 insertions(+), 34 delet
to
> other parts of the kernel. Exposing a struct avoids the need for
> bounds checking.
>
> Signed-off-by: David Brazdil
Acked-by: Mark Rutland
Mark.
> ---
> drivers/firmware/psci/psci.c | 29 ++---
> 1 file changed, 14 insertions(+), 15 deletions(-)
On Wed, Dec 02, 2020 at 06:41:02PM +, David Brazdil wrote:
> Make it possible to retrieve a copy of the psci_0_1_function_ids struct.
> This is useful for KVM if it is configured to intercept host's PSCI SMCs.
>
> Signed-off-by: David Brazdil
Acked-by: Mark Rutland
... ju
On Wed, Dec 02, 2020 at 06:41:12PM +, David Brazdil wrote:
> Add a handler of PSCI SMCs in nVHE hyp code. The handler is initialized
> with the version used by the host's PSCI driver and the function IDs it
> was configured with. If the SMC function ID matches one of the
> configured PSCI calls
On Fri, Nov 27, 2020 at 03:21:11PM +, Steven Price wrote:
> It's been a week, and I think the comments on v5 made it clear that
> enforcing PROT_MTE requirements on the VMM was probably the wrong
> approach. So since I've got swap working correctly without that I
> thought I'd post a v6 which h
On Thu, Dec 03, 2020 at 04:49:49PM +, Steven Price wrote:
> On 03/12/2020 16:09, Mark Rutland wrote:
> > On Fri, Nov 27, 2020 at 03:21:11PM +, Steven Price wrote:
> > > It's been a week, and I think the comments on v5 made it clear that
> > > enforcing PROT
On Mon, Dec 07, 2020 at 10:20:03AM +, Will Deacon wrote:
> On Fri, Dec 04, 2020 at 06:01:52PM +, Quentin Perret wrote:
> > On Thursday 03 Dec 2020 at 12:57:33 (+), Fuad Tabba wrote:
> >
> > > > +SYM_FUNC_START(__kvm_init_switch_pgd)
> > > > + /* Turn the MMU off */
> > > > +
> > set, eg. set bit for PSCI_CPU_SUSPEND if psci_ops.cpu_suspend != NULL.
> >
> > Previously config was split into multiple global variables. Put
> > everything into a single struct for convenience.
> >
> > Reported-by: Mark Rutland
> > Signed-off-by: David Braz
ilar situations in EFI stub and KVM as well.
>
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Marc Zyngier
> Cc: James Morse
> Cc: Suzuki K Poulose
> Cc: Ard Biesheuvel
> Cc: Mark Rutland
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: kvmarm@lists.cs.col
On Mon, Mar 08, 2021 at 01:30:53PM +, Will Deacon wrote:
> On Sun, Mar 07, 2021 at 05:24:21PM +0530, Anshuman Khandual wrote:
> > On 3/5/21 8:21 PM, Mark Rutland wrote:
> > > On Fri, Mar 05, 2021 at 08:06:09PM +0530, Anshuman Khandual wrote
init.S
> > +++ b/arch/arm64/kvm/hyp/nvhe/hyp-init.S
> > @@ -117,13 +117,7 @@ alternative_else_nop_endif
> > tlbialle2
> > dsb sy
> >
> > - /*
> > - * Preserve all the RES1 bits while settin
On Thu, Mar 11, 2021 at 11:35:29AM +, Mark Rutland wrote:
> Acked-by: Mark Rutland
Upon reflection, maybe I should spell my own name correctly:
Acked-by: Mark Rutland
... lest you decide to add a Mocked-by tag instead ;)
Mark.
___
kvm
On Mon, May 10, 2021 at 02:48:18PM +0100, Marc Zyngier wrote:
> As it turns out, not all the interrupt controllers are able to
> expose a vGIC maintenance interrupt as a distrete signal.
> And to be fair, it doesn't really matter as all we require is
> for *something* to kick us out of guest mode o
On Mon, May 10, 2021 at 06:44:49PM +0100, Marc Zyngier wrote:
> On Mon, 10 May 2021 17:19:07 +0100,
> Mark Rutland wrote:
> >
> > On Mon, May 10, 2021 at 02:48:18PM +0100, Marc Zyngier wrote:
> > > As it turns out, not all the interrupt controllers are able to
>
On Thu, May 20, 2021 at 01:22:53PM +0100, Marc Zyngier wrote:
> It looks like we have tolerated creating mixed-width VMs since...
> forever. However, that was never the intention, and we'd rather
> not have to support that pointless complexity.
>
> Forbid such a setup by making sure all the vcpus
On Thu, May 20, 2021 at 01:58:55PM +0100, Marc Zyngier wrote:
> On Thu, 20 May 2021 13:44:34 +0100,
> Mark Rutland wrote:
> >
> > On Thu, May 20, 2021 at 01:22:53PM +0100, Marc Zyngier wrote:
> > > It looks like we have tolerated creating mixed-width VMs since...
>
g sure all the vcpus have the same
> register width.
>
> Reported-by: Steven Price
> Signed-off-by: Marc Zyngier
> Cc: sta...@vger.kernel.org
Looks good to me!
Acked-by: Mark Rutland
Mark.
> ---
>
> Notes:
> v2: Fix missing check against ARM64_HAS_32BIT_EL1 (M
ate_to_vhe stuff, passing 'kvm-arm.mode=protected' should make the
kernel stick to EL1, right? So this should only affect M1 (or other HW
with a similar impediment).
One minor comment below; otherwise:
Acked-by: Mark Rutland
>
> Cc: David Brazdil
> Signed-off-by: Will Deacon
optimization, but in fact this allows symbol references on
> VHE-specific code paths to be dropped from the nVHE object.
>
> Expand the comment in has_vhe() to make this clearer, hopefully
> discouraging anybody from simplifying the code.
>
> Cc: David Brazdil
> Signed-off
On Thu, Jun 03, 2021 at 07:33:46PM +0100, Will Deacon wrote:
> Add support for a "linux,pkvm-guest-firmware-memory" reserved memory
> region, which can be used to identify a firmware image for protected
> VMs.
The idea that the guest's FW comes from the host's FW strikes me as
unusual; what's the
On Thu, Jun 03, 2021 at 07:33:47PM +0100, Will Deacon wrote:
> Introduce a new VM capability, KVM_CAP_ARM_PROTECTED_VM, which can be
> used to isolate guest memory from the host. For now, the EL2 portion is
> missing, so this documents and exposes the user ABI for the host.
>
> Signed-off-by: Will
On Fri, Jul 02, 2021 at 09:00:22AM -0700, Joe Perches wrote:
> On Fri, 2021-07-02 at 13:22 +0200, Peter Zijlstra wrote:
> > On Tue, Jun 22, 2021 at 05:42:49PM +0800, Zhu Lingshan wrote:
> > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
> []
> > > @@ -90,6 +90,27 @@ DEFINE_STATIC_CA
On Thu, Jul 15, 2021 at 11:00:42AM +0100, Robin Murphy wrote:
> On 2021-07-15 10:44, Qu Wenruo wrote:
> >
> >
> > On 2021/7/15 下午5:28, Robin Murphy wrote:
> > > On 2021-07-15 09:55, Qu Wenruo wrote:
> > > > Hi,
> > > >
> > > > Recently I'm playing around the Nvidia Xavier AGX board, which
> > >
On Thu, Sep 23, 2021 at 12:22:52PM +0100, Will Deacon wrote:
> When pKVM is enabled, the hypervisor code at EL2 and its data structures
> are inaccessible to the host kernel and cannot be torn down or replaced
> as this would defeat the integrity properies which pKVM aims to provide.
> Furthermore,
Hi,
I haven't looked at this in great detail, but I spotted a few issues
from an initial scan.
On Wed, Nov 24, 2021 at 12:07:07PM -0500, Tyler Baicar wrote:
> Add support for parsing the ARM Error Source Table and basic handling of
> errors reported through both memory mapped and system register
mplemented, LoadLOAcquire
and StoreLORelease must behave as LoadAcquire and StoreRelease
respectively. We can ensure this by clearing LORC_EL1.EN when a CPU's
EL2 is first initialized, as the host kernel will not modify this.
Signed-off-by: Mark Rutland
Reviewed-by: Vladimir Murzin
Cc:
On Tue, Feb 06, 2018 at 01:39:06PM +0100, Christoffer Dall wrote:
> Hi Mark,
>
> On Mon, Nov 27, 2017 at 04:37:59PM +0000, Mark Rutland wrote:
> > To allow EL0 (and/or EL1) to use pointer authentication functionality,
> > we must ensure that pointer authentication instruc
On Tue, Feb 13, 2018 at 11:27:42AM +0100, Christoffer Dall wrote:
> Hi Mark,
Hi Christoffer,
> On Mon, Feb 12, 2018 at 11:14:24AM +, Mark Rutland wrote:
> > We don't currently limit guest accesses to the LOR registers, which we
> > neither virtualize nor context-swit
r non-existence.
As noted in D7.2.67, when no LORegions are implemented, LoadLOAcquire
and StoreLORelease must behave as LoadAcquire and StoreRelease
respectively. We can ensure this by clearing LORC_EL1.EN when a CPU's
EL2 is first initialized, as the host kernel will not modify this.
Signed-of
On Wed, Feb 21, 2018 at 07:49:06AM -0600, Shanker Donthineni wrote:
> The DCache clean & ICache invalidation requirements for instructions
> to be data coherence are discoverable through new fields in CTR_EL0.
> The following two control bits DIC and IDC were defined for this
> purpose. No need to
On Wed, Feb 21, 2018 at 04:51:40PM +, Robin Murphy wrote:
> On 21/02/18 16:14, Shanker Donthineni wrote:
> [...]
> > > > @@ -1100,6 +1114,20 @@ static int cpu_copy_el2regs(void *__unused)
> > > > .enable = cpu_clear_disr,
> > > > },
> > > > #endif /* CONFIG_ARM64_RAS_E
On Thu, Feb 22, 2018 at 08:51:30AM -0600, Shanker Donthineni wrote:
> +#define CTR_B31_SHIFT31
Since this is just a RES1 bit, I think we don't need a mnemonic for it,
but I'll defer to Will and Catalin on that.
> ENTRY(invalidate_icache_range)
> +#ifdef CONFIG_ARM64_SKIP_CACHE_PO
On Thu, Feb 22, 2018 at 04:28:03PM +, Robin Murphy wrote:
> [Apologies to keep elbowing in, and if I'm being thick here...]
>
> On 22/02/18 15:22, Mark Rutland wrote:
> > On Thu, Feb 22, 2018 at 08:51:30AM -0600, Shanker Donthineni wrote:
> > > +#defin
Hi,
On Sat, Feb 24, 2018 at 06:09:53AM -0600, Shanker Donthineni wrote:
> +config ARM64_SKIP_CACHE_POU
> + bool "Enable support to skip cache POU operations"
Nit: s/POU/PoU/ in text
> + default y
> + help
> + Explicit point of unification cache operations can be eliminated
> +
On Mon, Mar 05, 2018 at 09:52:19AM -0600, Timur Tabi wrote:
> On Fri, Mar 2, 2018 at 3:50 PM, Shanker Donthineni
> wrote:
> > diff --git a/arch/arm64/include/asm/cpucaps.h
> > b/arch/arm64/include/asm/cpucaps.h
> > index bb26382..6ecc249 100644
> > --- a/arch/arm64/include/asm/cpucaps.h
> > +++ b
r as an early return:
static inline void __flush_icache_all(void)
{
if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC))
return;
asm("ic ialluis");
dsb(ish);
}
... which minimizes indentation, and the diffstat.
The rest looks fine to me
On Tue, Feb 06, 2018 at 01:38:47PM +0100, Christoffer Dall wrote:
> On Mon, Nov 27, 2017 at 04:38:04PM +0000, Mark Rutland wrote:
> > When pointer authentication is supported, a guest may wish to use it.
> > This patch adds the necessary KVM infrastructure for this to work, with
On Fri, Mar 16, 2018 at 02:49:00PM +0100, Andrey Konovalov wrote:
> Hi!
Hi,
> I've recently tried to boot clang built kernel on real hardware
> (Odroid C2 board) instead of using a VM. The issue that I stumbled
> upon is that arm64 kvm built with clang doesn't boot.
>
> Adding -fno-jump-tables
On Fri, Mar 16, 2018 at 02:13:14PM +, Mark Rutland wrote:
> On Fri, Mar 16, 2018 at 02:49:00PM +0100, Andrey Konovalov wrote:
> > Hi!
>
> Hi,
>
> > I've recently tried to boot clang built kernel on real hardware
> > (Odroid C2 board) instead of using a VM.
On Fri, Mar 16, 2018 at 04:52:08PM +, Nick Desaulniers wrote:
> + Sami (Google), Takahiro (Linaro)
>
> Just so I fully understand the problem enough to articulate it, we'd be
> looking for the compiler to keep the jump tables for speed (I would guess
> -fno-jump-tables would emit an if-else ch
On Thu, Mar 29, 2018 at 11:00:24PM +0800, Shannon Zhao wrote:
> From: zhaoshenglong
>
> Currently the VMID for some VM is allocated during VCPU entry/exit
> context and will be updated when kvm_next_vmid inversion. So this will
> cause the existing VMs exiting from guest and flush the tlb and ica
On Thu, Mar 29, 2018 at 04:27:58PM +0100, Mark Rutland wrote:
> On Thu, Mar 29, 2018 at 11:00:24PM +0800, Shannon Zhao wrote:
> > From: zhaoshenglong
> >
> > Currently the VMID for some VM is allocated during VCPU entry/exit
> > context and will be updated when kvm_n
BLY__ block.
Signed-off-by: Mark Rutland
Cc: Marc Zyngier
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/include/asm/kvm_asm.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
index 24961b732e65..306aaea
On Mon, Apr 09, 2018 at 02:58:18PM +0200, Christoffer Dall wrote:
> Hi Mark,
>
> [Sorry for late reply]
>
> On Fri, Mar 09, 2018 at 02:28:38PM +0000, Mark Rutland wrote:
> > On Tue, Feb 06, 2018 at 01:38:47PM +0100, Christoffer Dall wrote:
> > > On Mon, Nov 27,
On Tue, Feb 06, 2018 at 01:39:15PM +0100, Christoffer Dall wrote:
> On Mon, Nov 27, 2017 at 04:38:03PM +0000, Mark Rutland wrote:
> > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
> > index 525c01f48867..2205f0be3ced 100644
> > --- a/arch/arm64/kvm/h
erformance issues. A middle ground
> > is to convert the spinlock to a rwlock, and only take the read lock
> > on the fast path. If the check fails at that point, drop it and
> > acquire the write lock, rechecking the condition.
> >
> > This ensures that the above scen
On Tue, Apr 10, 2018 at 05:05:40PM +0200, Christoffer Dall wrote:
> On Tue, Apr 10, 2018 at 11:51:19AM +0100, Mark Rutland wrote:
> > I think we also need to update kvm->arch.vttbr before updating
> > kvm->arch.vmid_gen, otherwise another CPU can come in, see that the
>
l.org/r/1500480092-28480-1-git-send-email-mark.rutl...@arm.com
[3] https://lkml.kernel.org/r/20171127163806.31435-1-mark.rutl...@arm.com
[4] git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git
arm64/pointer-auth
[5] git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.g
ESR_ELx.EC code used when the new instructions are affected by
configurable traps
This patch adds the relevant definitions to and
for these, to be used by subsequent patches.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch
configure more flags for the host, so
lets add a HCR_HOST_NVHE_FLAGS defintion, adn consistently use both
HCR_HOST_VHE_FLAGS and HCR_HOST_NVHE_FLAGS in the kvm code and head.S.
We now use mov_q to generate the HCR_EL2 value, as we use when
configuring other registers in head.S.
Signed-off-by: Mark R
se ptrauth instructions, triggering a trap to EL2,
resulting in noise from kvm_handle_unknown_ec(). So let's write up a
handler for the PAC trap, which silently injects an UNDEF into the
guest, as if the feature were really missing.
Signed-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Marc Zyng
not enable support for KVM guests, since KVM manages HCR_EL2
itself when running VMs.
Signed-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: Will Deacon
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/include/asm/kvm_arm.h | 4 +++-
1 file changed, 3 inserti
out address authentication, so we only
need to check APA and API. It is assumed that if all CPUs support an IMP
DEF algorithm, the same algorithm is used across all CPUs.
Note that when we implement KVM support, we will also need to ensure
that CPUs have uniform support for GPA and GPI.
Signed-off-by: M
, allow each hook to be overridden indiviually,
by placing each under an #ifndef block. As architectures providing their
own hooks can't include this file today, this shouldn't adversely affect
any existing hooks.
Signed-off-by: Mark Rutland
Cc: Arnd Bergmann
Cc: linux-a...@vger.
is added for the generic key (APGAKey), though this cannot be
trapped or made to behave as a NOP. Its presence is not advertised with
a hwcap.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Ramana Radhakrishnan
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch/arm64/include/asm/mmu.h
-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Ramana Radhakrishnan
Cc: Will Deacon
---
arch/arm64/include/asm/pointer_auth.h | 8
arch/arm64/include/uapi/asm/ptrace.h | 7 +++
arch/arm64/kernel/ptrace.c| 38 +++
include/uapi/linux/elf.h
s the LR value, and not the
FP.
This only affects the in-kernel unwinder. When userspace performs
unwinding, it is up to userspace to strip PACs as necessary (which can
be determined from DWARF information).
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Ramana Radhakrishnan
Cc: Will D
Now that all the necessary bits are in place for userspace, add the
necessary Kconfig logic to allow this to be enabled.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/Kconfig | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch
Now that we've added code to support pointer authentication, add some
documentation so that people can figure out if/how to use it.
Signed-off-by: Mark Rutland
Cc: Andrew Jones
Cc: Catalin Marinas
Cc: Ramana Radhakrishnan
Cc: Will Deacon
---
Documentation/arm64/bootin
On Tue, Apr 17, 2018 at 09:56:02PM +0200, Arnd Bergmann wrote:
> On Tue, Apr 17, 2018 at 8:37 PM, Mark Rutland wrote:
> > Currently, an architecture must either implement all of the mm hooks
> > itself, or use all of those provided by the asm-generic implementation.
> > When
On Wed, Apr 18, 2018 at 03:19:26PM +0200, Andrew Jones wrote:
> On Tue, Apr 17, 2018 at 07:37:27PM +0100, Mark Rutland wrote:
> > @@ -1000,6 +1000,15 @@ static u64 read_id_reg(struct sys_reg_desc const *r,
> > bool raz)
> >
Hi Andrey,
On Fri, Apr 20, 2018 at 04:59:35PM +0200, Andrey Konovalov wrote:
> On Fri, Apr 20, 2018 at 10:13 AM, Marc Zyngier wrote:
> >> The issue is that
> >> clang doesn't know about the "S" asm constraint. I reported this to
> >> clang [2], and hopefully this will get fixed. In the meantime,
.
Thanks,
Mark.
Mark Rutland (3):
arm64: fix possible spectre-v1 in ptrace_hbp_get_event()
KVM: arm/arm64: vgic: fix possible spectre-v1 in vgic_get_irq()
KVM: arm/arm64: vgic: fix possible spectre-v1 in vgic_mmio_read_apr()
arch/arm64/kernel/ptrace.c | 14 ++
virt/kvm/arm
It's possible for userspace to control idx. Sanitize idx when using it
as an array index.
Found by smatch.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/kernel/ptrace.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a
It's possible for userspace to control intid. Sanitize intid when using
it as an array index.
At the same time, sort the includes when adding .
Found by smatch.
Signed-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: kvmarm@lists.cs.columbia.edu
---
virt/kvm/arm/vgic/v
is is
the case, and given this is a slow path it's better to always perform
the masking.
Found by smatch.
Signed-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: kvmarm@lists.cs.columbia.edu
---
virt/kvm/arm/vgic/vgic-mmio-v2.c | 5 +
1 file changed, 5 insertions(+)
di
On Fri, Apr 27, 2018 at 11:51:39AM +0200, Christoffer Dall wrote:
> On Tue, Apr 17, 2018 at 07:37:26PM +0100, Mark Rutland wrote:
> > In KVM we define the configuration of HCR_EL2 for a VHE HOST in
> > HCR_HOST_VHE_FLAGS, but we don't ahve a similar definition for the
>
>
On Wed, Apr 25, 2018 at 12:23:32PM +0100, Catalin Marinas wrote:
> Hi Mark,
>
> On Tue, Apr 17, 2018 at 07:37:31PM +0100, Mark Rutland wrote:
> > diff --git a/arch/arm64/include/asm/mmu_context.h
> > b/arch/arm64/include/asm/mmu_context.h
> > index 39ec0b8a689e..ca
configure more flags for the host, so
lets add a HCR_HOST_NVHE_FLAGS defintion, and consistently use both
HCR_HOST_VHE_FLAGS and HCR_HOST_NVHE_FLAGS in the kvm code and head.S.
We now use mov_q to generate the HCR_EL2 value, as we use when
configuring other registers in head.S.
Signed-off-by: Ma
l.org/r/20180417183735.56985-1-mark.rutl...@arm.com
[5] git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git
arm64/pointer-auth
[6] git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git
Mark Rutland (10):
arm64: add pointer authentication register bits
arm64/kvm: co
ESR_ELx.EC code used when the new instructions are affected by
configurable traps
This patch adds the relevant definitions to and
for these, to be used by subsequent patches.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch
not enable support for KVM guests, since KVM manages HCR_EL2
itself when running VMs.
Signed-off-by: Mark Rutland
Acked-by: Christoffer Dall
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: Will Deacon
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/include/asm/kvm_arm.h | 4 +++-
1 file changed,
se ptrauth instructions, triggering a trap to EL2,
resulting in noise from kvm_handle_unknown_ec(). So let's write up a
handler for the PAC trap, which silently injects an UNDEF into the
guest, as if the feature were really missing.
Signed-off-by: Mark Rutland
Reviewed-by: Andrew Jones
Reviewed-by: C
out address authentication, so we only
need to check APA and API. It is assumed that if all CPUs support an IMP
DEF algorithm, the same algorithm is used across all CPUs.
Note that when we implement KVM support, we will also need to ensure
that CPUs have uniform support for GPA and GPI.
Signed-off-by: M
is added for the generic key (APGAKey), though this cannot be
trapped or made to behave as a NOP. Its presence is not advertised with
a hwcap.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Ramana Radhakrishnan
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch/arm64/include/asm/mmu.h
Now that all the necessary bits are in place for userspace, add the
necessary Kconfig logic to allow this to be enabled.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/Kconfig | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch
s the LR value, and not the
FP.
This only affects the in-kernel unwinder. When userspace performs
unwinding, it is up to userspace to strip PACs as necessary (which can
be determined from DWARF information).
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Ramana Radhakrishnan
Cc: Will D
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