Re: fiasco.oc i.MX7d port

Hi, On Fri Oct 14, 2016 at 11:03:16 +0200, Marc CHALAND wrote: > OK, I see. My #ifndef was not good. Seems to work now. I've got the CPU[1] > goes to idle loop :). If you wish, I can send to you the patch to get it > work ? Good it works now. Please don't bother, I'll take care of that. :)

Re: fiasco.oc i.MX7d port

OK, I see. My #ifndef was not good. Seems to work now. I've got the CPU[1] goes to idle loop :). If you wish, I can send to you the patch to get it work ? Marc Le jeudi 13 octobre 2016, Adam Lackorzynski a écrit : > Hi Marc, > > On Wed Oct 12, 2016 at 11:17:36 +0200,

Re: fiasco.oc i.MX7d port

Hi Marc, On Wed Oct 12, 2016 at 11:17:36 +0200, Marc CHALAND wrote: > Le mercredi 12 octobre 2016, Adam Lackorzynski > a écrit : > > > > I do not see anything obviously wrong right away. I assume it passes the

fiasco.oc i.MX7d port

Le mercredi 12 octobre 2016, Adam Lackorzynski > a écrit : > > I do not see anything obviously wrong right away. I assume it passes the > while loop? > Yes, the while loop exits. In fact, I think uboot powers up

fiasco.oc i.MX7d port

platform_control-arm-imx7.cpp Hi Adam :) Le samedi 8 octobre 2016, Adam Lackorzynski > a écrit : > Hi, > >

Re: fiasco.oc i.MX7d port

Hi, On Wed Oct 05, 2016 at 19:50:45 +0200, Marc CHALAND wrote: > I'm trying to port fiasco.oc to i.MX7d. It works, but I cannot start second > core. I set trampoline addr into corresponding GPR and enables CORE1. But > nothing happens. I saw that trampoline assembler code enables SCU through >

fiasco.oc i.MX7d port

Hi, I'm trying to port fiasco.oc to i.MX7d. It works, but I cannot start second core. I set trampoline addr into corresponding GPR and enables CORE1. But nothing happens. I saw that trampoline assembler code enables SCU through external registers. But with cortex a7, SCU hasn't got external