Re: [PATCH v3 24/26] drm/bridge: remove the .of_node member

nel->dev->of_node; > - else if (lvds->bridge->of_node) > - remote = lvds->bridge->of_node; > else > remote = lvds->bridge->odev->of_node; > if (of_property_read_string(dev->of_node, "rockchip,output", )) for the Rockchip-part Acked-by: Heiko Stuebner

Re: [PATCH v3 01/26] drm/bridge: allow optionally specifying an owner .odev device

->of_node; > + else > + remote = lvds->bridge->odev->of_node; > if (of_property_read_string(dev->of_node, "rockchip,output", )) > /* default set it as output rgb */ > lvds->output = DISPLAY_OUTPUT_RGB; for the Rockchip-part Acked-by: Heiko Stuebner <he...@sntech.de>

Re: [PATCH v3 01/26] drm/bridge: allow optionally specifying an owner .odev device

ge->odev->of_node; > if (of_property_read_string(dev->of_node, "rockchip,output", )) > /* default set it as output rgb */ > lvds->output = DISPLAY_OUTPUT_RGB; for the Rockchip-part Acked-by: Heiko Stuebner

Re: [PATCH v5 4/4] drm/rockchip: support dp training outside dp firmware

Am Freitag, 18. Mai 2018, 17:36:56 CEST schrieb Sean Paul: > On Fri, May 18, 2018 at 10:52:17AM +0200, Heiko Stuebner wrote: > > Am Freitag, 18. Mai 2018, 03:45:46 CEST schrieb Brian Norris: > > > On Thu, May 17, 2018 at 6:41 PM, hl <h...@rock-chips.com> wrote: > > &g

Re: [PATCH v5 4/4] drm/rockchip: support dp training outside dp firmware

Am Freitag, 18. Mai 2018, 17:36:56 CEST schrieb Sean Paul: > On Fri, May 18, 2018 at 10:52:17AM +0200, Heiko Stuebner wrote: > > Am Freitag, 18. Mai 2018, 03:45:46 CEST schrieb Brian Norris: > > > On Thu, May 17, 2018 at 6:41 PM, hl wrote: > > > > On Thursday, Ma

Re: [PATCH v5 3/4] phy: rockchip-typec: support variable phy config value

Hi, Am Donnerstag, 17. Mai 2018, 11:17:59 CEST schrieb Lin Huang: > the phy config values used to fix in dp firmware, but some boards > need change these values to do training and get the better eye diagram > result. So support that in phy driver. > > Signed-off-by: Chris Zhong

Re: [PATCH v5 3/4] phy: rockchip-typec: support variable phy config value

Hi, Am Donnerstag, 17. Mai 2018, 11:17:59 CEST schrieb Lin Huang: > the phy config values used to fix in dp firmware, but some boards > need change these values to do training and get the better eye diagram > result. So support that in phy driver. > > Signed-off-by: Chris Zhong > Signed-off-by:

Re: [PATCH v5 2/4] Documentation: bindings: add phy_config for Rockchip USB Type-C PHY

Am Donnerstag, 17. Mai 2018, 11:17:58 CEST schrieb Lin Huang: > If want to do training outside DP Firmware, need phy voltage swing > and pre_emphasis value. > > Signed-off-by: Lin Huang > --- > Changes in v2: > - None > Changes in v3: > - modify property description and add

Re: [PATCH v5 2/4] Documentation: bindings: add phy_config for Rockchip USB Type-C PHY

Am Donnerstag, 17. Mai 2018, 11:17:58 CEST schrieb Lin Huang: > If want to do training outside DP Firmware, need phy voltage swing > and pre_emphasis value. > > Signed-off-by: Lin Huang > --- > Changes in v2: > - None > Changes in v3: > - modify property description and add this property to

Re: [PATCH v5 4/4] drm/rockchip: support dp training outside dp firmware

Am Freitag, 18. Mai 2018, 03:45:46 CEST schrieb Brian Norris: > On Thu, May 17, 2018 at 6:41 PM, hl wrote: > > On Thursday, May 17, 2018 09:51 PM, Sean Paul wrote: > >> On Thu, May 17, 2018 at 05:18:00PM +0800, Lin Huang wrote: > >>> DP firmware uses fixed phy config values

Re: [PATCH v5 4/4] drm/rockchip: support dp training outside dp firmware

Am Freitag, 18. Mai 2018, 03:45:46 CEST schrieb Brian Norris: > On Thu, May 17, 2018 at 6:41 PM, hl wrote: > > On Thursday, May 17, 2018 09:51 PM, Sean Paul wrote: > >> On Thu, May 17, 2018 at 05:18:00PM +0800, Lin Huang wrote: > >>> DP firmware uses fixed phy config values to do training, but

Re: [PATCH v2] PM / AVS: rockchip-io: add io selectors and supplies for PX30

the > pmu power domain. > > Signed-off-by: David Wu <david...@rock-chips.com> thanks for the fast respin, looks great now. Reviewed-by: Heiko Stuebner <he...@sntech.de>

Re: [PATCH v2] PM / AVS: rockchip-io: add io selectors and supplies for PX30

the > pmu power domain. > > Signed-off-by: David Wu thanks for the fast respin, looks great now. Reviewed-by: Heiko Stuebner

Re: [PATCH] PM / AVS: rockchip-io: add io selectors and supplies for PX30

"vccio6", > + "vccio1", > + "vccio2", > + "vccio3", > + "vccio4", > + "vccio5", > + "vccio_oscgpi", vccio-oscgpi ... aka with a "-" instead of "_" With the above fixed Reviewed-by: Heiko Stuebner <he...@sntech.de> Thanks Heiko

Re: [PATCH] PM / AVS: rockchip-io: add io selectors and supplies for PX30

"vccio1", > + "vccio2", > + "vccio3", > + "vccio4", > + "vccio5", > + "vccio_oscgpi", vccio-oscgpi ... aka with a "-" instead of "_" With the above fixed Reviewed-by: Heiko Stuebner Thanks Heiko

Re: [PATCH] pinctrl: rockchip: Add pinctrl support for PX30

pinctrl-area and I couldn't find anything looking out of the ordinary, so Reviewed-by: Heiko Stuebner <he...@sntech.de> Thanks Heiko

Re: [PATCH] pinctrl: rockchip: Add pinctrl support for PX30

hing looking out of the ordinary, so Reviewed-by: Heiko Stuebner Thanks Heiko

Re: [PATCH v2 04/13] soc: rockchip: power-domain: Fix wrong value when power up pd

Rockchips SoCs may have their power-domain control in registers > using a writemask-based access scheme (upper 16bit being the write > mask). So add a DOMAIN_M type and handle this case accordingly. > Signed-off-by: Elaine Zhang <zhangq...@rock-chips.com> > Signe

Re: [PATCH v2 04/13] soc: rockchip: power-domain: Fix wrong value when power up pd

using a writemask-based access scheme (upper 16bit being the write > mask). So add a DOMAIN_M type and handle this case accordingly. > Signed-off-by: Elaine Zhang > Signed-off-by: Heiko Stuebner > > Signed-off-by: Finley Xiao > Signed-off-by: Elaine Zhang

Re: [PATCH v1 04/13] soc: rockchip: power-domain: Fix wrong value when power up pd

Hi Elaine, Am Freitag, 11. Mai 2018, 05:30:49 CEST schrieb Elaine Zhang: please provide a patch description. This seems to affect rk3328 alone right now, but seems that rk3328 could only ever turn off power-domains but never turn them on again, right? Authorship comment from my previous comment

Re: [PATCH v1 04/13] soc: rockchip: power-domain: Fix wrong value when power up pd

Hi Elaine, Am Freitag, 11. Mai 2018, 05:30:49 CEST schrieb Elaine Zhang: please provide a patch description. This seems to affect rk3328 alone right now, but seems that rk3328 could only ever turn off power-domains but never turn them on again, right? Authorship comment from my previous comment

Re: [PATCH v1 11/13] dt-bindings: power: add PX30 SoCs header for power-domain

Hi Elaine, Am Freitag, 11. Mai 2018, 05:34:32 CEST schrieb Elaine Zhang: > According to a description from TRM, add all the power domains. > > Signed-off-by: Elaine Zhang > Signed-off-by: Finley Xiao that's a bit ambigous, having the

Re: [PATCH v1 11/13] dt-bindings: power: add PX30 SoCs header for power-domain

Hi Elaine, Am Freitag, 11. Mai 2018, 05:34:32 CEST schrieb Elaine Zhang: > According to a description from TRM, add all the power domains. > > Signed-off-by: Elaine Zhang > Signed-off-by: Finley Xiao that's a bit ambigous, having the Signed-offs like above. Either you are the author+sender

Re: [PATCH v0 2/2] arm64: dts: rockchip: Add sdmmc UHS support for roc-rk3328-cc

Hi Levin, Am Dienstag, 8. Mai 2018, 04:48:24 CEST schrieb d...@t-chip.com.cn: > From: Levin Du > > In roc-rk3328-cc board, the signal voltage of sdmmc is supplied by > the vcc_sdio regulator, which is a mux between 1.8V and 3.3V, > controlled by a special output only gpio

Re: [PATCH v0 2/2] arm64: dts: rockchip: Add sdmmc UHS support for roc-rk3328-cc

Hi Levin, Am Dienstag, 8. Mai 2018, 04:48:24 CEST schrieb d...@t-chip.com.cn: > From: Levin Du > > In roc-rk3328-cc board, the signal voltage of sdmmc is supplied by > the vcc_sdio regulator, which is a mux between 1.8V and 3.3V, > controlled by a special output only gpio pin. > > However,

Re: [PATCH v0 1/2] gpio: syscon: Add gpio-syscon for rk3328

}, > + { > + .compatible = "rockchip,rk3328-gpio-syscon10", rockchip,rk3328-gpio-mute [the naming from the TRM] could be a more suitable naming? Heiko>From 8894fdd9fc4ad90abec32336cc2e528d49abf887 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner <he...@

Re: [PATCH v0 1/2] gpio: syscon: Add gpio-syscon for rk3328

ct gpio_chip *chip, unsigned offset, int > val) > @@ -175,6 +203,10 @@ static const struct of_device_id syscon_gpio_ids[] = { > .compatible = "ti,keystone-dsp-gpio", > .data = _dsp_gpio, > }, > + { > + .compatible

Re: [PATCH] arm64: dts: rockchip: use canonical compatible for touchpad/touchscreen

Am Mittwoch, 2. Mai 2018, 00:46:28 CEST schrieb Dmitry Torokhov: > "atmel,atmel_mxt_tp" and "atmel,atmel_mxt_ts" are ChromeOS inventions, > let's replace them with canonical compatible string "atmel,maxtouch". > > Signed-off-by: Dmitry Torokhov I've amended the patch

Re: [PATCH] arm64: dts: rockchip: use canonical compatible for touchpad/touchscreen

Am Mittwoch, 2. Mai 2018, 00:46:28 CEST schrieb Dmitry Torokhov: > "atmel,atmel_mxt_tp" and "atmel,atmel_mxt_ts" are ChromeOS inventions, > let's replace them with canonical compatible string "atmel,maxtouch". > > Signed-off-by: Dmitry Torokhov I've amended the patch subject with a "on

Re: [PATCH 50/61] thermal: simplify getting .drvdata

ev, "%s: invalid tshut=%d, error=%d\n", > + dev_err(dev, "%s: invalid tshut=%d, error=%d\n", > __func__, thermal->tshut_temp, error); > } > for the Rockchip-part Reviewed-by: Heiko Stuebner <he...@sntech.de>

Re: [PATCH 50/61] thermal: simplify getting .drvdata

ut=%d, error=%d\n", > + dev_err(dev, "%s: invalid tshut=%d, error=%d\n", > __func__, thermal->tshut_temp, error); > } > for the Rockchip-part Reviewed-by: Heiko Stuebner

Re: [PATCH] video: fbdev: remove unused auo_k190xfb drivers

king project, reality is that I don't think I'll ever continue on trying to mainline these and if later someone wants to resurrect these (very old now) devices, they'll probably need a drm- driver anyway. So for the removal Reviewed-by: Heiko Stuebner <he...@sntech.de> Heiko

Re: [PATCH] video: fbdev: remove unused auo_k190xfb drivers

'll ever continue on trying to mainline these and if later someone wants to resurrect these (very old now) devices, they'll probably need a drm- driver anyway. So for the removal Reviewed-by: Heiko Stuebner Heiko

Re: [PATCH 1/1] arm: dts: rockchip: default serial for Tinker Board

Am Dienstag, 17. April 2018, 22:56:23 CEST schrieb Heinrich Schuchardt: > The Asus Tinker Board uses serial 2 with 115,200 baud by default for > communication in U-Boot. The same value is also chosen for other RK3288 > boards. > > So let us set the same value in the Tinker Board device tree. > >

Re: [PATCH 1/1] arm: dts: rockchip: default serial for Tinker Board

Am Dienstag, 17. April 2018, 22:56:23 CEST schrieb Heinrich Schuchardt: > The Asus Tinker Board uses serial 2 with 115,200 baud by default for > communication in U-Boot. The same value is also chosen for other RK3288 > boards. > > So let us set the same value in the Tinker Board device tree. > >

Re: [PATCH 2/6] dt-bindings: clock: add DDR3 standard speed bins.

Hi Enric, Am Donnerstag, 19. April 2018, 13:30:16 CEST schrieb Enric Balletbo i Serra: > On 19/04/18 13:10, Heiko Stuebner wrote: > > Am Donnerstag, 19. April 2018, 12:40:15 CEST schrieb Enric Balletbo i Serra: > >> DDR3 SDRAM Standard (JESD79-3F) defines some standard speed

Re: [PATCH 2/6] dt-bindings: clock: add DDR3 standard speed bins.

Hi Enric, Am Donnerstag, 19. April 2018, 13:30:16 CEST schrieb Enric Balletbo i Serra: > On 19/04/18 13:10, Heiko Stuebner wrote: > > Am Donnerstag, 19. April 2018, 12:40:15 CEST schrieb Enric Balletbo i Serra: > >> DDR3 SDRAM Standard (JESD79-3F) defines some standard speed

Re: [PATCH 2/6] dt-bindings: clock: add DDR3 standard speed bins.

Hi Enric, Am Donnerstag, 19. April 2018, 12:40:15 CEST schrieb Enric Balletbo i Serra: > DDR3 SDRAM Standard (JESD79-3F) defines some standard speed bins for > DDR3 memories. The devfreq/rk3399_dmc.txt binding refers to this file > which does not exist, so add a ddr.h file with the standard speed

Re: [PATCH 2/6] dt-bindings: clock: add DDR3 standard speed bins.

Hi Enric, Am Donnerstag, 19. April 2018, 12:40:15 CEST schrieb Enric Balletbo i Serra: > DDR3 SDRAM Standard (JESD79-3F) defines some standard speed bins for > DDR3 memories. The devfreq/rk3399_dmc.txt binding refers to this file > which does not exist, so add a ddr.h file with the standard speed

Re: [PATCH] drm/rockchip: vop: fixup linebuffer mode calc error

Hi Sandy, Am Dienstag, 17. April 2018, 12:15:07 CEST schrieb Sandy Huang: > When video width is bigger than 3840 the linebuffer mode > should be LB_YUV_3840X5. Can you explain that a bit better? I.e. when looking at the code, the very first check is width > 2560. So it seems your change

Re: [PATCH] drm/rockchip: vop: fixup linebuffer mode calc error

Hi Sandy, Am Dienstag, 17. April 2018, 12:15:07 CEST schrieb Sandy Huang: > When video width is bigger than 3840 the linebuffer mode > should be LB_YUV_3840X5. Can you explain that a bit better? I.e. when looking at the code, the very first check is width > 2560. So it seems your change

Re: [PATCH v2 3/5] soc: rockchip: power-domain: Use of_clk_get_parent_count() instead of open coding

cation below. > > Signed-off-by: Geert Uytterhoeven <geert+rene...@glider.be> Depending on how we plan on merging this series, I could either pick this patch for 4.19, after patch1 makes it into 4.18 or otherwise someone could pick the whole series together with my Reviewed-by: Heiko S

Re: [PATCH v2 3/5] soc: rockchip: power-domain: Use of_clk_get_parent_count() instead of open coding

cation below. > > Signed-off-by: Geert Uytterhoeven Depending on how we plan on merging this series, I could either pick this patch for 4.19, after patch1 makes it into 4.18 or otherwise someone could pick the whole series together with my Reviewed-by: Heiko Stuebner for this patch. Heiko

Re: [PATCH v2 1/5] clk: Extract OF clock helpers in

have to include . > > Suggested-by: Stephen Boyd <sb...@kernel.org> > Signed-off-by: Geert Uytterhoeven <geert+rene...@glider.be> Really cool move, Reviewed-by: Heiko Stuebner <he...@sntech.de>

Re: [PATCH v2 1/5] clk: Extract OF clock helpers in

have to include . > > Suggested-by: Stephen Boyd > Signed-off-by: Geert Uytterhoeven Really cool move, Reviewed-by: Heiko Stuebner

Re: [RESEND PATCH v6 5/5] ARM: dts: rockchip: set PWM delay backlight settings for Minnie

Am Mittwoch, 28. März 2018, 19:03:27 CEST schrieb Enric Balletbo i Serra: > The minnie devices comes with an AUO B101EAN01 panel which is different > from default veyron devices, thus the power on/off timing sequence is > slightly different. The datasheet specifies a pwm delay of 200 ms, so >

Re: [RESEND PATCH v6 5/5] ARM: dts: rockchip: set PWM delay backlight settings for Minnie

Am Mittwoch, 28. März 2018, 19:03:27 CEST schrieb Enric Balletbo i Serra: > The minnie devices comes with an AUO B101EAN01 panel which is different > from default veyron devices, thus the power on/off timing sequence is > slightly different. The datasheet specifies a pwm delay of 200 ms, so >

Re: [RESEND PATCH v6 4/5] ARM: dts: rockchip: set PWM delay backlight settings for Veyron.

Am Mittwoch, 28. März 2018, 19:03:26 CEST schrieb Enric Balletbo i Serra: > For veyron the binding should provide both PWM timings, the delay between > you enable the PWM and set the enable signal, and the delay between you > disable the PWM signal and clear the enable signal. Update the binding >

Re: [RESEND PATCH v6 4/5] ARM: dts: rockchip: set PWM delay backlight settings for Veyron.

Am Mittwoch, 28. März 2018, 19:03:26 CEST schrieb Enric Balletbo i Serra: > For veyron the binding should provide both PWM timings, the delay between > you enable the PWM and set the enable signal, and the delay between you > disable the PWM signal and clear the enable signal. Update the binding >

Re: [PATCH v4] usb: dwc2: dwc2_vbus_supply_init: fix error check

iz...@collabora.com> The patch that gets fixed here also breaks display-output on dwc2-based Rockchip devices (likely even more), probably due to making the regulator framework hickup. With this patch applied, apart from not seeing the NULL-ptr, I also get display output on my rk3288-veyc

Re: [PATCH v4] usb: dwc2: dwc2_vbus_supply_init: fix error check

reaks display-output on dwc2-based Rockchip devices (likely even more), probably due to making the regulator framework hickup. With this patch applied, apart from not seeing the NULL-ptr, I also get display output on my rk3288-veycron Chromebook again, so Tested-by: Heiko Stuebner > v2:

Re: [PATCH v8 2/3] mtd: spi-nor: add rockchip serial flash controller driver

Hi Andy, Am Sonntag, 8. April 2018, 14:08:45 CEST schrieb Andy Yan: > ping We're in the middle of the merge-window right now, so I do guess maintainers will possibly do other things than looking at new code. But you might want to address the kbuild-robot issue and resend in the meantime, as

Re: [PATCH v8 2/3] mtd: spi-nor: add rockchip serial flash controller driver

Hi Andy, Am Sonntag, 8. April 2018, 14:08:45 CEST schrieb Andy Yan: > ping We're in the middle of the merge-window right now, so I do guess maintainers will possibly do other things than looking at new code. But you might want to address the kbuild-robot issue and resend in the meantime, as

Re: [PATCH v8 07/14] ARM: dts: rockchip: add clocks in iommu nodes

Am Freitag, 23. März 2018, 08:38:07 CEST schrieb Jeffy Chen: > Add clocks in iommu nodes, since we are going to control clocks in > rockchip iommu driver. > > Signed-off-by: Jeffy Chen applied for 4.18 after splitting arm32+arm64 parts into 2 patches and adapting the

Re: [PATCH v8 07/14] ARM: dts: rockchip: add clocks in iommu nodes

Am Freitag, 23. März 2018, 08:38:07 CEST schrieb Jeffy Chen: > Add clocks in iommu nodes, since we are going to control clocks in > rockchip iommu driver. > > Signed-off-by: Jeffy Chen applied for 4.18 after splitting arm32+arm64 parts into 2 patches and adapting the subject for the arm64

Re: [PATCH v8 07/14] ARM: dts: rockchip: add clocks in iommu nodes

Am Montag, 9. April 2018, 23:49:58 CEST schrieb Heiko Stübner: > Am Montag, 9. April 2018, 17:55:40 CEST schrieb Heiko Stübner: > > Am Montag, 9. April 2018, 17:53:01 CEST schrieb Robin Murphy: > > > On 09/04/18 16:44, Heiko Stübner wrote: > > > > Hi Tomeu, > > > > > > > > Am Montag, 9. April

Re: [PATCH v8 07/14] ARM: dts: rockchip: add clocks in iommu nodes

Am Montag, 9. April 2018, 23:49:58 CEST schrieb Heiko Stübner: > Am Montag, 9. April 2018, 17:55:40 CEST schrieb Heiko Stübner: > > Am Montag, 9. April 2018, 17:53:01 CEST schrieb Robin Murphy: > > > On 09/04/18 16:44, Heiko Stübner wrote: > > > > Hi Tomeu, > > > > > > > > Am Montag, 9. April

Re: [PATCH v5 07/36] drm/bridge: analogix_dp: Move enable video into config_video()

Hi Archit, Am Mittwoch, 14. März 2018, 06:59:59 CET schrieb Archit Taneja: > On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote: > > From: Lin Huang > > > > We need to enable video before analogix_dp_is_video_stream_on(), so > > we can get the right video

Re: [PATCH v5 07/36] drm/bridge: analogix_dp: Move enable video into config_video()

Hi Archit, Am Mittwoch, 14. März 2018, 06:59:59 CET schrieb Archit Taneja: > On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote: > > From: Lin Huang > > > > We need to enable video before analogix_dp_is_video_stream_on(), so > > we can get the right video stream status. > > > >

Re: [PATCH v3 6/6] drm/rockchip: cdn-dp: remove the DP phy switch

Am Freitag, 16. Februar 2018, 13:09:56 CET schrieb Enric Balletbo i Serra: > From: Chris Zhong > > There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence > only one PHY can connect to DP controller at one time, the other should > be disconnected. The

Re: [PATCH v3 6/6] drm/rockchip: cdn-dp: remove the DP phy switch

Am Freitag, 16. Februar 2018, 13:09:56 CET schrieb Enric Balletbo i Serra: > From: Chris Zhong > > There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence > only one PHY can connect to DP controller at one time, the other should > be disconnected. The GRF_SOC_CON26 register has a

Re: [PATCH] ARM: dts: rockchip: fix uart4 pin-num for rk3288

Am Donnerstag, 15. März 2018, 08:17:14 CET schrieb Jacob Chen: > According to TRM, uart4 tx/rx should be 14/15 > > Signed-off-by: Jacob Chen applied for 4.17 (but may move to 4.18 depending on timing) Thanks Heiko

Re: [PATCH] ARM: dts: rockchip: fix uart4 pin-num for rk3288

Am Donnerstag, 15. März 2018, 08:17:14 CET schrieb Jacob Chen: > According to TRM, uart4 tx/rx should be 14/15 > > Signed-off-by: Jacob Chen applied for 4.17 (but may move to 4.18 depending on timing) Thanks Heiko

Re: [PATCH v2 6/6] arm64: dts: rockchip: enable typec-phy0 for rk3399-puma-haikou.

Am Donnerstag, 1. März 2018, 16:25:15 CET schrieb Enric Balletbo i Serra: > Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port > support for rk3399") caused a regression regarding the USB3. During > boot, the following message appears a few times: > > dwc3: failed to

Re: [PATCH v2 6/6] arm64: dts: rockchip: enable typec-phy0 for rk3399-puma-haikou.

Am Donnerstag, 1. März 2018, 16:25:15 CET schrieb Enric Balletbo i Serra: > Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port > support for rk3399") caused a regression regarding the USB3. During > boot, the following message appears a few times: > > dwc3: failed to

Re: [PATCH v2 5/6] arm64: dts: rockchip: enable typec-phy1 for rk3399-puma.

Am Donnerstag, 1. März 2018, 16:25:14 CET schrieb Enric Balletbo i Serra: > Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port > support for rk3399") caused a regression regarding the USB3. During boot, > the following message appears a few times: > > dwc3: failed to

Re: [PATCH v2 5/6] arm64: dts: rockchip: enable typec-phy1 for rk3399-puma.

Am Donnerstag, 1. März 2018, 16:25:14 CET schrieb Enric Balletbo i Serra: > Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port > support for rk3399") caused a regression regarding the USB3. During boot, > the following message appears a few times: > > dwc3: failed to

Re: [PATCH v2 3/6] arm64: dts: rockchip: enable typec-phy for rk3399-sapphire.

Am Donnerstag, 1. März 2018, 16:25:12 CET schrieb Enric Balletbo i Serra: > Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port > support for rk3399") caused a regression regarding the USB3 type-A port. > During boot, the following message appears a few times: > > dwc3: failed

Re: [PATCH v2 3/6] arm64: dts: rockchip: enable typec-phy for rk3399-sapphire.

Am Donnerstag, 1. März 2018, 16:25:12 CET schrieb Enric Balletbo i Serra: > Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port > support for rk3399") caused a regression regarding the USB3 type-A port. > During boot, the following message appears a few times: > > dwc3: failed

Re: [PATCH v2 4/6] arm64: dts: rockchip: enable typec-phy for rk3399-firefly.

Am Donnerstag, 1. März 2018, 16:25:13 CET schrieb Enric Balletbo i Serra: > Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port > support for rk3399") caused a regression regarding the USB3. During boot, > the following message appears a few times: > > dwc3: failed to

Re: [PATCH v2 4/6] arm64: dts: rockchip: enable typec-phy for rk3399-firefly.

Am Donnerstag, 1. März 2018, 16:25:13 CET schrieb Enric Balletbo i Serra: > Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port > support for rk3399") caused a regression regarding the USB3. During boot, > the following message appears a few times: > > dwc3: failed to

Re: [PATCH] clk: rockchip: Add 1.6GHz PLL rate

Am Dienstag, 13. März 2018, 21:37:19 CET schrieb Derek Basehore: > We need this rate to generate 100, 200, and 228.57MHz from the same > PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for > and external display. > > Signed-off-by: Derek Basehore applied

Re: [PATCH] clk: rockchip: Add 1.6GHz PLL rate

Am Dienstag, 13. März 2018, 21:37:19 CET schrieb Derek Basehore: > We need this rate to generate 100, 200, and 228.57MHz from the same > PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for > and external display. > > Signed-off-by: Derek Basehore applied for 4.17 Thanks Heiko

Re: [PATCH] arm64: dts: rockchip: assign clock rate for ACLK_VIO

Am Montag, 12. März 2018, 02:50:48 CET schrieb Shunqian Zheng: > The ACLK_VIO is a parent clock used by a several children, > its suggested clock rate is 400MHz. Right now it gets 400MHz > because it sources from CPLL(800M) and divides by 2 after reset. > It's good not to rely on default values

Re: [PATCH] arm64: dts: rockchip: assign clock rate for ACLK_VIO

Am Montag, 12. März 2018, 02:50:48 CET schrieb Shunqian Zheng: > The ACLK_VIO is a parent clock used by a several children, > its suggested clock rate is 400MHz. Right now it gets 400MHz > because it sources from CPLL(800M) and divides by 2 after reset. > It's good not to rely on default values

Re: [PATCH v5 4/4] ARM: rockchip: Set name of regmap_config

Am Montag, 12. März 2018, 10:51:42 CET schrieb Jeffy Chen: > We are now allowing to register debugfs without a valid device, and not > having a valid name will end up using "dummy*" to create debugfs dir. > > Signed-off-by: Jeffy Chen applied for 4.17 Thanks Heiko

Re: [PATCH v5 4/4] ARM: rockchip: Set name of regmap_config

Am Montag, 12. März 2018, 10:51:42 CET schrieb Jeffy Chen: > We are now allowing to register debugfs without a valid device, and not > having a valid name will end up using "dummy*" to create debugfs dir. > > Signed-off-by: Jeffy Chen applied for 4.17 Thanks Heiko

Re: [PATCH v4 03/38] drm/bridge: analogix_dp: detect Sink PSR state after configuring the PSR

Hi Enric, Am Montag, 5. März 2018, 23:22:55 CET schrieb Enric Balletbo i Serra: > From: Yakir Yang > > Make sure the request PSR state takes effect in analogix_dp_send_psr_spd() > function, or print the sink PSR error state if we failed to apply the > requested PSR setting.

Re: [PATCH v4 03/38] drm/bridge: analogix_dp: detect Sink PSR state after configuring the PSR

Hi Enric, Am Montag, 5. März 2018, 23:22:55 CET schrieb Enric Balletbo i Serra: > From: Yakir Yang > > Make sure the request PSR state takes effect in analogix_dp_send_psr_spd() > function, or print the sink PSR error state if we failed to apply the > requested PSR setting. > > Cc: 征增 王 > Cc:

Re: [PATCH v4 01/38] drm/bridge: analogix_dp: set psr activate/deactivate when enable/disable bridge

Am Montag, 5. März 2018, 23:22:53 CET schrieb Enric Balletbo i Serra: > From: zain wang > > There's a race between when bridge_disable and when vop_crtc_disable > are called. If the flush timer triggers a new psr work between these, > we will operate eDP without power

Re: [PATCH v4 02/38] drm/rockchip: Don't use atomic constructs for psr

Am Montag, 5. März 2018, 23:22:54 CET schrieb Enric Balletbo i Serra: > From: Sean Paul > > Instead of using timer and spinlocks, use delayed_work and > mutexes for rockchip psr. This allows us to make blocking > calls when enabling/disabling psr (which is sort of

Re: [PATCH v4 02/38] drm/rockchip: Don't use atomic constructs for psr

Am Montag, 5. März 2018, 23:22:54 CET schrieb Enric Balletbo i Serra: > From: Sean Paul > > Instead of using timer and spinlocks, use delayed_work and > mutexes for rockchip psr. This allows us to make blocking > calls when enabling/disabling psr (which is sort of important > given we're talking

Re: [PATCH v4 01/38] drm/bridge: analogix_dp: set psr activate/deactivate when enable/disable bridge

Am Montag, 5. März 2018, 23:22:53 CET schrieb Enric Balletbo i Serra: > From: zain wang > > There's a race between when bridge_disable and when vop_crtc_disable > are called. If the flush timer triggers a new psr work between these, > we will operate eDP without power shutdowned by

Re: [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing

Hi Daniel, Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: > The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. > Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. > > Signed-off-by: Daniel Schultz > --- > > The

Re: [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing

Hi Daniel, Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: > The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. > Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. > > Signed-off-by: Daniel Schultz > --- > > The binding will be added

Re: [PATCH] soc: rockchip: power-domain: use clk_bulk APIs

Hi Jeffy, Am Mittwoch, 28. Februar 2018, 13:41:43 CET schrieb Jeffy Chen: > Use clk_bulk APIs, and also add error handling for clk enable. > > Signed-off-by: Jeffy Chen [...] > - for (i = 0; i < clk_cnt; i++) { > - clk = of_clk_get(node, i); > -

Re: [PATCH] soc: rockchip: power-domain: use clk_bulk APIs

Hi Jeffy, Am Mittwoch, 28. Februar 2018, 13:41:43 CET schrieb Jeffy Chen: > Use clk_bulk APIs, and also add error handling for clk enable. > > Signed-off-by: Jeffy Chen [...] > - for (i = 0; i < clk_cnt; i++) { > - clk = of_clk_get(node, i); > - if (IS_ERR(clk)) {

Re: [PATCH v8 4/8] drm/rockchip: dw-mipi-dsi: Fix error handling path

Hi Enric, Am Freitag, 2. März 2018, 13:09:02 CET schrieb Enric Balletbo i Serra: > Hi Heiko, > > On 01/03/18 16:50, Heiko Stübner wrote: > > Hi Jeffy, Thierry, Enric, > > > > Am Mittwoch, 10. Januar 2018, 17:23:44 CET schrieb Thierry Escande: > >> From: Jeffy Chen >

Re: [PATCH v8 4/8] drm/rockchip: dw-mipi-dsi: Fix error handling path

Hi Enric, Am Freitag, 2. März 2018, 13:09:02 CET schrieb Enric Balletbo i Serra: > Hi Heiko, > > On 01/03/18 16:50, Heiko Stübner wrote: > > Hi Jeffy, Thierry, Enric, > > > > Am Mittwoch, 10. Januar 2018, 17:23:44 CET schrieb Thierry Escande: > >> From: Jeffy Chen > >> > >> Add missing

Re: [PATCH v3 3/5] arm64: dts: rockchip: add usb3-phy otg-port support for rk3399.

Am Samstag, 16. Dezember 2017, 18:06:50 CET schrieb Heiko Stuebner: > Am Freitag, 15. Dezember 2017, 12:00:03 CET schrieb Enric Balletbo i Serra: > > Add the usb3 phyter for the USB3.0 OTG controller. > > > > Signed-off-by: Enric Balletbo i Serra <enric.balle...@col

Re: [PATCH v3 3/5] arm64: dts: rockchip: add usb3-phy otg-port support for rk3399.

Am Samstag, 16. Dezember 2017, 18:06:50 CET schrieb Heiko Stuebner: > Am Freitag, 15. Dezember 2017, 12:00:03 CET schrieb Enric Balletbo i Serra: > > Add the usb3 phyter for the USB3.0 OTG controller. > > > > Signed-off-by: Enric Balletbo i Serra > > applied f

[PATCH] drm/rockchip: analogix_dp: reorder psr_unregister call in unbind

scande <thierry.esca...@collabora.com> Signed-off-by: Heiko Stuebner <he...@sntech.de> --- drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/ro

[PATCH] drm/rockchip: analogix_dp: reorder psr_unregister call in unbind

In bind the psr handler gets registered first before the core analogix_dp_bind() gets called. So it should be the other way around in unbind, first unbind the analogix_dp and then unregister the psr. Signed-off-by: Jeffy Chen Signed-off-by: Thierry Escande Signed-off-by: Heiko Stuebner

Re: [PATCH V2 1/2] [media] Add Rockchip RK1608 driver

Hi Leo, Am Dienstag, 27. Februar 2018, 04:15:46 CET schrieb 温暖: > Thank you for your advice! I will revise it according to your suggestion. please also keep an eye on my reply to Linus' mail pointing out some other issues where the driver should not tie into soc-specific areas like the clock

Re: [PATCH V2 1/2] [media] Add Rockchip RK1608 driver

Hi Leo, Am Dienstag, 27. Februar 2018, 04:15:46 CET schrieb 温暖: > Thank you for your advice! I will revise it according to your suggestion. please also keep an eye on my reply to Linus' mail pointing out some other issues where the driver should not tie into soc-specific areas like the clock

Re: [PATCH V2 1/2] [media] Add Rockchip RK1608 driver

Hi Linus, thanks for catching these things :-) . Am Montag, 26. Februar 2018, 11:12:30 CET schrieb Linus Walleij: > On Mon, Feb 26, 2018 at 9:16 AM, Wen Nuan wrote: > > + pdata->grf_gpio2b_iomux = ioremap((resource_size_t) > > +

Re: [PATCH V2 1/2] [media] Add Rockchip RK1608 driver

Hi Linus, thanks for catching these things :-) . Am Montag, 26. Februar 2018, 11:12:30 CET schrieb Linus Walleij: > On Mon, Feb 26, 2018 at 9:16 AM, Wen Nuan wrote: > > + pdata->grf_gpio2b_iomux = ioremap((resource_size_t) > > +

Re: [PATCH fixes v3] pinctrl: Really force states during suspend/resume

Am Montag, 19. Februar 2018, 19:03:27 CET schrieb Florian Fainelli: > On February 19, 2018 9:25:26 AM PST, Marc Zyngier > wrote: > >Hi all, > > > >On 2017-03-01 18:32, Florian Fainelli wrote: > >> In case a platform only defaults a "default" set of pins, but not a > >>

Re: [PATCH fixes v3] pinctrl: Really force states during suspend/resume

Am Montag, 19. Februar 2018, 19:03:27 CET schrieb Florian Fainelli: > On February 19, 2018 9:25:26 AM PST, Marc Zyngier > wrote: > >Hi all, > > > >On 2017-03-01 18:32, Florian Fainelli wrote: > >> In case a platform only defaults a "default" set of pins, but not a > >> "sleep" set of pins, and

Re: [RESEND PATCH v5 2/5] dt-bindings: pwm-backlight: add PWM delay proprieties.

Hi Lee, Am Montag, 19. Februar 2018, 10:22:47 CET schrieb Lee Jones: > On Fri, 16 Feb 2018, Enric Balletbo i Serra wrote: > > > Hardware needs a delay between setting an initial (non-zero) PWM and > > enabling the backlight using GPIO. The post-pwm-on-delay-ms specifies > > this delay in milli

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