From: Jon Hunter
Date: Jul/24/2019, 12:10:47 (UTC+00:00)
>
> On 24/07/2019 11:04, Jose Abreu wrote:
>
> ...
>
> > Jon, I was able to replicate (at some level) your setup:
> >
> > # dmesg | grep -i arm-smmu
> > [1.337322] arm-smmu 7004.iom
From: Ilias Apalodimas
Date: Jul/24/2019, 10:53:10 (UTC+00:00)
> Jose,
> > From: Ilias Apalodimas
> > Date: Jul/24/2019, 09:54:27 (UTC+00:00)
> >
> > > Hi David,
> > >
> > > > From: Jon Hunter
> > > > Date: Tue, 23 Jul 2019 13:09:00 +0100
> > > >
> > > > > Setting "iommu.passthrough=1"
From: Ilias Apalodimas
Date: Jul/24/2019, 09:54:27 (UTC+00:00)
> Hi David,
>
> > From: Jon Hunter
> > Date: Tue, 23 Jul 2019 13:09:00 +0100
> >
> > > Setting "iommu.passthrough=1" works for me. However, I am not sure where
> > > to go from here, so any ideas you have would be great.
> >
> >
From: Jon Hunter
Date: Jul/23/2019, 12:58:55 (UTC+00:00)
>
> On 23/07/2019 11:49, Jose Abreu wrote:
> > From: Jon Hunter
> > Date: Jul/23/2019, 11:38:33 (UTC+00:00)
> >
> >>
> >> On 23/07/2019 11:07, Jose Abreu wrote:
> >>> From: Jo
From: Robin Murphy
Date: Jul/23/2019, 11:29:28 (UTC+00:00)
> On 23/07/2019 11:07, Jose Abreu wrote:
> > From: Jon Hunter
> > Date: Jul/23/2019, 11:01:24 (UTC+00:00)
> >
> >> This appears to be a winner and by disabling the SMMU for the ethernet
> &
From: Jon Hunter
Date: Jul/23/2019, 11:38:33 (UTC+00:00)
>
> On 23/07/2019 11:07, Jose Abreu wrote:
> > From: Jon Hunter
> > Date: Jul/23/2019, 11:01:24 (UTC+00:00)
> >
> >> This appears to be a winner and by disabling the SMMU for the ethernet
>
From: Jon Hunter
Date: Jul/23/2019, 11:01:24 (UTC+00:00)
> This appears to be a winner and by disabling the SMMU for the ethernet
> controller and reverting commit 954a03be033c7cef80ddc232e7cbdb17df735663
> this worked! So yes appears to be related to the SMMU being enabled. We
> had to enable
From: Ondřej Jirman
Date: Jul/22/2019, 15:39:55 (UTC+00:00)
> On Mon, Jul 22, 2019 at 02:26:45PM +0000, Jose Abreu wrote:
> > From: Andrew Lunn
> > Date: Jul/22/2019, 15:19:43 (UTC+00:00)
> >
> > > On Mon, Jul 22, 2019 at 01:58:20PM +, Jose Abreu wr
From: Jose Abreu
Date: Jul/22/2019, 15:04:49 (UTC+00:00)
> From: Jon Hunter
> Date: Jul/22/2019, 13:05:38 (UTC+00:00)
>
> >
> > On 22/07/2019 12:39, Jose Abreu wrote:
> > > From: Lars Persson
> > > Date: Jul/22/2019, 12:11:50 (UTC+00:00)
> > >
From: Andrew Lunn
Date: Jul/22/2019, 15:19:43 (UTC+00:00)
> On Mon, Jul 22, 2019 at 01:58:20PM +0000, Jose Abreu wrote:
> > From: Andrew Lunn
> > Date: Jul/22/2019, 14:40:23 (UTC+00:00)
> >
> > > Does this mean that all stmmac variants support 1G? There are none
Some glue logic drivers support 1G without having GMAC/GMAC4/XGMAC.
Let's allow this speed by default.
Reported-by: Ondrej Jirman
Tested-by: Ondrej Jirman
Fixes: 5b0d7d7da64b ("net: stmmac: Add the missing speeds that XGMAC supports")
Signed-off-by: Jose Abreu
---
Cc: Giuseppe Cav
From: Jon Hunter
Date: Jul/22/2019, 13:05:38 (UTC+00:00)
>
> On 22/07/2019 12:39, Jose Abreu wrote:
> > From: Lars Persson
> > Date: Jul/22/2019, 12:11:50 (UTC+00:00)
> >
> >> On Mon, Jul 22, 2019 at 12:18 PM Ilias Apalodimas
> >> wrote:
> >&
From: Andrew Lunn
Date: Jul/22/2019, 14:40:23 (UTC+00:00)
> Does this mean that all stmmac variants support 1G? There are none
> which just support Fast Ethernet?
This glue logic drivers sometimes reflect a custom IP that's Synopsys
based but modified by customer, so I can't know before-hand
From: Ondřej Jirman
Date: Jul/22/2019, 13:42:40 (UTC+00:00)
> Hello Jose,
>
> On Tue, Jun 11, 2019 at 05:18:44PM +0200, Jose Abreu wrote:
> > [ Hope this diff looks better (generated with --minimal) ]
> >
> > This converts stmmac to use phylink. Besides the code r
From: Lars Persson
Date: Jul/22/2019, 12:11:50 (UTC+00:00)
> On Mon, Jul 22, 2019 at 12:18 PM Ilias Apalodimas
> wrote:
> >
> > On Thu, Jul 18, 2019 at 07:48:04AM +, Jose Abreu wrote:
> > > From: Jon Hunter
> > > Date: Jul/17/2019, 19:58:53 (UTC+00:00)
&
From: Jose Abreu
Date: Jul/22/2019, 10:47:44 (UTC+00:00)
> From: Jon Hunter
> Date: Jul/22/2019, 10:37:18 (UTC+00:00)
>
> >
> > On 22/07/2019 08:23, Jose Abreu wrote:
> > > From: Jon Hunter
> > > Date: Jul/19/2019, 14:35:52 (UTC+00:00)
> > >
From: Jon Hunter
Date: Jul/22/2019, 10:37:18 (UTC+00:00)
>
> On 22/07/2019 08:23, Jose Abreu wrote:
> > From: Jon Hunter
> > Date: Jul/19/2019, 14:35:52 (UTC+00:00)
> >
> >>
> >> On 19/07/2019 13:32, Jose Abreu wrote:
> >>> From: Jo
RX Descriptors are being cleaned after setting the buffers which may
lead to buffer addresses being wiped out.
Fix this by clearing earlier the RX Descriptors.
Fixes: 2af6106ae949 ("net: stmmac: Introducing support for Page Pool")
Signed-off-by: Jose Abreu
---
Cc: Giuseppe Cav
We need the memory to be zeroed upon allocation so use kcalloc()
instead.
Signed-off-by: Jose Abreu
---
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Jose Abreu
Cc: "David S. Miller"
Cc: Maxime Coquelin
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc:
Two fixes targeting -net.
---
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Jose Abreu
Cc: "David S. Miller"
Cc: Maxime Coquelin
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
From: Jon Hunter
Date: Jul/19/2019, 14:35:52 (UTC+00:00)
>
> On 19/07/2019 13:32, Jose Abreu wrote:
> > From: Jon Hunter
> > Date: Jul/19/2019, 13:30:10 (UTC+00:00)
> >
> >> I booted the board without using NFS and then started used dhclient to
&g
From: Jon Hunter
Date: Jul/19/2019, 13:30:10 (UTC+00:00)
> I booted the board without using NFS and then started used dhclient to
> bring up the network interface and it appears to be working fine. I can
> even mount the NFS share fine. So it does appear to be particular to
> using NFS to mount
From: Jose Abreu
Date: Jul/19/2019, 11:25:41 (UTC+00:00)
> Thanks. Can you add attached patch and check if WARN is triggered ?
BTW, also add the attached one in this mail. The WARN will probably
never get triggered without it.
Can you also print "buf->addr" after the WARN_
From: Jon Hunter
Date: Jul/19/2019, 09:49:10 (UTC+00:00)
>
> On 19/07/2019 09:44, Jose Abreu wrote:
> > From: Jon Hunter
> > Date: Jul/19/2019, 09:37:49 (UTC+00:00)
> >
> >>
> >> On 19/07/2019 08:51, Jose Abreu wrote:
> >>> From: Jo
From: Jon Hunter
Date: Jul/19/2019, 09:37:49 (UTC+00:00)
>
> On 19/07/2019 08:51, Jose Abreu wrote:
> > From: Jon Hunter
> > Date: Jul/18/2019, 10:16:20 (UTC+00:00)
> >
> >> Have you tried using NFS on a board with this ethernet controller?
> >
> &
From: Jon Hunter
Date: Jul/18/2019, 10:16:20 (UTC+00:00)
> Have you tried using NFS on a board with this ethernet controller?
I'm having some issues setting up the NFS server in order to replicate
so this may take some time.
Are you able to add some debug in stmmac_init_rx_buffers() to see
From: Jon Hunter
Date: Jul/17/2019, 19:58:53 (UTC+00:00)
> Let me know if you have any thoughts.
Can you try attached patch ?
---
Thanks,
Jose Miguel Abreu
0001-net-stmmac-RX-Descriptors-need-to-be-clean-before-se.patch
Description:
From: Jon Hunter
Date: Jul/17/2019, 19:58:53 (UTC+00:00)
> I am seeing a boot regression on one of our Tegra boards with both
> mainline and -next. Bisecting is pointing to this commit and reverting
> this commit on top of mainline fixes the problem. Unfortunately, there
> is not much of a
From: Joe Perches
Date: Jul/10/2019, 06:04:21 (UTC+00:00)
> Arguments are supposed to be ordered high then low.
>
> Signed-off-by: Joe Perches
If you submit another version please add:
Fixes: 293e4365a1ad ("stmmac: change descriptor layout")
Fixes: 9f93ac8d4085 ("net-next: stmmac: Add
set lower and upper value of descriptors address when initializing DMA
channels.
Luckly, this was working for me because I was assigning CMA to < 4GB
address space for performance reasons.
Fixes: a993db88d17d ("net: stmmac: Enable support for > 32 Bits addressing in
XGMAC")
Signed-of
Add support for coalescing RX path by specifying number of frames which
don't need to have interrupt on completion bit set.
This is only available when RX Watchdog is enabled.
Acked-by: Jakub Kicinski
Signed-off-by: Jose Abreu
---
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Jose Abreu
Some performace improvements (01/03 and 03/03) and a fix (02/03), all for -next.
---
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Jose Abreu
Cc: "David S. Miller"
Cc: Maxime Coquelin
Cc: Maxime Ripard
Cc: Chen-Yu Tsai
Cc: net...@vger.kernel.org
Cc: linux-s
)
- Reintroduce sync_single_for_device (Arnd / Ilias)
Signed-off-by: Jose Abreu
Acked-by: Ilias Apalodimas
---
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Jose Abreu
Cc: "David S. Miller"
Cc: Maxime Coquelin
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stor
From: Ilias Apalodimas | Date: Tue, Jul 09, 2019
at 08:23:56
> The patch from Ivan did get merged, can you change the free call to
> page_pool_destroy and re-spin? You can add my acked-by
Yes, I will re-spin then. Thanks!
---
Thanks,
Jose Miguel Abreu
From: Ilias Apalodimas | Date: Fri, Jul
05, 2019 at 16:24:53
> Well ideally we'd like to get the change in before the merge window ourselves,
> since we dont want to remove->re-add the same function in stable kernels. If
> that doesn't go in i am fine fixing it in the next merge window i guess,
hould be reverted upstream and in all
stable branches. Instead, the driver should implement the
ndo_select_queue operation and override the queue mapping there."
Fixes: c5acdbee22a1 ("net: stmmac: Send TSO packets always from Queue 0")
Suggested-by: Ben Hutchings
Signe
From: Ilias Apalodimas
> I think this look ok for now. One request though, on page_pool_free
Thanks for the review!
> A patch currently under review will slightly change that [1] and [2]
> Can you defer this a bit till that one gets merged?
> The only thing you'll have to do is respin this
set lower and upper value of descriptors address when initializing DMA
channels.
Luckly, this was working for me because I was assigning CMA to < 4GB
address space for performance reasons.
Fixes: a993db88d17d ("net: stmmac: Enable support for > 32 Bits addressing in
XGMAC")
Signed-off
Some performace improvements (01/03 and 03/03) and a fix (02/03), all for -next.
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Jose Abreu (3):
net: stmmac: Implement RX Coalesce Frames setting
net: stmmac: Fix descriptors address being in > 32 b
Add support for coalescing RX path by specifying number of frames which
don't need to have interrupt on completion bit set.
This is only available when RX Watchdog is enabled.
Acked-by: Jakub Kicinski
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc
/ Ilias)
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Ilias Apalodimas
Cc: Jesper Dangaard Brouer
Cc: Arnd Bergmann
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
drivers/net/ethernet/stmicro/stmmac/stmmac.h
From: Jesper Dangaard Brouer
> This code is okay, but I would likely write it as:
>
> if (rx_q->page_pool) {
> page_pool_request_shutdown(rx_q->page_pool));
> page_pool_free(rx_q->page_pool);
> }
>
> Because (as you noticed) page_pool_free() have some API misuse checks,
> that
From: Andrew Lunn
> Yes, that is all clear. The stmmac_mdio_c45_setup() does part of this
> setup. There is also a write to mii_address which i snipped out when
> replying. But why do you need to write to the data registers during a
> read? C22 does not need this write. Are there some bits in
From: Jesper Dangaard Brouer
> You can just use page_pool_free() (p.s I'm working on reintroducing
> page_pool_destroy wrapper). As you say, you will not have in-flight
> frames/pages in this driver use-case.
Well, if I remove the request_shutdown() it will trigger the "API usage
violation"
- XGMAC: 9.22 Gbps
Changes from v1:
- Use page_pool_get_dma_addr() (Jesper)
- Add a comment (Jesper)
- Add page_pool_free() call (Jesper)
- Reintroduce sync_single_for_device (Arnd / Ilias)
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc
Some performace improvements (01/03 and 03/03) and a fix (02/03), all for -next.
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Jose Abreu (3):
net: stmmac: Implement RX Coalesce Frames setting
net: stmmac: Fix descriptors address being in > 32 b
Add support for coalescing RX path by specifying number of frames which
don't need to have interrupt on completion bit set.
This is only available when RX Watchdog is enabled.
Acked-by: Jakub Kicinski
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc
set lower and upper value of descriptors address when initializing DMA
channels.
Luckly, this was working for me because I was assigning CMA to < 4GB
address space for performance reasons.
Fixes: a993db88d17d ("net: stmmac: Enable support for > 32 Bits addressing in
XGMAC")
Signed-off
From: Jesper Dangaard Brouer
> The page_pool_request_shutdown() API return indication if there are any
> in-flight frames/pages, to know when it is safe to call
> page_pool_free(), which you are also missing a call to.
>
> This page_pool_request_shutdown() is only intended to be called from
>
Thank you all for your review comments !
From: Ilias Apalodimas
> That's why i was concerned on what will happen on > 1000b frames and what the
> memory pressure is going to be.
> The trade off here is copying vs mapping/unmapping.
Well, the performance numbers I mentioned are for TSO with
From: Jesper Dangaard Brouer
> The page_pool DMA mapping cannot be "kept" when page traveling into the
> network stack attached to an SKB. (Ilias and I have a long term plan[1]
> to allow this, but you cannot do it ATM).
The reason I recycle the page is this previous call to:
++ Jesper: Who is most active committer of page pool API (?) ... Can you
please help review this ?
From: Jose Abreu
> Mapping and unmapping DMA region is an high bottleneck in stmmac driver,
> specially in the RX path.
>
> This commit introduces support for Page Pool API and uses
- XGMAC: 9.22 Gbps
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Maxime Coquelin
Cc: Maxime Ripard
Cc: Chen-Yu Tsai
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
drivers/net/ethernet/stmicro/stmmac
Some performace improvements (01/03 and 03/03) and a fix (02/03), all for -next.
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Maxime Coquelin
Cc: Maxime Ripard
Cc: Chen-Yu Tsai
Jose Abreu (3):
net: stmmac: Implement RX Coalesce Frames setting
net
set lower and upper value of descriptors address when initializing DMA
channels.
Luckly, this was working for me because I was assigning CMA to < 4GB
address space for performance reasons.
Fixes: a993db88d17d ("net: stmmac: Enable support for > 32 Bits addressing in
XGMAC")
Signed-off
Add support for coalescing RX path by specifying number of frames which
don't need to have interrupt on completion bit set.
This is only available when RX Watchdog is enabled.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Maxime
We support many speeds and it doesn't make much sense to list them all
in the Kconfig. Let's just call it Multi-Gigabit.
Suggested-by: David S. Miller
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro
From: David Miller
> About the Kconfig change, maybe it just doesn't make sense to list all
> of the various speeds the chip supports... just a thought.
What about: "STMicroelectronics Multi-Gigabit Ethernet driver" ?
Or, just "STMicroelectronics Ethernet driver" ?
From: Willem de Bruijn
> By the
>
> if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
> stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
> napi_schedule_irqoff(>rx_napi);
> }
>
> branch directly above? If so, is it possible to
Do not enable EEE feature in the PHY if MAC does not support it.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Only disable the interrupts if RX NAPI gets to be scheduled. Also,
schedule the TX NAPI only when the interrupts are disabled.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 10
Update the RX Tail Pointer to the last available SKB entry.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net
Currently, stmmac only supports 32 bits addressing for SKB. Enable the
support for upto 48 bits addressing in XGMAC core.
This avoids the use of bounce buffers and increases performance.
Changes from v1:
- Fallback to 32 bits in failure (Andrew)
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Enable the EDMA feature by default which gives higher performance.
Changes from v1:
- Do not use magic values (David)
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 4
We support more speeds now. Update the Kconfig entry.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net
Undefined burst shall only be set if pdata asks to.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
This is a performance killer and anyways the interrupts are being
disabled by RX NAPI so no need to disable them again.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 8
XGMAC supports following speeds:
- 10G XGMII
- 5G XGMII
- 2.5G XGMII
- 2.5G GMII
- 1G GMII
- 100M MII
- 10M MII
Add them to the stmmac driver.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc
] 0.00-600.00 sec 643 GBytes 9.21 Gbits/sec1 sender
[ 5] 0.00-600.00 sec 643 GBytes 9.21 Gbits/sec receiver
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Jose Abreu (10):
net: stmmac: dwxgmac: Enable EDMA by default
For performance reasons decrease the default RX Watchdog value for the
minimum allowed.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/common.h | 2 +-
drivers/net/ethernet/stmicro/stmmac
From: Andrew Lunn
> On Thu, Jun 27, 2019 at 01:33:59PM +0000, Jose Abreu wrote:
> > From: Andrew Lunn
> >
> > > There have been some drivers gaining patches for ACPI. That is
> > > probably the better long term solution, ask ACPI where is the PHY and
> &
ki
Tested-by: Katsuhiro Suzuki
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Sergei Shtylyov
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/d
From: Andrew Lunn
> There have been some drivers gaining patches for ACPI. That is
> probably the better long term solution, ask ACPI where is the PHY and
> what MDIO protocol to use to talk to it.
Hmmm, I'm not sure this is going to work that way ...
My setup is a PCI EP which is
From: Voon Weifeng
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dw_tsn_lib.c
> b/drivers/net/ethernet/stmicro/stmmac/dw_tsn_lib.c
> new file mode 100644
> index ..cba27c604cb1
> --- /dev/null
> +++ b/drivers/net/ethernet/stmicro/stmmac/dw_tsn_lib.c
XGMAC also supports TSN
From: Andrew Lunn
> > +
> > + if (priv->dma_cap.addr64) {
> > + ret = dma_set_mask_and_coherent(device,
> > + DMA_BIT_MASK(priv->dma_cap.addr64));
> > + if (!ret)
> > + dev_info(priv->device, "Using %d bits DMA width\n",
> > +
From: Andrew Lunn
> On Wed, Jun 26, 2019 at 03:47:44PM +0200, Jose Abreu wrote:
> > On PCI based setups that are connected to C45 PHY we won't have DT
> > bindings specifying what's the correct PHY type.
>
> You can associate a DT node to a PCI device. The driver does not
Update the RX Tail Pointer to the last available SKB entry.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net
On PCI based setups that are connected to C45 PHY we won't have DT
bindings specifying what's the correct PHY type.
Fallback to C45 if everything else fails when trying to acquire PHY.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
This is a performance killer and anyways the interrupts are being
disabled by RX NAPI so no need to disable them again.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 8
Undefined burst shall only be set if pdata asks to.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Do not enable EEE feature in the PHY if MAC does not support it.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Enable the EDMA feature by default which gives higher performance.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 ++
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 2
] 0.00-600.00 sec 643 GBytes 9.21 Gbits/sec1 sender
[ 5] 0.00-600.00 sec 643 GBytes 9.21 Gbits/sec receiver
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Jose Abreu (10):
net: stmmac: dwxgmac: Enable EDMA by default
Currently, stmmac only supports 32 bits addressing for SKB. Enable the
support for upto 48 bits addressing in XGMAC core.
This avoids the use of bounce buffers and increases performance.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
For performance reasons decrease the default RX Watchdog value for the
minimum allowed.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/common.h | 2 +-
drivers/net/ethernet/stmicro/stmmac
Only disable the interrupts if RX NAPI gets to be scheduled. Also,
schedule the TX NAPI only when the interrupts are disabled.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 10
XGMAC supports following speeds:
- 10G XGMII
- 5G XGMII
- 2.5G XGMII
- 2.5G GMII
- 1G GMII
- 100M MII
- 10M MII
Add them to the stmmac driver.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc
++ Katsuhiro
From: Jose Abreu
> Some DT bindings do not have the PHY handle. Let's fallback to manually
> discovery in case phylink_of_phy_connect() fails.
>
> Reported-by: Katsuhiro Suzuki
> Fixes: 74371272f97f ("net: stmmac: Convert to phylink and remove phylib
&g
From: Jon Hunter
> I have been looking at this a bit closer and I can see the problem. What
> happens is that ...
>
> 1. stmmac_mac_link_up() is called and priv->eee_active is set to false
> 2. stmmac_eee_init() is called but because priv->eee_active is false,
>timer_setup() for
Some DT bindings do not have the PHY handle. Let's fallback to manually
discovery in case phylink_of_phy_connect() fails.
Reported-by: Katsuhiro Suzuki
Fixes: 74371272f97f ("net: stmmac: Convert to phylink and remove phylib logic")
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David
From: Katsuhiro Suzuki
> I checked drivers/net/ethernet/stmicro/stmmac/stmmac_main.c and found
> stmmac_init_phy() is going to fail if ethernet device node does not
> have following property:
>- phy-handle
>- phy
>- phy-device
>
> This commit broke the device-trees such as
From: Jon Hunter
> Any further feedback? I am still seeing this issue on today's -next.
Apologies but I was in FTO.
Is there any possibility you can just disable the ethX configuration in
the rootfs mount and manually configure it after rootfs is done ?
I just want to make sure in which
From: Jon Hunter
> I am not certain but I don't believe so. We are using a static IP address
> and mounting the root file-system via NFS when we see this ...
Can you please add a call to napi_synchronize() before every
napi_disable() calls, like this:
if (queue < rx_queues_cnt) {
From: Jon Hunter
> I am seeing a boot regression on -next for some of our boards that have
> a synopsys ethernet controller that uses the dwmac-dwc-qos-ethernet
> driver. Git bisect is pointing to this commit, but unfortunately this
> cannot be cleanly reverted on top of -next to confirm.
Labbe
Fixes: 74371272f97f ("net: stmmac: Convert to phylink and remove phylib logic")
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 ++--
drivers/net/ethernet/stmi
From: Corentin Labbe
> since this patch I hit
> dwmac-sun8i 1c3.ethernet: ethernet@1c3 PHY address 29556736 is too
> large
>
> any idea ?
This is because phy_node is no longer pointing to the same place so
sun8i_dwmac_set_syscon() fails.
I'm seeing this pattern of using phy_node in
From: Russell King - ARM Linux admin
> If this is not used, I don't really see the point of splitting this from
> the rest of the patch. Also, I don't see the point of all those NULL
> initialisers either.
Thanks for the feedback. Please see previous discussion here that lead
to the
Start adding the phylink callbacks.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Russell King
Cc: Andrew Lunn
Cc: Florian Fainelli
Cc: Heiner Kallweit
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
drivers/net
Convert everything to phylink.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Russell King
Cc: Andrew Lunn
Cc: Florian Fainelli
Cc: Heiner Kallweit
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 2 -
drivers/net
Fainelli
Cc: Heiner Kallweit
Jose Abreu (3):
net: stmmac: Prepare to convert to phylink
net: stmmac: Start adding phylink support
net: stmmac: Convert to phylink and remove phylib logic
drivers/net/ethernet/stmicro/stmmac/Kconfig | 3 +-
drivers/net/ethernet/stmicro/stmmac/stmmac.h
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