On Sat, Mar 17, 2018 at 01:55:13AM +0100, Niklas Cassel wrote:
> On Fri, Mar 16, 2018 at 06:02:20PM +0000, Lorenzo Pieralisi wrote:
> > On Thu, Mar 08, 2018 at 02:33:26PM +0100, Niklas Cassel wrote:
> > > If a BAR supports 64-bit width or not depends on the hardware,
> &g
On Fri, Mar 16, 2018 at 05:41:27PM +, Dexuan Cui wrote:
> > From: Lorenzo Pieralisi
> > Sent: Friday, March 16, 2018 03:54
> > ...
> > Dexuan,
> > while applying/updating these patches I notice this one may be squashed
> > into: https://patchwork.ozlabs.o
On Thu, Mar 08, 2018 at 02:33:26PM +0100, Niklas Cassel wrote:
> If a BAR supports 64-bit width or not depends on the hardware,
> and should thus not depend on sizeof(dma_addr_t).
>
> Since this driver is generic, default to always using BAR width
> of 32-bits. 64-bit BARs can easily be tested by
On Wed, Jan 03, 2018 at 02:39:04PM +0800, Honghui Zhang wrote:
> On Tue, 2018-01-02 at 10:56 +0000, Lorenzo Pieralisi wrote:
> > On Thu, Dec 28, 2017 at 09:39:12AM +0800, Honghui Zhang wrote:
> > > On Wed, 2017-12-27 at 12:45 -0600, Bjorn Helgaas wrote:
> > > > On W
On Wed, Dec 27, 2017 at 12:45:42PM -0600, Bjorn Helgaas wrote:
[...]
> > + /* Set up class code for MT7622 */
> > + val = PCI_CLASS_BRIDGE_PCI << 16;
> > + writel(val, port->base + PCIE_CONF_CLASS);
>
> 1) Your comments mention MT7622 specifically, but this code is
On Fri, Jan 05, 2018 at 07:51:47PM +0800, Honghui Zhang wrote:
> On Thu, 2018-01-04 at 19:04 +, Marc Zyngier wrote:
> > On 04/01/18 18:40, Lorenzo Pieralisi wrote:
> > > [+Marc]
> > >
> > > On Wed, Dec 27, 2017 at 08:59:53AM +0800, honghui.zh...@mediatek.co
On Thu, Mar 15, 2018 at 02:21:51PM +, Dexuan Cui wrote:
> Since we serialize the present/eject work items now, we don't need the
> semaphore any more.
>
> Signed-off-by: Dexuan Cui
> Reviewed-by: Michael Kelley
> Acked-by: Haiyang Zhang
> Cc: Vitaly Kuznetsov
> Cc: Jack Morgenstein
> Cc:
[CC'ed Gustavo]
On Fri, Mar 09, 2018 at 09:53:24AM +0530, Vignesh R wrote:
>
>
> On Tuesday 06 March 2018 08:42 PM, Lorenzo Pieralisi wrote:
> > On Thu, Feb 15, 2018 at 09:59:21AM +0530, Vignesh R wrote:
> >> Hi,
> >>
> >> On Monday 12 February 2
On Wed, Jan 31, 2018 at 03:41:49PM +0800, Ryder Lee wrote:
> A root complex usually consist of a host bridge and multiple P2P bridges,
> and someone may express that in the form of a root node with many subnodes
> and list all four interrupts for each slot (child node) in the root node
> like this:
On Thu, Mar 15, 2018 at 02:20:53PM +, Dexuan Cui wrote:
> When we hot-remove the device, we first receive a PCI_EJECT message and
> then receive a PCI_BUS_RELATIONS message with bus_rel->device_count == 0.
>
> The first message is offloaded to hv_eject_device_work(), and the second
> is offloa
On Thu, Mar 15, 2018 at 12:03:07AM +, Sridhar Pitchai wrote:
> Whenever PCI bus is added, HyperV guarantees the BUS id is unique. Even
"Whenever a PCI bus is added"
> with that when a first device is added to the bus, it overrides bus domain
> ID with the device serial number. Sometime this c
On Wed, Mar 14, 2018 at 01:13:14PM +0100, Thierry Reding wrote:
> On Wed, Mar 14, 2018 at 01:06:11PM +0100, Arnd Bergmann wrote:
> > On Wed, Mar 14, 2018 at 12:45 PM, Thierry Reding
> > wrote:
> > > On Tue, Mar 13, 2018 at 12:52:05PM +0100, Arnd Bergmann wrote:
> > >> Building the tegra PCIe host
On Tue, Mar 13, 2018 at 06:23:39PM +, Dexuan Cui wrote:
[...]
> Hi Lorenzo, Bjorn, and all,
> Do you need more ACKs? Currently Michael and Haiyang reviewed and ack'd
> the patchset.
>
> Should I send a v4 that just removes the "CC: sta...@vger.kernel.org" tag
> for patches 1, 2, 4 and 5? I
On Wed, Mar 07, 2018 at 09:34:29AM +0100, Julia Lawall wrote:
> From: Fengguang Wu
>
> Remove unneeded semicolon.
>
> Generated by: scripts/coccinelle/misc/semicolon.cocci
>
> Signed-off-by: Fengguang Wu
> Signed-off-by: Julia Lawall
> ---
>
> tree: https://git.kernel.org/pub/scm/linux/ke
On Tue, Mar 13, 2018 at 12:52:05PM +0100, Arnd Bergmann wrote:
> Building the tegra PCIe host driver without MSI results in a link
> failure:
>
> drivers/pci/host/pci-tegra.o:(.data+0x70): undefined reference to
> `pci_msi_unmask_irq'
> drivers/pci/host/pci-tegra.o:(.data+0x74): undefined referen
On Tue, Mar 13, 2018 at 06:23:39PM +, Dexuan Cui wrote:
> > From: Dexuan Cui
> > Sent: Wednesday, March 7, 2018 13:40
> > To: Lorenzo Pieralisi
> > Cc: bhelg...@google.com; linux-...@vger.kernel.org; KY Srinivasan
> > ; Stephen Hemminger ;
> > o...@
Hi Jaehoon,
On Thu, Dec 21, 2017 at 09:14:06PM +0900, Jaehoon Chung wrote:
> PCI_EXYNOS has the dependency with SOC_EXYNOS5440.
> It's modified to ARCH_EXYNOS from SOC_EXYNOS5440, because other
> SoCs needs to use this driver.
>
> Signed-off-by: Jaehoon Chung
> ---
> drivers/pci/dwc/Kconfig | 2
On Fri, Mar 09, 2018 at 05:02:34AM +, Sridhar Pitchai wrote:
> When PCI BUS is added, PCI_BUS domain ID is set. When PCI_BUS and a device
> added to the bus is racing against each other, the first device tends to
> overwrite the domain ID. In order to avoid the race, this patch make sure
> when
On Wed, Feb 28, 2018 at 04:06:13PM -0600, Jeremy Linton wrote:
[...]
> diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
> index 0c6f658054d2..1446d3f053a2 100644
> --- a/include/linux/cacheinfo.h
> +++ b/include/linux/cacheinfo.h
> @@ -97,6 +97,15 @@ int func(unsigned int cpu)
On Fri, Mar 02, 2018 at 11:42:07AM +0100, Thierry Reding wrote:
> On Fri, Mar 02, 2018 at 12:37:24AM +0100, Rasmus Villemoes wrote:
> > Simplify the code slightly by having seq_open_data do the ->private
> > assignment.
> >
> > Signed-off-by: Rasmus Villemoes
> > ---
> > drivers/pci/host/pci-teg
On Tue, Mar 06, 2018 at 06:21:56PM +, Dexuan Cui wrote:
> 1. With the patch "x86/vector/msi: Switch to global reservation mode"
> (4900be8360), the recent v4.15 and newer kernels always hang for 1-vCPU
> Hyper-V VM with SR-IOV. This is because when we reach hv_compose_msi_msg()
> by request_irq
On Tue, Dec 19, 2017 at 03:01:26PM +0530, Kishon Vijay Abraham I wrote:
> Add properties to enable PCIe x2 lane mode since all dra7
> based SoCs support x2 lane mode.
>
> However only dra76-evm has a slot which can support x2 lane
> cards. Hence only enable x2 lane mode in dra76-evm.
> (am571x-idk
On Wed, Jan 10, 2018 at 03:43:41PM +0200, Ilya Ledvich wrote:
> Hi Lucas,
>
> On 01/08/2018 12:43 PM, Lucas Stach wrote:
> >Am Donnerstag, den 04.01.2018, 15:52 +0200 schrieb Ilya Ledvich:
> >>i.MX7D variant of the IP can use either Crystal Oscillator input
> >>or internal clock input as a Referen
On Thu, Feb 15, 2018 at 09:59:21AM +0530, Vignesh R wrote:
> Hi,
>
> On Monday 12 February 2018 11:28 PM, Lorenzo Pieralisi wrote:
> > On Fri, Feb 09, 2018 at 05:34:14PM +0530, Vignesh R wrote:
> >> We need to ensure that there are no pending MSI IRQ vector set (i.e
&g
On Thu, Mar 01, 2018 at 03:40:30PM +0100, Niklas Cassel wrote:
> On Wed, Feb 28, 2018 at 02:21:48PM +0000, Lorenzo Pieralisi wrote:
> > On Tue, Feb 27, 2018 at 12:59:05PM +0100, Niklas Cassel wrote:
> > > A 64-bit BAR uses the succeeding BAR for the upper bits, therefore
&g
On Thu, Mar 01, 2018 at 09:01:53PM +0530, Vignesh R wrote:
> Hi Lorenzo,
>
> On 15-Feb-18 9:59 AM, Vignesh R wrote:
> > Hi,
> >
> > On Monday 12 February 2018 11:28 PM, Lorenzo Pieralisi wrote:
> >> On Fri, Feb 09, 2018 at 05:34:14PM +0530, Vignesh R wrote:
&g
On Wed, Feb 14, 2018 at 11:27:58AM +0800, Ryder Lee wrote:
> dtc recently added PCI bus checks. Fix these warnings:
>
> Warning (pci_bridge): Node /pcie@1a14/pcie@0,0 missing bus-range for PCI
> bridge
> Warning (pci_bridge): Node /pcie@1a14/pcie@1,0 missing bus-range for PCI
> bridge
>
On Wed, Feb 28, 2018 at 06:32:17PM +0100, Rolf Evers-Fischer wrote:
> This is version 5 of a patchset to avoid double free in function
> 'pci_epf_create()'.
>
> When I accidentally created a new endpoint device with an empty name,
> the kernel warned about "attempted to be registered with empty na
On Fri, Jan 19, 2018 at 09:26:51PM -0600, Gustavo A. R. Silva wrote:
> Bool initializations should use true and false.
>
> This issue was detected with the help of Coccinelle.
>
> Fixes: eaa6111b70a7 ("PCI: altera: Add Altera PCIe host controller driver")
> Signed-off-by: Gustavo A. R. Silva
> -
On Tue, Feb 27, 2018 at 12:59:05PM +0100, Niklas Cassel wrote:
> A 64-bit BAR uses the succeeding BAR for the upper bits, therefore
> we cannot call pci_epc_set_bar() on a BAR that follows a 64-bit BAR.
>
> If pci_epc_set_bar() is called with flag PCI_BASE_ADDRESS_MEM_TYPE_64,
PCI_BASE_ADDRESS_ME
On Wed, Feb 28, 2018 at 02:07:19PM +0100, Rolf Evers-Fischer wrote:
> From: Rolf Evers-Fischer
>
> Removes the goto labels completely, handles the errors at the
> respective call site and just returns instead of jumping around.
>
> Signed-off-by: Rolf Evers-Fischer
> ---
> drivers/pci/endpoint
On Tue, Feb 27, 2018 at 11:02:30AM +0100, Rolf Evers-Fischer wrote:
> From: Rolf Evers-Fischer
>
> 'put_device()' calls the relase function 'pci_epf_dev_release()',
> which already frees 'epf->name' and 'epf'.
>
> Therefore we must not free them again after 'put_device()'.
>
> Fixes: 5e8cb40338
On Tue, Feb 27, 2018 at 11:02:28AM +0100, Rolf Evers-Fischer wrote:
> This is version 3 of a patchset to avoid double free in function
> 'pci_epf_create()'.
>
> When I accidentally created a new endpoint device with an empty name,
> the kernel warned about "attempted to be registered with empty na
On Thu, Feb 08, 2018 at 01:33:45PM +0100, Niklas Cassel wrote:
> A 64-bit BAR uses the succeeding BAR for the upper bits,
> so we cannot simply call pci_ioremap_bar() on every single BAR.
>
> Ignore BARs that does not have a valid resource length.
>
> pci :01:00.0: BAR 4: assigned [mem 0xc030
On Thu, Feb 15, 2018 at 01:26:37PM +, srinivas.kandaga...@linaro.org wrote:
> From: Srinivas Kandagatla
>
> This patch converts existing regulators to use regulator bulk apis,
> to make it consistent with msm8996 changes also cut down some redundant code.
>
> Signed-off-by: Srinivas Kandagat
On Thu, Feb 15, 2018 at 01:22:48PM +, srinivas.kandaga...@linaro.org wrote:
> From: Srinivas Kandagatla
>
> This patch adds supplies that are required for msm8996. vdda
> is analog supply that go in to controller, and vddpe_3v3 is
> supply to PCIe endpoint.
>
> Without these supplies PCIe en
On Tue, Feb 13, 2018 at 02:11:18PM +, Ard Biesheuvel wrote:
> Reapply the SynQuacer quirk for ITS frames that are matched by 'SCX0005'
> based ACPI devices, replacing the dummy fwnode with the one populated by
> the ACPI device core.
>
> This allows the SynQuacer ACPI tables to publish a devic
On Tue, Dec 19, 2017 at 02:28:23PM +0530, Kishon Vijay Abraham I wrote:
> dra74x/dra76x and dra72x has separate compatible strings. Add support
s/has/have
> for these compatible strings in pci-dra7xx driver to perform syscon
> configurations required to get x2 mode working.
>
> Signed-off-by: Ki
On Thu, Feb 01, 2018 at 03:02:23PM +0100, Niklas Cassel wrote:
> Fix typo in error message. s/deb_base2/dbi_base2/
>
> Signed-off-by: Niklas Cassel
> ---
> drivers/pci/dwc/pcie-designware-ep.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to pci/dwc for v4.17, thanks.
Lorenzo
On Fri, Feb 23, 2018 at 06:38:42PM +0100, Rolf Evers-Fischer wrote:
> Hi Kishon,
>
> On Fri, 23 Feb 2018, Kishon Vijay Abraham I wrote:
> > On Friday 23 February 2018 03:06 PM, Lorenzo Pieralisi wrote:
> > > On Fri, Feb 23, 2018 at 11:40:49AM +0530, Kishon Vijay Abraham I
On Fri, Feb 23, 2018 at 12:29:49PM +, Colin King wrote:
> From: Colin Ian King
>
> Bit pattern RCAR_PCI_INT_SIGRETABORT is being bit-wise or'd twice;
> remove the redundant 2nd RCAR_PCI_INT_SIGRETABORT.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/pci/host/pci-rcar-gen2.c | 1 -
> 1 f
On Tue, Feb 06, 2018 at 11:11:06PM +0100, Ulf Magnusson wrote:
> 'default N' should be 'default n', though they happen to have the same
> effect here, due to undefined symbols (N in this case) evaluating to n
> in a tristate sense.
>
> Remove the default instead of changing it. bool and tristate s
On Thu, Jan 25, 2018 at 09:56:30AM -0600, Jeremy Linton wrote:
> Hi,
>
> On 01/25/2018 06:15 AM, Xiongfeng Wang wrote:
> >Hi Jeremy,
> >
> >I have tested the patch with the newest UEFI. It prints the below error:
> >
> >[4.017371] BUG: arch topology borken
> >[4.021069] BUG: arch topology
On Thu, Feb 22, 2018 at 06:21:42PM -0600, Bjorn Helgaas wrote:
> On Fri, Feb 23, 2018 at 12:42:28AM +0100, Ulf Magnusson wrote:
> > On Fri, Feb 23, 2018 at 12:00 AM, Bjorn Helgaas wrote:
> > > On Tue, Feb 06, 2018 at 11:11:06PM +0100, Ulf Magnusson wrote:
> > >> 'default N' should be 'default n',
On Fri, Feb 23, 2018 at 11:40:49AM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On Thursday 22 February 2018 11:49 PM, Lorenzo Pieralisi wrote:
> > On Wed, Feb 21, 2018 at 01:47:06PM +0100, Rolf Evers-Fischer wrote:
> >> From: Rolf Evers-Fischer
> >&g
On Wed, Feb 21, 2018 at 01:47:06PM +0100, Rolf Evers-Fischer wrote:
> From: Rolf Evers-Fischer
>
> This commit decreases the number of jump labels and ensures
> that the next commit doesn't increase the number of occurrences
> of 'kfree(func_name)'.
>
> Change-Id: I0d1b6fd652395b85f82b11c43bf9b7
On Thu, Feb 15, 2018 at 12:47:25PM +0100, Rafael J. Wysocki wrote:
> On Thu, Feb 15, 2018 at 12:19 PM, John Garry wrote:
> >> Nothing apart from only being used by arm64 platforms today, which is
> >> circumstantial.
> >>
> >>>
> >>> I understand you need to find a place to add the:
> >>>
> >>> ac
On Wed, Feb 14, 2018 at 01:45:31AM +0800, John Garry wrote:
> On some platforms (such as arm64-based hip06/hip07), access to legacy
> ISA/LPC devices through access IO space is required, similar to x86
> platforms. As the I/O for these devices are not memory mapped like
> PCI/PCIE MMIO host bridges
On Fri, Feb 09, 2018 at 06:14:49PM +0530, Kishon Vijay Abraham I wrote:
> Hi Bjorn,
>
> On Friday 09 February 2018 03:27 AM, Bjorn Helgaas wrote:
> > On Thu, Feb 08, 2018 at 06:17:32PM +0530, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 08 February 2018 06:03 PM, Niklas Cassel wrot
On Fri, Feb 09, 2018 at 05:34:14PM +0530, Vignesh R wrote:
> We need to ensure that there are no pending MSI IRQ vector set (i.e
> PCIE_MSI_INTR0_STATUS reads 0 at least once) before exiting
> dra7xx_pcie_msi_irq_handler(). Else, the dra7xx PCIe wrapper will not
> register new MSI IRQs even though
On Thu, Feb 08, 2018 at 10:37:54AM +0800, Jia He wrote:
>
>
> On 2/7/2018 7:41 PM, Lorenzo Pieralisi Wrote:
> >On Tue, Feb 06, 2018 at 08:11:34PM -0800, Jia He wrote:
> >>In commit 316ca8804ea8 ("ACPI/IORT: Remove linker section for IORT entries
> >>
"),
> this line was back incorrectly.
>
> It does no harm except for adding some useless symbols, so fix it.
>
> Signed-off-by: Jia He
> ---
> include/asm-generic/vmlinux.lds.h | 1 -
> 1 file changed, 1 deletion(-)
Acked-by: Lorenzo Pieralisi
Who is picking this u
On Tue, Jan 30, 2018 at 10:12:36PM +0100, Cyrille Pitchen wrote:
[...]
> >>> v4 -> v5:
> >>> - rebase on today's (20180128) linux-pci/next
> >>
> >> Don't bother rebasing onto linux-pci/next.
> >>
> >> If your patches actually *depend* on something that has already been
> >> merged onto a PCI top
On Thu, Feb 01, 2018 at 09:56:09AM +0100, Niklas Cassel wrote:
> On Thu, Feb 01, 2018 at 10:51:14AM +1100, Stephen Rothwell wrote:
> > Hi Bjorn,
> >
> > After merging the pci tree, today's linux-next build (arm
> > multi_v7_defconfig) failed like this:
> >
> > drivers/pci/dwc/pcie-designware-ep.c
On Wed, Jan 31, 2018 at 12:10:47PM +, Shameerali Kolothum Thodi wrote:
[...]
> > I went back and re-read the patches, I think the point here is that the
> > perf driver (ie PATCH 2 that, by the way, is not maiinline) uses
> > devm_ioremap_resource() to map the counters and that's what is caus
On Tue, Jan 30, 2018 at 10:39:20AM +, Shameerali Kolothum Thodi wrote:
> Hi Neil/Lorenzo,
>
> > -Original Message-
> > From: linux-arm-kernel [mailto:linux-arm-kernel-boun...@lists.infradead.org]
> > On Behalf Of Neil Leeder
> > Sent: Friday, August 04, 2017 8:59 PM
> > To: Will Deacon
On Sun, Jan 28, 2018 at 03:47:41PM -0600, Bjorn Helgaas wrote:
> On Sun, Jan 28, 2018 at 09:40:14PM +0100, Cyrille Pitchen wrote:
> > Hi all,
> >
> > this series of patches adds support to the Cadence PCIe controller.
> > It was tested on a ARM64 platform emulated by a Palladium running the
> > pc
t (*cpu_suspend)(u32 state, unsigned long entry_point);
> @@ -41,6 +46,7 @@ struct psci_operations {
> unsigned long lowest_affinity_level);
> int (*migrate_info_type)(void);
> enum psci_conduit conduit;
> + enum smccc_variant variant;
Nit: I would add an smccc_ prefix to the variant field (or rename it
to smccc_version).
You can add my:
Acked-by: Lorenzo Pieralisi
; drivers/firmware/psci.c | 28 +++-
> include/linux/psci.h| 7 +++
> 2 files changed, 30 insertions(+), 5 deletions(-)
Acked-by: Lorenzo Pieralisi
> diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
> index 8b25d31e8401..e9493da2b111 100
On Fri, Jan 19, 2018 at 08:40:05PM -0600, Bjorn Helgaas wrote:
> On Fri, Jan 19, 2018 at 11:18:59AM +0000, Lorenzo Pieralisi wrote:
> > On Fri, Jan 19, 2018 at 10:39:06AM +0100, Niklas Cassel wrote:
> > > If CONFIG_PCI=n and CONFIG_PCI_DRA7XX_EP=y, the build fails with:
> >
a dummy for pci_irqd_intx_xlate().
>
> Acked-by: Arnd Bergmann
> Acked-by: Lorenzo Pieralisi
> Signed-off-by: Niklas Cassel
Thanks for the patch.
I think the commit log should be rewritten (when you write it think at
someone reading it in some time - what you wrote won't prob
tag that references 524d59f6e30a
>
> Looks fine to me, but I'd put the '{ return 0; }' in a new line for
> consistency
> with the other functions here, and maybe return -EINVAL instead of
> zero.
>
> Can you submit that as a proper patch and add my
>
>
On Thu, Jan 18, 2018 at 02:15:54PM +0100, Arnd Bergmann wrote:
> It was a nice idea to split out the PCI host and endpoint mode configuration
> into separate options. Unfortunately it doesn't build:
>
> drivers/pci/dwc/pci-dra7xx.c:229:11: error: 'pci_irqd_intx_xlate' undeclared
> here (not in a
[+cc Mika]
On Tue, Jan 09, 2018 at 02:00:12PM +0100, Andrew Lunn wrote:
> On Tue, Jan 09, 2018 at 11:22:00AM +0100, Marcin Wojtas wrote:
> > 2018-01-09 11:19 GMT+01:00 Graeme Gregory :
> > > On Mon, Jan 08, 2018 at 06:17:06PM +0100, Marcin Wojtas wrote:
> > >> Hi Andrew,
> > >>
> > >>
> > >>
> > >
On Wed, Jan 10, 2018 at 11:47:35PM +0100, Cyrille Pitchen wrote:
> This patch adds support to the Cadence PCIe controller in host mode.
>
> Signed-off-by: Cyrille Pitchen
> ---
> MAINTAINERS | 7 +
> drivers/pci/Kconfig | 1 +
> drivers/pci/Mak
On Wed, Jan 10, 2018 at 11:47:32PM +0100, Cyrille Pitchen wrote:
> This patchs moves generic source code from
> drivers/pci/host/pci-host-common.c into drivers/pci/probe.c.
>
> Indeed the extracted lines of code were duplicated by many host
> controller drivers. Regrouping them into a generic func
On Tue, Jan 16, 2018 at 04:46:12PM +0530, Kishon Vijay Abraham I wrote:
[...]
> > +static struct platform_driver cdns_pcie_host_driver = {
> > + .driver = {
> > + .name = "cdns-pcie-host",
> > + .of_match_table = cdns_pcie_host_of_match,
> > + },
> > + .probe = cdns_pcie
On Tue, Jan 16, 2018 at 06:15:46PM +0900, Hiraku Toyooka wrote:
> Hello,
>
> I found a NULL pointer dereference in PCI/MSI when I tried to run kdump
> kernel on i.MX6(MCIMX6Q-SDB). This error occurs when masking MSI irq
> which does not have msi_desc.
> I added NULL check to avoid the error, and k
On Thu, Jan 11, 2018 at 02:00:57PM +0530, Kishon Vijay Abraham I wrote:
> After commit 723288836628bc1c08 ("of: restrict DMA configuration"),
> of_dma_configure doesn't configure the coherent_dma_mask/dma_mask
> of endpoint function device (since it doesn't have a dt node associated
> with and henc
On Fri, Dec 29, 2017 at 05:11:31PM +0530, Vignesh R wrote:
> It is possible that more than one legacy IRQ may be set at the same
> time, therefore iterate and handle all the pending INTx interrupts
> before clearing the status and exiting the IRQ handler. Otherwise, some
> interrupts would be lost.
On Fri, Dec 29, 2017 at 05:11:30PM +0530, Vignesh R wrote:
> Legacy INTD IRQ handling is broken on dra7xx due to fact that driver
> uses hwirq in range of 1-4 for INTA, INTD whereas IRQ domain is of size
> 4 which is numbered 0-3. Therefore when INTD IRQ line is used with
> pci-dra7xx driver follow
On Thu, Jan 11, 2018 at 12:36:16PM -0800, Ray Jui wrote:
> With the inbound DMA mapping supported added, the iProc PCIe driver
> parses DT property "dma-ranges" through call to
> "of_pci_dma_range_parser_init". In the case of BCMA, this results in a
> NULL pointer deference due to a missing of_node
On Tue, Jan 09, 2018 at 11:45:40AM -0800, Ray Jui wrote:
> With the inbound DMA mapping supported added, the iProc PCIe driver
> parses DT property "dma-ranges" through call to
> "of_pci_dma_range_parser_init". In the case of BCMA, this results in a
> NULL pointer deference due to a missing of_node
On Tue, Dec 19, 2017 at 02:06:27PM +0530, Kishon Vijay Abraham I wrote:
> After commit 723288836628bc1c08 ("of: restrict DMA configuration"),
> of_dma_configure doesn't configure the coherent_dma_mask/dma_mask
> of endpoint function device (since it doesn't have a dt node associated
> with and henc
can easily rework the log before sending it
upstream.
I will send it upstream for the next cycle along with patch (2), or
if you prefer to send it yourself:
Acked-by: Lorenzo Pieralisi
Thanks for putting it together,
Lorenzo
> This patch removes the dependency on physical_package_id from th
4704/
>
> Regards,
>
> czou
>
>
> On 12/22/2017 05:35 PM, Marc Zyngier wrote:
> >On 22/12/17 07:38, Cao Zou wrote:
> >>
> >>On 12/22/2017 11:04 AM, Cao Zou wrote:
> >>>
> >>>On 12/20/2017 12:20 AM, Lorenzo Pieralisi wrote:
> >&
On Mon, Jan 08, 2018 at 07:18:59PM +0530, Vignesh R wrote:
>
>
> On Thursday 04 January 2018 09:42 PM, Lorenzo Pieralisi wrote:
> > On Thu, Jan 04, 2018 at 07:04:30PM +0530, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 04 January 2
On Mon, Dec 18, 2017 at 07:16:06PM +0100, Cyrille Pitchen wrote:
> This patch adds support to the Cadence PCIe controller in host mode.
>
> The "cadence/" entry in drivers/pci/Makefile is placed after the
> "endpoint/" entry so when the next patch introduces a EPC driver for the
> Cadence PCIe con
On Mon, Dec 18, 2017 at 07:16:03PM +0100, Cyrille Pitchen wrote:
> This patchs moves generic source code from
> drivers/pci/host/pci-host-common.c into drivers/pci/probe.c.
>
> Indeed the extracted lines of code were duplicated by many host
> controller drivers. Regrouping them into a generic func
[+Marc]
On Wed, Dec 27, 2017 at 08:59:53AM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> There maybe a same IRQ reentry scenario after IRQ received in current
> IRQ handle flow:
> EP device PCIe host driverEP driver
> 1. issue an IRQ
>
On Thu, Jan 04, 2018 at 03:58:38PM +0100, Maxime Ripard wrote:
> On Thu, Jan 04, 2018 at 10:37:46PM +0800, Chen-Yu Tsai wrote:
> > This is v2 of my sun9i SMP support with MCPM series which was started
> > over two years ago [1]. We've tried to implement PSCI for both the A80
> > and A83T. Results w
On Thu, Jan 04, 2018 at 07:04:30PM +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 04 January 2018 11:38 AM, Kishon Vijay Abraham I wrote:
> >
> >
> > On Friday 29 December 2017 05:11 PM, Vignesh R wrote:
> >> Legacy INTD IRQ handling is broken on dra7xx due to fact that driver
> >> u
s, so that it
> can be invoked outside of the PSCI driver where necessary.
>
> Signed-off-by: Will Deacon
> ---
> drivers/firmware/psci.c | 2 ++
> include/linux/psci.h| 1 +
> 2 files changed, 3 insertions(+)
Acked-by: Lorenzo Pieralisi
> diff --git a/drivers/fir
On Wed, Jan 03, 2018 at 01:38:27PM +0100, Julia Lawall wrote:
>
>
> On Wed, 3 Jan 2018, Lorenzo Pieralisi wrote:
>
> > On Tue, Jan 02, 2018 at 02:28:00PM +0100, Julia Lawall wrote:
> > > This driver creates various const structures that it stores in the
> > >
On Tue, Jan 02, 2018 at 02:28:00PM +0100, Julia Lawall wrote:
> This driver creates various const structures that it stores in the
> data field of an of_device_id array.
>
> Adding const to the declaration of the location that receives the
> const value from the data field ensures that the compile
On Wed, Jan 03, 2018 at 02:39:04PM +0800, Honghui Zhang wrote:
> On Tue, 2018-01-02 at 10:56 +0000, Lorenzo Pieralisi wrote:
> > On Thu, Dec 28, 2017 at 09:39:12AM +0800, Honghui Zhang wrote:
> > > On Wed, 2017-12-27 at 12:45 -0600, Bjorn Helgaas wrote:
> > > > On W
On Wed, Jan 03, 2018 at 02:26:29PM +0900, Jaehoon Chung wrote:
> On 01/03/2018 01:34 AM, Lorenzo Pieralisi wrote:
> > On Wed, Dec 27, 2017 at 06:43:27PM +0900, Jaehoon Chung wrote:
> >> pci-exynos had updated to use the PHY framework.
> >> (drivers/phy/samsung/phy-exyn
and manage the PHY.
Remove the deprecated PHY initialization code in the Exynos PCI host
bridge driver by updating the driver to use the PHY framework API;
modify the DT binding documentation accordingly.
Signed-off-by: Jaehoon Chung
[lorenzo.pieral...@arm.com: updated commit log]
Signed-off-b
On Fri, Dec 29, 2017 at 05:11:31PM +0530, Vignesh R wrote:
> It is possible that more than one legacy IRQ may be set at the same
> time, therefore iterate and handle all the pending INTx interrupts
> before clearing the status and exiting the IRQ handler. Otherwise, some
> interrupts would be lost.
On Thu, Dec 28, 2017 at 09:39:12AM +0800, Honghui Zhang wrote:
> On Wed, 2017-12-27 at 12:45 -0600, Bjorn Helgaas wrote:
> > On Wed, Dec 27, 2017 at 08:59:54AM +0800, honghui.zh...@mediatek.com wrote:
> > > From: Honghui Zhang
> > >
> > > The hardware default value of IDs and class type is not co
On Thu, Dec 28, 2017 at 08:09:55AM -0800, Stephen Boyd wrote:
> On 12/28, Joao Pinto wrote:
> > > if (pp->ops->get_msi_data)
> > > msg.data = pp->ops->get_msi_data(pp, pos);
> > >
> >
> > Thanks for the patch.
> > Gustavo' patch-set targeting the update of the Interrupt API for
> > pc
On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas Cassel wrote:
> This is a series that adds:
> - PCI endpoint mode support in the ARTPEC-6 driver.
> - ARTPEC-7 SoC support in the ARTPEC-6 driver (the SoCs are very similar).
> - Small fixes for MSI in designware-ep and designware-host,
> needed to
On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas Cassel wrote:
> This is a series that adds:
> - PCI endpoint mode support in the ARTPEC-6 driver.
> - ARTPEC-7 SoC support in the ARTPEC-6 driver (the SoCs are very similar).
> - Small fixes for MSI in designware-ep and designware-host,
> needed to
On Fri, Dec 01, 2017 at 10:36:52AM +0530, Vignesh R wrote:
> Declare dra7xx_pcie_shutdown() as a static function as its not used
> elsewhere.
>
> Signed-off-by: Vignesh R
> ---
> drivers/pci/dwc/pci-dra7xx.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to pci/dwc for v4.16.
On Fri, Dec 01, 2017 at 04:53:14PM +, Lorenzo Pieralisi wrote:
> On Fri, Dec 01, 2017 at 10:43:53AM +0530, Keerthy wrote:
> >
> >
> > On Friday 01 December 2017 10:36 AM, Vignesh R wrote:
> > > Declare dra7xx_pcie_shutdown() as a static function a
On Fri, Dec 01, 2017 at 11:43:08AM +0530, Vignesh R wrote:
> Errata i870 is applicable in both EP and RC mode. Therefore rename
> function dra7xx_pcie_ep_unaligned_memaccess(), that implements errata
> workaround, to dra7xx_pcie_unaligned_memaccess() and call it from a
> common place. So, that erra
On Mon, Dec 18, 2017 at 10:02:20AM +0800, Cao Zou wrote:
>
>
> On 12/16/2017 01:20 AM, Marc Zyngier wrote:
> >On 15/12/17 16:17, Lorenzo Pieralisi wrote:
> >>[+Marc]
> >>
> >>On Thu, Dec 14, 2017 at 10:21:23AM +0800, cao@windriver.com wrote:
>
t; being very difficult to find a time slot available for running this tests.
>
> I hope in this week I could give you go/not go flag. Sorry the delay...
>
> Regards,
>
> Gustavo
>
>
> On 18/12/2017 15:57, Lorenzo Pieralisi wrote:
>
> Hi Gustavo,
>
>
On Thu, Dec 07, 2017 at 11:15:20AM +0100, Geert Uytterhoeven wrote:
> rcar_pcie_parse_request_of_pci_ranges() can fail and return an error
> code, but this is not checked nor handled.
>
> Fix this by adding the missing error handling.
>
> Fixes: 5d2917d469faab72 ("PCI: rcar: Convert to DT resourc
On Tue, Dec 19, 2017 at 03:25:41PM +0530, Kishon Vijay Abraham I wrote:
> ->get_msi() now checks MSI_EN bit in the MSI CAPABILITY register to
> find whether the host supports MSI instead of using the
> MSI ADDRESS in the MSI CAPABILITY register.
>
> This fixes the issue with the following sequence
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