Re: [PATCH 1/4] clk: meson: mpll: add init callback and regs

Hi Jerome, On Mon, Apr 8, 2019 at 9:38 AM Jerome Brunet wrote: > > On Fri, 2019-04-05 at 13:43 -0700, Stephen Boyd wrote: > > Quoting Michael Turquette (2019-04-05 08:43:40) > > > Hi Jerome, > > > > > > On Fri, Mar 29, 2019 at 3:58 PM Jerome Brunet > &

Re: [PATCH 1/4] clk: meson: mpll: add init callback and regs

Using the callback clearly shows the relationship between the init and the > clock. I think it is a lot better. > > In the same series, I have added some init for the controller. In this case > the init target a group of clocks, so having the init in the controller makes > sense for that > > > -- Michael Turquette CEO BayLibre - At the Heart of Embedded Linux http://baylibre.com/ Schedule a meeting: https://calendly.com/mturquette

Re: [RFC PATCH 0/3] Add support of busfreq

/imx/Makefile > create mode 100644 drivers/interconnect/imx/busfreq-imx8mm.c > create mode 100644 drivers/interconnect/imx/busfreq.c > create mode 100644 drivers/interconnect/imx/busfreq.h > create mode 100644 include/dt-bindings/interconnect/imx8mm.h > > -- > 2.19.2 -- Michael Turquette CEO BayLibre - At the Heart of Embedded Linux http://baylibre.com/ Schedule a meeting: https://calendly.com/mturquette

Re: [PATCH v12 0/7] Introduce on-chip interconnect API

Hi Olof, Georgi, Happy new year! :-) Quoting Georgi Djakov (2018-12-08 21:15:35) > Hi Olof, > > On 9.12.18 2:33, Olof Johansson wrote: > > Hi Georgi, > > > > On Sat, Dec 8, 2018 at 9:02 AM Georgi Djakov > > wrote: > >> > >> Modern SoCs have multiple processors and various dedicated cores

Re: [PATCH RESEND V4 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support

he recalc rate will still return 0 as > there's still no proper preset rate. Enable such divider will give user > a reminder error message. > > Cc: Stephen Boyd > Cc: Michael Turquette > Cc: Shawn Guo > Signed-off-by: Dong Aisheng > > --- > ChangeLog: > v

Re: [PATCH RESEND V4 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support

he recalc rate will still return 0 as > there's still no proper preset rate. Enable such divider will give user > a reminder error message. > > Cc: Stephen Boyd > Cc: Michael Turquette > Cc: Shawn Guo > Signed-off-by: Dong Aisheng > > --- > ChangeLog: > v

Re: [PATCH] MAINTAINERS: add myself as co-maintainer of gpiolib

son > > Cc: Kevin Hilman > > Cc: Michael Turquette > > Signed-off-by: Bartosz Golaszewski > > Excellent, patch applied for fixes. Welcome aboard! :D Completely unnecessary: Acked-by: Michael Turquette ;-) Best regards, Mike > > Yours, > Linus Walleij

Re: [PATCH] MAINTAINERS: add myself as co-maintainer of gpiolib

son > > Cc: Kevin Hilman > > Cc: Michael Turquette > > Signed-off-by: Bartosz Golaszewski > > Excellent, patch applied for fixes. Welcome aboard! :D Completely unnecessary: Acked-by: Michael Turquette ;-) Best regards, Mike > > Yours, > Linus Walleij

Re: [PATCH] clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL

Quoting Christian Hewitt (2018-10-13 12:04:46) > On the Khadas VIM2 (GXM) and LePotato (GXL) board there are problems > with reboot; e.g. a ~60 second delay between issuing reboot and the > board power cycling (and in some OS configurations reboot will fail > and require manual power cycling). >

Re: [PATCH] clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL

Quoting Christian Hewitt (2018-10-13 12:04:46) > On the Khadas VIM2 (GXM) and LePotato (GXL) board there are problems > with reboot; e.g. a ~60 second delay between issuing reboot and the > board power cycling (and in some OS configurations reboot will fail > and require manual power cycling). >

Re: [PATCH v4] clk: add duty cycle support

Quoting Jerome Brunet (2018-06-19 07:41:41) > Add the possibility to apply and query the clock signal duty cycle ratio. > > This is useful when the duty cycle of the clock signal depends on some > other parameters controlled by the clock framework. > > For example, the duty cycle of a divider

Re: [PATCH v4] clk: add duty cycle support

Quoting Jerome Brunet (2018-06-19 07:41:41) > Add the possibility to apply and query the clock signal duty cycle ratio. > > This is useful when the duty cycle of the clock signal depends on some > other parameters controlled by the clock framework. > > For example, the duty cycle of a divider

Re: [PATCH 2/2] clk: fix CLK_SET_RATE_GATE with clock rate protection

Quoting Jerome Brunet (2018-06-19 06:40:51) > CLK_SET_RATE_GATE should prevent any operation which may result in a rate > change or glitch while the clock is prepared/enabled. > > IOW, the following sequence is not allowed anymore with CLK_SET_RATE_GATE: > * clk_get() > * clk_prepare_enable() > *

Re: [PATCH 2/2] clk: fix CLK_SET_RATE_GATE with clock rate protection

Quoting Jerome Brunet (2018-06-19 06:40:51) > CLK_SET_RATE_GATE should prevent any operation which may result in a rate > change or glitch while the clock is prepared/enabled. > > IOW, the following sequence is not allowed anymore with CLK_SET_RATE_GATE: > * clk_get() > * clk_prepare_enable() > *

Re: [PATCH 1/2] clk: qcom: drop CLK_SET_RATE_GATE from sdc clocks

Quoting Jerome Brunet (2018-06-19 06:40:50) > the mmci driver (drivers/mmc/host/mmci.c) does the following sequence: > * clk_prepare_enable() > * clk_set_rate() > > on SDCx_clk which is a children of SDCx_src. SDCx_src has > CLK_SET_RATE_GATE so this sequence should not be allowed but this was

Re: [PATCH 1/2] clk: qcom: drop CLK_SET_RATE_GATE from sdc clocks

Quoting Jerome Brunet (2018-06-19 06:40:50) > the mmci driver (drivers/mmc/host/mmci.c) does the following sequence: > * clk_prepare_enable() > * clk_set_rate() > > on SDCx_clk which is a children of SDCx_src. SDCx_src has > CLK_SET_RATE_GATE so this sequence should not be allowed but this was

Re: [PATCH 0/9] clk: davinci: outstanding fixes

Hi David, Quoting David Lechner (2018-05-25 11:11:41) > This is a resend of all of the outstanding DaVinci clock patches plus one new > patch. All of the patches (except the new one) have been reviewed and tested > by someone other than me. > > The new patch ("clk: davinci: Fix link errors when

Re: [PATCH 0/9] clk: davinci: outstanding fixes

Hi David, Quoting David Lechner (2018-05-25 11:11:41) > This is a resend of all of the outstanding DaVinci clock patches plus one new > patch. All of the patches (except the new one) have been reviewed and tested > by someone other than me. > > The new patch ("clk: davinci: Fix link errors when

Re: [PATCH 6/9] clk: davinci: pll: allow dev == NULL

Hi David, Quoting David Lechner (2018-05-25 11:11:47) > This modifies the TI Davinci PLL clock driver to allow for the case > when dev == NULL. On some (most) SoCs that use this driver, the PLL > clock needs to be registered during early boot because it is used > for clocksource/clkevent and

Re: [PATCH 6/9] clk: davinci: pll: allow dev == NULL

Hi David, Quoting David Lechner (2018-05-25 11:11:47) > This modifies the TI Davinci PLL clock driver to allow for the case > when dev == NULL. On some (most) SoCs that use this driver, the PLL > clock needs to be registered during early boot because it is used > for clocksource/clkevent and

Re: [PATCH 00/12] introduce support for early platform drivers

Hi Rob, Quoting Rob Herring (2018-05-14 06:20:57) > On Mon, May 14, 2018 at 6:38 AM, Bartosz Golaszewski wrote: > > 2018-05-11 22:13 GMT+02:00 Rob Herring : > >> On Fri, May 11, 2018 at 11:20 AM, Bartosz Golaszewski > >> wrote: > >>> This series is a follow-up to the RFC[1] posted a couple

Re: [PATCH 00/12] introduce support for early platform drivers

Hi Rob, Quoting Rob Herring (2018-05-14 06:20:57) > On Mon, May 14, 2018 at 6:38 AM, Bartosz Golaszewski wrote: > > 2018-05-11 22:13 GMT+02:00 Rob Herring : > >> On Fri, May 11, 2018 at 11:20 AM, Bartosz Golaszewski > >> wrote: > >>> This series is a follow-up to the RFC[1] posted a couple

Re: [PATCH 4/9] clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled

Quoting David Lechner (2018-05-25 11:11:45) > From: Sekhar Nori > > PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot > be disabled. Mark it so to prevent unused clock disable > infrastructure from disabling it. > > Signed-off-by: Sekhar Nori > Reviewed-by: David Lechner > --- >

Re: [PATCH 4/9] clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled

Quoting David Lechner (2018-05-25 11:11:45) > From: Sekhar Nori > > PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot > be disabled. Mark it so to prevent unused clock disable > infrastructure from disabling it. > > Signed-off-by: Sekhar Nori > Reviewed-by: David Lechner > --- >

Re: [PATCH v5 00/10] clk: implement clock rate protection mechanism

Quoting Jerome Brunet (2018-02-02 04:50:28) > On Thu, 2018-02-01 at 09:43 -0800, Stephen Boyd wrote: > > > > > Applied to clk-protect-rate, with the exception that I did not apply > > > > > "clk: fix CLK_SET_RATE_GATE with clock rate protection" as it breaks > > > > > qcom clk code. > > > > > > >

Re: [PATCH v5 00/10] clk: implement clock rate protection mechanism

Quoting Jerome Brunet (2018-02-02 04:50:28) > On Thu, 2018-02-01 at 09:43 -0800, Stephen Boyd wrote: > > > > > Applied to clk-protect-rate, with the exception that I did not apply > > > > > "clk: fix CLK_SET_RATE_GATE with clock rate protection" as it breaks > > > > > qcom clk code. > > > > > > >

Re: [PATCH v2 4/8] clk: migrate the count of orphaned clocks at init

Excerpts from Heiko Stübner's message of February 15, 2018 1:01 pm: Am Mittwoch, 14. Februar 2018, 14:43:36 CET schrieb Jerome Brunet: The orphan clocks reparents should migrate any existing count from the orphan clock to its new acestor clocks, otherwise we may have inconsistent counts in the

Re: [PATCH v2 4/8] clk: migrate the count of orphaned clocks at init

Excerpts from Heiko Stübner's message of February 15, 2018 1:01 pm: Am Mittwoch, 14. Februar 2018, 14:43:36 CET schrieb Jerome Brunet: The orphan clocks reparents should migrate any existing count from the orphan clock to its new acestor clocks, otherwise we may have inconsistent counts in the

Re: [PATCH v2 00/19] clk: meson: use regmap in clock controllers

Bonjour Jerome, Excerpts from Jerome Brunet's message of February 12, 2018 6:58 am: This changeset is a rework of meson's clock controllers to use regmap instead of directly using io memory. It based clk-meson next/drivers and depends on few core clock patches, mainly to export generic clocks

Re: [PATCH v2 00/19] clk: meson: use regmap in clock controllers

Bonjour Jerome, Excerpts from Jerome Brunet's message of February 12, 2018 6:58 am: This changeset is a rework of meson's clock controllers to use regmap instead of directly using io memory. It based clk-meson next/drivers and depends on few core clock patches, mainly to export generic clocks

Re: [PATCH v2 00/12] Introduce STM32MP1 clock driver

Excerpts from gabriel.fernan...@st.com's message of March 8, 2018 8:53 am: From: Gabriel Fernandez v2: - Don't use MFD, use existing binding of STM32 RCC. - Rework Peripheral and Kernel clocks - cosmetic changes This patch-set introduces clock driver for

Re: [PATCH v2 00/12] Introduce STM32MP1 clock driver

Excerpts from gabriel.fernan...@st.com's message of March 8, 2018 8:53 am: From: Gabriel Fernandez v2: - Don't use MFD, use existing binding of STM32 RCC. - Rework Peripheral and Kernel clocks - cosmetic changes This patch-set introduces clock driver for STM32MP157 based on Arm

Re: [PATCH v2 0/8] clk: helpers and fixes

Excerpts from Jerome Brunet's message of February 14, 2018 5:43 am: This changset is consist of various patches I have recently sent for the clock framework. They are gathered here for your convinience. The first two changes exports helpers of the generic clocks (divider and mux). The goal is

Re: [PATCH v2 0/8] clk: helpers and fixes

Excerpts from Jerome Brunet's message of February 14, 2018 5:43 am: This changset is consist of various patches I have recently sent for the clock framework. They are gathered here for your convinience. The first two changes exports helpers of the generic clocks (divider and mux). The goal is

Re: [PATCH v5 12/44] clk: davinci: Add platform information for TI DA850 PSC

Hi Bartosz, all, On Fri, Feb 9, 2018 at 8:22 AM, Bartosz Golaszewski wrote: > 2018-01-08 3:17 GMT+01:00 David Lechner : >> This adds platform-specific declarations for the PSC clocks on TI DA850/ >> OMAP-L138/AM18XX SoCs. >> >> Signed-off-by: David Lechner

Re: [PATCH v5 12/44] clk: davinci: Add platform information for TI DA850 PSC

Hi Bartosz, all, On Fri, Feb 9, 2018 at 8:22 AM, Bartosz Golaszewski wrote: > 2018-01-08 3:17 GMT+01:00 David Lechner : >> This adds platform-specific declarations for the PSC clocks on TI DA850/ >> OMAP-L138/AM18XX SoCs. >> >> Signed-off-by: David Lechner >> --- >>

Re: [PATCH 1/3] dt-bindings: ARM: Mediatek: Fix ethsys documentation

Quoting Matthias Brugger (2017-12-20 09:13:12) > > > On 12/19/2017 02:32 AM, Stephen Boyd wrote: > > On 12/14, Matthias Brugger wrote: > >> Hi Stephen, Michael, > >> > >> On 12/01/2017 01:07 PM, Matthias Brugger wrote: > >>> The ethsys registers a reset controller, so we need to specify a > >>>

Re: [PATCH 1/3] dt-bindings: ARM: Mediatek: Fix ethsys documentation

Quoting Matthias Brugger (2017-12-20 09:13:12) > > > On 12/19/2017 02:32 AM, Stephen Boyd wrote: > > On 12/14, Matthias Brugger wrote: > >> Hi Stephen, Michael, > >> > >> On 12/01/2017 01:07 PM, Matthias Brugger wrote: > >>> The ethsys registers a reset controller, so we need to specify a > >>>

Re: [PATCH] clk: fix spin_lock/unlock imbalance on bad clk_enable() reentrancy

Quoting David Lechner (2017-12-20 10:53:27) > On 12/19/2017 04:29 PM, Michael Turquette wrote: > > Hi David, > > > > Quoting David Lechner (2017-12-15 08:29:56) > >> On 12/12/2017 10:14 PM, David Lechner wrote: > >>> On 12/12/2017 05:43 PM, David Lechn

Re: [PATCH] clk: fix spin_lock/unlock imbalance on bad clk_enable() reentrancy

Quoting David Lechner (2017-12-20 10:53:27) > On 12/19/2017 04:29 PM, Michael Turquette wrote: > > Hi David, > > > > Quoting David Lechner (2017-12-15 08:29:56) > >> On 12/12/2017 10:14 PM, David Lechner wrote: > >>> On 12/12/2017 05:43 PM, David Lechn

Re: [PATCH v5 00/10] clk: implement clock rate protection mechanism

Quoting Jerome Brunet (2017-12-01 13:51:50) > This Patchset is related the RFC [0] and the discussion around > CLK_SET_RATE_GATE available here [1] > > This patchset introduce clock protection to the CCF core. This can then > be used for: > > * Provide a way for a consumer to claim exclusivity

Re: [PATCH v5 00/10] clk: implement clock rate protection mechanism

Quoting Jerome Brunet (2017-12-01 13:51:50) > This Patchset is related the RFC [0] and the discussion around > CLK_SET_RATE_GATE available here [1] > > This patchset introduce clock protection to the CCF core. This can then > be used for: > > * Provide a way for a consumer to claim exclusivity

Re: [PATCH] clk: fix spin_lock/unlock imbalance on bad clk_enable() reentrancy

Hi David, Quoting David Lechner (2017-12-15 08:29:56) > On 12/12/2017 10:14 PM, David Lechner wrote: > > On 12/12/2017 05:43 PM, David Lechner wrote: > >> If clk_enable() is called in reentrant way and spin_trylock_irqsave() is > >> not working as expected, it is possible to get a negative

Re: [PATCH] clk: fix spin_lock/unlock imbalance on bad clk_enable() reentrancy

Hi David, Quoting David Lechner (2017-12-15 08:29:56) > On 12/12/2017 10:14 PM, David Lechner wrote: > > On 12/12/2017 05:43 PM, David Lechner wrote: > >> If clk_enable() is called in reentrant way and spin_trylock_irqsave() is > >> not working as expected, it is possible to get a negative

Re: [PATCH v2 1/2] clk: tegra: Mark HCLK, SCLK, EMC, MC and PLL_P outputs as critical

Quoting Dmitry Osipenko (2017-12-19 12:20:56) > On 19.12.2017 22:56, Michael Turquette wrote: > > Quoting Dmitry Osipenko (2017-12-18 19:59:06) > >> Machine dies if HCLK, SCLK or EMC is disabled, hence mark these clocks > >> as critical. Currently some of drivers do

Re: [PATCH v2 1/2] clk: tegra: Mark HCLK, SCLK, EMC, MC and PLL_P outputs as critical

Quoting Dmitry Osipenko (2017-12-19 12:20:56) > On 19.12.2017 22:56, Michael Turquette wrote: > > Quoting Dmitry Osipenko (2017-12-18 19:59:06) > >> Machine dies if HCLK, SCLK or EMC is disabled, hence mark these clocks > >> as critical. Currently some of drivers do

Re: [PATCH v2 1/2] clk: tegra: Mark HCLK, SCLK, EMC, MC and PLL_P outputs as critical

Quoting Dmitry Osipenko (2017-12-18 19:59:06) > Machine dies if HCLK, SCLK or EMC is disabled, hence mark these clocks > as critical. Currently some of drivers do not manage clocks properly, > expecting clocks to be 'always enabled', these clocks are MC and PLL_P > outputs. Let's mark MC or PLL_P

Re: [PATCH v2 1/2] clk: tegra: Mark HCLK, SCLK, EMC, MC and PLL_P outputs as critical

Quoting Dmitry Osipenko (2017-12-18 19:59:06) > Machine dies if HCLK, SCLK or EMC is disabled, hence mark these clocks > as critical. Currently some of drivers do not manage clocks properly, > expecting clocks to be 'always enabled', these clocks are MC and PLL_P > outputs. Let's mark MC or PLL_P

Re: [PATCH v2] clk: check ops pointer on clock register

Quoting Jerome Brunet (2017-12-19 00:33:29) > Nothing really prevents a provider from (trying to) register a clock > without providing the clock ops structure. > > We do check the individual fields before using them, but not the > structure pointer itself. This may have the usual nasty

Re: [PATCH v2] clk: check ops pointer on clock register

Quoting Jerome Brunet (2017-12-19 00:33:29) > Nothing really prevents a provider from (trying to) register a clock > without providing the clock ops structure. > > We do check the individual fields before using them, but not the > structure pointer itself. This may have the usual nasty

Re: [PATCH] clk: check ops pointer on clock register

Hi Jerome & Stephen, On Mon, Dec 18, 2017 at 12:06 PM, Jerome Brunet wrote: > On Mon, 2017-12-18 at 11:03 -0800, Stephen Boyd wrote: >> On 12/18, Jerome Brunet wrote: >> > Nothing really prevents a provider from (trying to) register a clock >> > without providing the clock

Re: [PATCH] clk: check ops pointer on clock register

Hi Jerome & Stephen, On Mon, Dec 18, 2017 at 12:06 PM, Jerome Brunet wrote: > On Mon, 2017-12-18 at 11:03 -0800, Stephen Boyd wrote: >> On 12/18, Jerome Brunet wrote: >> > Nothing really prevents a provider from (trying to) register a clock >> > without providing the clock ops structure. >> > >>

Re: [PATCH 0/2] Add support for Hi6220 coresight

Quoting Wei Xu (2017-10-13 10:57:02) > Hi Leo, > > On 2017/10/7 13:18, Leo Yan wrote: > > Hi Stephen, Wei, > > > > On Thu, Aug 31, 2017 at 06:33:01PM -0700, Stephen Boyd wrote: > >> On 09/01, Leo Yan wrote: > >>> This patch series adds support for coresight on Hi6220; the first patch > >>> is to

Re: [PATCH 0/2] Add support for Hi6220 coresight

Quoting Wei Xu (2017-10-13 10:57:02) > Hi Leo, > > On 2017/10/7 13:18, Leo Yan wrote: > > Hi Stephen, Wei, > > > > On Thu, Aug 31, 2017 at 06:33:01PM -0700, Stephen Boyd wrote: > >> On 09/01, Leo Yan wrote: > >>> This patch series adds support for coresight on Hi6220; the first patch > >>> is to

Re: [PATCH v4 09/10] clk: add clk_rate_exclusive api

Hi Jérôme, On Tue, Oct 31, 2017 at 5:29 PM, Jerome Brunet <jbru...@baylibre.com> wrote: > On Thu, 2017-10-26 at 07:26 +0200, Michael Turquette wrote: >> Hi Jerome, >> >> Quoting Jerome Brunet (2017-09-24 22:00:29) >> > @@ -1778,6 +1867,50 @@ int clk_set

Re: [PATCH v4 09/10] clk: add clk_rate_exclusive api

Hi Jérôme, On Tue, Oct 31, 2017 at 5:29 PM, Jerome Brunet wrote: > On Thu, 2017-10-26 at 07:26 +0200, Michael Turquette wrote: >> Hi Jerome, >> >> Quoting Jerome Brunet (2017-09-24 22:00:29) >> > @@ -1778,6 +1867,50 @@ int clk_set_rate(struct clk

Re: [PATCH v4 09/10] clk: add clk_rate_exclusive api

Hi Jerome, Quoting Jerome Brunet (2017-09-24 22:00:29) > @@ -1778,6 +1867,50 @@ int clk_set_rate(struct clk *clk, unsigned long rate) > EXPORT_SYMBOL_GPL(clk_set_rate); > > /** > + * clk_set_rate_exclusive - specify a new rate get exclusive control > + * @clk: the clk whose rate is being

Re: [PATCH v4 09/10] clk: add clk_rate_exclusive api

Hi Jerome, Quoting Jerome Brunet (2017-09-24 22:00:29) > @@ -1778,6 +1867,50 @@ int clk_set_rate(struct clk *clk, unsigned long rate) > EXPORT_SYMBOL_GPL(clk_set_rate); > > /** > + * clk_set_rate_exclusive - specify a new rate get exclusive control > + * @clk: the clk whose rate is being

Re: [PATCH v3 1/3] interconnect: Add generic on-chip interconnect API

Hi all, On Fri, Oct 20, 2017 at 3:34 PM, Bjorn Andersson wrote: > On Fri 20 Oct 07:43 PDT 2017, Georgi Djakov wrote: > >> Hi, >> >> On 09/08/2017 08:18 PM, Georgi Djakov wrote: >> > This patch introduce a new API to get requirements and configure the >> > interconnect

Re: [PATCH v3 1/3] interconnect: Add generic on-chip interconnect API

Hi all, On Fri, Oct 20, 2017 at 3:34 PM, Bjorn Andersson wrote: > On Fri 20 Oct 07:43 PDT 2017, Georgi Djakov wrote: > >> Hi, >> >> On 09/08/2017 08:18 PM, Georgi Djakov wrote: >> > This patch introduce a new API to get requirements and configure the >> > interconnect buses across the entire

Re: [PATCH v2 0/7] Improve ap806 clk support on Marvell Armada 7K/8K

Hi Gregory, Quoting Gregory CLEMENT (2017-05-31 23:07:21) > Hi, > > This series modifies the device tree binding of the clock of the AP806 > part that we find in the Marvell Armada 7K/8K SoCs. > > As for the previsous series the only change in this second version is > about the binding

Re: [PATCH v2 0/7] Improve ap806 clk support on Marvell Armada 7K/8K

Hi Gregory, Quoting Gregory CLEMENT (2017-05-31 23:07:21) > Hi, > > This series modifies the device tree binding of the clock of the AP806 > part that we find in the Marvell Armada 7K/8K SoCs. > > As for the previsous series the only change in this second version is > about the binding

Re: [PATCH 3/6] gpio: dt-bindings: Add documentation for gpio controllers on Armada 7K/8K

Quoting Rob Herring (2017-05-31 07:23:58) > On Mon, May 29, 2017 at 10:08:16AM +0200, Linus Walleij wrote: > > On Tue, May 23, 2017 at 3:06 PM, Gregory CLEMENT > > wrote: > > > On mar., mai 23 2017, Linus Walleij wrote: > > > > >>

Re: [PATCH 3/6] gpio: dt-bindings: Add documentation for gpio controllers on Armada 7K/8K

Quoting Rob Herring (2017-05-31 07:23:58) > On Mon, May 29, 2017 at 10:08:16AM +0200, Linus Walleij wrote: > > On Tue, May 23, 2017 at 3:06 PM, Gregory CLEMENT > > wrote: > > > On mar., mai 23 2017, Linus Walleij wrote: > > > > >> Please rebase and resend the rest of the patches. > > > > > >

Re: [PATCH v4 03/11] clk: bcm: Add clocks for Stingray SOC

Hello Anup, Quoting Anup Patel (2017-05-22 04:58:19) > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include Are all of those headers really needed? > +CLK_OF_DECLARE(sr_genpll3_clk, "brcm,sr-genpll3", > +

Re: [PATCH v4 03/11] clk: bcm: Add clocks for Stingray SOC

Hello Anup, Quoting Anup Patel (2017-05-22 04:58:19) > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include Are all of those headers really needed? > +CLK_OF_DECLARE(sr_genpll3_clk, "brcm,sr-genpll3", > +

Re: [PATCH] MAINTAINERS: Add maintainers for the meson clock driver

Quoting Jerome Brunet (2017-03-31 12:14:17) > Suggested-by: Michael Turquette <mturque...@baylibre.com> > Cc: Kevin Hilman <khil...@baylibre.com>, > Signed-off-by: Jerome Brunet <jbru...@baylibre.com> > Signed-off-by: Neil Armstrong <narmstr...@baylibre

Re: [PATCH] MAINTAINERS: Add maintainers for the meson clock driver

Quoting Jerome Brunet (2017-03-31 12:14:17) > Suggested-by: Michael Turquette > Cc: Kevin Hilman , > Signed-off-by: Jerome Brunet > Signed-off-by: Neil Armstrong > --- > > Hi Mike, Stephen, > > If this is OK with you, this will be the first patch of our upcoming pu

Re: [PATCH v3 1/4] dt-bindings: clock: gxbb: expose UART clocks

Quoting Helmut Klein (2017-03-31 18:54:34) > Expose the clock ids of the three none AO uarts to the dt-bindings > > Signed-off-by: Helmut Klein <hgkr.kl...@gmail.com> Acked-by: Michael Turquette <mturque...@baylibre.com> > --- > drivers/clk/meson/gxbb.h

Re: [PATCH v3 1/4] dt-bindings: clock: gxbb: expose UART clocks

Quoting Helmut Klein (2017-03-31 18:54:34) > Expose the clock ids of the three none AO uarts to the dt-bindings > > Signed-off-by: Helmut Klein Acked-by: Michael Turquette > --- > drivers/clk/meson/gxbb.h | 6 +++--- > include/dt-bindings/clock/gxbb-clkc.h

Re: [PATCH v1 0/8] clk: meson: gxbb: more clock controller update for audio support

a new clock divider driver to implement the necessary > policy for the i2s master clock (see patch changelog) > > This patchset has been test on the gxbb p200 and gxl p230. First off, this series looks fine to me. Please add, Acked-by: Michael Turquette <mturque...@baylibre.com

Re: [PATCH v1 0/8] clk: meson: gxbb: more clock controller update for audio support

a new clock divider driver to implement the necessary > policy for the i2s master clock (see patch changelog) > > This patchset has been test on the gxbb p200 and gxl p230. First off, this series looks fine to me. Please add, Acked-by: Michael Turquette Secondly, it seems the AmLo

Re: [PATCH v2 0/5] clk: meson: Fix GXBB and GXL/GXM GP0 PLL

Hi Neil, Quoting Neil Armstrong (2017-03-22 03:32:22) > This patchset fixes support for the Amlogic GXBB then GXL/GXM embedded GP0 > PLL. > > The current support is done via a very generic interface where only the > N/M/OD parameters are changed in the control registers. > > But unlike the

Re: [PATCH v2 0/5] clk: meson: Fix GXBB and GXL/GXM GP0 PLL

Hi Neil, Quoting Neil Armstrong (2017-03-22 03:32:22) > This patchset fixes support for the Amlogic GXBB then GXL/GXM embedded GP0 > PLL. > > The current support is done via a very generic interface where only the > N/M/OD parameters are changed in the control registers. > > But unlike the

Re: [PATCH v4 3/3] ARM64: dts: meson-gx: Add MALI nodes for GXBB and GXL

Quoting Kevin Hilman (2017-03-24 12:20:31) > Neil Armstrong writes: > > > The same MALI-450 MP3 GPU is present in the GXBB and GXL SoCs. > > > > The node is simply added in the meson-gxbb.dtsi file. > > > > For GXL, since a lot is shared with the GXM that has a MALI-T820

Re: [PATCH v4 3/3] ARM64: dts: meson-gx: Add MALI nodes for GXBB and GXL

Quoting Kevin Hilman (2017-03-24 12:20:31) > Neil Armstrong writes: > > > The same MALI-450 MP3 GPU is present in the GXBB and GXL SoCs. > > > > The node is simply added in the meson-gxbb.dtsi file. > > > > For GXL, since a lot is shared with the GXM that has a MALI-T820 IP, this > > patch adds

Re: [PATCH v2 0/9] clk: meson: update clock controller for audio support

Quoting Kevin Hilman (2017-03-10 16:39:27) > Jerome Brunet writes: > > > This patchset is a first round of update to the meson clock controllers > > to bring audio support. The patchset is based on clk-next. It could be > > rebased on amlogic tree later on, if you prefer

Re: [PATCH v2 0/9] clk: meson: update clock controller for audio support

Quoting Kevin Hilman (2017-03-10 16:39:27) > Jerome Brunet writes: > > > This patchset is a first round of update to the meson clock controllers > > to bring audio support. The patchset is based on clk-next. It could be > > rebased on amlogic tree later on, if you prefer the patches to go

Re: [PATCH 3/5] clk: meson-gxbb: Add GXL/GXM GP0 Variant

Quoting Neil Armstrong (2017-03-22 02:22:57) > On 03/22/2017 12:49 AM, Michael Turquette wrote: > > Hi Neil, > > > > Quoting Neil Armstrong (2017-03-13 06:26:42) > >> @@ -821,6 +893,7 @@ struct pll_params_table gxbb_gp0_params_table[] = { > >>

Re: [PATCH 3/5] clk: meson-gxbb: Add GXL/GXM GP0 Variant

Quoting Neil Armstrong (2017-03-22 02:22:57) > On 03/22/2017 12:49 AM, Michael Turquette wrote: > > Hi Neil, > > > > Quoting Neil Armstrong (2017-03-13 06:26:42) > >> @@ -821,6 +893,7 @@ struct pll_params_table gxbb_gp0_params_table[] = { > >>

Re: [PATCH v3 2/3] clk: meson-gxbb: Add MALI clocks

Quoting Neil Armstrong (2017-03-22 02:14:40) > On 03/22/2017 12:31 AM, Michael Turquette wrote: > > Hi Neil, > > > > Quoting Neil Armstrong (2017-03-09 04:53:46) > >> The Mali is clocked by two identical clock paths behind a glitch free mux > >> t

Re: [PATCH v3 2/3] clk: meson-gxbb: Add MALI clocks

Quoting Neil Armstrong (2017-03-22 02:14:40) > On 03/22/2017 12:31 AM, Michael Turquette wrote: > > Hi Neil, > > > > Quoting Neil Armstrong (2017-03-09 04:53:46) > >> The Mali is clocked by two identical clock paths behind a glitch free mux > >> t

Re: [RFC v0 1/2] interconnect: Add generic interconnect controller API

Hi Georgi, Quoting Georgi Djakov (2017-03-01 10:22:34) > diff --git a/Documentation/devicetree/bindings/interconnect/interconnect.txt > b/Documentation/devicetree/bindings/interconnect/interconnect.txt > new file mode 100644 > index ..c62d86e4c52d > --- /dev/null > +++

Re: [RFC v0 1/2] interconnect: Add generic interconnect controller API

Hi Georgi, Quoting Georgi Djakov (2017-03-01 10:22:34) > diff --git a/Documentation/devicetree/bindings/interconnect/interconnect.txt > b/Documentation/devicetree/bindings/interconnect/interconnect.txt > new file mode 100644 > index ..c62d86e4c52d > --- /dev/null > +++

Re: [PATCH 3/5] clk: meson-gxbb: Add GXL/GXM GP0 Variant

Hi Neil, Quoting Neil Armstrong (2017-03-13 06:26:42) > @@ -821,6 +893,7 @@ struct pll_params_table gxbb_gp0_params_table[] = { > _hdmi_pll, > _sys_pll, > _gp0_pll, > + _gp0_pll, Is there a reason for adding the pointer to this array here? It seems to me that the

Re: [PATCH 3/5] clk: meson-gxbb: Add GXL/GXM GP0 Variant

Hi Neil, Quoting Neil Armstrong (2017-03-13 06:26:42) > @@ -821,6 +893,7 @@ struct pll_params_table gxbb_gp0_params_table[] = { > _hdmi_pll, > _sys_pll, > _gp0_pll, > + _gp0_pll, Is there a reason for adding the pointer to this array here? It seems to me that the

Re: [PATCH 1/5] clk: meson: Add support for parameters for specific PLLs

Quoting Neil Armstrong (2017-03-13 06:26:40) > In recent Amlogic GXBB, GXL and GXM SoCs, the GP0 PLL needs some specific > parameters in order to initialize and lock correctly. > > This patch adds an optional PARAM table used to initialize the PLL to a > default value with it's parameters in

Re: [PATCH 1/5] clk: meson: Add support for parameters for specific PLLs

Quoting Neil Armstrong (2017-03-13 06:26:40) > In recent Amlogic GXBB, GXL and GXM SoCs, the GP0 PLL needs some specific > parameters in order to initialize and lock correctly. > > This patch adds an optional PARAM table used to initialize the PLL to a > default value with it's parameters in

Re: [PATCH v2 6/9] clk: meson: gxbb: mpll: use rw operation

Quoting Jerome Brunet (2017-03-09 02:41:51) > Use read/write operations for the mpll clocks instead of the > read-only ones. > > Signed-off-by: Jerome Brunet Looks good to me. Regards, Mike > --- > drivers/clk/meson/gxbb.c | 6 +++--- > 1 file changed, 3 insertions(+),

Re: [PATCH v2 6/9] clk: meson: gxbb: mpll: use rw operation

Quoting Jerome Brunet (2017-03-09 02:41:51) > Use read/write operations for the mpll clocks instead of the > read-only ones. > > Signed-off-by: Jerome Brunet Looks good to me. Regards, Mike > --- > drivers/clk/meson/gxbb.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > >

Re: [PATCH v3 2/3] clk: meson-gxbb: Add MALI clocks

Hi Neil, Quoting Neil Armstrong (2017-03-09 04:53:46) > The Mali is clocked by two identical clock paths behind a glitch free mux > to safely change frequency while running. > > The two "mali_0" and "mali_1" clocks are composed of a mux, divider and gate. > Expose these two clocks trees using

Re: [PATCH v3 2/3] clk: meson-gxbb: Add MALI clocks

Hi Neil, Quoting Neil Armstrong (2017-03-09 04:53:46) > The Mali is clocked by two identical clock paths behind a glitch free mux > to safely change frequency while running. > > The two "mali_0" and "mali_1" clocks are composed of a mux, divider and gate. > Expose these two clocks trees using

Re: [PATCH v2 7/9] clk: meson8b: add the mplls clocks 0, 1 and 2

Quoting Jerome Brunet (2017-03-09 02:41:52) > Signed-off-by: Jerome Brunet Hmm, even for obvious patches like this it is still better to have some sort of changelog :-/ Otherwise patch appears fine to me. Regards, Mike > --- > drivers/clk/meson/meson8b.c | 103 >

Re: [PATCH v2 3/9] clk: meson8b: put dividers and muxes in tables

Quoting Jerome Brunet (2017-03-09 02:41:48) > Until now, there was only 1 divider and 1 mux declared for the meson8b > platform. With the ongoing work on various system, including audio, this > is about to change. Use the same approach as gates for dividers and muxes, > putting them in tables to

Re: [PATCH v2 5/9] clk: meson: mpll: add rw operation

Quoting Jerome Brunet (2017-03-09 02:41:50) > This patch adds new callbacks to the meson-mpll driver to control > and set the pll rate. For this, we also need to add the enable bit and > sdm enable bit. The corresponding parameters are added to mpll data > structure. > > Signed-off-by: Jerome

Re: [PATCH v3 1/3] clk: meson-gxbb: Add MALI clock IDS

Quoting Neil Armstrong (2017-03-09 04:53:45) > Add missing MALI clock IDs and expose the muxes and gates in the dt-bindings. > > Signed-off-by: Neil Armstrong Looks good to me. Regards, Mike > --- > drivers/clk/meson/gxbb.h | 9 - >

Re: [PATCH v2 7/9] clk: meson8b: add the mplls clocks 0, 1 and 2

Quoting Jerome Brunet (2017-03-09 02:41:52) > Signed-off-by: Jerome Brunet Hmm, even for obvious patches like this it is still better to have some sort of changelog :-/ Otherwise patch appears fine to me. Regards, Mike > --- > drivers/clk/meson/meson8b.c | 103 >

Re: [PATCH v2 3/9] clk: meson8b: put dividers and muxes in tables

Quoting Jerome Brunet (2017-03-09 02:41:48) > Until now, there was only 1 divider and 1 mux declared for the meson8b > platform. With the ongoing work on various system, including audio, this > is about to change. Use the same approach as gates for dividers and muxes, > putting them in tables to

Re: [PATCH v2 5/9] clk: meson: mpll: add rw operation

Quoting Jerome Brunet (2017-03-09 02:41:50) > This patch adds new callbacks to the meson-mpll driver to control > and set the pll rate. For this, we also need to add the enable bit and > sdm enable bit. The corresponding parameters are added to mpll data > structure. > > Signed-off-by: Jerome

Re: [PATCH v3 1/3] clk: meson-gxbb: Add MALI clock IDS

Quoting Neil Armstrong (2017-03-09 04:53:45) > Add missing MALI clock IDs and expose the muxes and gates in the dt-bindings. > > Signed-off-by: Neil Armstrong Looks good to me. Regards, Mike > --- > drivers/clk/meson/gxbb.h | 9 - > include/dt-bindings/clock/gxbb-clkc.h

  1   2   3   4   5   6   7   >