On 4/11/21 7:14 PM, Jens Axboe wrote:
On 4/11/21 4:34 PM, Stephen Rothwell wrote:
Hi all,
Commit
6fa6517fe62e ("ata: ahci_tegra: call tegra_powergate_power_off only when PM
domain is not present")
is missing a Signed-off-by from its author.
Sowjana, please reply that you're OK with me
This patch adds check to call legacy power domain API
tegra_powergate_power_off() only when PM domain is not present.
This is a follow-up patch to Tegra186 AHCI support patch series.
---
drivers/ata/ahci_tegra.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
This includes a follow up patch to Tegra186 AHCI support patch series
https://lore.kernel.org/patchwork/cover/1408752/
Delta between patch versions:
[v2]: v1 has missing PM domain check in error path. Fixed in v2.
Sowjanya Komatineni (1):
ata: ahci_tegra: call tegra_powergate_power_off only
On 4/8/21 12:58 PM, Dmitry Osipenko wrote:
08.04.2021 19:40, Sowjanya Komatineni пишет:
This patch adds a check on present of PM domain and calls legacy power
domain API tegra_powergate_power_off() only when PM domain is not present.
This is a follow-up patch to Tegra186 AHCI support patch
This patch adds a check on present of PM domain and calls legacy power
domain API tegra_powergate_power_off() only when PM domain is not present.
This is a follow-up patch to Tegra186 AHCI support patch series
https://lore.kernel.org/patchwork/cover/1408752/
Signed-off-by: Sowjanya Komatineni
This includes a follow up patch to Tegra186 AHCI support patch series
https://lore.kernel.org/patchwork/cover/1408752/
Sowjanya Komatineni (1):
ata: ahci_tegra: call tegra_powergate_power_off only when PM domain is
not present
drivers/ata/ahci_tegra.c | 3 ++-
1 file changed, 2
On 4/7/21 3:57 PM, Sowjanya Komatineni wrote:
On 4/7/21 2:36 PM, Dmitry Osipenko wrote:
07.04.2021 04:25, Sowjanya Komatineni пишет:
+ if (!tegra->pdev->dev.pm_domain) {
+ ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
+ tegra->
On 4/7/21 2:36 PM, Dmitry Osipenko wrote:
07.04.2021 04:25, Sowjanya Komatineni пишет:
+ if (!tegra->pdev->dev.pm_domain) {
+ ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
+ tegra->
This patch converts text based dt-binding document to YAML based
dt-binding document.
Reviewed-by: Rob Herring
Signed-off-by: Sowjanya Komatineni
---
.../devicetree/bindings/ata/nvidia,tegra-ahci.yaml | 138 +
.../bindings/ata/nvidia,tegra124-ahci.txt | 44
This patch adds dt-bindings documentation for Tegra186 AHCI
controller.
Reviewed-by: Rob Herring
Signed-off-by: Sowjanya Komatineni
---
.../devicetree/bindings/ata/nvidia,tegra-ahci.yaml | 38 ++
1 file changed, 38 insertions(+)
diff --git a/Documentation/devicetree
to
SoC specific strcuture tegra_ahci_soc and updated their implementation
accordingly.
Signed-off-by: Sowjanya Komatineni
---
drivers/ata/ahci_tegra.c | 60 +---
1 file changed, 47 insertions(+), 13 deletions(-)
diff --git a/drivers/ata/ahci_tegra.c b
[v2]: v1 feedback related to yaml dt-binding.
Removed conditional reset order in yaml and updated dts files
to maintain same order for commonly available resets across
Tegra124 thru Tegra186.
Sowjanya Komatineni (3):
dt-bindings: ata: tegra: Convert binding documentation
On 3/16/21 12:18 AM, Sudeep Holla wrote:
On Mon, Mar 15, 2021 at 11:13:24AM -0700, Sowjanya Komatineni wrote:
Hi Sudeep,
I see you are one of the maintainer of PSCI driver. Please add any other
right persons if you think should also agree/comment.
Can you please comment on below 2 items
Re-sending as it went out as HTML instead of plain text.
On 3/15/21 11:13 AM, Sowjanya Komatineni wrote:
Hi Sudeep,
I see you are one of the maintainer of PSCI driver. Please add any
other right persons if you think should also agree/comment.
Can you please comment on below 2 items based
On 3/10/21 6:52 PM, Sudeep Holla wrote:
On Mon, Mar 08, 2021 at 10:32:17AM -0800, Sowjanya Komatineni wrote:
On 3/7/21 8:37 PM, Sudeep Holla wrote:
On Wed, Mar 03, 2021 at 10:08:10PM -0800, Sowjanya Komatineni wrote:
This patch adds cpu-idle-states and corresponding state nodes to
Tegra194
On 3/8/21 10:32 AM, Sowjanya Komatineni wrote:
On 3/7/21 8:37 PM, Sudeep Holla wrote:
On Wed, Mar 03, 2021 at 10:08:10PM -0800, Sowjanya Komatineni wrote:
This patch adds cpu-idle-states and corresponding state nodes to
Tegra194 CPU in dt-binding document
I see that this platform has PSCI
On 3/7/21 8:37 PM, Sudeep Holla wrote:
On Wed, Mar 03, 2021 at 10:08:10PM -0800, Sowjanya Komatineni wrote:
This patch adds cpu-idle-states and corresponding state nodes to
Tegra194 CPU in dt-binding document
I see that this platform has PSCI support. Can you care to explain why
you need
Add Tegra CPUIDLE driver section with maintainers and mailing list
entries.
Signed-off-by: Sowjanya Komatineni
---
MAINTAINERS | 12
1 file changed, 12 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index cac8429..277fcfd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4679,6
This patch adds CPU core and cluster idle states to Tegra194
device tree
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot
tasks and states information provided by
CPU idle driver.
CPU idle driver provides deepest cluster power state, core power
state transition request, estimated time of next wake-up and states
crossover thresholds to MCE firmware through Tegra mce driver.
Signed-off-by: Sowjanya Komatineni
---
drivers
This patch adds cpu-idle-states and corresponding state nodes to
Tegra194 CPU in dt-binding document
Signed-off-by: Sowjanya Komatineni
---
.../bindings/arm/nvidia,tegra194-ccplex.yaml | 53 ++
1 file changed, 53 insertions(+)
diff --git a/Documentation/devicetree
-by: Sowjanya Komatineni
---
drivers/firmware/tegra/Kconfig| 11 +++
drivers/firmware/tegra/Makefile | 4 +
drivers/firmware/tegra/mce-tegra194.c | 155 ++
drivers/firmware/tegra/mce.c | 88 +++
include/soc/tegra/mce.h
-bindings for Tegra194 cpu idle states
- Add cpuidle driver to support Tegra194 CPUs idle state management
- Update Tegra194 device tree with cpuidle support to Tegra194 CPUs.
Sowjanya Komatineni (5):
MAINTAINERS: Add Tegra CPUIDLE driver section
firmware: tegra: Add Tegra194 MCE ARI driver
dt
-by: Sowjanya Komatineni
---
drivers/i2c/busses/i2c-tegra.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 6f08c0c..4a27782 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c
().
Sowjanya Komatineni (1):
i2c: tegra: Create i2c_writesl_vi() to use with VI I2C for filling TX
FIFO
drivers/i2c/busses/i2c-tegra.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
--
2.7.4
On 1/11/21 9:56 PM, Dmitry Osipenko wrote:
12.01.2021 07:06, Sowjanya Komatineni пишет:
VI I2C don't have DMA support and uses PIO mode all the time.
Current driver uses writesl() to fill TX FIFO based on available
empty slots and with this seeing strange silent hang during any I2C
register
On 1/12/21 1:32 AM, David Laight wrote:
From: Sowjanya Komatineni
Sent: 11 January 2021 17:38
...
Using writesl() for filling TX_FIFO causing silent hang immediate on any
i2c register access after filling FIFO with 8 words and some times with
6 words as well.
So couldn't INTERRUPT_STATUS
to write all words
to TX FIFO instead of using writesl() helps for large transfers in
PIO mode.
So, this patch creates i2c_writesl_vi() API to use with VI I2C for
filling TX FIFO.
Signed-off-by: Sowjanya Komatineni
---
drivers/i2c/busses/i2c-tegra.c | 20 +++-
1 file changed, 19
Patch in this series is to fix silent hang seen when using writesl()
for filling VI I2C TX FIFO.
Delta between patch versions:
[v2]: Creates i2c_writesl_vi() for vi i2c based on v1 feedback.
[v1]: Updates i2c_writesl() to use writel() followed by i2c_readl().
Sowjanya Komatineni (1):
i2c
On 1/11/21 11:29 AM, Dmitry Osipenko wrote:
11.01.2021 20:38, Sowjanya Komatineni пишет:
On 1/11/21 4:09 AM, Dmitry Osipenko wrote:
11.01.2021 14:50, Dmitry Osipenko пишет:
20.10.2020 19:37, Sowjanya Komatineni пишет:
On 10/20/20 12:48 AM, Thierry Reding wrote:
On Mon, Oct 19, 2020 at 09
On 1/11/21 4:09 AM, Dmitry Osipenko wrote:
11.01.2021 14:50, Dmitry Osipenko пишет:
20.10.2020 19:37, Sowjanya Komatineni пишет:
On 10/20/20 12:48 AM, Thierry Reding wrote:
On Mon, Oct 19, 2020 at 09:03:54PM -0700, Sowjanya Komatineni wrote:
VI I2C don't have DMA support and uses PIO mode
On 12/31/20 10:33 AM, Rob Herring wrote:
On Mon, 21 Dec 2020 13:17:32 -0800, Sowjanya Komatineni wrote:
This patch adds YAML based device tree binding document for Tegra
Quad SPI driver.
Signed-off-by: Sowjanya Komatineni
---
.../bindings/spi/nvidia,tegra210-quad.yaml | 117
This patch enables QSPI on Jetson Xavier NX.
Signed-off-by: Sowjanya Komatineni
---
.../arm64/boot/dts/nvidia/tegra194-p3509-+p3668-.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-+p3668-.dts
b/arch/arm64/boot/dts
This patch enables QSPI on Jetson Nano.
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra210-p3450-.dts | 12
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++--
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts
Tegra194 has 2 QSPI controllers.
This patch adds DT node for these 2 QSPI controllers.
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b
hardware maximum dummy
cycles limit, driver transfers dummy bytes from the software.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra210-quad.c | 34 +++---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-tegra210-quad.c b
This patch marks dummy transfer by setting dummy_data bit to 1.
Controllers supporting dummy transfer by hardware use this bit field
to skip software transfer of dummy bytes and use hardware dummy bytes
transfer.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-mem.c | 1 +
include
Tegra SoC has a Quad SPI controller starting from Tegra210.
This patch adds support for Tegra210 QSPI controller.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/Kconfig |9 +
drivers/spi/Makefile|1 +
drivers/spi/spi-tegra210-quad.c | 1382
Add maintainers and mailing list entries to Tegra Quad SPI driver
section.
Signed-off-by: Sowjanya Komatineni
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5b20bab..19db61f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17447,6
This patch adds YAML based device tree binding document for Tegra
Quad SPI driver.
Signed-off-by: Sowjanya Komatineni
---
.../bindings/spi/nvidia,tegra210-quad.yaml | 117 +
1 file changed, 117 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spi
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
when using DDR interface mode.
This patch adds clock ID for this to dt-binding.
Acked-by: Rob Herring
Signed-off-by: Sowjanya Komatineni
---
include/dt-bindings/clock/tegra210-car.h | 2 +-
1 file changed, 1 insertion(+), 1
feedback on some cleanup.
Sowjanya Komatineni (9):
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
dt-bindings: spi: Add Tegra Quad SPI device tree binding
MAINTAINERS: Add Tegra Quad SPI driver section
spi: tegra210-quad: Add support for Tegra210 QSPI controller
spi: spi
On 12/18/20 12:44 PM, Mark Brown wrote:
On Fri, Dec 18, 2020 at 08:41:02PM +, Mark Brown wrote:
On Sat, Dec 19, 2020 at 12:49:38AM +0530, Pratyush Yadav wrote:
Anyway, if the SPI maintainers think this is worth it, I won't object.
This gets kind of circular, for me it's a question of if
On 12/18/20 1:57 AM, Boris Brezillon wrote:
On Fri, 18 Dec 2020 14:51:08 +0530
Pratyush Yadav wrote:
Hi Sowjanya,
On 17/12/20 12:28PM, Sowjanya Komatineni wrote:
This patch marks dummy transfer by setting dummy_data bit to 1.
Controllers supporting dummy transfer by hardware use this bit
This patch enables QSPI on Jetson Nano.
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra210-p3450-.dts | 12
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++--
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
when using DDR interface mode.
This patch adds clock ID for this to dt-binding.
Acked-by: Rob Herring
Signed-off-by: Sowjanya Komatineni
---
include/dt-bindings/clock/tegra210-car.h | 2 +-
1 file changed, 1 insertion(+), 1
This patch enables QSPI on Jetson Xavier NX.
Signed-off-by: Sowjanya Komatineni
---
.../arm64/boot/dts/nvidia/tegra194-p3509-+p3668-.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-+p3668-.dts
b/arch/arm64/boot/dts
Tegra194 has 2 QSPI controllers.
This patch adds DT node for these 2 QSPI controllers.
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b
This patch marks dummy transfer by setting dummy_data bit to 1.
Controllers supporting dummy transfer by hardware use this bit field
to skip software transfer of dummy bytes and use hardware dummy bytes
transfer.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-mem.c | 1 +
include
Add maintainers and mailing list entries to Tegra Quad SPI driver
section.
Signed-off-by: Sowjanya Komatineni
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5b20bab..19db61f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17447,6
transfer from software for
these controllers.
- Updated dt-binding doc with tx/rx tap delay properties.
- Added qspi_out clock to dt-binding doc which will be used later with
ddr mode support.
- All other v1 feedback on some cleanup.
Sowjanya Komatineni
Tegra SoC has a Quad SPI controller starting from Tegra210.
This patch adds support for Tegra210 QSPI controller.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/Kconfig |9 +
drivers/spi/Makefile|1 +
drivers/spi/spi-tegra210-quad.c | 1382
hardware maximum dummy
cycles limit, driver transfers dummy bytes from the software.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra210-quad.c | 41 -
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-tegra210-quad.c b
This patch adds YAML based device tree binding document for Tegra
Quad SPI driver.
Signed-off-by: Sowjanya Komatineni
---
.../bindings/spi/nvidia,tegra210-quad.yaml | 117 +
1 file changed, 117 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spi
On 12/13/20 3:28 AM, Boris Brezillon wrote:
On Sun, 13 Dec 2020 10:54:26 +0100
Boris Brezillon wrote:
On Sat, 12 Dec 2020 09:28:50 -0800
Sowjanya Komatineni wrote:
On 12/12/20 2:57 AM, Boris Brezillon wrote:
On Fri, 11 Dec 2020 13:15:59 -0800
Sowjanya Komatineni wrote:
This patch
On 12/12/20 2:57 AM, Boris Brezillon wrote:
On Fri, 11 Dec 2020 13:15:59 -0800
Sowjanya Komatineni wrote:
This patch adds a flag SPI_MASTER_USES_HW_DUMMY_CYCLES for the controllers
that support transfer of dummy cycles by the hardware directly.
Hm, not sure this is a good idea. I mean
This patch enables QSPI on Jetson Xavier NX.
Signed-off-by: Sowjanya Komatineni
---
.../arm64/boot/dts/nvidia/tegra194-p3509-+p3668-.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-+p3668-.dts
b/arch/arm64/boot/dts
from spi_message.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-mem.c | 18 +++---
include/linux/spi/spi.h | 8
2 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index f3a3f19..38a523b 100644
--- a/drivers
Tegra Quad SPI controller hardware supports sending dummy cycles
after address bytes.
This patch adds this support.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra210-quad.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi
Add maintainers and mailing list entries to Tegra Quad SPI driver
section.
Signed-off-by: Sowjanya Komatineni
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5b20bab..19db61f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17447,6
.
- All other v1 feedback on some cleanup.
Sowjanya Komatineni (9):
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
dt-bindings: spi: Add Tegra Quad SPI device tree binding
MAINTAINERS: Add Tegra Quad SPI driver section
spi: tegra210-quad: Add support for Tegra210 QSPI
Tegra194 has 2 QSPI controllers.
This patch adds DT node for these 2 QSPI controllers.
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch
This patch enables QSPI on Jetson Nano.
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra210-p3450-.dts | 12
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++--
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts
Tegra SoC has a Quad SPI controller starting from Tegra210.
This patch adds support for Tegra210 QSPI controller.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/Kconfig |9 +
drivers/spi/Makefile|1 +
drivers/spi/spi-tegra210-quad.c | 1387
This patch adds YAML based device tree binding document for Tegra
Quad SPI driver.
Signed-off-by: Sowjanya Komatineni
---
.../bindings/spi/nvidia,tegra210-quad.yaml | 130 +
1 file changed, 130 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spi
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
when using DDR interface mode.
This patch adds clock ID for this to dt-binding.
Signed-off-by: Sowjanya Komatineni
---
include/dt-bindings/clock/tegra210-car.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Sorry rob, mixed patches went out accidentally.
Will resend v2
On 12/11/20 12:56 PM, Rob Herring wrote:
On Fri, 11 Dec 2020 09:01:20 -0800, Sowjanya Komatineni wrote:
This patch adds YAML based device tree binding document for Tegra
Quad SPI driver.
Signed-off-by: Sowjanya Komatineni
Sorry mark mixed patches went out.
Will resend v2 and will add other people you have CC'd as well
On 12/11/20 10:33 AM, Mark Brown wrote:
On Fri, Dec 11, 2020 at 09:01:24AM -0800, Sowjanya Komatineni wrote:
This patch adds a flag SPI_MASTER_USES_HW_DUMMY_CYCLES for the controllers
in gang are configured together during the corresponding
video device node streaming for x8 captures.
x8 capture with gang ports are supported with HDMI-to-CSI bridges
where they split 4K image into left half onto one x4 port and
right half onto second x4 port.
Signed-off-by: Sowjanya Komatineni
from spi_message.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-mem.c | 18 +++---
include/linux/spi/spi.h | 8
2 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index f3a3f19..38a523b 100644
--- a/drivers
is not
allowed and Tegra video driver calls vb2_queue_error to signal a
fatal error if a notification of this event happens during an active
streaming.
Signed-off-by: Sowjanya Komatineni
---
drivers/staging/media/tegra-video/vi.c| 3 +++
drivers/staging/media/tegra-video/video.c | 18
-by: Sowjanya Komatineni
---
drivers/staging/media/tegra-video/tegra210.c | 10 +-
drivers/staging/media/tegra-video/vi.c | 26 +-
drivers/staging/media/tegra-video/vi.h | 4
3 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/staging
This patch adds support for log_status ioctl.
Signed-off-by: Sowjanya Komatineni
---
drivers/staging/media/tegra-video/vi.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/staging/media/tegra-video/vi.c
b/drivers/staging/media/tegra-video/vi.c
index bc38136..c280117
+ additional patch for x8 capture support
Sowjanya Komatineni (13):
media: tegra-video: Use zero crop settings if subdev has no
get_selection
media: tegra-video: Enable VI pixel transform for YUV and RGB formats
media: tegra-video: Fix V4L2 pixel format RGB and YUV
media: tegra-video: Add
Some CSI2 receivers support 8 data lanes.
So, this patch updates CSI2 maximum data lanes to be 8.
Acked-by: Sakari Ailus
Signed-off-by: Sowjanya Komatineni
---
include/media/v4l2-fwnode.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/media/v4l2-fwnode.h b/include
lanes.
Acked-by: Rob Herring
Acked-by: Sakari Ailus
Signed-off-by: Sowjanya Komatineni
---
.../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20
Current implementation uses v4l2_ctrl_subscribe_event() and this
does not handle V4L2_EVENT_SOURCE_CHANGE.
So, update driver to handle V4L2_EVENT_SOURCE_CHANGE.
Signed-off-by: Sowjanya Komatineni
---
drivers/staging/media/tegra-video/vi.c | 14 +-
1 file changed, 13 insertions
V4L2 pixel format is incorrect for RGB and YUV formats.
This patch fixes it.
Signed-off-by: Sowjanya Komatineni
---
drivers/staging/media/tegra-video/tegra210.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/media/tegra-video/tegra210
-off-by: Sowjanya Komatineni
---
drivers/staging/media/tegra-video/tegra210.c | 13 +
drivers/staging/media/tegra-video/vi.c | 2 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/staging/media/tegra-video/tegra210.c
b/drivers/staging/media/tegra-video/tegra210.c
index
This patch adds below v4l2 DV timing ioctls to support HDMI-to-CSI
bridges.
Signed-off-by: Sowjanya Komatineni
---
drivers/staging/media/tegra-video/vi.c | 99 ++
1 file changed, 99 insertions(+)
diff --git a/drivers/staging/media/tegra-video/vi.c
b/drivers
This patch adds support for EDID get and set v4l2 ioctl ops to use
with HDMI to CSI bridges.
Signed-off-by: Sowjanya Komatineni
---
drivers/staging/media/tegra-video/vi.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/staging/media/tegra-video/vi.c
b
to
calling get_selection ops and continues with try or set format with
zero crop settings for subdevices that don't have get_selection and
returns -EINVAL only for subdevices that has get_selection ops.
Signed-off-by: Sowjanya Komatineni
---
drivers/staging/media/tegra-video/vi.c | 17
write to
memory.
So, this patch enables pixel transform for YUV and RGB and keeps
it bypass for RAW formats.
Signed-off-by: Sowjanya Komatineni
---
drivers/staging/media/tegra-video/tegra210.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/media
Tegra194 has 2 QSPI controllers.
This patch adds DT node for these 2 QSPI controllers.
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch
This patch adds YAML based device tree binding document for Tegra
QSPI driver.
Signed-off-by: Sowjanya Komatineni
---
.../bindings/spi/nvidia,tegra210-quad.yaml | 128 +
1 file changed, 128 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spi
Add maintainers and mailing list entries to Tegra QSPI driver section.
Signed-off-by: Sowjanya Komatineni
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5b20bab..19db61f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17447,6 +17447,14
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
when using DDR interface mode.
This patch adds clock ID for this to dt-binding.
Signed-off-by: Sowjanya Komatineni
---
include/dt-bindings/clock/tegra210-car.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
This patch enables QSPI on Jetson Nano.
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra210-p3450-.dts | 12
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++--
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts
Tegra SoC has a Quad SPI controller starting from Tegra210.
This patch adds support for Tegra210 QSPI controller.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/Kconfig |9 +
drivers/spi/Makefile|1 +
drivers/spi/spi-tegra210-quad.c | 1387
for
these controllers.
- Updated dt-binding doc with tx/rx tap delay properties.
- Added qspi_out clock to dt-binding doc which will be used later with
ddr mode support.
- All other v1 feedback on some cleanup.
Sowjanya Komatineni (9):
dt-bindings: clock: tegra: Add clock ID
Tegra Quad SPI controller hardware supports sending dummy cycles
after address bytes.
This patch adds this support.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra210-quad.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi
This patch enables QSPI on Jetson Xavier NX.
Signed-off-by: Sowjanya Komatineni
---
.../arm64/boot/dts/nvidia/tegra194-p3509-+p3668-.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-+p3668-.dts
b/arch/arm64/boot/dts
This patch adds YAML based device tree binding document for Tegra
Quad SPI driver.
Signed-off-by: Sowjanya Komatineni
---
.../bindings/spi/nvidia,tegra210-quad.yaml | 130 +
1 file changed, 130 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spi
Add maintainers and mailing list entries to Tegra Quad SPI driver
section.
Signed-off-by: Sowjanya Komatineni
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5b20bab..19db61f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17447,6
On 12/9/20 12:28 PM, Sowjanya Komatineni wrote:
On 12/9/20 9:26 AM, Rob Herring wrote:
On Tue, Dec 01, 2020 at 01:12:43PM -0800, Sowjanya Komatineni wrote:
This patch adds YAML based device tree binding document for Tegra
QSPI driver.
Signed-off-by: Sowjanya Komatineni
On 12/9/20 9:26 AM, Rob Herring wrote:
On Tue, Dec 01, 2020 at 01:12:43PM -0800, Sowjanya Komatineni wrote:
This patch adds YAML based device tree binding document for Tegra
QSPI driver.
Signed-off-by: Sowjanya Komatineni
---
.../devicetree/bindings/spi/nvidia,tegra-qspi.yaml | 77
On 12/8/20 11:59 AM, Sakari Ailus wrote:
Hi Hans,
On Mon, Dec 07, 2020 at 11:47:38AM +0100, Hans Verkuil wrote:
On 03/12/2020 19:59, Sowjanya Komatineni wrote:
Some CSI2 receivers support 8 data lanes.
So, this patch updates CSI2 maximum data lanes to be 8.
Signed-off-by: Sowjanya
On 12/6/20 10:16 AM, Lukas Wunner wrote:
On Tue, Dec 01, 2020 at 01:12:44PM -0800, Sowjanya Komatineni wrote:
+ ret = devm_spi_register_master(>dev, master);
[...]
+static int tegra_qspi_remove(struct platform_device *pdev)
+{
+ struct spi_master *master = platform_get_drvd
On 12/4/20 2:46 PM, Mark Brown wrote:
On Fri, Dec 04, 2020 at 01:04:46PM -0800, Sowjanya Komatineni wrote:
On 12/4/20 10:52 AM, Mark Brown wrote:
On Thu, Dec 03, 2020 at 04:22:54PM -0800, Sowjanya Komatineni wrote:
Also unpack mode needs to manually put the bytes together from read data
Thanks Thierry. Will address below suggestions in v2.
Some inline comments below regarding client data part of controller driver.
Regards,
Sowjanya
On 12/4/20 4:11 AM, Thierry Reding wrote:
On Tue, Dec 01, 2020 at 01:12:44PM -0800, Sowjanya Komatineni wrote:
Tegra SoC has a Quad SPI
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