On 19/01/2021 01:25, Isaac Chen wrote:
> This is printed during kernel boot, match it with other supported x86 cpus.
> [0.00] KERNEL supported cpus:
> [0.00] Intel GenuineIntel
> [0.00] AMD AuthenticAMD
> [0.00] Hygon HygonGenuine
> [
On 11/01/2021 19:03, Borislav Petkov wrote:
> On Mon, Jan 11, 2021 at 06:51:59PM +0800, Tony W Wang-oc wrote:
>> This issue will be enhanced by hardware and patch submit will be pending.
>
> I have no clue what that has to do with your current patch... you might
> need to expl
On 07/01/2021 23:52, Dave Hansen wrote:
> On 1/6/21 10:19 PM, Tony W Wang-oc wrote:
>> +/*
>> + * These CPUs declare support SSE4.2 instruction sets but
>> + * having low performance CRC32C instruction implementation.
>> + */
>> +if (c-&
On 07/01/2021 14:37, Borislav Petkov wrote:
> On Thu, Jan 07, 2021 at 02:19:06PM +0800, Tony W Wang-oc wrote:
>> SSE4.2 on Zhaoxin CPUs are compatible with Intel. The presence of
>> CRC32C instruction is enumerated by CPUID.01H:ECX.SSE4_2[bit 20] = 1.
>> Some Zhaoxin CPUs d
On 03/01/2021 05:12, Herbert Xu wrote:
> On Tue, Dec 15, 2020 at 06:28:11PM +0800, Tony W Wang-oc wrote:
>> The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.
>> On platforms with Zhaoxin CPUs supporting this X86 feature, when
>> crc32c-intel and crc32c-generi
cember 16, 2020 1:56:45 AM GMT+08:00, Eric Biggers
>>>> wrote:
>>>>> On Tue, Dec 15, 2020 at 10:15:29AM +0800, Tony W Wang-oc wrote:
>>>>>>
>>>>>> On 15/12/2020 04:41, Eric Biggers wrote:
>>>>>>> On Mon, Dec 14,
to indicates low performance CRC32C instruction
implementation, set this flag in Zhaoxin CPUs specific init phase,
and exclude CPUs which setting this flag from the driver crc32c-intel.
https://lkml.org/lkml/2020/12/21/789
Tony W Wang-oc (3):
x86/cpufeatures: Add low performance CRC32C instruction CPU
Low performance CRC32C instruction CPUs expect to use the driver
crc32c-generic. So remove these CPUs support from crc32c-intel.
Signed-off-by: Tony W Wang-oc
---
arch/x86/crypto/crc32c-intel_glue.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/x86/crypto/crc32c-intel_glue.c
b
Some Zhaoxin CPUs declare support SSE4.2 instruction sets but
having a CRC32C instruction implementation that not working as
intended. Set low performance CRC32C flag on these CPUs for later
use.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/centaur.c | 7 +++
arch/x86/kernel/cpu
that the CRC32C instruction is
not working as intended. This low performance CRC32C instruction flag
is depend on X86_FEATURE_XMM4_2.
Signed-off-by: Tony W Wang-oc
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/cpuid-deps.c | 1 +
2 files changed, 2 insertions(+)
diff --git
remove these Zhaoxin CPUs support from
crc32c-intel.
Signed-off-by: Tony W Wang-oc
---
arch/x86/crypto/crc32c-intel_glue.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/x86/crypto/crc32c-intel_glue.c
b/arch/x86/crypto/crc32c-intel_glue.c
index
On 15/12/2020 16:58, Peter Zijlstra wrote:
> On Mon, Dec 14, 2020 at 11:59:52AM +0800, Tony W Wang-oc wrote:
>
> Didn't I mention something about a comment?
>
Really sorry for this.
>> static const struct x86_cpu_id crc32c_cpu_id[] = {
>> +X86_MATCH_VENDOR_
On 15/12/2020 04:41, Eric Biggers wrote:
> On Mon, Dec 14, 2020 at 10:28:19AM +0800, Tony W Wang-oc wrote:
>> On 12/12/2020 01:43, Eric Biggers wrote:
>>> On Fri, Dec 11, 2020 at 07:29:04PM +0800, Tony W Wang-oc wrote:
>>>> The driver crc32c-intel match CPUs
remove these Zhaoxin CPUs support from
crc32c-intel.
Signed-off-by: Tony W Wang-oc
---
arch/x86/crypto/crc32c-intel_glue.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/x86/crypto/crc32c-intel_glue.c
b/arch/x86/crypto/crc32c-intel_glue.c
index feccb52
On 12/12/2020 18:54, Ard Biesheuvel wrote:
> On Sat, 12 Dec 2020 at 10:36, Ard Biesheuvel wrote:
>>
>> On Fri, 11 Dec 2020 at 20:07, Eric Biggers wrote:
>>>
>>> On Fri, Dec 11, 2020 at 07:29:04PM +0800, Tony W Wang-oc wrote:
>>>>
On 12/12/2020 01:43, Eric Biggers wrote:
> On Fri, Dec 11, 2020 at 07:29:04PM +0800, Tony W Wang-oc wrote:
>> The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.
>> On platforms with Zhaoxin CPUs supporting this X86 feature, When
>> crc32c-intel and crc32c-generi
On 11/12/2020 21:00, Peter Zijlstra wrote:
> On Fri, Dec 11, 2020 at 07:29:04PM +0800, Tony W Wang-oc wrote:
>> The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.
>> On platforms with Zhaoxin CPUs supporting this X86 feature, When
>> crc32c-intel and cr
crc32c-generic driver for
some Zhaoxin CPUs to get performance gain, So remove these Zhaoxin
CPUs support from crc32c-intel.
Signed-off-by: Tony W Wang-oc
---
arch/x86/crypto/crc32c-intel_glue.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/x86/crypto/crc32c-intel_glue.c
b/arch
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: 33b4711df4c1b3aec7c267c60fc24abccfadd40c
Gitweb:
https://git.kernel.org/tip/33b4711df4c1b3aec7c267c60fc24abccfadd40c
Author:Tony W Wang-oc
AuthorDate:Tue, 08 Sep 2020 18:57:46 +08:00
Committer
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: 8687bdc04128b2bd16faaae11db10128ad0da7b8
Gitweb:
https://git.kernel.org/tip/8687bdc04128b2bd16faaae11db10128ad0da7b8
Author:Tony W Wang-oc
AuthorDate:Tue, 08 Sep 2020 18:57:45 +08:00
Committer
Use if-case instead two-condition switch-case.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/centaur.c | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index c5cf336..5f811586
add Centaur Family >=7 CPUs specific initialization support in centaur.c
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/centaur.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 5f811
New Centaur CPUs have Family >= 7. So, add specific initialization
for these CPUs in centaur.c
In order to handle Family >= 7, also use if instead two-condition
switch-case in centaur.c
Tony W Wang-oc (2):
x86/cpu: replace two-condition switch-case with if statement
x86/cpu: add C
On 07/07/2020 00:02, Luck, Tony wrote:
> On Mon, Jun 29, 2020 at 07:21:29PM +0800, Tony W Wang-oc wrote:
>> Add new Zhaoxin CPU features for enumeration in /proc/cpuinfo:
>> SM2, SM2_EN, SM3, SM4, SM3_EN, SM4_EN, PARALLAX, PARALLAX_EN,
>> TM3, TM3_EN, RNG2, RNG2_EN, PHE2,
-by: Tony W Wang-oc
---
arch/x86/include/asm/cpufeatures.h | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeatures.h
b/arch/x86/include/asm/cpufeatures.h
index c693ebf..a6c2d2b 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch
On Sat, Oct 5, 2019, Sean Christopherson wrote:
>Add an entry in struct cpuinfo_x86 to track VMX capabilities and fill
>the capabilities during IA32_FEATURE_CONTROL MSR initialization.
>
>Make the VMX capabilities dependent on X86_INTEL_FEATURE_CONTROL and
>X86_FEATURE_NAMES so as to avoid
The following commit has been merged into the ras/core branch of tip:
Commit-ID: 6e898d2bf67a82df0aa0c955adc9278faba9a635
Gitweb:
https://git.kernel.org/tip/6e898d2bf67a82df0aa0c955adc9278faba9a635
Author:Tony W Wang-oc
AuthorDate:Wed, 18 Sep 2019 14:19:30 +08:00
The following commit has been merged into the ras/core branch of tip:
Commit-ID: 5a3d56a034be9e8e87a6cb9ed3f2928184db1417
Gitweb:
https://git.kernel.org/tip/5a3d56a034be9e8e87a6cb9ed3f2928184db1417
Author:Tony W Wang-oc
AuthorDate:Wed, 18 Sep 2019 14:19:32 +08:00
The following commit has been merged into the ras/core branch of tip:
Commit-ID: 70f0c230031dfef3c9b3e37b2a8c18d3f7186fb2
Gitweb:
https://git.kernel.org/tip/70f0c230031dfef3c9b3e37b2a8c18d3f7186fb2
Author:Tony W Wang-oc
AuthorDate:Wed, 18 Sep 2019 14:19:33 +08:00
All Zhaoxin newer CPUs support CMCI that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin CMCI in
mce/core.c and mce/intel.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 25 +
arch/x86/kernel/cpu/mce/in
atch 3/4)
- Fix redefinition of "mce_zhaoxin_feature_clear" (patch 4/4)
Tony W Wang-oc (4):
x86/mce: Add Zhaoxin MCE support
x86/mce: Make 3 functions non-static
x86/mce: Add Zhaoxin CMCI support
x86/mce: Add Zhaoxin LMCE support
arch/x86/kernel/cpu/mce/core.c | 83
All Zhaoxin newer CPUs support MCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin MCE in
mce/core.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 38 --
1 file changed, 28 inserti
These functions are declared static and cannot be used in others
.c source file. this commit removes the static attribute and adds
the declaration to the header for these functions.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/intel.c| 6 +++---
arch/x86/kernel/cpu/mce
Zhaoxin newer CPUs support LMCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin LMCE
in mce/core.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
On Mon, Sep 16, 2019, Luck, Tony wrote:
>On Mon, Sep 16, 2019 at 11:37:18AM +0000, Tony W Wang-oc wrote:
>> Zhaoxin newer CPUs support LMCE that compatible with Intel's
>> "Machine-Check Architecture", so add support for Zhaoxin LMCE
>> in mce/core.c.
>
Zhaoxin newer CPUs support LMCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin LMCE
in mce/core.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 35 +--
1 file changed, 33 insertions(+), 2
All Zhaoxin newer CPUs support CMCI that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin CMCI in
mce/core.c and mce/intel.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 25 +
arch/x86/kernel/cpu/mce/in
All Zhaoxin newer CPUs support MCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin MCE in
mce/core.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 38 --
1 file changed, 28 inserti
These functions are declared static and cannot be used in others
.c source file. this commit removes the static attribute and adds
the declaration to the header for these functions.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/intel.c| 6 +++---
arch/x86/kernel/cpu/mce
Zhaoxin newer CPUs support MCE, CMCI and LMCE that compatible with
Intel's "Machine-Check Architecture".
To enable the supports of Linux kernel to Zhaoxin's MCA, add
specific patches for Zhaoxin's MCE, CMCI and LMCE. patches about
Zhaoxin's CMCI, LMCE use 3 functions in mce/intel.c, so make these
On Mon, Sep 16, 2019, Thomas Gleixner wrote:
>On Mon, 16 Sep 2019, Tony W Wang-oc wrote:
>
>> On Mon, Sep 16, 2019, Thomas Gleixner wrote:
>> >On Wed, 11 Sep 2019, Tony W Wang-oc wrote:
>> >
>> >> These functions are declared static and cannot be used i
On Mon, Sep 16, 2019, Thomas Gleixner wrote:
>On Wed, 11 Sep 2019, Tony W Wang-oc wrote:
>
>> These functions are declared static and cannot be used in others
>> .c source file. this commit removes the static attribute and adds
>> the declaration to the header for these fun
Zhaoxin newer CPUs support LMCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin LMCE
in mce/core.c.
Signed-off-by: Tony W Wang-oc
---
v2->v3:
- Rework mce_zhaoxin_feature_clear() as static
- Add comment and change coding style
v1->v2:
-
All Zhaoxin newer CPUs support CMCI that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin CMCI in
mce/core.c and mce/intel.c.
Signed-off-by: Tony W Wang-oc
---
v2->v3:
- Rework mce_zhaoxin_feature_init() as static
- Rework comment about Zhaoxin MCA
These functions are declared static and cannot be used in others
.c source file. this commit removes the static attribute and adds
the declaration to the header for these functions.
Signed-off-by: Tony W Wang-oc
---
v2->v3:
- Revert 1 unused function
arch/x86/kernel/cpu/mce/intel.c
All Zhaoxin newer CPUs support MCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin MCE in
mce/core.c.
Signed-off-by: Tony W Wang-oc
---
v2->v3:
- Make ifelse-case to switch-case
- Simplify Zhaoxin CPU FMS checking
arch/x86/kernel/cpu/mc
On Tue, Sep 10, 2019, Borislav Petkov wrote:
>On Tue, Sep 10, 2019 at 08:19:44AM +0000, Tony W Wang-oc wrote:
>> @@ -1777,6 +1777,29 @@ static void mce_centaur_feature_init(struct
>cpuinfo_x86 *c)
>> }
>> }
>>
>> +#ifdef CONFIG_CPU_SUP_ZHAOXIN
>
&g
On Tue, Sep 10, 2019, Borislav Petkov wrote:
>On Tue, Sep 10, 2019 at 08:20:07AM +0000, Tony W Wang-oc wrote:
>> Zhaoxin newer CPUs support LMCE that compatible with Intel's
>> "Machine-Check Architecture", so add support for Zhaoxin LMCE
>> in mce/core.c.
>
On Tue, Sep 10, 2019, Borislav Petkov wrote:
>On Tue, Sep 10, 2019 at 08:19:08AM +0000, Tony W Wang-oc wrote:
>> All Zhaoxin newer CPUs support MCE that compatible with Intel's
>> "Machine-Check Architecture", so add support for Zhaoxin MCE in
>> mce/core.c.
>
On Tue, Sep 10, 2019, Borislav Petkov wrote:
>On Tue, Sep 10, 2019 at 08:19:20AM +0000, Tony W Wang-oc wrote:
>> These functions are declared static and cannot be used in others
>> .c source file. this commit removes the static attribute and adds
>> the decl
All Zhaoxin newer CPUs support CMCI that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin CMCI in
mce/core.c and mce/intel.c.
Signed-off-by: Tony W Wang-oc
---
v1->v2:
- Fix redefinition of "mce_zhaoxin_feature_init"
arch/x86/incl
These functions are declared static and cannot be used in others
.c source file. this commit removes the static attribute and adds
the declaration to the header for these functions.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/intel.c| 8
arch/x86/kernel/cpu/mce
Zhaoxin newer CPUs support LMCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin LMCE
in mce/core.c.
Signed-off-by: Tony W Wang-oc
---
v1->v2:
- Fix redefinition of "mce_zhaoxin_feature_clear"
arch/x86/include/asm/mce.h | 2 ++
All Zhaoxin newer CPUs support MCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin MCE in
mce/core.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 30 --
1 file changed, 24 insertions(+), 6
rop us a note to help
>improve the system]
>
>url:
>https://github.com/0day-ci/linux/commits/Tony-W-Wang-oc/x86-mce-Add-Zhao
>xin-MCE-support/20190909-190435
>config: i386-randconfig-b002-201936 (attached as .config)
>compiler: gcc-7 (Debian 7.4.0-11) 7.4.0
>reproduce:
>
Zhaoxin newer CPUs support LMCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin LMCE
in mce/core.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/include/asm/mce.h | 2 ++
arch/x86/kernel/cpu/mce/core.c | 25 +++--
2 files c
These functions are declared static and cannot be used in others
.c source file. this commit removes the static attribute and adds
the declaration to the header for these functions.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/intel.c| 8
arch/x86/kernel/cpu/mce
All Zhaoxin newer CPUs support MCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin MCE in
mce/core.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 30 --
1 file changed, 24 insertions(+), 6
All Zhaoxin newer CPUs support CMCI that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin CMCI in
mce/core.c and mce/intel.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/include/asm/mce.h | 6 ++
arch/x86/kernel/cpu/mce/co
Add the new PCI ID 0x1d17 0x3288 Zhaoxin controller support
Signed-off-by: Tony W Wang-oc
---
sound/pci/hda/hda_intel.c | 4
1 file changed, 4 insertions(+)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 324a4b2..d08da0e 100644
--- a/sound/pci/hda/hda_intel.c
On Tue, 25 Jun 2019, Thomas Gleixner wrote:
> Tony,
>
> On Tue, 25 Jun 2019, Tony W Wang-oc wrote:
> > On Sun, Jun 23, 2019, Joe Perches wrote:
> > > > x86/cpu: Create Zhaoxin processors architecture support file
> > > >
> > > []
> > >
On Sun, Jun 23, 2019, Joe Perches wrote:
> > x86/cpu: Create Zhaoxin processors architecture support file
> >
> []
> > diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
> []
> > +static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
> > +{
> > + u32 lo, hi;
> > +
> > +
Commit-ID: f8c0e061cb83bd528ff0843e717bcebc846d4838
Gitweb: https://git.kernel.org/tip/f8c0e061cb83bd528ff0843e717bcebc846d4838
Author: Tony W Wang-oc
AuthorDate: Tue, 18 Jun 2019 08:37:29 +
Committer: Thomas Gleixner
CommitDate: Sat, 22 Jun 2019 11:45:58 +0200
x86/acpi/cstate
Commit-ID: 773b2f30a3fc026f3ed121a8b945b0ae19b64ec5
Gitweb: https://git.kernel.org/tip/773b2f30a3fc026f3ed121a8b945b0ae19b64ec5
Author: Tony W Wang-oc
AuthorDate: Tue, 18 Jun 2019 08:37:14 +
Committer: Thomas Gleixner
CommitDate: Sat, 22 Jun 2019 11:45:57 +0200
ACPI, x86: Add
Commit-ID: 761fdd5e3327db6c646a09bab5ad48cd42680cd2
Gitweb: https://git.kernel.org/tip/761fdd5e3327db6c646a09bab5ad48cd42680cd2
Author: Tony W Wang-oc
AuthorDate: Tue, 18 Jun 2019 08:37:05 +
Committer: Thomas Gleixner
CommitDate: Sat, 22 Jun 2019 11:45:57 +0200
x86/cpu: Create
Add x86 architecture support for new Zhaoxin processors.
Carve out initialization code needed by Zhaoxin processors into
a separate compilation unit.
To identify Zhaoxin CPU, add a new vendor type X86_VENDOR_ZHAOXIN
for system recognition.
Signed-off-by: Tony W Wang-oc
---
MAINTAINERS
Zhaoxin CPUs have NONSTOP TSC feature, so enable the ACPI
driver support for it.
Signed-off-by: Tony W Wang-oc
---
drivers/acpi/acpi_pad.c | 1 +
drivers/acpi/processor_idle.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c
index
Same as Intel, Zhaoxin MP CPUs support C3 share cache and on all
recent Zhaoxin platforms ARB_DISABLE is a nop. So set related
flags correctly in the same way as Intel does.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/acpi/cstate.c | 15 +++
1 file changed, 15 insertions
As a new x86 CPU Vendor, Shanghai Zhaoxin Semiconductor Co., Ltd.
("Zhaoxin") provide high performance general-purpose x86 processors.
CPU Vendor ID "Shanghai" belongs to Zhaoxin.
To enable the supports of Linux kernel to Zhaoxin's CPUs, add a new vendor
type (X86_VENDOR_ZHAOXIN, with value of
Same as Intel, Zhaoxin MP CPUs support C3 share cache and on all
recent Zhaoxin platforms ARB_DISABLE is a nop. So set related
flags correctly in the same way as Intel does.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/acpi/cstate.c | 15 +++
1 file changed, 15 insertions
Zhaoxin CPUs have NONSTOP TSC feature, so enable the ACPI
driver support for it.
Signed-off-by: Tony W Wang-oc
---
drivers/acpi/acpi_pad.c | 1 +
drivers/acpi/processor_idle.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c
index
On Fri, May 31, 2019, Raj, Ashok wrote:
> On Thu, May 30, 2019 at 09:13:39AM +0000, Tony W Wang-oc wrote:
> > On Thu, May 30, 2019, Tony W Wang-oc wrote:
> > > Hi Ashok,
> > > I have two questions about this patch, could you help to check:
> > >
> > >
On Thu, May 30, 2019, Tony W Wang-oc wrote:
> Hi Ashok,
> I have two questions about this patch, could you help to check:
>
> 1, for broadcast #MC exceptions, this patch seems require #MC exception
> errors
> set MCG_STATUS_RIPV = 1.
> But for Intel CPU, some #MC
ffline CPU
handle these LMCE errors, is that okay?
Thanks
Tony W Wang-oc
wrong place?
Thanks
Tony W Wang-oc
Add x86 architecture support for new Zhaoxin processors.
Carve out initialization code needed by Zhaoxin processors into
a separate compilation unit.
To identify Zhaoxin CPU, add a new vendor type X86_VENDOR_ZHAOXIN
for system recognition.
Signed-off-by: Tony W Wang-oc
---
MAINTAINERS
As a new x86 CPU Vendor, Shanghai Zhaoxin Semiconductor Co., Ltd.
("Zhaoxin") provide high performance general-purpose x86 processors.
CPU Vendor ID "Shanghai" belongs to Zhaoxin.
To enable the supports of Linux kernel to Zhaoxin's CPUs, add a new vendor
type (X86_VENDOR_ZHAOXIN, with value of
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