It's quite possible that multiple pcf857x can be hooked up
to the same interrupt line with the processor. So add IRQF_SHARED
in request irq..
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/gpio/gpio-pcf857x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Thu, May 22, 2014 at 04:27:05PM +0100, Srinivas Kandagatla wrote:
> >
> >The EOT is not used for every transaction. It is part of a handshaking
> >protocol with the attached peripheral, much like the NWD (notify when done).
> > As
> >near as I can tell today, no peripheral depends on the
> >Why do I only have this patch? Where is the rest of the set? Also,
> >it's on v5 and I don't recall seeing the other 4 versions?
>
> It's strange I've sent whole series on
>
> linux-kernel@vger.kernel.org
> linux-arm-ker...@lists.infradead.org
> linux-...@vger.kernel.org
>
On Mon, May 19, 2014 at 03:49:45PM -0700, Ben Segall wrote:
> @@ -3783,7 +3787,7 @@ static void __maybe_unused
> unthrottle_offline_cfs_rqs(struct rq *rq)
>* clock_task is not advancing so we just need to make sure
>* there's some valid quota amount
>
On Thu, May 22, 2014 at 05:04:51PM +0200, Peter Zijlstra wrote:
> On Thu, May 22, 2014 at 03:40:45PM +0100, Mel Gorman wrote:
>
> > > +static bool __wake_up_common(wait_queue_head_t *q, unsigned int mode,
> > > int nr_exclusive, int wake_flags, void *key)
> > > {
> > >
> This patch enables SDHCI STI platform driver.
>
> Signed-off-by: Peter Griffin
> ---
> arch/arm/configs/multi_v7_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Lee Jones
> diff --git a/arch/arm/configs/multi_v7_defconfig
> b/arch/arm/configs/multi_v7_defconfig
> index
On Thu, May 22, 2014 at 04:42:41PM +0800, Lai Jiangshan wrote:
> system_highpri_wq is exported to modules via EXPORT_SYMBOL_GPL(),
> but it was forgotten to be declared in workqueue.h. So we add the declaration
> and a short description for it.
>
> Signed-off-by: Lai Jiangshan
Applied to
Hi Rob,
On Thu, 2014-05-22 at 08:27AM -0500, Rob Herring wrote:
> On Tue, May 20, 2014 at 5:30 PM, Sören Brinkmann
> wrote:
> > Hi,
> >
> > I guess this is just to evaluate how big the lynch mob will be. Anyway:
> > Triggered by this discussion https://lkml.org/lkml/2014/5/15/46, I
> > looked a
On Thu, May 22, 2014 at 04:43:44PM +0800, Lai Jiangshan wrote:
> WORK_CPU_END is totally unused since 4e8b22bd. It should be removed.
Please use 12_CHAR_PREFIX_OF_SHA1 ("SUBJ") when referring to other
commits.
> After it is removed, the comment "special cpu IDs" is not precise due to
> there is
On Thu, 22 May 2014, Peter Griffin wrote:
> The second controller is only present on the stih416 SoC. Also
> mark this as non-removeable as its eMMC.
>
> Signed-off-by: Peter Griffin
> Signed-off-by: Giuseppe Cavallaro
> ---
> arch/arm/boot/dts/stih416-b2020.dts | 8
> 1 file
On Thu, May 22, 2014 at 04:43:56PM +0800, Lai Jiangshan wrote:
> In 8930caba, setting last CPU and clearing PENDING got merged into a single
Ditto.
> operation (set_work_cpu_and_clear_pending()), which resulted that the
> internal routine work_clear_pending() is not used any more.
>
>
On Thu, May 22, 2014 at 04:44:07PM +0800, Lai Jiangshan wrote:
> first_worker() actually returns the first idle workers, the name
> first_idle_worker() which is self-commnet will be better.
>
> All the callers of first_worker() expect it returns an idle worker,
> the name first_idle_worker() with
On Thu, May 22, 2014 at 05:08:09PM +0200, Vlastimil Babka wrote:
> > RIP: 0010:[] []
> > PageTransHuge.part.23+0xb/0xd
> > Call Trace:
> > [] isolate_migratepages_range+0x7a3/0x870
> > [] compact_zone+0x370/0x560
> > [] compact_zone_order+0xa2/0x110
> > []
On Thu, 22 May 2014, Peter Griffin wrote:
> Because the first sdhci controller is present on both stih415 and
> stih416 SoC which can both populate the b2020 board, it can be
> enabled in the generic DT file.
>
> Signed-off-by: Peter Griffin
> Signed-off-by: Giuseppe Cavallaro
These are the
Hello,
On Thu, May 22, 2014 at 07:01:16PM +0800, Lai Jiangshan wrote:
> While freezing takes place globally, its execution is per-workqueue;
> however, the current implementation makes use of the per-worker_pool
> POOL_FREEZING flag. While it's not broken, the flag makes the code
> more
Hi Peter
On 05/22/2014 05:18 PM, Peter Griffin wrote:
This platform driver adds initial support for the SDHCI host controller
found on STMicroelectronics SoCs.
It has been tested on STiH41x b2020 platforms currently.
Signed-off-by: Peter Griffin
Signed-off-by: Giuseppe Cavallaro
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Hi Peter,
On 05/22/2014 05:18 PM, Peter Griffin wrote:
This series adds a SDHCI platform driver for ST SoCs, along with
the additional device tree bindings and configuration to enable
the controller to work properly.
Initially it supports the stih416 and stih415 SoCs, and has
been tested on a
On 05/22/2014 05:18 PM, Peter Griffin wrote:
This patch adds the device tree binding documentation for ST
SDHCI driver. It contains the differences between the core properties
in mmc.txt and the properties used by the sdhci-st driver.
Signed-off-by: Peter Griffin
Signed-off-by: Giuseppe
At Thu, 22 May 2014 17:08:54 +0200,
Benoit Taine wrote:
>
> We should prefer `const struct pci_device_id` over
> `DEFINE_PCI_DEVICE_TABLE` to meet kernel coding style guidelines.
> This issue was reported by checkpatch.
>
> A simplified version of the semantic patch that makes this change is as
>> So I think we can reduce it to just the one rwsem (with recursion) if we
>> shoot CPU_POST_DEAD in the head.
>
> Here's the first bullet. Stressing my box here with Steve's hotplug
> script seems to work fine.
>
> Tony, any objections?
what was this comment referring to:
/* intentionally
On 05/22/2014 05:18 PM, Peter Griffin wrote:
This adds the required pin config for both SDHCI controllers on
the stih416 SoC.
Signed-off-by: Peter Griffin
Signed-off-by: Giuseppe Cavallaro
---
arch/arm/boot/dts/stih416-pinctrl.dtsi | 39 ++
1 file changed,
On 05/22/2014 03:17 AM, Tushar Behera wrote:
> If master clock is provided through device tree, then update
> the master clock frequency during set_sysclk.
>
> Documentation has been updated to reflect the change.
> diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c
> @@
This patch moves data allocated using kzalloc to managed data allocated
using devm_kzalloc and cleans now unnecessary kfrees in probe and remove
functions. The input_allocate_device is replaced by the corresponding
devm version and error handling code is cleaned up. Also, label err and
err1 no
On 05/22/2014 05:09 AM, Mel Gorman wrote:
> From: Dave Chinner
>
> We will like to unregister the sb shrinker before ->kill_sb().
> This will allow cached objects to be counted without call to
> grab_super_passive() to update ref count on sb. We want
> to avoid locking during memory reclamation
Please address Sergei's feedback, except the indentation one which
as you stated is correct.
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Please
On Thu, May 22, 2014 at 08:10:48AM -0700, Guenter Roeck wrote:
> On Wed, May 21, 2014 at 11:19:28PM -0300, Flavio Leitner wrote:
> > From: Flavio Leitner
> >
> > It is possible to increase left fan speed on a
> > DELL Precision 490n system up to 3.
> >
> > valuefan rpm
> > 1
Tegra SDHCI controllers, by default, report a base clock frequency
of 208Mhz in SDHCI_CAPABILTIES which may or may not be equal to the
actual base clock frequency. This is because the clock rate is
configured by the clock controller, which is external to the SD/MMC
controller. Since the SD/MMC
On 22/05/14 16:32, Andy Gross wrote:
On Thu, May 22, 2014 at 04:27:05PM +0100, Srinivas Kandagatla wrote:
The EOT is not used for every transaction. It is part of a handshaking
protocol with the attached peripheral, much like the NWD (notify when done). As
near as I can tell today, no
> This patch adds the required pin config for the sdhci controller
> present in the stih415 SoC.
>
> Signed-off-by: Peter Griffin
> Signed-off-by: Giuseppe Cavallaro
Switch these round - same with all the other patches.
> ---
> arch/arm/boot/dts/stih415-pinctrl.dtsi | 21
On Thu, 22 May 2014, Peter Griffin wrote:
> This patch adds device tree config for both sdhci controllers
> on the stih416 SoC.
>
> Signed-off-by: Peter Griffin
> Signed-off-by: Giuseppe Cavallaro
> ---
> arch/arm/boot/dts/stih416.dtsi | 24
> 1 file changed, 24
On Thu, 2014-05-22 at 10:18 +0100, Lee Jones wrote:
> drivers/mfd/axp20x.c:159:3:
> warning: initialization discards ‘const’ qualifier from pointer target type
>.parent_supplies = axp20x_supplies,
[]
> diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
[]
> @@ -140,7 +140,7 @@ static
On 05/22/2014 05:09 AM, Mel Gorman wrote:
> From: Tim Chen
>
> We remove the call to grab_super_passive in call to super_cache_count.
> This becomes a scalability bottleneck as multiple threads are trying to do
> memory reclamation, e.g. when we are doing large amount of file read and
> page
On Thu, 22 May 2014, Peter Griffin wrote:
> This adds the required pin config for both SDHCI controllers on
> the stih416 SoC.
>
> Signed-off-by: Peter Griffin
> Signed-off-by: Giuseppe Cavallaro
> ---
> arch/arm/boot/dts/stih416-pinctrl.dtsi | 39
> ++
> 1
Program TEGRA_SDHCI_VENDOR_MISC_CTRL so that UHS modes aren't advertised
in SDHCI_CAPABILITIES_1. While the Tegra SDHCI controller does support
these modes, they require Tegra-specific tuning and calibration routines
which the driver does not support yet.
Signed-off-by: Andrew Bresticker
Le 22/05/2014 17:10, Horia Geanta a écrit :
From: Lei Xu
Currently the sha256 icv truncation length is set to 96bit
while the length is defined as 128bit in RFC4868.
This may result in somer errors when working with other IPsec devices
with the standard truncation length.
Thus, change the
On 05/22/2014 05:09 AM, Mel Gorman wrote:
> Commit "mm: vmscan: obey proportional scanning requirements for kswapd"
> ensured that file/anon lists were scanned proportionally for reclaim from
> kswapd but ignored it for direct reclaim. The intent was to minimse direct
> reclaim latency but Yuanhan
> This patch adds the device tree binding documentation for ST
> SDHCI driver. It contains the differences between the core properties
> in mmc.txt and the properties used by the sdhci-st driver.
>
> Signed-off-by: Peter Griffin
> Signed-off-by: Giuseppe Cavallaro
> ---
>
> > drivers/mfd/axp20x.c:159:3:
> > warning: initialization discards ‘const’ qualifier from pointer target
> > type
> >.parent_supplies = axp20x_supplies,
> []
> > diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
> []
> > @@ -140,7 +140,7 @@ static const struct regmap_irq_chip
> >
On Thu, May 22, 2014 at 10:09:36AM +0100, Mel Gorman wrote:
> This series is aimed at regressions noticed during reclaim activity. The
> first two patches are shrinker patches that were posted ages ago but never
> merged for reasons that are unclear to me. I'm posting them again to see if
> there
On 05/22/2014 06:33 PM, Lee Jones wrote:
Why do I only have this patch? Where is the rest of the set? Also,
it's on v5 and I don't recall seeing the other 4 versions?
It's strange I've sent whole series on
linux-kernel@vger.kernel.org
linux-arm-ker...@lists.infradead.org
Aborting a search does not sound like a correct solution.
How does a higher level user (eg for_each_pci_dev) know that a search
was aborted and decide whether it should try again, assuming it would
be ok repeating the action on the devices visited the first time?
Francesco
On Thu, May 22, 2014
This patch adds the necessary node to probe the global clock
controller on APQ8084 platforms.
Signed-off-by: Georgi Djakov
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi
This patch adds support for the global clock controller found on
the APQ8084 based devices.
The APQ8084 and MSM8974 share a lot of clock data, so instead of
duplicating all the data, we add support to the MSM8974 code.
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/Kconfig
Add the necessary DT node to probe the serial driver on
APQ8084 platforms.
Signed-off-by: Georgi Djakov
---
arch/arm/boot/dts/qcom-apq8084.dtsi |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi
b/arch/arm/boot/dts/qcom-apq8084.dtsi
index
This patchset adds support for the global clock controller found on the
APQ8084 based platforms.
It applies to the clk-next tree and the following patchset on top of it:
https://lkml.org/lkml/2014/5/16/666
Georgi Djakov (5):
clk: qcom: Add APQ8084 Global Clock Controller documentation
clk:
The APQ8084 and MSM8974 SoCs share a lot of clock data. Instead of
duplicating all the data, we can add the support for APQ8084 into
the MSM8974 code and just describe the differences by using an
override function.
This patch applies to the clk-next tree and the following patchset
on top of it:
Add the compatible string for the APQ8084 global clock controller
to the clock binding documentation.
Signed-off-by: Georgi Djakov
---
.../devicetree/bindings/clock/qcom,gcc.txt |1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
On Thu, 22 May 2014 08:12:59 -0700, Guenter Roeck wrote:
> On Thu, May 22, 2014 at 10:28:31AM +0200, Thomas Bogendoerfer wrote:
> > On Wed, May 21, 2014 at 08:32:24PM -0700, Guenter Roeck wrote:
> > > On 05/21/2014 07:19 PM, Flavio Leitner wrote:
> > > >From: Flavio Leitner
> > > >
> > > >It is
On Fri, May 23, 2014 at 12:14:16AM +0800, Yuanhan Liu wrote:
> On Thu, May 22, 2014 at 10:09:36AM +0100, Mel Gorman wrote:
> > This series is aimed at regressions noticed during reclaim activity. The
> > first two patches are shrinker patches that were posted ages ago but never
> > merged for
On 05/22/2014 07:14 PM, Ivan Khoronzhuk wrote:
On 05/22/2014 06:33 PM, Lee Jones wrote:
Why do I only have this patch? Where is the rest of the set? Also,
it's on v5 and I don't recall seeing the other 4 versions?
It's strange I've sent whole series on
linux-kernel@vger.kernel.org
On Wednesday, May 21, 2014 5:40 PM, Chase Southwood wrote:
>
> This function is already compliant with the comedi API and is behaving as
> comedi core expects. This patch moves it out of
> addi-data/hwdrv_apci1564.c and into the driver proper since no further
> work needs to be done on it.
>
>
Arnd, Olof, Kevin,
Another AT91 DT pull-request for 3.16. This one is the conversion of two more
SoC to Common Clock Framework (aka CCF). I identified it as a "DT" pull-request
but it modifies slightly a couple of files in mach-at91 (use of a configuration
option).
This pull-request depends on:
-
On May 22, 2014, at 11:24 AM, Georgi Djakov wrote:
> Add the necessary DT node to probe the serial driver on
> APQ8084 platforms.
>
> Signed-off-by: Georgi Djakov
> ---
> arch/arm/boot/dts/qcom-apq8084.dtsi |7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git
On Wednesday, May 21, 2014 5:41 PM, Chase Southwood wrote:
>
> This function is already compliant with the comedi API and is behaving as
> comedi core expects. This patch moves it out of
> addi-data/hwdrv_apci1564.c and into the driver proper since no further
> work needs to be done on it.
>
>
This patch adds the Device Tree binding document for the Broadcom
Set-top-box Level 2 interrupt controller hardware.
Signed-off-by: Brian Norris
Signed-off-by: Florian Fainelli
---
Changes in v2:
- respin
.../bindings/interrupt-controller/brcm,l2-intc.txt | 29 ++
1 file
Hi Thomas, Jason,
This patch set adds an irqchip driver for the Broadcom Set Top Box Level-2
interrupt controller hardware, as well as a corresponding Device Tree binding
document.
Thanks!
Florian Fainelli (2):
irqchip: add Broadcom Set Top Box Level-2 interrupt controller
Documentation:
This patch adds support for the Level-2 interrupt controller hardware
found in Broadcom Set Top Box System-on-a-Chip devices. This interrupt
controller is implemented using the generic IRQ chip driver with
separate enable and disable registers.
Signed-off-by: Brian Norris
Signed-off-by: Florian
On May 22, 2014, at 11:24 AM, Georgi Djakov wrote:
> This patch adds support for the global clock controller found on
> the APQ8084 based devices.
>
> The APQ8084 and MSM8974 share a lot of clock data, so instead of
> duplicating all the data, we add support to the MSM8974 code.
>
>
On 05/21/2014 02:59 AM, Viresh Kumar wrote:
> Tegra had always been switching to intermediate frequency (pll_p_clk) since
> ever. CPUFreq core has better support for handling notifications for these
> frequencies and so we can adapt Tegra's driver to it.
>
> Also do a WARN() if clk_set_parent()
This is a patch to add i2c algorith support for nxp sc18im700
master i2c bus controller with uart interface
Signed-off-by: Raghavendra Chandra Ganiga
---
drivers/i2c/algos/Kconfig | 2 +
drivers/i2c/algos/Makefile | 1 +
drivers/i2c/algos/i2c-algo-sc18im700.c | 274
From: Davidlohr Bueso
Our mutexes have gone a long ways since the original implementation
back in 2005/2006. However, the mutex-design.txt document is still
stuck in the past, to the point where most of the information there
is practically useless and, more important, simply incorrect. This
On 05/21/2014 02:59 AM, Viresh Kumar wrote:
> Douglas Anderson, recently pointed out an interesting problem due to which
> udelay() was expiring earlier than it should.
>
> While transitioning between frequencies few platforms may temporarily switch
> to
> a stable frequency, waiting for the
On Thu, 2014-05-22 at 17:08 +0100, Lee Jones wrote:
> To be frank, I've never known what the double const means. Care to
> enlighten?
There's a nice table here:
http://stackoverflow.com/questions/14562845/why-does-passing-char-as-const-char-generate-a-warning
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These patches introduce keystone reset driver.
The keystone SoC can be rebooted in several ways. By external reset
pin, by soft and by watchdogs. This driver allows software reset and reset
by one of the watchdogs. Also added opportunity to set soft/hard reset type.
Based on linux-next/master
The keystone SoC can be rebooted in several ways. By external reset
pin, by soft and by watchdogs. To allow keystone SoC reset if
watchdog is triggered we have to enable it in reset mux configuration
register regarding of watchdog configuration. Also we need to set
soft/hard reset we are going to
Remove reset stuff in flavour of using keystone reset driver:
driver/power/reset/keystone-reset.c
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/mach-keystone/keystone.c | 34 --
1 file changed, 34 deletions(-)
diff --git
The Keystone II devices have a set of registers that are used to control
the status of its peripherals. This node is intended to allow access to
this functionality.
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
.../devicetree/bindings/mfd/ti-keystone-devctrl.txt | 19
Enable reset driver support in order to have opportunity
to reboot SoC by watchdog and by software.
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/configs/keystone_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/keystone_defconfig
The pll controller register set and device state control registers
include sets of registers with different purposes, so it's logically
to add syscon entry to be able to access them from appropriate places.
So added pll controller and device state control syscon entries.
The keystone driver
The main pll controller used to drive theC66x CorePacs, the switch fabric,
and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
the NETCP modules) requires a PLL Controller to manage the various clock
divisions, gating, and synchronization.
Reviewed-by: Arnd Bergmann
Paul Bolle writes:
> Do you want to know how to test this patch on a 32 bit powermac? Ie, see
> if it has any effect, and whether that effect improves things or make
> things worse.
Yes.
Andreas.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3
This node is intended to allow SoC reset in case of software reset
or appropriate watchdogs.
The Keystone SoCs can contain up to 4 watchdog timers to reset
SoC. Each watchdog timer event input is connected to the Reset Mux
block. The Reset Mux block can be configured to cause reset or not.
write{b,w,l,q}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.
This patch adds dummy macros for the write accessors to tile, in the
same vein as the dummy definitions for the relaxed read
Parsing and registration of fixed PHY devices was needed with the use of
of_phy_connect_fixed_link() because this function was using the
designated PHY address identifier (first cell of the property) as the
address to bind the PHY on the emulated bus.
Since commit
All in-tree drivers have been converted to use the new pair of
functions: of_is_fixed_phy_link() plus of_phy_register_fixed_link(), we
can now safely remove of_phy_connect_fixed_link.
Signed-off-by: Florian Fainelli
---
No changes in v2
drivers/of/of_mdio.c| 38
write{b,w,l,q}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O writes with weaker barrier semantics than the
non-relaxed variants.
This patch implements these write macros for Alpha, in the same vein as
the relaxed read macros, which are already implemented.
write{b,w,l}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.
This patch adds dummy macros for the write accessors to Cris, in the same
vein as the dummy definitions for the relaxed read
write{b,w,l,q}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.
This patch adds dummy macros for the read and write accessors to x86,
which simply expand to the non-relaxed variants. Note that
> This platform driver adds initial support for the SDHCI host controller
> found on STMicroelectronics SoCs.
>
> It has been tested on STiH41x b2020 platforms currently.
>
> Signed-off-by: Peter Griffin
> Signed-off-by: Giuseppe Cavallaro
> ---
> drivers/mmc/host/Kconfig| 12 +++
>
write{b,w,l,q}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.
This patch adds dummy macros for the write accessors to powerpc, in the
same vein as the dummy definitions for the relaxed read
of_phy_connect_fixed_link() is becoming obsolete, and also required
platform code to register the fixed PHYs at the specified addresses for
those to be usable. Get rid of it and use the new of_phy_is_fixed_link()
plus of_phy_register_fixed_link() helpers to transition over the new
scheme.
of_phy_connect_fixed_link() is becoming obsolete, and also required
platform code to register the fixed PHYs at the specified addresses for
those to be usable. Get rid of it and use the new of_phy_is_fixed_link()
plus of_phy_register_fixed_link() helpers to transition over the new
scheme.
Now that no architectures using asm-generic/io.h define their own relaxed
accessors, the dummy definitions can be used unconditionally.
Cc: Arnd Bergmann
Signed-off-by: Will Deacon
---
include/asm-generic/io.h | 16
1 file changed, 16 deletions(-)
diff --git
write{b,w,l}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.
This patch adds dummy macros for the write accessors to m68k, in the
same vein as the dummy definitions for the relaxed read
On Wed, 21 May 2014 01:52:17 +0400 Anton Saraev wrote:
> On Tue, May 20, 2014 at 10:24:11AM -0600, Jake Edge wrote:
> > On Tue, 20 May 2014 10:47:57 -0400 Jason Cooper wrote:
> >
> > but some kind of tests are needed to ensure nothing breaks before
> > digging into that ...
>
> I have some test:
Hi all,
This is version 2 of the series I originally posted here:
https://lkml.org/lkml/2014/4/17/269
Changes since v1 include:
- Added relevant acks from arch maintainers
- Fixed potential compiler re-ordering issue for x86 definitions
I'd *really* appreciate some feedback on the
write{b,w,l,q}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.
This patch adds dummy macros for the write accessors to sparc, in the
same vein as the dummy definitions for the relaxed read
Update the Freescale TSEC PHY, Broadcom GENET & SYSTEMPORT Device Tree
binding documentation to refer to the fixed-link Device Tree binding in
fixed-link.txt.
Reviewed-by: Thomas Petazzoni
Signed-off-by: Florian Fainelli
---
No changes in v2
write{b,w,l}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.
This patch adds dummy macros for the write accessors to m32r, in the
same vein as the dummy definitions for the relaxed read
write{b,w,l}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.
This patch adds dummy macros for the write accessors to frv, in the same
vein as the dummy definitions for the relaxed read
of_phy_connect_fixed_link() is becoming obsolete, and also required
platform code to register the fixed PHYs at the specified addresses for
those to be usable. Get rid of it and use the new of_phy_is_fixed_link()
plus of_phy_register_fixed_link() helpers to transition over the new
scheme.
This patch extends the paragraph describing the relaxed read io accessors
so that the relaxed accessors are defined to be:
- Ordered with respect to each other if accessing the same peripheral
- Unordered with respect to normal memory accesses
- Unordered with respect to LOCK/UNLOCK
write{b,w,l,q}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.
This patch adds dummy macros for the write accessors to ia64, which may
be able to be optimised in a similar manner to the
of_phy_connect_fixed_link() is becoming obsolete, and also required
platform code to register the fixed PHYs at the specified addresses for
those to be usable. Get rid of it and use the new of_phy_is_fixed_link()
plus of_phy_register_fixed_link() helpers to transition over the new
scheme.
These are now defined by asm-generic/io.h, so we don't need the private
definitions anymore.
Cc: Chris Zankel
Cc: Max Filippov
Signed-off-by: Will Deacon
---
arch/xtensa/include/asm/io.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/arch/xtensa/include/asm/io.h
of_phy_connect_fixed_link() is becoming obsolete, and also required
platform code to register the fixed PHYs at the specified addresses for
those to be usable. Get rid of it and use the new of_phy_is_fixed_link()
plus of_phy_register_fixed_link() helpers to transition over the new
scheme.
write{b,w,l}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.
This patch adds dummy macros for the write accessors to mn10300, in the
same vein as the dummy definitions for the relaxed read
Hi all,
This patch set removes of_phy_connect_fixed_link() from the tree now that
we have a better solution for dealing with fixed PHY (emulated PHY) devices
for drivers that require them.
First two patches update the 'fixed-link' Device Tree binding and drivers to
refere to it.
Patches 3 to 7
These are now defined by asm-generic/io.h, so we don't need the private
definitions anymore.
Cc: Heiko Carstens
Cc: Martin Schwidefsky
Signed-off-by: Will Deacon
---
arch/s390/include/asm/io.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/arch/s390/include/asm/io.h
801 - 900 of 1602 matches
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