MMC on DRA7 SoCs require different IO Delay values to be configured
depending on the MMC mode. In order to confgiure these IO Delay values
CONFIG_PINCTRL_TI_IODELAY must be enabled. Document this dependency
here so that it can be added by anyone using custom .config.
Signed-off-by: Kishon Vijay
On Fri, May 19, 2017 at 01:42:55PM +0530, surenderpols...@gmail.com wrote:
> -static DEVICE_ATTR(power_state, S_IRUGO | S_IWUSR,
> - tsl2x7x_power_state_show, tsl2x7x_power_state_store);
> +static DEVICE_ATTR_RW(tsl2x7x_power_state);
You do realize you just renamed the sysfs file,
Use the new compatible string "ti,dra7-hsmmc" that was specifically
added for dra7 and dra72. This is required since for dra7 and dra72
processors iodelay values has to be set unlike other processors.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sekhar Nori
---
On Thu, May 11, 2017 at 3:38 PM, Linus Walleij wrote:
> On Fri, Apr 28, 2017 at 10:43 AM, Sebastian Reichel
> wrote:
>> On Fri, Apr 28, 2017 at 10:22:24AM +0200, Linus Walleij wrote:
>>> On Thu, Apr 27, 2017 at 4:19 PM, Sebastian Reichel
>>> wrote:
>>>
>>> > Back in January I sent patches
From: Sekhar Nori
Add pinmux configuration for MMC module including IODELAY
values suggested in the data manual for the various supported
modes.
IOdelay data for both silicon revision 1.0 and 2.0 is
added here.
The datamanual revisions used are:
* AM571x Silicon Revision 2.0: SPRS957D,
Include dra72x-mmc-iodelay.dtsi which has pinmux and IODelay
configuration values for the various MMC modes for dra72 SoC
and use it in the pinctrl properties of MMC devicetree
nodes present in dra72-evm.dts.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra72-evm.dts | 14
On Thu, May 18, 2017 at 07:43:13PM +0300, Andy Shevchenko wrote:
> On Thu, May 18, 2017 at 5:38 PM, Mika Westerberg
> wrote:
> > Thunderbolt fabric consists of one or more switches. This fabric is
> > called domain and it is controlled by an entity called connection
> > manager. The connection
On Thu, May 18, 2017 at 11:42:34PM -0400, Steven Rostedt wrote:
>
> One of my the configs I use to test ftrace with (configs that have
> caused failures in the past), has lots of irq issues and fails to
> initialize the network of my box. I bisected the problem down to a
> single commit, and when
Add missing goto.
Addresses-Coverity-ID: 1226913
Signed-off-by: Gustavo A. R. Silva
---
drivers/uwb/i1480/dfu/phy.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/uwb/i1480/dfu/phy.c b/drivers/uwb/i1480/dfu/phy.c
index 3b1a87d..1ac8526 100644
--- a/drivers/uwb/i1480/dfu/phy.c
+++
Enable PINCTRL_TI_IODELAY since it is required for MMC module in
DRA7 family of processors to configure "IODelay" values
depending on the enumerated MMC modes.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
On 18 May 2017 at 00:17, David Woods wrote:
> Using the device_property interfaces allows mmc drivers to work
> on platforms which run on either device tree or ACPI.
>
> Signed-off-by: David Woods
> Reviewed-by: Chris Metcalf
> Cc: sta...@vger.linux.org
> ---
> drivers/mmc/core/host.c | 72
>
Include dra72x-mmc-iodelay.dtsi which has pinmux and IODelay
configuration values for the various MMC modes for dra72 SoC
and use it in the pinctrl properties of MMC devicetree
nodes present in dra72-evm-revc.dts.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra72-evm-revc.dts |
On DRA7 family SoCs, MMC1 controller supports SDR104,
SDR50, DDR50, SDR25 and SDR12 UHS modes (These UHS modes
are not supported in beagle-x15 because it's not possible
to switch IO lines supply voltage to 1.8v).
MMC2 controller supports HS200 and DDR modes. (Since some of the
boards like
Enable PINCTRL_TI_IODELAY since it is required for MMC module in
DRA7 family of processors to configure "IODelay" values
depending on the enumerated MMC modes.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/configs/omap2plus_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
On Thu, May 18, 2017 at 10:19:11PM +0300, Andy Shevchenko wrote:
> On Thu, May 18, 2017 at 5:39 PM, Mika Westerberg
> wrote:
> > The device DROM contains name of the vendor and device among other
> > things. Extract this information and expose it to the userspace via two
> > new attributes.
>
>
Add vmmc_aux-supply property to mmc1 dt node and populate
it with ldo1_reg to reflect ldo1_out is connected to mmc1 IO lines.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra72-evm.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/dra72-evm.dts
The data manual of J6/J6 Eco recommends to set different IODELAY values
depending on the mode in which the MMC/SD is enumerated in order to
ensure IO timings are met.
Add support to set the IODELAY values depending on the various MMC
modes using the pinctrl APIs.
Signed-off-by: Kishon Vijay
On Thu, May 18, 2017 at 10:35:19PM +0300, Andy Shevchenko wrote:
> On Thu, May 18, 2017 at 5:39 PM, Mika Westerberg
> wrote:
> > Starting from Intel Falcon Ridge the NVM firmware can be upgraded by
> > using DMA configuration based mailbox commands. If we detect that the
> > host or device
MMC2 interface on AM57xx Beagle-x15, connected to
onboard eMMC, has IO voltage fixed to 3.3V.
Add no-1-8-v device-tree property to mmc2 node
in the board's device-tree file to reflect
this.
Note that the AM57xx SoC itself supports dual-voltage
on MMC2. The limitation above is due to the board.
omap hsmmc host controller has ADMA2 feature. Enable it here
for better read and write throughput.
Signed-off-by: Kishon Vijay Abraham I
[misael.lo...@ti.com: handle ADMA errors]
Signed-off-by: Misael Lopez Cruz
[nsek...@ti.com: restore adma settings after context loss]
Signed-off-by: Sekhar
omap_hsmmc doesn't support polled I/O. So remove *use_dma*
which is always set to '1'.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sekhar Nori
---
drivers/mmc/host/omap_hsmmc.c | 37 -
1 file changed, 16 insertions(+), 21 deletions(-)
diff --git
Include dra74x-mmc-iodelay.dtsi which has pinmux and IODelay
configuration values for the various MMC modes for dra74x SoC
and use it in the pinctrl properties of MMC devicetree
nodes present in am572x-idk.dts.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/am572x-idk.dts | 19
From: Sekhar Nori
OMAP HSMMC driver assumes that if the controller does
not support dual-volt, then it supports only 1.8V IO.
This assumption can be incorrect. For example, on K2G
MMC0 supports 3.3V IO only. AM57x Beagle-x15 and IDK
boards support only 3.3V IO on eMMC interface.
Support
Hi,
On 18/05/17 08:16, Icenowy Zheng wrote:
> Add support of AXP803 regulators in the Pine64 device tree, in order to
> enable many future functionalities, e.g. Wi-Fi.
>
> Signed-off-by: Icenowy Zheng
> ---
> Changes in v6:
> - Rebased on next-20170517.
>
>
From: Ravikumar Kattekola
On dra72/dra71 evms, mmc2 vdd/ios are connected to a common 1.8V supply
not 3.3V. Also the regulator that supplies 1.8V is different on dra71-evm
so move the supply property from common dtsi to evm specific dts files.
Fixes: a4240d3af677 ("ARM: dts: Add support for
Include dra74x-mmc-iodelay.dtsi which has pinmux and IODelay
configuration values for the various MMC modes for dra74 SoC
and use it in the pinctrl properties of MMC devicetree
nodes present in dra7-evm.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7-evm.dts | 18
Hi Gerd and Alex,
>-Original Message-
>From: Gerd Hoffmann [mailto:kra...@redhat.com]
>Sent: Friday, May 19, 2017 4:05 PM
>To: Alex Williamson
>Cc: Chen, Xiaoguang ; Tian, Kevin
>; linux-kernel@vger.kernel.org; zhen...@linux.intel.com;
>Lv, Zhiyuan ; intel-gvt-...@lists.freedesktop.org;
From: Mugunthan V N
DRA7 Errata No i834: When using high speed HS200 and SDR104
cards, the functional clock for MMC module will be 192MHz.
At this frequency, the maximum obtainable timeout (DTO =0xE)
in hardware is (1/192MHz)*2^27 = 700ms. Commands taking longer
than 700ms will be affected by
No functional change. Add separate case statements for certain timing
like MMC_TIMING_SD_HS and MMC_TIMING_MMC_HS even though AC12_UHSMC_RES
has to be written to the AC12 register (same as for default modes).
Also have separate case sections for MMC_TIMING_UHS_SDR104 and
MMC_TIMING_UHS_HS200 even
于 2017年5月19日 GMT+08:00 下午4:27:21, Andre Przywara 写到:
>Hi,
>
>On 18/05/17 08:16, Icenowy Zheng wrote:
>> Add support of AXP803 regulators in the Pine64 device tree, in order
>to
>> enable many future functionalities, e.g. Wi-Fi.
>>
>> Signed-off-by: Icenowy Zheng
>> ---
>> Changes in v6:
>> -
Fix the error path sequence so that clk_disable, runtime_disable etc
are done in the reverse order of how they were enabled.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sekhar Nori
---
drivers/mmc/host/omap_hsmmc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
On 16 May 2017 at 11:36, Jan Glauber wrote:
> Hi Ulf,
>
> here are some bug fixes for the new mmc driver. The only
> non-trivial fix should be the platform thing in patch #4 and #5.
>
> Tested on OcteonTx and on various MIPS boxes.
>
> thanks,
> Jan
>
> David Daney (2):
> mmc: cavium-octeon:
On 16 May 2017 at 08:17, Jisheng Zhang wrote:
> Currently, the xenon_clean_phy() is only used for freeing phy_params.
> The phy_params is allocated by devm_kzalloc(), there's no need to free
> is explicitly.
>
> Signed-off-by: Jisheng Zhang
Thanks, applied for fixes!
Kind regards
Uffe
> ---
>
HCTL is now set based on ios.signal_voltage set by mmc core and not
hardcoded to 3V0 if OMAP_HSMMC_SUPPORTS_DUAL_VOLT is set. If
OMAP_HSMMC_SUPPORTS_DUAL_VOLT is set, it means HCTL can be set to either
3V0 or 1V8. And it should be set to 3V0 or 1V8 depending on
ios.signal_voltage.
Also it is now
This series adds UHS, HS200, DDR mode and ADMA support to
omap_hsmmc driver used to improve the throughput of MMC/SD in dra7
SoCs.
The functionality implemented in this series was sent before ([1]) but
was never followed up since supporting high speed modes in dra7 required
IODelay values to be
Add support for vmmc_aux to switch to 1.8v. Also use "iov" instead of
"vdd" to indicate io voltage. This is in preparation for adding support
for io signal voltage switch.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sekhar Nori
---
drivers/mmc/host/omap_hsmmc.c | 50
On 19.05.2017 09:59, Konstantin Khlebnikov wrote:
Show count of global oom killer invocations in /proc/vmstat
Oops, this actually counts memcg kills too. Will redo.
Signed-off-by: Konstantin Khlebnikov
---
include/linux/vm_event_item.h |1 +
mm/oom_kill.c |1 +
On Tue, Mar 14, 2017 at 10:19 PM, santosh.shilim...@oracle.com
wrote:
> On 3/14/17 2:11 PM, Arnd Bergmann wrote:
>>
>> gcc-7 notices that the length we pass to strncat is wrong:
>>
>> drivers/firmware/ti_sci.c: In function 'ti_sci_probe':
>> drivers/firmware/ti_sci.c:204:32: error: specified
On 13 May 2017 at 15:17, SF Markus Elfring
wrote:
> From: Markus Elfring
> Date: Sat, 13 May 2017 15:05:28 +0200
>
> Omit an extra message for a memory allocation failure in this function.
>
> This issue was detected by using the Coccinelle software.
>
> Link:
>
ci_role BUGs when the role is >= CI_ROLE_END.
This is the case while the role is changing.
Signed-off-by: Michael Thalmeier
---
drivers/usb/chipidea/core.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index
Hi,
On Fri, May 19, 2017 at 03:06:06PM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This is v4 of my A83T CCU series. This is for 4.13.
Applied the patches 1-5. Can you resubmit patch 6 after 4.13-rc1 ?
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
Operations on blkg objects in blk-cgroup are protected with the
request_queue lock, which is no more the lock that protects
I/O-scheduler operations in blk-mq. The latter are now protected with
finer-grained per-scheduler-instance locks. As a consequence, if blkg
and blkg-related objects are
The error handling code in omap_ocp2scp_probe fails to invoke
pm_runtime_disable and fails to initialize return value in
certain cases. Fix it here.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sekhar Nori
---
drivers/bus/omap-ocp2scp.c | 9 +++--
1 file changed, 7 insertions(+), 2
Add all R-Car M2-N Clock Pulse Generator Core Clock Outputs, as listed
in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2
Hardware User's Manual rev. 2.00.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Niklas Söderlund
---
v2:
- Add Reviewed-by.
---
Document use of the Renesas Clock Pulse Generator / Module Standby and
Software Reset DT Bindings for various member of the R-Car Gen2 family
(H2, M2-W, V2H, M2-N, and E2).
Signed-off-by: Geert Uytterhoeven
Acked-by: Rob Herring
---
v2:
- Add Acked-by.
---
Add all R-Car H2 Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2a ("List of Clocks [R-Car H2]") of the R-Car Gen2 Hardware
User's Manual rev. 2.00.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Niklas Söderlund
---
v2:
- Add Reviewed-by.
---
Add a new R-Car H2 Clock Pulse Generator / Module Standby and Software
Reset driver, using the CPG/MSSR driver core. This will enable support
for module resets, which are not supported by the existing driver.
The old driver can still be used through a Kconfig option, to preserve
backward
Add a new R-Car V2H Clock Pulse Generator / Module Standby and Software
Reset driver, using the CPG/MSSR driver core. This will enable support
for module resets, which are not supported by the existing driver.
The old driver can still be used through a Kconfig option, to preserve
backward
Add a new R-Car E2 Clock Pulse Generator / Module Standby and Software
Reset driver, using the CPG/MSSR driver core. This will enable support
for module resets, which are not supported by the existing driver.
The old driver can still be used through a Kconfig option, to preserve
backward
Add all R-Car M2-W Clock Pulse Generator Core Clock Outputs, as listed
in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2
Hardware User's Manual rev. 2.00.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Niklas Söderlund
---
v2:
- Add Reviewed-by.
---
Add a new R-Car M2-W/N Clock Pulse Generator / Module Standby and
Software Reset driver, using the CPG/MSSR driver core. This will enable
support for module resets, which are not supported by the existing
driver.
The old driver can still be used through a Kconfig option, to preserve
backward
Add all R-Car V2H Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2c ("List of Clocks [R-Car V2H]") of the R-Car Gen2 Hardware
User's Manual rev. 2.00.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Niklas Söderlund
---
v2:
- Add Reviewed-by.
---
Add all R-Car E2 Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2d ("List of Clocks [R-Car E2]") of the R-Car Gen2 Hardware
User's Manual rev. 2.00.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Niklas Söderlund
---
v2:
- Add Reviewed-by.
---
Hi all,
Currently Renesas R-Car Gen2 SoCs use the common clk-rcar-gen2,
clk-mstp, and clk-div6 drivers, which depend on most clocks being
described in DT. Especially the module (MSTP) clocks are cumbersome and
error prone, due to 3 arrays (clocks, clock-indices, and
clock-output-names)
On 05/18/2017 08:25 PM, Laurent Pinchart wrote:
Hi Archit,
On Thursday 18 May 2017 13:56:19 Archit Taneja wrote:
On 05/17/2017 12:16 AM, Eric Anholt wrote:
[snip]
In terms of physical connections:
[15-pin "DSI" connector on 2835]
| I2C | DSI
/ \SPI
Hi,
On 19/05/17 09:29, Icenowy Zheng wrote:
>
>
> 于 2017年5月19日 GMT+08:00 下午4:27:21, Andre Przywara 写到:
>> Hi,
>>
>> On 18/05/17 08:16, Icenowy Zheng wrote:
>>> Add support of AXP803 regulators in the Pine64 device tree, in order
>> to
>>> enable many future functionalities, e.g. Wi-Fi.
>>>
>>>
Hi William,
Em Thu, 18 May 2017 22:13:55 -0400
William Breathitt Gray escreveu:
> On Thu, May 18, 2017 at 10:24:00PM -0300, Mauro Carvalho Chehab wrote:
> >Each text file under Documentation follows a different
> >format. Some doesn't even have titles!
> >
> >Change its representation to follow
On 05/15/2017 10:58 AM, Michal Hocko wrote:
> From: Michal Hocko
>
> The current memory hotplug implementation relies on having all the
> struct pages associate with a zone/node during the physical hotplug phase
> (arch_add_memory->__add_pages->__add_section->__add_zone). In the vast
> majority
On 2017/5/18 17:46, Xishi Qiu wrote:
> Hi, my system triggers this bug, and the vmcore shows the anon_vma seems be
> freed.
> The kernel is RHEL 7.2, and the bug is hard to reproduce, so I don't know if
> it
> exists in mainline, any reply is welcome!
>
When we alloc anon_vma, we will init
On Fri, May 19, 2017 at 04:29:01PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年5月19日 GMT+08:00 下午4:27:21, Andre Przywara 写到:
> >Hi,
> >
> >On 18/05/17 08:16, Icenowy Zheng wrote:
> >> Add support of AXP803 regulators in the Pine64 device tree, in order
> >to
> >> enable many future
Hi,
> >We could also do it the other way around: Instead of having the kernel
> >returning
>
> >the plane description userspace could pass it in, and the kernel throws
> >-EINVAL in
>
> >case it doesn't match due to things having changed meanwhile.
>
> Or just return a dmabuf based on
Hi all,
this series changes our automatic MSI-X vector assignment so that it
takes all present CPUs into account instead of all online ones. This
allows to better deal with cpu hotplug events, which could happen
frequently due to power management for example.
Changes since V1:
- rebase to
This will allow us to spread MSI/MSI-X affinity over all present CPUs and
thus better deal with systems where cpus are take on and offline all the
time.
Signed-off-by: Christoph Hellwig
---
kernel/irq/manage.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Currently we only assign spread vectors to online CPUs, which ties the
IRQ mapping to the currently online devices and doesn't deal nicely with
the fact that CPUs could come and go rapidly due to e.g. power management.
Instead assign vectors to all present CPUs to avoid this churn.
Unlike most drіvers that simply pass the maximum possible vectors to
pci_alloc_irq_vectors NVMe needs to configure the device before allocting
the vectors, so it needs a manual update for the new scheme of using
all present CPUs.
Signed-off-by: Christoph Hellwig
---
drivers/nvme/host/pci.c | 2
Factor out code from the x86 cpu hot plug code to program the affinity
for a vector for a hot plug / hot unplug event.
Signed-off-by: Christoph Hellwig
---
arch/x86/kernel/irq.c | 23 ++-
include/linux/interrupt.h | 1 +
kernel/irq/affinity.c | 26
Currently we only create hctx for online CPUs, which can lead to a lot
of churn due to frequent soft offline / online operations. Instead
allocate one for each present CPU to avoid this and dramatically simplify
the code.
Signed-off-by: Christoph Hellwig
---
block/blk-mq.c | 120
Remove a CPU from the affinity mask when it goes offline and add it
back when it returns. In case the vetor was assigned only to the CPU
going offline it will be shutdown and re-started when the CPU
reappears.
Signed-off-by: Christoph Hellwig
---
arch/x86/kernel/irq.c | 3 +-
This way we get a nice distribution independent of the current cpu
online / offline state.
Signed-off-by: Christoph Hellwig
---
block/blk-mq-cpumap.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/block/blk-mq-cpumap.c b/block/blk-mq-cpumap.c
index
Hi
Here are some patches to support Intel PT Power events and PTWRITE.
Power events report changes to C-state but I have also added support
for the existing CBR (core-to-bus ratio) packet and included that
when outputting power events. The PTWRITE packet is associated with
the new ptwrite
Fix message because cpu list option is -C not -c
Signed-off-by: Adrian Hunter
---
tools/perf/util/session.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/util/session.c b/tools/perf/util/session.c
index 7dc1096264c5..d19c40a81040 100644
---
Add itrace option to output power events.
Signed-off-by: Adrian Hunter
---
tools/perf/Documentation/itrace.txt | 5 +++--
tools/perf/util/auxtrace.c | 4
tools/perf/util/auxtrace.h | 2 ++
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git
Factor out intel_pt_set_event_name() so it can be reused.
Signed-off-by: Adrian Hunter
---
tools/perf/util/intel-pt.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c
index
Sometimes a FUP packet is associated with a TSX transaction and a flag is
set to indicate that. Ensure that flag is cleared on any error condition
because at that point the decoder can no longer assume it is correct.
Signed-off-by: Adrian Hunter
---
On Fri, May 19, 2017 at 10:45 AM, Geert Uytterhoeven
wrote:
> Currently Renesas R-Car Gen2 SoCs use the common clk-rcar-gen2,
> clk-mstp, and clk-div6 drivers, which depend on most clocks being
> described in DT. Especially the module (MSTP) clocks are cumbersome and
> error prone, due to 3
Decoding auxtrace data can take a long time. To avoid decoding
unnecessarily, filter auxtrace data that is collected per-cpu before it is
decoded.
Signed-off-by: Adrian Hunter
---
tools/perf/builtin-report.c | 1 +
tools/perf/builtin-script.c | 1 +
tools/perf/util/auxtrace.c | 10 ++
The decoder uses its current timestamp in samples. Usually that is a
timestamp that has already passed, but in some cases it is a timestamp for
a branch that the decoder is walking towards, and consequently hasn't
reached. Improve that situation by using the pkt_state to determine when
to use the
Add script intel-pt-events.py that provides an example of how to unpack the
raw data for power events and PTWRITE.
Signed-off-by: Adrian Hunter
---
.../perf/scripts/python/bin/intel-pt-events-record | 13 +++
.../perf/scripts/python/bin/intel-pt-events-report | 3 +
CBR (core-to-bus ratio) packets provide an indication of CPU frequency. A
more accurate measure can be made by counting the cycles (given by CYC
packets) in between other timing packets (either MTC or TSC). Using TSC
packets has at least 2 issues: 1) timing might have stopped (e.g. mwait) or
2)
intel_pt_synth_events() uses the same attr structure to create each event.
Move the code around a bit to simplify that.
Signed-off-by: Adrian Hunter
---
tools/perf/util/intel-pt.c | 45 ++---
1 file changed, 22 insertions(+), 23 deletions(-)
diff --git
Update documentation to include new ptwrite and power events.
Signed-off-by: Adrian Hunter
---
tools/perf/Documentation/intel-pt.txt | 42 +--
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/tools/perf/Documentation/intel-pt.txt
Synthesize new power and ptwrite events.
Signed-off-by: Adrian Hunter
---
tools/perf/util/intel-pt.c | 283 +
1 file changed, 283 insertions(+)
diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c
index ace79a405f98..754e92ee6c3e
Tidy print messages into called function intel_pt_synth_event().
Signed-off-by: Adrian Hunter
---
tools/perf/util/intel-pt.c | 42 ++
1 file changed, 18 insertions(+), 24 deletions(-)
diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c
Add definitions for synthesized Intel PT events for power and ptwrite.
Signed-off-by: Adrian Hunter
---
tools/perf/builtin-script.c | 114 +++-
tools/perf/util/event.h | 90 ++
2 files changed, 203 insertions(+), 1
Tidy the lookup of the Intel PT selected event (perf_evsel) into a separate
function.
Signed-off-by: Adrian Hunter
---
tools/perf/util/intel-pt.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/tools/perf/util/intel-pt.c
On Thu, May 18, 2017 at 10:31:13PM -0400, David Miller wrote:
> From: Babu Moger
> Date: Thu, 18 May 2017 18:36:08 -0600
>
> > @@ -82,6 +82,7 @@ config SPARC64
> > select HAVE_ARCH_AUDITSYSCALL
> > select ARCH_SUPPORTS_ATOMIC_RMW
> > select HAVE_NMI
> > + select
Join needlessly wrapped lines.
Signed-off-by: Adrian Hunter
---
tools/perf/util/intel-pt.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c
index f8237a0e2946..b670502b0264 100644
--- a/tools/perf/util/intel-pt.c
Remove unused struct intel_pt member instructions_sample_period.
Signed-off-by: Adrian Hunter
---
tools/perf/util/intel-pt.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c
index dbff5dca09f0..f8237a0e2946 100644
---
Factor out common code in functions synthesizing event samples i.e.
intel_pt_synth_branch_sample(), intel_pt_synth_instruction_sample() and
intel_pt_synth_transaction_sample().
Signed-off-by: Adrian Hunter
---
tools/perf/util/intel-pt.c | 222 -
1
Add itrace option to output ptwrite events.
Signed-off-by: Adrian Hunter
---
tools/perf/Documentation/itrace.txt | 7 ---
tools/perf/util/auxtrace.c | 4
tools/perf/util/auxtrace.h | 2 ++
3 files changed, 10 insertions(+), 3 deletions(-)
diff --git
Add byte-swapping macros to kernel.h
Signed-off-by: Adrian Hunter
---
tools/include/linux/kernel.h | 35 +--
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/tools/include/linux/kernel.h b/tools/include/linux/kernel.h
index
'transactions_sample_type' is needed to correctly inject transactions
samples but it was not being set. Set it from the event sample type.
Signed-off-by: Adrian Hunter
---
tools/perf/util/intel-pt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf/util/intel-pt.c
Instruction trace decoders such as Intel PT may have additional information
recorded in the trace. For example, Intel PT has power information and a
there is a new instruction 'ptwrite' that can write a value into a PTWRITE
trace packet. Such information may be associated with an IP and so can be
On 05/19/2017 08:59 AM, Konstantin Khlebnikov wrote:
> Show count of global oom killer invocations in /proc/vmstat
Maybe some more rationale why is that useful?
Vlastimil
> Signed-off-by: Konstantin Khlebnikov
> ---
> include/linux/vm_event_item.h |1 +
> mm/oom_kill.c |
Add a field to display the content the raw_data of a synthesized event.
Signed-off-by: Adrian Hunter
---
tools/perf/Documentation/perf-script.txt | 6 +-
tools/perf/builtin-script.c | 20 ++--
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git
Add decoder support for informing the tools of changes to the core-to-bus
ratio (CBR).
Signed-off-by: Adrian Hunter
---
tools/perf/util/intel-pt-decoder/intel-pt-decoder.c | 19 +++
tools/perf/util/intel-pt-decoder/intel-pt-decoder.h | 2 ++
2 files changed, 21 insertions(+)
Move decoder error setting into one condition.
Signed-off-by: Adrian Hunter
---
tools/perf/util/intel-pt-decoder/intel-pt-decoder.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c
Fix message because field list option is -F not -f.
Signed-off-by: Adrian Hunter
---
tools/perf/builtin-script.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c
index d05aec491cff..79a101e0e13b 100644
---
Future proof CBR packet decoding by passing through also the undefined
'reserved' byte in the packet payload.
Signed-off-by: Adrian Hunter
---
tools/perf/util/intel-pt-decoder/intel-pt-decoder.c | 2 +-
tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c | 2 +-
2 files changed, 2
'initial_skip' is checked inside the sample synthesis functions which means
it is actually being done twice for 'instructions' and 'transactions'
samples. Remove the redundant checks.
Signed-off-by: Adrian Hunter
---
tools/perf/util/intel-pt.c | 8 ++--
1 file changed, 2 insertions(+), 6
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