When migrating callbacks from a newly offlined CPU, we are already
holding the root rcu_node structure's lock, so it costs almost nothing
to advance and accelerate the newly migrated callbacks. This patch
therefore makes this advancing and acceleration happen.
Signed-off-by: Paul E. McKenney
2017-07-25 5:58 GMT+08:00 Paul E. McKenney :
> From: Wanpeng Li
>
> BUG: using smp_processor_id() in preemptible [] code: 99-trinity/181
What's the meaning of EXP? Btw, the patch is in linus's tree currently.
Regards,
Wanpeng Li
On 07/24/2017 04:52 AM, Johan Hovold wrote:
> Since commit a8636c89648a ("PM / Runtime: Don't allow to suspend a
> device with an active child"), which went into 4.10, it is no longer
> permitted to set RPM_SUSPENDED state for a device with active children
> (unless power.ignore_children is
Tree RCU guarantees that every online CPU has a memory barrier between
any given grace period and any of that CPU's RCU read-side sections that
must be ordered against that grace period. Since RCU doesn't always
know where read-side critical sections are, the actual implementation
guarantees
Classic SRCU is no more, so this commit removes the corresponding
rcutorture boot-parameters file.
Signed-off-by: Paul E. McKenney
---
tools/testing/selftests/rcutorture/configs/rcu/SRCU-C.boot | 1 -
1 file changed, 1 deletion(-)
delete mode 100644
The function process_srcu() is not invoked outside of srcutree.c, so
this commit makes it static and drops the EXPORT_SYMBOL_GPL().
Signed-off-by: Paul E. McKenney
---
include/linux/srcutree.h | 2 --
kernel/rcu/srcutree.c| 4 ++--
2 files changed, 2
Hello!
This series contains torture-test updates:
1. Move SRCU status printing to SRCU implementations.
2. Print SRCU lock/unlock totals because I am getting tired of
doing the addition in my head.
3. Remove CONFIG_TASKS_RCU ifdef from rcuperf.c.
4. Select
Hclk is the MCAN's interface clock. However, for OMAP based devices such as
DRA7 SoC family the interface clock is handled by hwmod. Therefore, this
interface clock is managed by hwmod driver via pm_runtime_get and
pm_runtime_put calls. Therefore, this interface clock isn't defined in DT
and thus
On Mon, 24 Jul 2017, Juergen Gross wrote:
> On 22/07/17 02:11, Stefano Stabellini wrote:
> > Send PVCALLS_ACCEPT to the backend. Allocate a new active socket. Make
> > sure that only one accept command is executed at any given time by
> > setting PVCALLS_FLAG_ACCEPT_INFLIGHT and waiting on the
> >
Add PM runtime support to the MCAN driver. To support devices that don't
use PM runtime leave the original clk calls in the driver. Perhaps in the
future when it makes sense we can remove these non pm runtime clk calls.
Version 2 changes:
Used NULL instead of 0 for unused hclk handle
Franklin S
Aviad Krawczyk :
[...]
> hinic_remove - If insmod failed and someone calls rmmod, we will get a
> crash because the resource are already free. Therefore we test if the
> device exists, please tell me if you meant to something different
The module won't even proceed
From: "Dennis Zhou (Facebook)"
The bitmap allocator must keep metadata consistent. The easiest way is
to scan after every allocation for each affected block and the entire
chunk. This is rather expensive.
The free path can take advantage of current contig hints to prevent
From: "Dennis Zhou (Facebook)"
The largest free region will either be a block level contig hint or an
aggregate over the left_free and right_free areas of blocks. This is a
much smaller set of free areas that need to be checked than a full
traverse.
Signed-off-by: Dennis
From: "Dennis Zhou (Facebook)"
This patch introduces the bitmap metadata blocks and adds the skeleton
of the code that will be used to maintain these blocks. Each chunk's
bitmap is made up of full metadata blocks. These blocks maintain basic
metadata to help prevent
From: "Dennis Zhou (Facebook)"
This patch makes the contig hint starting offset optimization from the
previous patch as honest as it can be. For both chunk and block starting
offsets, make sure it keeps the starting offset with the best alignment.
The block skip
From: "Dennis Zhou (Facebook)"
The simple, and expensive, way to find a free area is to iterate over
the entire bitmap until an area is found that fits the allocation size
and alignment. This patch makes use of an iterate that find an area to
check by using the block level
From: "Dennis Zhou (Facebook)"
This patch adds first_bit to keep track of the first free bit in the
bitmap. This hint helps prevent scanning of fully allocated blocks.
Signed-off-by: Dennis Zhou
---
mm/percpu-internal.h | 2 +-
mm/percpu-stats.c
From: "Dennis Zhou (Facebook)"
Metadata is kept per block to keep track of where the contig hints are.
Scanning can be avoided when the contig hints are not broken. In that
case, left and right contigs have to be managed manually.
This patch changes the allocation path
From: "Dennis Zhou (Facebook)"
The area map allocator only used a bitmap for the backing page state.
The new bitmap allocator will use bitmaps to manage the allocation
region in addition to this.
This patch generalizes the bitmap iterators so they can be reused with
the
On Tue, Jul 18, 2017 at 08:58:50AM +0800, Caesar Wang wrote:
> Rob,
>
> 在 2017年07月18日 04:07, Rob Herring 写道:
> > On Mon, Jul 17, 2017 at 04:14:28PM +0800, Caesar Wang wrote:
> > > This patch adds the MALI's power-model to set the IPA model to be used
> > > for power management.
> > What's IPA?
On Mon, Jul 17, 2017 at 03:39:55PM +0200, Sebastian Reichel wrote:
> From: Milo Kim
>
> Add DT binding for ti-lmu devices.
>
> Signed-off-by: Milo Kim
> Signed-off-by: Sebastian Reichel
> ---
>
On Thu, 20 Jul 2017 12:17:12 +0100
Robin Murphy wrote:
> On 20/07/17 10:10, Will Deacon wrote:
> > On Thu, Jul 20, 2017 at 09:32:00AM +0530, Anup Patel wrote:
> >> On Wed, Jul 19, 2017 at 5:23 PM, Will Deacon wrote:
> >>> There are two things here:
On Tue, Jul 18, 2017 at 03:33:29PM +0800, Icenowy Zheng wrote:
> Allwinner H5 has a Mali-450 MP4 GPU, which has a reset line like other
> Allwinner SoCs with Mali Utgard, but it's a Mali-450, so it needs a new
> compatible.
>
> Add the new compatible to Mali Utgard binding document.
>
>
On Tegra186, the BPMP (Boot and Power Management Processor) exposes an
interface to thermal sensors on the system-on-chip. This driver
implements access to the interface. It supports reading the
temperature, setting trip points and receiving notification of a
tripped trip point.
Signed-off-by:
Em Mon, Jul 24, 2017 at 10:46:38AM -0700, Andi Kleen escreveu:
> On Mon, Jul 24, 2017 at 02:34:37PM -0300, Arnaldo Carvalho de Melo wrote:
> > Em Sun, Jul 23, 2017 at 08:46:20AM -0700, Andi Kleen escreveu:
> > > On Sun, Jul 23, 2017 at 07:46:05AM +0900, Namhyung Kim wrote:
> > > > Hi Arnaldo and
On Mon, Jul 24, 2017 at 10:19:24AM -0700, Greg Hackmann wrote:
> Commit ff86bf0c65f1 ("alarmtimer: Rate limit periodic intervals") sets a
> minimum bound on the alarm timer interval. This minimum bound shouldn't
> be applied if the interval is 0. Otherwise, one-shot timers will be
> converted
On 07/22/2017 09:50 AM, Tejun Heo wrote:
> Hello, Waiman.
>
> On Fri, Jul 21, 2017 at 04:34:51PM -0400, Waiman Long wrote:
>> The special prefix '#' attached to a controller name can now be written
>> into the cgroup.subtree_control file to set that controller in bypass
>> mode in all the child
On Mon, Jul 24, 2017 at 2:07 AM, Ingo Molnar wrote:
>
> * Kees Cook wrote:
>
>> +config ARCH_HAS_REFCOUNT
>> + bool
>> + help
>> + An architecture selects this when it has implemented refcount_t
>> + using primitizes that provide a
On Tue, Jul 18, 2017 at 04:27:15PM +0530, Keerthy wrote:
> Add a separate compatible for keystone-k2g soc
>
> Signed-off-by: Keerthy
> ---
> Documentation/devicetree/bindings/gpio/gpio-davinci.txt | 3 ++-
> drivers/gpio/gpio-davinci.c | 1 +
> 2
2017-07-24 18:59+0200, Paolo Bonzini:
> This reverts the change of commit f85c758dbee54cc3612a6e873ef7cecdb66ebee5,
> as the behavior it modified was intended.
>
> The VM is running in 32-bit PAE mode, and Table 4-7 of the Intel manual
> says:
>
> Table 4-7. Use of CR3 with PAE Paging
> Bit
On 07/12/2017 03:30 AM, Naresh Kamboju wrote:
> Hi Fathi and Shuah,
>
> On 29 June 2017 at 14:07, Fathi Boudra wrote:
>> On 28 June 2017 at 17:21, Shuah Khan wrote:
>>> On 06/28/2017 02:30 AM, Fathi Boudra wrote:
On 23 June 2017 at 22:44, Shuah
On Mon, Jul 24, 2017 at 1:57 AM, Viresh Kumar wrote:
> On 23-07-17, 08:54, Joel Fernandes wrote:
>> Currently the iowait_boost feature in schedutil makes the frequency go to max
>> on iowait wakeups. This feature was added to handle a case that Peter
>> described where
On Mon, 24 Jul 2017 10:33:25 -0700
Feng Kan wrote:
> On Sun, Jul 23, 2017 at 7:06 PM, Alex Williamson
> wrote:
> > On Fri, 21 Jul 2017 13:20:18 -0700
> > Feng Kan wrote:
> >
> >> On Thu, Jul 20, 2017 at 3:22 PM, Alex Williamson
> >>
On Mon, Jul 24, 2017 at 03:56:27PM +, Kani, Toshimitsu wrote:
> Yes, Mauro has already pointed this out. As I replied to him, we do
> have a separate series of platforms that do not have built-in RAS, and
So this whitelist entry
+static struct acpi_oemlist oemlist[] = {
+ {"HPE ",
[ Trimming CC list ]
On 19/07/2017 21:07, Doug Berger wrote:
> From: Florian Fainelli
>
> The only usage of the irq_gc_mask_disable_reg_and_ack() function
> is by the Tango irqchip driver. This usage is replaced by the
> irq_gc_mask_disable_and_ack_set() function since it
Use the new descriptor based GPIO API instead of
the legacy one, which results in cleaner code
with less lines of code.
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c | 74 +
1 file changed, 27
While physical size information is automatically parsed for EDID
based displays, we need to provide it manually for displays providing
one fixed mode.
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/omapdrm/dss/omapdss.h| 2 ++
Add support for regulators used by panels found inside
of the Nokia N950, N9 and Motorola Droid 4.
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c | 57 +++--
1 file changed, 53 insertions(+), 4
When walking the page tables to resolve an address that points to
!present_p*d() entry, huge_pte_offset() returns inconsistent values
depending on the level of page table (PUD or PMD).
In the case of a PUD entry, it returns NULL while in the case of a PMD
entry, it returns a pointer to the page
Add support to load physical size information from DT using
the properties defined by the common panel binding.
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c | 19 +++
1 file changed, 19 insertions(+)
Em Mon, Jul 24, 2017 at 07:09:07PM +0800, Jin Yao escreveu:
> Current --branch-history LBR annotation displays confused
> data. For example, each cycles report is duplicated on both
> "from" and "to" entries.
Andi, can you take a look at this? An Acked-by you or Reviewed-by would
be great to
In Tegra186, the BPMP (Boot and Power Management Processor) implements
an interface that is used to read system temperatures, including CPU
cluster and GPU temperatures. This binding describes the thermal sensor
that is exposed by BPMP.
Signed-off-by: Mikko Perttunen
On 07/18/2017 12:37 PM, Florian Fainelli wrote:
> Adds support for the Broadcom reference board BCM947189ACDMBR which
> features the following:
>
> * 128MB of DRAM
> * External MoCA support through a Broadcom BCM6802 chip
> * 1x external Gigabit PHY through the external BCM6802
> * 1x USB 2.0
On 24/07/17 18:20, Jassi Brar wrote:
> On Mon, Jul 24, 2017 at 4:50 AM, André Przywara
> wrote:
>> On 02/07/17 06:55, Jassi Brar wrote:
>>
+ mbox_chan_received_data(link, (void *)res.a0);
+
>>> Or you can update the 'data' with value from 'a0' ?
>>
>>
On Sun, 2017-07-23 at 12:54 +0300, Andy Shevchenko wrote:
> On Sun, Jul 23, 2017 at 4:15 AM, Lyude wrote:
>
> > So, call hid_hw_open() in rmi_post_resume() so we make sure that
> > the
> > device is alive before we try talking to it.
> >
> > This fixes RMI device
On Mon, 2017-07-24 at 18:37 +0200, Borislav Petkov wrote:
> On Mon, Jul 24, 2017 at 03:56:27PM +, Kani, Toshimitsu wrote:
> > Yes, Mauro has already pointed this out. As I replied to him, we
> > do have a separate series of platforms that do not have built-in
> > RAS, and
>
> So this
On Mon, Jul 24, 2017 at 02:34:37PM -0300, Arnaldo Carvalho de Melo wrote:
> Em Sun, Jul 23, 2017 at 08:46:20AM -0700, Andi Kleen escreveu:
> > On Sun, Jul 23, 2017 at 07:46:05AM +0900, Namhyung Kim wrote:
> > > Hi Arnaldo and Taeung,
> > >
> > > (+ Andi)
> > >
> > > On Fri, Jul 21, 2017 at
On Sat, Jul 22, 2017 at 1:25 PM, Eric W. Biederman
wrote:
> I played with some clever changes such as limiting the copy to 48 bytes,
> disabling the memset and the like but I could not get a strong enough
> signal to say that any one change removed the extra or a clear part
On Mon, Jul 24, 2017 at 02:42:09PM -0300, Arnaldo Carvalho de Melo wrote:
> Em Mon, Jul 24, 2017 at 04:16:49PM +0200, Jiri Olsa escreveu:
> > On Fri, Jul 21, 2017 at 05:31:59PM -0700, Sukadev Bhattiprolu wrote:
> > > Andi Kleen [a...@firstfloor.org] wrote:
> > > > From: Andi Kleen
On Mon, Jul 17, 2017 at 02:25:38PM -0500, Christopher Bostic wrote:
> Describe device tree optional properties:
>
> * aspeed,reset-type = "cpu|soc|system|none"
> One of three different, mutually exclusive, values
>
> "cpu" : ARM CPU reset on signal
> "soc" : 'System on chip'
On Mon, Jul 24, 2017 at 06:57:53PM +0300, Andrey Ryabinin wrote:
>
>
> On 07/24/2017 06:37 PM, Kirill A. Shutemov wrote:
> > On Mon, Jul 24, 2017 at 06:25:58PM +0300, Andrey Ryabinin wrote:
> >> KASAN fills kernel page tables with repeated values to map several
> >> TBs of the virtual memory to
On 07/24/2017 09:40 AM, Marc Gonzalez wrote:
> [ Trimming CC list ]
>
> On 19/07/2017 21:07, Doug Berger wrote:
>
>> From: Florian Fainelli
>>
>> The only usage of the irq_gc_mask_disable_reg_and_ack() function
>> is by the Tango irqchip driver. This usage is replaced by
On Mon, 2017-07-24 at 20:50 +0300, Boris Petkov wrote:
> On July 24, 2017 8:44:03 PM GMT+03:00, "Kani, Toshimitsu" @hpe.com> wrote:
> > I assumed our platforms w/o build-in RAS do not implement GHES,
>
> If we make it a normal module, it will be decoupled from GHES and it
> will rely only on the
Em Mon, 24 Jul 2017 15:56:27 +
"Kani, Toshimitsu" escreveu:
> On Mon, 2017-07-24 at 17:37 +0200, Borislav Petkov wrote:
> > On Mon, Jul 24, 2017 at 03:25:34PM +, Kani, Toshimitsu wrote:
> :
> >
> > > We've been providing this model for many years now.
> >
> >
On Mon, 2017-07-24 at 14:56 -0300, Mauro Carvalho Chehab wrote:
> Em Mon, 24 Jul 2017 15:56:27 +
:
> That's probably too late for me as I received a new HP machine
> we bought just last week, but for the next time I would need to
> get a new hardware, what would be the non-RAS equivalent to
>
On Tue 25-07-17 00:42:05, kbuild test robot wrote:
> Hi Michal,
>
> [auto build test ERROR on mmotm/master]
> [also build test ERROR on v4.13-rc2 next-20170724]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improve the system]
>
Now bisected and verified via revert, the culprit is:
cf8e0fedf078 mm/zsmalloc: simplify zs_max_alloc_size handling
Reproducer: ltp::testcases/bin/zram03.
-Mike
Add static inline stubs to bpmp.h when CONFIG_BPMP is not enabled.
This allows building BPMP-related drivers with COMPILE_TEST.
Signed-off-by: Mikko Perttunen
---
v2:
- added patch
include/soc/tegra/bpmp.h | 42 +++---
1 file changed,
On Mon, Jul 24, 2017 at 6:09 PM, Jerome Brunet wrote:
> On Mon, 2017-07-24 at 14:26 +0200, Neil Armstrong wrote:
>> On 07/24/2017 02:06 PM, Neil Armstrong wrote:
>> > On 07/23/2017 07:03 PM, Joseph Kogut wrote:
>> > > Hi Kevin,
>> > >
>> > > I tested on a P212 reference
This implements refcount_t overflow protection on x86 without a noticeable
performance impact, though without the fuller checking of REFCOUNT_FULL.
This is done by duplicating the existing atomic_t refcount implementation
but with normally a single instruction added to detect if the refcount
has
The coming x86 refcount protection needs to be able to add trailing
instructions to the GEN_*_RMWcc() operations. This extracts the
difference between the goto/non-goto cases so the helper macros
can be defined outside the #ifdef cases. Additionally adds argument
naming to the resulting asm for
This series implements a fast refcount overflow protection for x86,
which is needed to provide coverage for the several refcount-overflow
use-after-free flaws the kernel has seen over the last many years.
Patch 1 provides support for adding additional assembly to the GEN_*_RMWcc
macros, patch 2
This creates an unreachable annotation in asm for CONFIG_STACK_VALIDATION.
While here, adjust earlier uses of \t\n into \n\t.
Suggested-by: Josh Poimboeuf
Signed-off-by: Kees Cook
---
include/linux/compiler-gcc.h | 13 +
Hi Michal,
[auto build test ERROR on mmotm/master]
[also build test ERROR on v4.13-rc2 next-20170724]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Michal-Hocko/mm-oom-allow-oom-reaper-to-race
On 24/07/17 11:29, Suzuki K Poulose wrote:
> Add a helper to map a device node to a logical CPU number to avoid
> duplication. Currently this is open coded in different places (e.g
> gic-v3, coresight). The helper tries to map device node to a "possible"
> logical CPU id, which may not be online
On 07/20/2017 06:42 AM, Egil Hjelmeland wrote:
> Must be set to 1 by user space when STP is used on the lan9303.
> If bridging without local STP, leave at 0, so external STP BPDUs
> are forwarded.
>
> Hopefully the kernel can be improved so the driver can handle this
> without user intervention,
To be able to use the common 4k zero page in DAX we need to have our PTE
fault path look more like our PMD fault path where a PTE entry can be
marked as dirty and writeable as it is first inserted rather than waiting
for a follow-up dax_pfn_mkwrite() => finish_mkwrite_fault() call.
Right now we
On Wed, Jul 19, 2017 at 10:58 AM, Thomas Garnier wrote:
> The work pending loop can call set_fs after addr_limit_user_check
> removed the _TIF_FSCHECK flag. To prevent the infinite loop, move
> the addr_limit_user_check call at the beginning of the loop.
>
> Fixes:
On 20 July 2017 at 04:17, Suzuki K Poulose wrote:
> Coresight TMC splits 64bit registers into a pair of 32bit registers
> (e.g DBA, RRP, RWP). Provide helpers to read/write to these registers.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K
On 20 July 2017 at 04:17, Suzuki K Poulose wrote:
> This series adds support for ARM Coresight SoC-600 IP, which implements
> Coresight V3 architecture. It also does some clean up of the replicator
> driver namings used in the driver to prevent confusions to the user.
>
>
Hi Nick,
[auto build test WARNING on linus/master]
[also build test WARNING on v4.13-rc2 next-20170724]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Nick-Terrell/Add-xxhash-and-zstd-modules
On Mon, Jul 24, 2017 at 6:09 PM, Andrey Smirnov
wrote:
> Add a driver for RAVE Supervisory Processor, an MCU implementing
> varoius bits of housekeeping functionality (watchdoging, backlight
> control, LED control, etc) on RAVE family of products by Zodiac
> Inflight
Remove driver (un)register API defines. They do not even exist
anymore.
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/omapdrm/dss/omapdss.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h
Group timers callback initializers together in
x86_intel_mid_early_setup() for easy to find and maintain.
No functional change intended.
Signed-off-by: Andy Shevchenko
---
arch/x86/platform/intel-mid/intel-mid.c | 2 +-
1 file changed, 1 insertion(+), 1
Hi,
This adds support for command mode DSI panels to
omapdrm. I tested the patches on Nokia N950 (omap3)
and Motorola Droid 4 (omap4). This is basically
PATCHv3 of my series adding N950 display support,
but I started from scratch without reverting the
removal of manual display update support.
Add basic panel support for the Nokia N950. It must be tweaked a
little bit later, since the panel was built into the device
upside-down. Also the first 5 and the last 5 pixels are covered
by plastic.
Signed-off-By: Sebastian Reichel
---
Ack. You have numbers, it's all good.
Except I'd still want you to comment on why you cared and about which
piece of your upcoming code this is going to matter for, ok?
Linus
On 07/22/2017 09:43 AM, Tejun Heo wrote:
> Hello, Waiman.
>
> On Fri, Jul 21, 2017 at 04:34:50PM -0400, Waiman Long wrote:
>> When thread mode is used, it is possible that some cgroups may be
>> in an invalid state. Currently users may not be aware that they are
>> invalid until they try to
On July 24, 2017 8:44:03 PM GMT+03:00, "Kani, Toshimitsu"
wrote:
>I assumed our platforms w/o build-in RAS do not implement GHES,
If we make it a normal module, it will be decoupled from GHES and it will rely
only on the whitelist to load.
--
Sent from a small device:
On Mon, Jul 24, 2017 at 11:08 PM, Sudeep Holla wrote:
> On 24/07/17 18:20, Jassi Brar wrote:
>>
>>> I see that the SCPI firmware driver (as the user of the mailbox API) is
>>> expecting the return value from a0 as returned above, translating the
>>> firmware error codes
Em Mon, 24 Jul 2017 18:44:00 +0200
Borislav Petkov escreveu:
> On Mon, Jul 24, 2017 at 01:04:13PM -0300, Mauro Carvalho Chehab wrote:
> > If the Kernel force those users to use ghes_edac by default,
> > they they won't see the error counts anymore, but, instead,
> > hardware
On Tue, Jul 18, 2017 at 03:29:40PM +0800, Icenowy Zheng wrote:
> Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use
> an out-of-band interrupt pin instead of SDIO in-band interrupt.
>
> Add the device tree binding of this chip, in order to make it possible
> to add this
(Sending to your other mail address because there's some temporary resolution
issue:
msmtp: recipient address mche...@s-opensource.com not accepted by the server
msmtp: server message: 451 4.3.0 : Temporary lookup
failure
msmtp: could not send mail (account alien8.de
On Tue, Jul 18, 2017 at 03:46:07PM +0100, Harvey Hunt wrote:
> Update links to the PDFs of PCI and interrupt mapping bindings, as
> the previous links are broken.
>
> Signed-off-by: Harvey Hunt
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
>
On Mon, Jul 24, 2017 at 10:24:41AM +0200, Daniel Vetter wrote:
> On Mon, Jul 24, 2017 at 2:03 AM, Stephen Rothwell
> wrote:
> > Hi Daniel,
> >
> > On Fri, 21 Jul 2017 09:24:49 +0200 Daniel Vetter
> > wrote:
> >>
> >> How are we going to handle
This adds the thermal sensor device provided by the BPMP, and the
relevant thermal sensors to the Tegra186 device tree.
Signed-off-by: Mikko Perttunen
---
v2:
- added trips and cooling-maps nodes
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 103
Now that we no longer insert struct page pointers in DAX radix trees we can
remove the special casing for DAX in page_cache_tree_insert(). This also
allows us to make dax_wake_mapping_entry_waiter() local to fs/dax.c,
removing it from dax.h.
Signed-off-by: Ross Zwisler
When servicing mmap() reads from file holes the current DAX code allocates
a page cache page of all zeroes and places the struct page pointer in the
mapping->page_tree radix tree. This has three major drawbacks:
1) It consumes memory unnecessarily. For every 4k page that is read via a
DAX
dax_load_hole() will soon need to call dax_insert_mapping_entry(), so it
needs to be moved lower in dax.c so the definition exists.
dax_wake_mapping_entry_waiter() will soon be removed from dax.h and be made
static to dax.c, so we need to move its definition above all its callers.
Signed-off-by:
Now that we no longer insert struct page pointers in DAX radix trees the
page cache code no longer needs to know anything about DAX exceptional
entries. Move all the DAX exceptional entry definitions from dax.h to
fs/dax.c.
Signed-off-by: Ross Zwisler
Suggested-by:
On 20 July 2017 at 04:17, Suzuki K Poulose wrote:
> The coresight SoC 600 supports ETR save-restore which allows us
> to restore a trace session by retaining the RRP/RWP/STS.Full values
> when the TMC leaves the Disabled state. However, the TMC doesn't
> have a
On Mon, 24 Jul 2017, Johan Hovold wrote:
> On Mon, Jul 24, 2017 at 10:38:41AM -0400, Alan Stern wrote:
> > On Mon, 24 Jul 2017, Johan Hovold wrote:
> >
> > > Make sure that the controller is runtime resumed when system suspending
> > > to avoid an external abort when accessing the interrupt
Commit ff86bf0c65f1 ("alarmtimer: Rate limit periodic intervals") sets a
minimum bound on the alarm timer interval. This minimum bound shouldn't
be applied if the interval is 0. Otherwise, one-shot timers will be
converted into periodic ones.
This patch is against 4.9.39, and is only needed in
On Mon, Jul 24, 2017 at 4:50 AM, André Przywara wrote:
> On 02/07/17 06:55, Jassi Brar wrote:
>
>>> + mbox_chan_received_data(link, (void *)res.a0);
>>> +
>> Or you can update the 'data' with value from 'a0' ?
>
> Mmh, I am a bit puzzled by this. Why would this be
This prepares framedone interrupt handling for
manual display update support.
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/omapdrm/omap_crtc.c | 48 +
drivers/gpu/drm/omapdrm/omap_drv.h | 2 ++
In preparation for manually updated display support, such as DSI
command mode panels, this adds a simple helper to see if a connector
is manually updated.
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/omapdrm/omap_connector.c | 8
This adds the required infrastructure for manually
updated displays, such as DSI command mode panels.
While those panels often support partial updates
we currently always do a full refresh. Display
will be refreshed when something calls the dirty
callback, such as libdrm's drmModeDirtyFB().
This
Hi,
The generic implementation of huge_pte_offset() has inconsistent
behaviour when looking up hugepage PUDs vs PMDs entries that are not
present (returning NULL vs pte_t*).
Similarly, it returns NULL when encountering swap entries although all
the callers have special checks to properly deal
The wrappers have been removed in commit 5a35876e2830
(drm: omapdrm: Remove manual update display support)
and will not be reintroduced, since the normal sys
functions properly call the dirty callback.
Signed-off-by: Sebastian Reichel
---
On Sun, Jul 23, 2017 at 7:06 PM, Alex Williamson
wrote:
> On Fri, 21 Jul 2017 13:20:18 -0700
> Feng Kan wrote:
>
>> On Thu, Jul 20, 2017 at 3:22 PM, Alex Williamson
>> wrote:
>> > On Wed, 19 Jul 2017 17:46:51 -0700
>> > Feng
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