This patchset adds support for some perf events features,
targeted at ARM64, implemented in a generic fashion.
The two main features are as follows:
- support for arch/vendor/platform pmu events directory structure
- to support this, topic subdirectory support needs to be dropped
- support for
This patch fixes the Cavium ThunderX2 JSON to use event definitions
from the ARMv8 recommended events.
The brief description is kept for readability, but is not strictly
required.
Cc: Ganapatrao Kulkarni
Signed-off-by: John Garry
---
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 60
Hi,
On Fri, Feb 23, 2018 at 08:25:46PM +0800, Icenowy Zheng wrote:
> As the new H6 SoC has holes in the IRQ registers, refactor the IRQ
> related register function for getting the full pinctrl desc structure.
>
> Signed-off-by: Icenowy Zheng
> ---
> New patch in v3.
>
> drivers/pinctrl/sunxi/p
Since jevents now supports vendor subdirectory, relocate
the ThunderX2 JSON to Cavium subdirectory.
Cc: Ganapatrao Kulkarni
Signed-off-by: John Garry
---
.../arch/arm64/cavium/thunderx2-imp-def.json | 62 --
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 62 +
For some architectures (like arm), there are architecture-
defined events. Sometimes these events may be "recommended"
according to the architecture standard, in that the
implementer is free ignore the "recommendation" and create
its custom event.
This patch adds support for parsing standard event
On Mon, 19 Feb 2018 23:46:53 +0530
Aishwarya Pant wrote:
> Documentation has been compiled from git commit logs and descriptions in
> Documentation/aoe/aoe.txt. This should be useful for scripting and
> tracking changes in the ABI.
>
> Signed-off-by: Aishwarya Pant
Applied to the docs tree, th
On Fri, Feb 23, 2018 at 08:25:47PM +0800, Icenowy Zheng wrote:
> The Allwinner H6 SoC have its pin controllers with the first IRQ-capable
> GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. This
> situation cannot be processed with the current pinctrl IRQ code, as it
> only expects a offse
On Sat, 10 Feb 2018 13:11:04 +0530
Aishwarya Pant wrote:
> Add documentation for core and hardware specific infiniband interfaces.
> The descriptions have been collected from git commit logs, reading
> through code and data sheets. Some drivers have incomplete doc and are
> annotated with the com
On Fri, Feb 23, 2018 at 3:55 PM, Maciej S. Szmigiero
wrote:
> This reverts commit 92a8046c9d952a2a7d21dfcd3afadc72a0bc0f72.
>
> Now that the patch series changing ISA_BUS_API dependency to selection
> was merged this reversion will do the same for gpio-winbond driver to
> make it consistent with o
On 02/23/2018 05:12 PM, Boris Ostrovsky wrote:
On 02/21/2018 03:03 AM, Oleksandr Andrushchenko wrote:
+
+struct drm_driver xen_drm_driver = {
+ .driver_features = DRIVER_GEM | DRIVER_MODESET |
+DRIVER_PRIME | DRIVER_ATOMIC,
+ .lastclose
On Fri, Feb 23, 2018 at 12:41:05PM +, James Ettle wrote:
> I'm OK with that. (This is the first time I've ventured into kernel space so
> I thought it better to at least sketch a solution and let the experts do it
> correctly ;) Glad it's passed the review!)
OK, thanks!--b.
On Fri, 2018-02-23 at 16:19 +0100, Arnd Bergmann wrote:
> On Fri, Feb 23, 2018 at 3:55 PM, Maciej S. Szmigiero
> wrote:
> I would really like to avoid mixing
> 'select' and 'depends on' here, as that will likely cause other
> circular
> dependencies in the future.
Agree. And it doesn't make se
On Fri, Feb 23, 2018 at 08:35:54PM +0800, Icenowy Zheng wrote:
> Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its
> memory map fully reworked and some high-speed peripherals (PCIe, USB
> 3.0) introduced.
>
> This commit adds the basical DTSI file of it, including the clock
On Sat, 17 Feb 2018 11:43:04 +0530
Aishwarya Pant wrote:
> Documentation has been compiled from git logs and by reading through
> code.
>
> Signed-off-by: Aishwarya Pant
> ---
> For drivers/block/loop.c, I don't see any maintainers or mailing lists except
> for LKML. I am guessing linux-block m
I can see this warnings as well and yes, kvm_arch_irq_routing_update seems to
be available
for CONFIG_HAVE_KVM_EVENTFD=y and =n.
Seems that irqchip.c is compile independly from CONFIG_HAVE_KVM_EVENTFD,
so
Acked-by: Christian Borntraeger
On 02/22/2018 01:05 PM, Sebastian Ott wrote:
> Move the k
On Thu, Feb 22, 2018 at 10:42:52AM -0800, Linus Torvalds wrote:
> So what we could perhaps do is:
>
> - make console_verbose() actually reset things to at least LOGLEVEL_DEBUG
>
> - make sure the *default* loglevel be LOGLEVEL_WARNING
>
> - now you can use pr_debug() in the oops code to prin
于 2018年2月23日 GMT+08:00 下午11:20:38, Maxime Ripard 写到:
>On Fri, Feb 23, 2018 at 08:35:54PM +0800, Icenowy Zheng wrote:
>> Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with
>its
>> memory map fully reworked and some high-speed peripherals (PCIe, USB
>> 3.0) introduced.
>>
>> Thi
On Tue, 6 Feb 2018 13:08:41 +0530
Aishwarya Pant wrote:
> Patchset contains documentation of the sysfs interfaces for the
> following five backlight drivers-
> 1) lm3639
> 2) adp5520
> 3) adp8860
>
> It was compiled from data sheets, reading code and git history logs. In v2 of
> the patches, doc
As a part of working on MII time stamping infrastructure, I was trying
to figure out how netdev->phydev gets assigned, and I stumbled across
this. Ever since the new phylink code came in, the field is assigned
twice.
The function, phylink_connect_phy(), calls
phy_attach_direct()
On Fri, 19 Jan 2018 18:01:47 +0530
Aishwarya Pant wrote:
> Right now, the description of the rapidio sysfs interfaces is in
> Documentation/rapidio/sysfs.txt. Since these are a part of the ABI, they
> should be in Documentation/ABI along with the rest.
>
> Signed-off-by: Aishwarya Pant
Applied
On 02/21/2018 03:03 AM, Oleksandr Andrushchenko wrote:
> +static struct xen_gem_object *gem_create(struct drm_device *dev, size_t size)
> +{
> + struct xen_drm_front_drm_info *drm_info = dev->dev_private;
> + struct xen_gem_object *xen_obj;
> + int ret;
> +
> + size = round_up(size,
On Fri, Feb 23, 2018 at 04:19:01PM +0100, Arnd Bergmann wrote:
>On Fri, Feb 23, 2018 at 3:55 PM, Maciej S. Szmigiero
> wrote:
>> This reverts commit 92a8046c9d952a2a7d21dfcd3afadc72a0bc0f72.
>>
>> Now that the patch series changing ISA_BUS_API dependency to selection
>> was merged this reversion wi
Hi Daniel,
On 21 February 2018 at 16:29, Daniel Lezcano wrote:
> +
> +/**
> + * struct cpuidle_cooling_device - data for the idle cooling device
> + * @cdev: a pointer to a struct thermal_cooling_device
> + * @cpumask: a cpumask containing the CPU managed by the cooling device
> + * @timer: a hrt
Dear Thomas,
On the ASRock E350M1 (AMD A50M), since Linux 4.15 I get the message below.
do_IRQ: 1.55 No irq handler for vector
Kind regards,
Paul
smime.p7s
Description: S/MIME Cryptographic Signature
Em Fri, Feb 23, 2018 at 09:25:00AM +0100, Peter Zijlstra escreveu:
> On Fri, Feb 23, 2018 at 10:35:58PM +0800, Jin Yao wrote:
> > Unlike the perf report interactive annotate mode, the perf annotate
> > doesn't display the LBR data.
> > perf record -b ...
> > perf annotate function
> > It should s
On 02/23/2018 07:58 AM, Yafang Shao wrote:
> sk is already allocated in inet_create/inet6_create, hence when
> BPF_CGROUP_RUN_PROG_INET_SOCK is executed sk will never be NULL.
>
> The logic is as bellow,
> sk = sk_alloc();
> if (!sk)
> goto out;
> BPF_CGROUP_RUN_PRO
I am Ms.Ella Golan, I am the Executive Vice President Banking Division with
FIRST INTERNATIONAL BANK OF ISRAEL LTD (FIBI). I am getting in touch with you
regarding an extremely important and urgent matter. If you would oblige me the
opportunity, I shall provide you with details upon your respons
On 02/23/2018 05:26 PM, Boris Ostrovsky wrote:
On 02/21/2018 03:03 AM, Oleksandr Andrushchenko wrote:
+static struct xen_gem_object *gem_create(struct drm_device *dev, size_t size)
+{
+ struct xen_drm_front_drm_info *drm_info = dev->dev_private;
+ struct xen_gem_object *xen_obj;
+
On Fri, Feb 23, 2018 at 03:22:15PM +0100, Robin Jarry wrote:
> When libelf headers and libs are not found and CONFIG_UNWINDER_ORC is
> selected, there is a make error introduced by
> commit 3dd40cb320fe ("objtool: Upgrade libelf-devel warning to error for
> CONFIG_ORC_UNWINDER").
>
> Host headers
32-bit architectures generally cannot use writeq(), so we now get a build
failure for the lpfc driver:
drivers/scsi/lpfc/lpfc_sli.c: In function 'lpfc_sli4_wq_put':
drivers/scsi/lpfc/lpfc_sli.c:145:4: error: implicit declaration of function
'writeq'; did you mean 'writeb'? [-Werror=implicit-funct
> Given this is the current state of the code (it's part of btrfs) I believe
> the following could/should be done:
Is there benchmarking data to show that a custom lock is justified
(especiaally given it's going to mean btrfs and rtlinux don't play
together nicely since it won't be able to see th
On Fri, Feb 23, 2018 at 04:06:39PM +0530, Vivek Gautam wrote:
> On Fri, Feb 23, 2018 at 5:22 AM, Jordan Crouse wrote:
> > On Wed, Feb 07, 2018 at 04:01:19PM +0530, Vivek Gautam wrote:
> >> From: Sricharan R
> >>
> >> The smmu device probe/remove and add/remove master device callbacks
> >> gets ca
> Il giorno 23 feb 2018, alle ore 16:07, Ming Lei ha
> scritto:
>
> Hi Paolo,
>
> On Wed, Feb 07, 2018 at 10:19:20PM +0100, Paolo Valente wrote:
>> Commit 'a6a252e64914 ("blk-mq-sched: decide how to handle flush rq via
>> RQF_FLUSH_SEQ")' makes all non-flush re-prepared requests for a device
On Mon, Feb 19, 2018 at 11:13:19AM +0100, Arnd Bergmann wrote:
> As discussed with Greg, I've had my randconfig builder build 4.9-stable
> kernels
> over the weekend, here is what it found missing. There are 45 patches that can
> be backported cleanly from mainline, plus another 9 that are either
In preparation for suspend-resume support for AM33XX, add
the assembly file with the code which is copied to internal
memory (OCMC RAM) during bootup and runs from there.
As part of the low power entry (DeepSleep0 mode in AM33XX TRM),
the code running from OCMC RAM does the following
1. Calls rout
> Regarding the older architectures I mentioned (m32r, frv, mn10300),
> the situation is a bit different as they don't have the problems with
> build testing but they do have problems with using less of the
> standard interfaces (syscall, timer, gpio, rtc, ...), so they do add
> more to the mainten
Most of the PM code needed for am335x and am437x can be moved into a
module under drivers but some core code must remain in mach-omap2 at the
moment. This includes some internal clockdomain APIs and low-level ARM
APIs which are also not exported for use by modules.
Implement a few functions that h
AM335x and AM437x support various low power modes as documented
in section 8.1.4.3 of the AM335x Technical Reference Manual and
section 6.4.3 of the AM437x Technical Reference Manual.
DeepSleep0 mode offers the lowest power mode with limited
wakeup sources without a system reboot and is mapped as
Although similar to AM33XX, introduce a new low-level asm file for
suspend containing new context save and restore paths for EMIF and l2
cache disabling and enabling.
Signed-off-by: Dave Gerlach
---
arch/arm/mach-omap2/sleep43xx.S | 385
1 file changed, 3
Hi,
This is a minor update to previous series sent here [1] to switch to
SPDX license headers. Because update is so minor I have included original
cover letter below unmodified with the exception of updated links.
This series contains the remaining code to enable suspend to mem and standby
on am3
Hi all,
While fuzzing arm64/v4.16-rc2 with syzkaller, I simultaneously hit a
number of splats in the block layer:
* inconsistent {HARDIRQ-ON-W} -> {IN-HARDIRQ-R} usage in
jbd2_trans_will_send_data_barrier
* BUG: sleeping function called from invalid context at mm/mempool.c:320
* WARNING: CPU:
hi Radoslaw
The gpio-keys tests it's now functional on H7, great.
However the gpio-key test only the bank1 (like stm32f429).
Like the H7 introduce the multi-bank management,
we must perform complementary test.
comment below about ack in handler
On 02/23/2018 09:31 AM, Radoslaw Pietrzyk wrote:
The kasan_slab_free hook's return value denotes whether the reuse of a
slab object must be delayed (e.g. when the object is put into memory
qurantine).
The current way SLUB handles this hook is by ignoring its return value
and hardcoding checks similar (but not exactly the same) to the ones
perfor
Hi,
On 19/01/2018 17:10, Tvrtko Ursulin wrote:
Hi,
On 19/01/2018 16:45, Peter Zijlstra wrote:
On Thu, Jan 18, 2018 at 06:40:07PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
For situations where sysadmins might want to allow different level of
of access control for different PMUs, we
On Fri, Feb 23, 2018 at 08:17:51AM -0500, Rob Clark wrote:
> From: Brian Starkey
>
> Writeback connectors represent writeback engines which can write the
> CRTC output to a memory framebuffer. Add a writeback connector type and
> related support functions.
>
> Drivers should initialize a writeba
On Fri, Feb 23, 2018 at 5:36 PM, Arnd Bergmann wrote:
> 32-bit architectures generally cannot use writeq(), so we now get a build
> failure for the lpfc driver:
>
> drivers/scsi/lpfc/lpfc_sli.c: In function 'lpfc_sli4_wq_put':
> drivers/scsi/lpfc/lpfc_sli.c:145:4: error: implicit declaration of fu
On 23.02.2018 17:38, Alan Cox wrote:
>> Given this is the current state of the code (it's part of btrfs) I believe
>> the following could/should be done:
>
> Is there benchmarking data to show that a custom lock is justified
> (especiaally given it's going to mean btrfs and rtlinux don't play
>
From: Arnd Bergmann
Date: Thu, 22 Feb 2018 17:56:12 +0100
> I expect to do the same for gcc-8. Most of the fixes are trivial
> anyway, and some of them fix actual bugs that would otherwise get
> missed.
It does make the code easier to understand and you can more directly
see what it's trying to
From: Eric Dumazet
When a large BPF percpu map is destroyed, I have seen
pcpu_balance_workfn() holding cpu for hundreds of milliseconds.
On KASAN config and 112 hyperthreads, average time to destroy a chunk
is ~4 ms.
[ 2489.841376] destroy chunk 1 in 4148689 ns
...
[ 2490.093428] destroy chunk
On Fri, Feb 23, 2018 at 5:59 PM, Andy Shevchenko
wrote:
> On Fri, Feb 23, 2018 at 5:36 PM, Arnd Bergmann wrote:
> IIRC memcpy_toio() doesn't increment the destination address.
>
> lo_hi or hi_lo helpers sound better.
Ah, sorry, I messed up with writesl() / etc.
memcpy_toio() has another side-e
On Fri, Feb 23, 2018 at 08:17:52AM -0500, Rob Clark wrote:
> From: Brian Starkey
>
> Add the WRITEBACK_OUT_FENCE_PTR property to writeback connectors, to
> enable userspace to get a fence which will signal once the writeback is
> complete. It is not allowed to request an out-fence without a
> fra
On Tue, Feb 13, 2018 at 05:50:01PM -0800, Dongwon Kim wrote:
> Reference document for hyper_DMABUF driver
>
> Documentation/hyper-dmabuf-sharing.txt
This should likely be patch 1 in order for reviewers to have the
appropriate context.
>
> Signed-off-by: Dongwon Kim
> ---
> Documentation/hyper
On Fri, Feb 23, 2018 at 4:19 PM, Shawn Lin wrote:
> On 2018/2/23 21:27, Andy Shevchenko wrote:
>> On Fri, Feb 23, 2018 at 8:41 AM, Jaehoon Chung
>> wrote:
>>>
>>> 'clock-freq-min-max' property had already deprecated.
>>> Remove the 'clock-freq-min-max' property that is kept to maintain
>>> the co
On Fri, Feb 23, 2018 at 9:37 PM, Mylène Josserand
wrote:
> On Cortex-A7, the CNTVOFF register from arch timer is uninitialized.
> It should be done by the bootloader but it is currently not the case,
> even for boot CPU because this SoC is booting in secure mode.
> It leads to an random offset val
On 02/23/2018 04:46 PM, Ludovic BARRE wrote:
hi Radoslaw
The gpio-keys tests it's now functional on H7, great.
However the gpio-key test only the bank1 (like stm32f429).
Like the H7 introduce the multi-bank management,
we must perform complementary test.
comment below about ack in handler
On
Hi Paolo,
On Fri, Feb 23, 2018 at 04:41:36PM +0100, Paolo Valente wrote:
>
>
> > Il giorno 23 feb 2018, alle ore 16:07, Ming Lei ha
> > scritto:
> >
> > Hi Paolo,
> >
> > On Wed, Feb 07, 2018 at 10:19:20PM +0100, Paolo Valente wrote:
> >> Commit 'a6a252e64914 ("blk-mq-sched: decide how to ha
On Tue, Feb 20, 2018 at 12:54:47PM +0100, Arnd Bergmann wrote:
> Like the earlier series of randconfig build fixes for 4.9, this is the
> equivalent for 4.4. Again, most of it is for harmless warnings, but there
> are also fixes for excessive stack consumption that can be possibly
> dangerous, and
On Fri, Feb 23, 2018 at 10:59:35AM -0500, Sean Paul wrote:
> On Fri, Feb 23, 2018 at 08:17:51AM -0500, Rob Clark wrote:
> > From: Brian Starkey
> >
> > Writeback connectors represent writeback engines which can write the
> > CRTC output to a memory framebuffer. Add a writeback connector type and
2018-02-23, Josh Poimboeuf:
> Hi Robin,
>
> Did you test this? I see some issues:
>
> a) I don't see where the host_cflags variable comes from (and btw, it's
>misspelled...)
Hi Josh,
Shame on me... Last minute fix. I had tested this first by forcing
HOSTCC="gcc " but I found it rather dir
Hi all,
ARM System Control and Management Interface(SCMI) is more flexible and
easily extensible than any of the existing interfaces. Many vendors were
involved in the making of this formal specification and is now published[1].
There is a strong trend in the industry to provide micro-controllers
The power protocol is intended for management of power states of various
power domains. The power domain management protocol provides commands to
describe the protocol version, discover the implementation specific
attributes, set and get the power state of a domain.
This patch adds support for the
On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control including CPU DVFS. SCMI Message Protocol is used to
communicate with the SCP.
This patch adds a cpufreq driver for such systems using SCMI interface
to dr
The cpufreq core provides option for drivers to implement fast_switch
callback which is invoked for frequency switching from interrupt context.
This patch adds support for fast_switch callback in SCMI cpufreq driver
by making use of polling based SCMI transfer. It also sets the flag
fast_switch_po
This patch hooks up the support for device power domain provided by
SCMI using the Linux generic power domain infrastructure.
Cc: Kevin Hilman
Reviewed-by: Ulf Hansson
Signed-off-by: Sudeep Holla
---
drivers/firmware/Kconfig | 13 +++
drivers/firmware/arm_scmi/Makefile
Create a driver to add support for SoC sensors exported by the System
Control Processor (SCP) via the System Control and Management Interface
(SCMI). The supported sensor types is one of voltage, temperature,
current, and power.
The sensor labels and values provided by the SCP are exported via the
It's useful to know the maximum types of sensor supported by hwmon
framework. It can be used to allocate some data structures when sorting
the monitors based on their type.
This will be used by scmi hwmon support.
Cc: linux-hw...@vger.kernel.org
Acked-by: Guenter Roeck
Signed-off-by: Sudeep Holl
On Fri, Feb 23, 2018 at 10:59 AM, Sean Paul wrote:
>
> Have we considered hiding writeback behind a client cap instead?
It is kinda *almost* unneeded, since the connector reports itself as
disconnected.
I'm not sure what the reason was to drop the cap, but I think it would
be better to have a ca
On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control. System Control and Management Interface(SCMI) Message Protocol
is defined for the communication between the Application Cores(AP)
and the SCP.
This patch
Now that we have basic support for all the protocols in the
specification, let's probe them individually and initialise them.
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Signed-off-by: Sudeep Holla
---
drivers/firmware/arm_scmi/driver.c | 51 +-
1 file changed,
In order to maintain the channel information per protocol, we need
some sort of list or hashtable to hold all this information. IDR
provides sparse array mapping of small integer ID numbers onto arbitrary
pointers. In this case the arbitrary pointers can be pointers to the
channel information.
Thi
I am Ms.Ella Golan, I am the Executive Vice President Banking Division with
FIRST INTERNATIONAL BANK OF ISRAEL LTD (FIBI). I am getting in touch with you
regarding an extremely important and urgent matter. If you would oblige me the
opportunity, I shall provide you with details upon your respons
It would be useful to have options to perform some SCMI transfers
atomically by polling for the completion flag instead of interrupt
driven. The SCMI specification has option to disable the interrupt and
poll for the completion flag in the shared memory.
This patch adds support for polling based S
In order to support per-protocol channels if available, we need to
factor out all the mailbox channel information(Tx/Rx payload and
channel handle) out of the main SCMI instance information structure.
This patch refactors the existing channel information into a separate
chan_info structure.
Cc: A
On Fri, Feb 23, 2018 at 5:11 PM, Enric Balletbo i Serra
wrote:
> From: Wei-Ning Huang
>
> Add ACPI module device table for matching cros-ec devices to load the
> cros_ec_i2c driver automatically.
> +static const struct acpi_device_id cros_ec_i2c_acpi_id[] = {
> + { "GOOG0008", 0 },
> +
In order to implement fast CPU DVFS switching, we need to perform all
DVFS operations atomically. Since SCMI transfer already provide option
to choose between pooling vs interrupt driven(default), we can opt for
polling based transfers for set,get performance domain operations.
This patch adds opt
The SCMI specification encompasses various protocols. However, not every
protocol has to be present on a given platform/implementation as not
every protocol is relevant for it.
Furthermore, the platform chooses which protocols it exposes to a given
agent. The only protocol that must be implemented
The clock protocol is intended for management of clocks. It is used to
enable or disable clocks, and to set and get the clock rates. This
protocol provides commands to describe the protocol version, discover
various implementation specific attributes, describe a clock, enable
and disable a clock an
The sensor protocol provides functions to manage platform sensors, and
provides the commands to describe the protocol version and the various
attribute flags. It also provides commands to discover various sensors
implemented and managed by the platform, read any sensor synchronously
or asynchronous
On Fri, Feb 23, 2018 at 5:11 PM, Enric Balletbo i Serra
wrote:
> From: Joseph Lo
>
> The cros_ec_i2c driver is still active after it had suspended or before it
> resumes. Besides that, it also tried to transfer data even after the I2C
> host had been suspended. This will lead the system to crash.
Many users of the mailbox controllers depend on the shared memory
between the two end points to exchange the main data while using simple
doorbell mechanism to alert the end points of the presence of a message.
This patch defines device tree bindings to represent such shared memory
in a generic wa
The performance protocol is intended for the performance management of
group(s) of device(s) that run in the same performance domain. It
includes even the CPUs. A performance domain is defined by a set of
devices that always have to run at the same performance level.
For example, a set of CPUs that
On Fri, Feb 23, 2018 at 5:05 PM, Enric Balletbo i Serra
wrote:
> Hi,
>
> This is a second version of a patchset that collects some patches
> already send but that needed some rework due the patchset to split the
> cros_ec_devs modules in 2 parts [1]. This patchset contains some of
> imrpovements a
The base protocol describes the properties of the implementation and
provide generic error management. The base protocol provides commands
to describe protocol version, discover implementation specific
attributes and vendor/sub-vendor identification, list of protocols
implemented and the various ag
This patch adds devicetree binding for System Control and Management
Interface (SCMI) Message Protocol used between the Application Cores(AP)
and the System Control Processor(SCP). The MHU peripheral provides a
mechanism for inter-processor communication between SCP's M3 processor
and AP.
SCP offe
The SCMI is intended to allow OSPM to manage various functions that are
provided by the hardware platform it is running on, including power and
performance functions. SCMI provides two levels of abstraction, protocols
and transports. Protocols define individual groups of system control and
manageme
On Fri, Feb 23, 2018 at 08:17:54AM -0500, Rob Clark wrote:
> In a way, based on the original writeback patch from Jilai Wang, but a
> lot has shifted around since then.
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/Makefile | 1 +
> drivers/gpu/drm/msm/disp/mdp5/mdp5_cr
On Fri, Feb 23, 2018 at 08:17:53AM -0500, Rob Clark wrote:
> Note there seems to be a slight disagreement between public 8x16 HRD
> (which claims WB2 has offset of 0x65000, relative to start of MDP), and
> reality (which claims WB2 has offset of 0x64800). I sided with reality.
>
> There should al
From: Colin Ian King
The function __battery_hook_unregister is local to the source and does
not need to be in global scope, so make it static.
Cleans up sparse warning:
drivers/acpi/battery.c:654:6: warning: symbol '__battery_hook_unregister'
was not declared. Should it be static?
Signed-off-by
On Fri, Feb 23, 2018 at 05:22:55PM +0100, Robin Jarry wrote:
> 2018-02-23, Josh Poimboeuf:
> > Hi Robin,
> >
> > Did you test this? I see some issues:
> >
> > a) I don't see where the host_cflags variable comes from (and btw, it's
> >misspelled...)
>
> Hi Josh,
>
> Shame on me... Last minu
On Thu 25 Jan 17:13 PST 2018, Stephen Boyd wrote:
+ Rob
> Some qcom platforms make some GPIOs or pins unavailable for use
> by non-secure operating systems, and thus reading or writing the
> registers for those pins will cause access control issues.
> Introduce a DT property to describe the set o
On Tue, Feb 20, 2018 at 07:26:05PM +0100, Peter Zijlstra wrote:
> On Tue, Feb 20, 2018 at 04:33:52PM +, Morten Rasmussen wrote:
> > On Mon, Feb 19, 2018 at 04:10:11PM +0100, Peter Zijlstra wrote:
> > > On Thu, Feb 15, 2018 at 04:20:51PM +, Morten Rasmussen wrote:
> > > > +/*
> > > > + * gro
On Fri, Feb 23, 2018 at 04:21:05PM +, Liviu Dudau wrote:
> On Fri, Feb 23, 2018 at 10:59:35AM -0500, Sean Paul wrote:
> > On Fri, Feb 23, 2018 at 08:17:51AM -0500, Rob Clark wrote:
> > > From: Brian Starkey
> > >
> > > Writeback connectors represent writeback engines which can write the
> > >
From: Arnd Bergmann
> Sent: 23 February 2018 15:37
>
> 32-bit architectures generally cannot use writeq(), so we now get a build
> failure for the lpfc driver:
>
> drivers/scsi/lpfc/lpfc_sli.c: In function 'lpfc_sli4_wq_put':
> drivers/scsi/lpfc/lpfc_sli.c:145:4: error: implicit declaration of fu
As of today we use hardcoded MCIP debug mask, so if we launch
kernel via debugger and kick fever cores than HW has all cpus
hang at the momemt of setup MCIP debug mask.
So update MCIP debug mask when the new cpu came online, instead of
use hardcoded MCIP debug mask.
Signed-off-by: Eugeniy Paltsev
As we have option in u-boot to set CPU mask for running linux,
we want to pass information to kernel about CPU cores should
be brought up. So we patch kernel dtb in u-boot to set
possible-cpus property.
This also allows us to have correctly setuped MCIP debug mask.
Signed-off-by: Eugeniy Paltsev
Currently GFRC is running regardless state of ARC cores in the SMP cluster.
That means even if ARC cores are halted when doing JTAG debugging GFRC
[our source of wall-time] continues to run giving us unexpected warnings
once we allow ARC cores to run due to some tasks being stuck for too
long.
Sta
On Fri, Feb 23, 2018 at 11:25:11AM -0500, Rob Clark wrote:
> On Fri, Feb 23, 2018 at 10:59 AM, Sean Paul wrote:
> >
> > Have we considered hiding writeback behind a client cap instead?
>
> It is kinda *almost* unneeded, since the connector reports itself as
> disconnected.
>
> I'm not sure what
On Fri, Feb 23, 2018 at 5:41 PM, David Laight wrote:
> From: Arnd Bergmann
>> Sent: 23 February 2018 15:37
>>
>> 32-bit architectures generally cannot use writeq(), so we now get a build
>> failure for the lpfc driver:
>>
>> drivers/scsi/lpfc/lpfc_sli.c: In function 'lpfc_sli4_wq_put':
>> drivers/
Property to set initial value of pin output buffer.
This can be useful for configure hardware in overlay files, and in early boot
for checking it states in QA sanity tests.
This modification maintain the legacy property style, but the idea is to
continue working in this driver to implement suppo
On Fri, Feb 23, 2018 at 04:38:06PM +, Morten Rasmussen wrote:
> > Or am I now terminally confused again?
>
> No, I think you are right, or I'm equally confused.
:-)
Would it make sense to also track max_capacity, but then based on the
value before RT scaling ?
That should readily be able to
401 - 500 of 1387 matches
Mail list logo
