From: Joerg Roedel
This splits out the mapping sanity check and the actual
mapping of the LDT to user-space from the map_ldt_struct()
function in a way so that it is re-usable for PAE paging.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/ldt.c | 82 ---
From: Joerg Roedel
Reserve 2MB/4MB of address-space for mapping the LDT to
user-space on 32 bit PTI kernels.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/pgtable_32_types.h | 7 +--
arch/x86/mm/dump_pagetables.c | 9 +
2 files changed, 14 insertions(+), 2 deletion
From: Joerg Roedel
We need separate kernel PMDs in the user page-table when PTI
is enabled to map the per-process LDT for user-space.
Signed-off-by: Joerg Roedel
---
arch/x86/mm/pgtable.c | 100 --
1 file changed, 81 insertions(+), 19 deletions(-
From: Joerg Roedel
Make them available on 32 bit and clone_pgd_range() happy.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/pgtable.h| 49 +++
arch/x86/include/asm/pgtable_64.h | 49 ---
2 files changed, 49 inse
On Fri, Mar 16, 2018 at 10:02:22PM +1100, Balbir Singh wrote:
> On Fri, Mar 16, 2018 at 9:33 PM, Ram Pai wrote:
> > Applications need the ability to associate an address-range with some
> > key and latter revert to its initial default key. Pkey-0 comes close to
> > providing this function but fall
From: Joerg Roedel
Define INIT_PGD to point to the correct initial page-table
for 32 and 64 bit and use it where needed. This fixes the
build on 32 bit with CONFIG_PAGE_TABLE_ISOLATION enabled.
Signed-off-by: Joerg Roedel
---
arch/x86/mm/dump_pagetables.c | 12 ++--
1 file changed, 6 i
From: Joerg Roedel
Move it out of the X86_64 specific processor defines so
that its visible for 32bit too.
Reviewed-by: Andy Lutomirski
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/processor-flags.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/i
From: Joerg Roedel
Also populate the user-spage pgd's in the user page-table.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/pgtable-2level.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/x86/include/asm/pgtable-2level.h
b/arch/x86/include/asm/pgtable-2level.h
index
From: Joerg Roedel
The addr counter will overflow if we clone the last PMD of
the address space, resulting in an endless loop.
Check for that and bail out of the loop when it happens.
Signed-off-by: Joerg Roedel
---
arch/x86/mm/pti.c | 4
1 file changed, 4 insertions(+)
diff --git a/arc
From: Joerg Roedel
Warn the user in case the performance can be significantly
improved by switching to a 64-bit kernel.
Suggested-by: Andy Lutomirski
Signed-off-by: Joerg Roedel
---
arch/x86/mm/pti.c | 16
1 file changed, 16 insertions(+)
diff --git a/arch/x86/mm/pti.c b/arc
From: Joerg Roedel
Add a config option that enabled code to check that we enter
and leave the kernel with the correct cr3. This is needed
because we have no NX protection of user-addresses in the
kernel-cr3 on x86-32 and wouldn't notice that type of bug
otherwise.
Signed-off-by: Joerg Roedel
--
From: Joerg Roedel
Generic page-table code populates all non-leaf entries with
_KERNPG_TABLE bits set. This is fine for all paging modes
except PAE.
In PAE mode only a subset of the bits is allowed to be set.
Make sure we only set allowed bits by masking out the
reserved bits.
Signed-off-by: Jo
From: Joerg Roedel
There it is also usable from 32 bit code.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/pgtable.h| 23 +++
arch/x86/include/asm/pgtable_64.h | 21 -
2 files changed, 23 insertions(+), 21 deletions(-)
diff --git a/arch/x86/i
From: Joerg Roedel
The NMI handler is special, as it needs to leave with the
same cr3 as it was entered with. We need to do this because
we could enter the NMI handler from kernel code with
user-cr3 already loaded.
Signed-off-by: Joerg Roedel
---
arch/x86/entry/entry_32.S | 41
From: Joerg Roedel
These two functions are required for PTI on 32 bit:
* pgdp_maps_userspace()
* pgd_large()
Also re-implement pgdp_maps_userspace() so that it will work
on 64 and 32 bit kernels.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/pgtable-2level_types.h | 3
From: Joerg Roedel
When we populate a PGD entry, make sure we populate it in
the user page-table too.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/pgtable-3level.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/include/asm/pgtable-3level.h
b/arch/x86/include/asm/p
From: Joerg Roedel
Use a separate return path when we know we are returning to
the kernel. This allows us to put the PTI cr3-switch and the
switch to the entry-stack into the return-to-user path
without further checking.
Signed-off-by: Joerg Roedel
---
arch/x86/entry/entry_32.S | 11 --
From: Joerg Roedel
Allocate a kernel and a user page-table root when PTI is
enabled. Also allocate a full page per root for PAE because
otherwise the bit to flip in cr3 to switch between them
would be non-constant, which creates a lot of hassle.
Keep that for a later optimization.
Signed-off-by:
From: Joerg Roedel
With PTI we need to map the per-process LDT into the kernel
address-space for each process, so we need separate kernel
PMDs per PGD.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/pgtable-3level_types.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff -
From: Joerg Roedel
With the way page-table folding is implemented on 32 bit, we
are not only setting PGDs with this functions, but also PUDs
and even PMDs. Give the function a more generic name to
reflect that.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/pgtable_64.h | 12 ++--
From: Joerg Roedel
Add unconditional cr3 switches between user and kernel cr3
to all non-NMI entry and exit points.
Signed-off-by: Joerg Roedel
---
arch/x86/entry/entry_32.S | 83 ---
1 file changed, 79 insertions(+), 4 deletions(-)
diff --git a/arc
From: Joerg Roedel
The common exception entry code now handles the
entry-from-sysenter stack situation and makes sure to leave
with the same stack as it entered the kernel.
So there is no need anymore for the special handling in the
debug entry code.
Signed-off-by: Joerg Roedel
---
arch/x86/e
> From: Lorenzo Pieralisi
> Sent: Friday, March 16, 2018 11:32
> ...
>
> OK, patch series reworked and queued in my pci/hv branch please have
> a look and let me know if that looks OK for you, I won't ask Bjorn
> to move it into -next till you give me the go-ahead.
>
> Lorenzo
Yes, it looks goo
From: Joerg Roedel
We want x86_tss.sp0 point to the entry stack later to use
it as a trampoline stack for other kernel entry points
besides SYSENTER.
So store the task stack pointer in x86_tss.sp1, which is
otherwise unused by the hardware, as Linux doesn't make use
of Ring 1.
Signed-off-by: Jo
From: Joerg Roedel
NMI will no longer use most of the shared return path,
because NMI needs special handling when the CR3 switches for
PTI are added. This patch prepares for that.
Signed-off-by: Joerg Roedel
---
arch/x86/entry/entry_32.S | 8 ++--
1 file changed, 6 insertions(+), 2 deletio
From: Joerg Roedel
These macros will be used in the NMI handler code and
replace plain SAVE_ALL and RESTORE_REGS there. We will add
the NMI-specific CR3-switch to these macros later.
Signed-off-by: Joerg Roedel
---
arch/x86/entry/entry_32.S | 15 +++
1 file changed, 11 insertions(+
From: Joerg Roedel
Use the entry-stack as a trampoline to enter the kernel. The
entry-stack is already in the cpu_entry_area and will be
mapped to userspace when PTI is enabled.
Signed-off-by: Joerg Roedel
---
arch/x86/entry/entry_32.S| 136 +++
arch
On 16 March 2018 at 20:52, Greg Kroah-Hartman
wrote:
> This is the start of the stable review cycle for the 4.15.11 release.
> There are 128 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Respons
From: Joerg Roedel
Switch back to the trampoline stack before returning to
userspace.
Signed-off-by: Joerg Roedel
---
arch/x86/entry/entry_32.S | 79 +--
1 file changed, 77 insertions(+), 2 deletions(-)
diff --git a/arch/x86/entry/entry_32.S b/arch/
On Fri, Mar 16, 2018 at 02:25:59PM -0500, Eddie James wrote:
> From: Christopher Bostic
>
> Expose the gpiN_fault fields of mfr_status as individual debugfs
> attributes. This provides a way for users to be easily notified of gpi
> faults. Also provide the whole mfr_status register in debugfs.
>
From: Joerg Roedel
Now that we store the task-stack in tss.sp1 we can also use
it as cpu_current_top_of_stack. This unifies the handling
with x86-64.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/processor.h | 4
arch/x86/include/asm/thread_info.h | 2 --
arch/x86/kernel/cpu/comm
From: Joerg Roedel
It can happen that we enter the kernel from kernel-mode and
on the entry-stack. The most common way this happens is when
we get an exception while loading the user-space segment
registers on the kernel-to-userspace exit path.
The segment loading needs to be done after the entr
Hi,
here is an updated version of my PTI enablement patches for
the x86-32 architecture. I worked in the review comments for
v3 and updated the patches here and there. The patch that
re-organized RESTORE_REGS to load segments first is dropped
now.
A notable addition in this version is the last
pa
From: Joerg Roedel
These offsets will be used in 32 bit assembly code as well,
so make them available for all of x86 code.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/asm-offsets.c| 4
arch/x86/kernel/asm-offsets_64.c | 2 --
2 files changed, 4 insertions(+), 2 deletions(-)
diff
From: Joerg Roedel
The stack address doesn't need to be stored in tss.sp0 if
we switch manually like on sysenter. Rename the offset so
that it still makes sense when we change its location.
We will also use this stack for all kernel-entry points, not
just sysenter. Reflect that in the name as we
On Fri 16 Mar 11:26 PDT 2018, Stephen Boyd wrote:
> Quoting Bjorn Andersson (2018-03-07 11:02:49)
> > On Tue 06 Mar 07:57 PST 2018, Lina Iyer wrote:
> >
> > > On Mon, Mar 05 2018 at 16:15 -0700, Bjorn Andersson wrote:
> > > > On Mon 26 Feb 09:58 PST 2018, Lina Iyer wrote:
> >
> > > > As such I t
Commit-ID: 2613f36ed965d0e5a595a1d931fd3b480e82d6fd
Gitweb: https://git.kernel.org/tip/2613f36ed965d0e5a595a1d931fd3b480e82d6fd
Author: Borislav Petkov
AuthorDate: Wed, 14 Mar 2018 19:36:14 +0100
Committer: Thomas Gleixner
CommitDate: Fri, 16 Mar 2018 20:55:51 +0100
x86/microcode: Atte
Commit-ID: bb8c13d61a629276a162c1d2b1a20a815cbcfbb7
Gitweb: https://git.kernel.org/tip/bb8c13d61a629276a162c1d2b1a20a815cbcfbb7
Author: Borislav Petkov
AuthorDate: Wed, 14 Mar 2018 19:36:15 +0100
Committer: Thomas Gleixner
CommitDate: Fri, 16 Mar 2018 20:55:51 +0100
x86/microcode: Fix
On Fri, Mar 16, 2018 at 8:27 PM, Linus Torvalds
wrote:
> On Fri, Mar 16, 2018 at 10:55 AM, Al Viro wrote:
>>
>> That's not them, that's C standard regarding ICE.
>
> Yes. The C standard talks about "integer constant expression". I know.
> It's come up in this very thread before.
>
> The C standar
On 03/16, Dan Carpenter wrote:
> Generally, it's better to fix the bug in the existing code, and then
> do the cleanup later. That way the fixes can be backported to stable
> kernels more easily.
Hummm... the backport argue make a lot of sense for me. I will generate
a v2 with the bug fixes in th
Proper form for iteration over an array is below:
int a[] = {1, 2, 3, 5};
for (int x: a) {
...
}
Your macro forces an iterator to be pointer which is uh-oh.
On Fri, Mar 16, 2018 at 11:30 AM, David Miller wrote:
>
> I imagine one of the things you'd like to do is declare that syscall
> entries use a different (better) argument passing scheme. For
> example, passing values in registers instead of on the stack.
Actually, it's almost exactly the reverse
On 16 March 2018 at 20:52, Greg Kroah-Hartman
wrote:
> This is the start of the stable review cycle for the 4.14.28 release.
> There are 109 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Respons
On 03/16/2018 02:59 PM, Guenter Roeck wrote:
On Fri, Mar 16, 2018 at 02:25:59PM -0500, Eddie James wrote:
From: Christopher Bostic
Expose the gpiN_fault fields of mfr_status as individual debugfs
attributes. This provides a way for users to be easily notified of gpi
faults. Also provide the
The following patch series cleans up miscellaneous code fragments and
then the driver is moved from staging to mainline IIO subsytem directory.
Note that the last patch to move driver is *not* generated using '-M' flag,
which is used for detecting renames, since it may help reviewers to
suggest mo
Rename the macro definitions with suitable names specifying their
purpose.
* ADIS16201_STARTUP_DELAY_MS: Remove the comment specifying the delay in
microseconds and rename it with addtition of _MS suffix.
* ADIS16201_MSC_CTRL_ACTIVE_DATA_RDY_HIGH: Rename the macro to make it
similar to other
Move the adis16201 driver out of staging directory and merge to the
mainline IIO subsystem.
Signed-off-by: Himanshu Jha
---
v2:
-no change in this patch.
drivers/iio/accel/Kconfig | 12 ++
drivers/iio/accel/Makefile| 1 +
drivers/iio/accel/adis16201.c | 327
Dave Hansen writes:
> On 03/16/2018 12:00 PM, Dave Hansen wrote:
>> On 01/15/2018 04:40 PM, Eric W. Biederman wrote:
>>> The addr_lsb fields is only valid and available when the
>>> signal is SIGBUS and the si_code is BUS_MCEERR_AR or BUS_MCEERR_AO.
>>> Document this with a comment and place the
Group register definitions with its register field bits to improve
readability and easy identification. A small comment is also added to
denote the purpose/functionality of the grouped register definitions.
Signed-off-by: Himanshu Jha
---
v2:
-reordered patch series.
drivers/staging/iio/acce
Prefer reverse christmas tree ordering of declarations to improve
readability.
Signed-off-by: Himanshu Jha
---
v2:
-no change in this patch.
drivers/staging/iio/accel/adis16201.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/iio/accel/adis16201.c
b/
In adis16201_read_raw() adjust an argument to match an open parentheses
using tabs and spaces.
Signed-off-by: Himanshu Jha
---
v2:
-aligned perfectly to match open parentheses.
drivers/staging/iio/accel/adis16201.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/s
Clarify the conversion and formation of resultant data in the
adis16201_read_raw() with sufficient comments and remove the unnecessary
comments.
Signed-off-by: Himanshu Jha
---
v2:
-clarify voltage base conversions.
drivers/staging/iio/accel/adis16201.c | 27 ++-
1 fi
Use sign_extned32() for 32 bit sign extending rather than hard coding.
Signed-off-by: Himanshu Jha
---
v2:
-no change in this patch.
drivers/staging/iio/accel/adis16201.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/iio/accel/adis16201.c
b/drivers
Add a _REG suffix to distinguish between registers and the register bit
fileds.
Signed-off-by: Himanshu Jha
---
v2:
-reordered patch series.
drivers/staging/iio/accel/adis16201.c | 84 +--
1 file changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers
Remove few unnecessary comments since the macro definitions clearly
justify their purpose.
Signed-off-by: Himanshu Jha
---
v2:
-reodered patch series.
drivers/staging/iio/accel/adis16201.c | 36 ---
1 file changed, 36 deletions(-)
diff --git a/drivers/staging
On Fri, Mar 16, 2018 at 12:27:23PM -0700, Linus Torvalds wrote:
> But it sure isn't "variable" either as far as the standard is
> concerned, because the standard doesn't even have that concept (it
> uses "variable" for argument numbers and for variables).
Huh? 6.7.5.2p4:
If the size is not pres
On 03/16/2018 02:54 PM, Andrew Lunn wrote:
>> The phydrv->mdiodrv.flags can be accessible only after call to
>> of_phy_connect()/phy_connect(),
>
> You need to use a function like of_phy_find_device() to get the
> phydev, set the flag, and then call phy_connect_direct().
So, do you propose me
On 16.03.2018 15:50, Christian Brauner wrote:
> This patch adds a receive method to NETLINK_KOBJECT_UEVENT netlink sockets
> to allow sending uevent messages into the network namespace the socket
> belongs to.
>
> Currently non-initial network namespaces are already isolated and don't
> receive ue
On Fri, Mar 16, 2018 at 1:03 PM, Miguel Ojeda
wrote:
>>
>> Kees - is there some online "gcc-4.4 checker" somewhere? This does
>> seem to work with my gcc. I actually tested some of those files you
>> pointed at now.
>
> I use this one:
>
> https://godbolt.org/
Well, my *test* code works on that
On Fri, Mar 16, 2018 at 1:12 PM, Al Viro wrote:
>
> That's C99, straight from N1256.pdf (C99-TC3)...
I checked C90, since the error is
ISO C90 forbids variable length array
and I didn't see anything there.
Admittedly I only found a draft copy.
Linus
On Fri, Mar 16, 2018 at 02:30:21PM -0400, David Miller wrote:
> From: Dominik Brodowski
> Date: Fri, 16 Mar 2018 18:05:52 +0100
>
> > The rationale of this change is described in patch 1 of part 1[*] as
> > follows:
> >
> > The syscall entry points to the kernel defined by SYSCALL_DEFINEx()
On Fri, Mar 16, 2018 at 01:15:27PM -0700, Linus Torvalds wrote:
> On Fri, Mar 16, 2018 at 1:12 PM, Al Viro wrote:
> >
> > That's C99, straight from N1256.pdf (C99-TC3)...
>
> I checked C90, since the error is
>
>ISO C90 forbids variable length array
>
> and I didn't see anything there.
Wel
This reverts commit df42a04b15f1 ("iommu/amd: Avoid locking
get_irq_table() from atomic context").
Its goal is to avoid a warning/bug on RT. While I generally support that
goal this change is colliding with larger rework which accomplishes the
same goal but different.
Cc: Scott Wood
Signed-off-by
get_irq_table() has a special ioapic argument. If set then it will
pre-allocate / reserve the first 32 indexes. The argument is only once
true and it would make get_irq_table() a little simpler if we would
extract the special bits to the caller.
Signed-off-by: Sebastian Andrzej Siewior
---
drive
The irq_remap_table is allocated while the iommu_table_lock is held with
interrupts disabled. While this works it makes RT scream very loudly.
>From looking at the call sites, all callers are in the early device
initialisation (apic_bsp_setup(), pci_enable_device(),
pci_enable_msi()) so make sense
Before commit 0bb6e243d7fb ("iommu/amd: Support IOMMU_DOMAIN_DMA type
allocation") amd_iommu_devtable_lock had a read_lock() user but now
there are none. In fact, after the mentioned commit we had only
write_lock() user of the lock. Since there is no reason to keep it as
writer lock, change its typ
On Thu, Mar 15, 2018 at 08:12:27PM +0530, Manish Narani wrote:
> The AMS includes an ADC as well as on-chip sensors that can be used to
> sample external voltages and monitor on-die operating conditions, such as
> temperature and supply voltage levels. The AMS has two SYSMON blocks.
> PL-SYSMON blo
On Fri, Mar 16, 2018 at 1:14 PM, Linus Torvalds
wrote:
>
> It does not work with gcc-4.1.x, but works with gcc-4.4.x.
>
> I can't seem to see the errors any way, I wonder if
> __builtin_choose_expr() simply didn't exist back then.
No, that goes further back.
It seems to be -Wvla itself that does
The variable of type struct irq_remap_table is always named `table'
except in amd_iommu_update_ga() where it is called `irt'. Make it
consistent and name it also `table'.
Signed-off-by: Sebastian Andrzej Siewior
---
drivers/iommu/amd_iommu.c | 10 +-
1 file changed, 5 insertions(+), 5 de
Setting the IRQ remap table for a specific devid (or its alias devid)
includes three steps. Those three steps are always repeated each time
this is done.
Introduce a new helper function, move those steps there and use that
function instead. The compiler can still decide if it is worth to
inline.
S
alloc_dev_data() adds new items to dev_data_list and search_dev_data()
is searching for items in this list. Both protect the access to the list
with a spinlock.
There is no need to navigate forth and back within the list and there is
also no deleting of a specific item. This qualifies the list to b
The goal here is to make the memory allocation in get_irq_table() not
with disabled interrupts and having as little raw_spin_lock as possible
while having them if the caller is also holding one (like desc->lock
during IRQ-affinity changes).
I reverted one patch one patch in the iommu while rebasing
domain_id_alloc() and domain_id_free() is used for id management. Those
two function share a bitmap (amd_iommu_pd_alloc_bitmap) and set/clear
bits based on id allocation. There is no need to share this with
amd_iommu_devtable_lock, it can use its own lock for this operation.
Signed-off-by: Sebasti
The function get_irq_table() reads/writes irq_lookup_table while holding
the amd_iommu_devtable_lock. It also modifies
amd_iommu_dev_table[].data[2].
set_dte_entry() is using amd_iommu_dev_table[].data[0|1] (under the
domain->lock) so it should be okay. The access to the iommu is
serialized with it
find_dev_data() does not check whether the return value alloc_dev_data()
is NULL. This was okay once because the pointer was returned once as-is.
Since commit df3f7a6e8e85 ("iommu/amd: Use is_attach_deferred
call-back") the pointer may be used within find_dev_data() so a NULL
check is required.
Cc
On Fri, Mar 16, 2018 at 10:44 AM, David Laight wrote:
>
> I looked at the generated code for one of the constant sized VLA that
> the compiler barfed at.
> It seemed to subtract constants from %sp separately for the VLA.
> So it looks like the compiler treats them as VLA even though it
> knows the
Commit-ID: edb39592a5877bd91b2e6ee15194268f35b04892
Gitweb: https://git.kernel.org/tip/edb39592a5877bd91b2e6ee15194268f35b04892
Author: Peter Zijlstra
AuthorDate: Thu, 15 Mar 2018 17:36:56 +0100
Committer: Thomas Gleixner
CommitDate: Fri, 16 Mar 2018 20:44:12 +0100
perf: Fix sibling it
Commit-ID: 24868367cdcac447232ebcb2aa06e1bf91291586
Gitweb: https://git.kernel.org/tip/24868367cdcac447232ebcb2aa06e1bf91291586
Author: Mark Rutland
AuthorDate: Fri, 16 Mar 2018 12:51:40 +
Committer: Thomas Gleixner
CommitDate: Fri, 16 Mar 2018 20:44:32 +0100
perf/core: Clear sibli
On 03/16/2018 02:11 PM, Florian Fainelli wrote:
> On March 16, 2018 11:42:21 AM PDT, Grygorii Strashko
> wrote:
>>
>>
>> On 03/16/2018 12:34 PM, Florian Fainelli wrote:
>>>
>>>
>>> On 03/16/2018 10:22 AM, Andrew Lunn wrote:
On Wed, Mar 14, 2018 at 05:26:22PM -0500, Grygorii Strashko wrote:
Hi Masahiro,
I love your patch! Perhaps something to improve:
[auto build test WARNING on v4.16-rc4]
[also build test WARNING on next-20180316]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits
On 03/16/2018 01:06 PM, Eric W. Biederman wrote:
>> It does not revert cleanly so I reverted it manually. Patch doing that
>> is attached. Should we do this, or is there a better option?
> Please see:
> 859d880cf544 ("signal: Correct the offset of si_pkey in struct siginfo")
It would be really n
> The phydrv->mdiodrv.flags can be accessible only after call to
> of_phy_connect()/phy_connect(),
You need to use a function like of_phy_find_device() to get the
phydev, set the flag, and then call phy_connect_direct().
Andrew
From: Jérôme Glisse
User of hmm_vma_fault() and hmm_vma_get_pfns() provide a flags array
and pfn shift value allowing them to define their own encoding for HMM
pfn that are fill inside the pfns array of the hmm_range struct. With
this device driver can get pfn that match their own private encodin
From: Jérôme Glisse
No functional change, just create one function to handle pmd and one
to handle pte (hmm_vma_handle_pmd() and hmm_vma_handle_pte()).
Signed-off-by: Jérôme Glisse
Cc: Evgeny Baskakov
Cc: Ralph Campbell
Cc: Mark Hairgrove
Cc: John Hubbard
---
mm/hmm.c | 174 +++
From: Jérôme Glisse
Make naming consistent accross code, DEVICE_PRIVATE is the name use
outside HMM code so use that one.
Signed-off-by: Jérôme Glisse
Cc: Evgeny Baskakov
Cc: Ralph Campbell
Cc: Mark Hairgrove
Cc: John Hubbard
---
include/linux/hmm.h | 4 ++--
mm/hmm.c| 2 +-
2
From: Jérôme Glisse
This change hmm_vma_fault() to not take a global write fault flag
for a range but instead rely on caller to populate HMM pfns array
with proper fault flag ie HMM_PFN_VALID if driver want read fault
for that address or HMM_PFN_VALID and HMM_PFN_WRITE for write.
Moreover by set
Quoting sean.w...@mediatek.com (2018-02-17 11:54:36)
> From: Sean Wang
>
> All ethsys, pciesys and ssusbsys internally include reset controller, so
> explicitly add back these missing cell definitions to related bindings
> and examples.
>
> Signed-off-by: Sean Wang
> Cc: Rob Herring
> Cc: Mich
From: Jérôme Glisse
Move hmm_pfns_clear() closer to where it is use to make it clear it
is not use by page table walkers.
Signed-off-by: Jérôme Glisse
Cc: Evgeny Baskakov
Cc: Ralph Campbell
Cc: Mark Hairgrove
Cc: John Hubbard
---
mm/hmm.c | 16
1 file changed, 8 insertions
Get rid of ple_window_actual_max, because its benefits are really
minuscule and the logic is complicated.
The overflows(and underflow) are controlled in __ple_window_grow
and _ple_window_shrink respectively.
Suggested-by: Radim Krčmář
Signed-off-by: Babu Moger
---
arch/x86/kvm/vmx.c | 22 +
Bring the PLE(pause loop exit) logic to AMD svm driver.
While testing, we found this helping in situations where numerous
pauses are generated. Without these patches we could see continuos
VMEXITS due to pause interceptions. Tested it on AMD EPYC server with
boot parameter idle=poll on a VM with 3
This patch adds the support for pause filtering threshold. This feature
support is indicated by CPUID Fn8000_000A_EDX. See AMD APM Vol 2 Section
15.14.4 Pause Intercept Filtering for more details.
In this mode, a 16-bit pause filter threshold field is added in VMCB.
The threshold value is a cycle
This series adds PLE(pause loop exit) logic from VMX to SVM.
We have noticed considerable reduction in number of VMEXITS due to pause
interceptions after these changes. Here are the numbers on one guest with
32 vcpus on AMD EPYC system. We have used boot parameter idle=poll to
simulate extensive p
This patch brings some of the code from vmx to x86.h header file. Now, we
can share this code between vmx and svm. Modified couple functions to make
it common.
Signed-off-by: Babu Moger
---
arch/x86/kvm/vmx.c | 48 +---
arch/x86/kvm/x86.h | 35
The vmx module parameters are supposed to be unsigned variants.
Also fixed the checkpatch errors like the one below.
WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal
permissions '0444'.
+module_param(ple_gap, uint, S_IRUGO);
Signed-off-by: Babu Moger
---
arch/x8
IMA will use the module_signature format for append signatures, so export
the relevant definitions and factor out the code which verifies that the
appended signature trailer is valid.
Also, create a CONFIG_MODULE_SIG_FORMAT option so that IMA can select it
and be able to use validate_module_sig()
With the introduction of another IMA signature type (modsig), some places
will need to check for both of them. It is cleaner to do that if there's a
helper function to tell whether an xattr_value represents an IMA
signature.
Suggested-by: Mimi Zohar
Signed-off-by: Thiago Jung Bauermann
---
secu
IMA will need to know the key that signed a given PKCS#7 message, so add
pkcs7_get_message_sig().
It will also need to verify an already parsed PKCS#7 message. For this
purpose, add verify_pkcs7_message_sig() which takes a struct pkcs7_message
for verification instead of the raw bytes that verify_
ima_read_modsig() will need it so that it can show an error message.
Signed-off-by: Thiago Jung Bauermann
---
security/integrity/ima/ima.h| 2 ++
security/integrity/ima/ima_policy.c | 12 ++--
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/security/integrity/ima/
Define new "d-sig" template field which holds the digest that is expected
to match the one contained in the modsig.
Also add modsig support to the "sig" template field, allowing the the
contents of the modsig to be included in the measurement list.
Suggested-by: Mimi Zohar
Signed-off-by: Thiago
This patch actually implements the appraise_type=imasig|modsig option,
allowing IMA to read and verify modsig signatures.
In case both are present in the same file, IMA will first check whether the
key used by the xattr signature is present in the kernel keyring. If not,
it will try the appended s
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