4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Kees Cook
commit 5c3070890d06ff82eecb808d02d2ca39169533ef upstream
When speculation flaw mitigations are opt-in (via prctl), using seccomp
will automatically opt-in to these protections, since
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Thomas Gleixner
commit b617cfc858161140d69cc0b5cc211996b557a1c7 upstream
Add two new prctls to control aspects of speculation related vulnerabilites
and their mitigations to provide finer
On 07/15, Chao Yu wrote:
> On 2018/7/15 11:13, Jaegeuk Kim wrote:
> > On 07/15, Chao Yu wrote:
> >> Hi Jaegeuk,
> >>
> >> On 2018/7/15 9:27, Jaegeuk Kim wrote:
> >>> On 07/08, Chao Yu wrote:
> From: Chao Yu
>
> Some devices has small max_{hw,}discard_sectors, so that in
>
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Kees Cook
commit 7bbf1373e228840bb0295a2ca26d548ef37f448e upstream
Adjust arch_prctl_get/set_spec_ctrl() to operate on tasks other than
current.
This is needed both for /proc/$pid/status
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Sascha Hauer
commit f78e5623f45bab2b726eec29dc5cefbbab2d0b1c upstream.
The fastmap update code might erase the current fastmap anchor PEB
in case it doesn't find any new free PEB. When a power
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Thomas Gleixner
commit 356e4bfff2c5489e016fdb925adbf12a1e3950ee upstream
For certain use cases it is desired to enforce mitigations so they cannot
be undone afterwards. That's important for
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Richard Weinberger
commit 74f2c6e9a47cf4e508198c8594626cc82906a13d upstream.
Since PEB erasure is asynchornous it can happen that there is
more than one Fastmap on the MTD. This is fine
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Richard Weinberger
commit f7d11b33d4e8cedf19367c09b891bbc705163976 upstream.
Usually Fastmap is free to consider every PEB in one of the pools
as newer than the existing PEB. Since PEBs in a
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Kees Cook
commit fae1fa0fc6cca8beee3ab8ed71d54f9a78fa3f64 upstream
As done with seccomp and no_new_privs, also show speculation flaw
mitigation state in /proc/$pid/status.
Signed-off-by: Kees
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Thomas Gleixner
commit b849a812f7eb92e96d1c8239b06581b2cfd8b275 upstream
Use PR_SPEC_FORCE_DISABLE in seccomp() because seccomp does not allow to
widen restrictions.
Signed-off-by: Thomas
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Konrad Rzeszutek Wilk
commit 9f65fb29374ee37856dbad847b4e121aab72b510 upstream
Intel collateral will reference the SSB mitigation bit in IA32_SPEC_CTL[2]
as SSBD (Speculative Store Bypass
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Kees Cook
commit f21b53b20c754021935ea43364dbf53778eeba32 upstream
Unless explicitly opted out of, anything running under seccomp will have
SSB mitigations enabled. Choosing the "prctl" mode
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Kees Cook
commit 00a02d0c502a06d15e07b857f8ff921e3e402675 upstream
If a seccomp user is not interested in Speculative Store Bypass mitigation
by default, it can set the new
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: David Woodhouse
(cherry picked from commit fc67dd70adb711a45d2ef34e12d1a8be75edde61)
Add three feature bits exposed by new microcode on Intel CPUs for
speculation control.
Signed-off-by:
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Thomas Gleixner
commit 8bf37d8c067bb7eb8e7c381bdadf9bd89182b6bc upstream
The migitation control is simpler to implement in architecture code as it
avoids the extra function call to check the
On Mon, Jul 23, 2018 at 2:42 PM, Mark Rutland wrote:
>> >> > Hi all-
>> >> >
>> >> > It would be really nice to make KASAN compatible with VMAP_STACK.
>> >> > Both are valuable memory debugging features, and the fact that you
>> >> > can't use both is disappointing.
>> >> >
>> >> > As far as I
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Jim Mattson
commit 5f2b745f5e1304f438f9b2cd03ebc8120b6e0d3b upstream
Cast val and (val >> 32) to (u32), so that they fit in a
general-purpose register in both 32-bit and 64-bit code.
[ tglx:
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Kyle Huey
commit b9894a2f5bd18b1691cb6872c9afe32b148d0132 upstream
The debug control MSR is "highly magical" as the blockstep bit can be
cleared by hardware under not well documented
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Thomas Gleixner
commit 52817587e706686fcdb27f14c1b000c92f266c96 upstream
The SSBD enumeration is similarly to the other bits magically shared
between Intel and AMD though the mechanisms are
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Borislav Petkov
commit dd0792699c4058e63c0715d9a7c2d40226fcdddc upstream
Fix some typos, improve formulations, end sentences with a fullstop.
Signed-off-by: Borislav Petkov
Signed-off-by:
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Kyle Huey
commit af8b3cd3934ec60f4c2a420d19a9d416554f140b upstream
Help the compiler to avoid reevaluating the thread flags for each checked
bit by reordering the bit checks and providing an
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Jiri Kosina
commit 7bb4d366cba992904bffa4820d24e70a3de93e76 upstream
cpu_show_common() is not used outside of arch/x86/kernel/cpu/bugs.c, so
make it static.
Signed-off-by: Jiri Kosina
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Konrad Rzeszutek Wilk
commit e96f46ee8587607a828f783daa6eb5b44d25004d upstream
The style for the 'status' file is CamelCase or this. _.
Fixes: fae1fa0fc ("proc: Provide details on speculation
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Jiri Kosina
commit d66d8ff3d21667b41eddbe86b35ab411e40d8c5f upstream
__ssb_select_mitigation() returns one of the members of enum ssb_mitigation,
not ssb_mitigation_cmd; fix the prototype to
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Andy Shevchenko
commit f5fbf848303c8704d0e1a1e7cabd08fd0a49552f upstream
Merrifield2 is actually Moorefield.
Rename it accordingly and drop tail digit from Merrifield1.
Signed-off-by: Andy
Thanks for the reply :)
On 2018/7/23 20:24, Stefan Richter wrote:
Adding Cc: LSML
On Jul 23 Jia-Ju Bai wrote:
sbp2_scsi_queuecommand() is only set to .queuecommand of
"struct scsi_host_template", and this function pointer is never called
in atomic context.
As far as I remember,
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Konrad Rzeszutek Wilk
commit 0cc5fa00b0a88dad140b4e5c2cead9951ad36822 upstream
Add the CPU feature bit CPUID.7.0.EDX[31] which indicates whether the CPU
supports Reduced Data Speculation.
[
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Konrad Rzeszutek Wilk
commit 5cf687548705412da47c9cec342fd952d71ed3d5 upstream
A guest may modify the SPEC_CTRL MSR from the value used by the
kernel. Since the kernel doesn't use IBRS, this
4.17-stable review patch. If anyone has any objections, please let me know.
--
From: Damien Le Moal
commit f13cff6c25bd8986627365346d123312ee7baa78 upstream.
Fix the description of sd_zbc_check_zone_size() to correctly explain that
the returned value is a number of device
On 07/22/2018 10:45 AM, Andy Lutomirski wrote:
> static void __init pti_clone_user_shared(void)
> {
> + unsigned cpu;
> +
> pti_clone_p4d(CPU_ENTRY_AREA_BASE);
> +
> + for_each_possible_cpu(cpu) {
> + /*
> + * The SYSCALL64 entry code needs to be able to
On Mon, Jul 23, 2018 at 2:46 PM, Dmitry Vyukov wrote:
> On Mon, Jul 23, 2018 at 2:33 PM, Miklos Szeredi wrote:
> On Mon, Jul 23, 2018 at 9:59 AM, syzbot
> wrote:
>> Hello,
>>
>> syzbot found the following crash on:
>>
>> HEAD commit:d72e90f33aa4 Linux 4.18-rc6
On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote:
> The 2D and 3D clocks have an IDLE field in bits 15:8 so add these
> clocks by making a 2D and 3D mux, and split the divider into the
> standard 2D/3D ones and 2D/3D idle clocks.
>
> Signed-off-by: Ben Dooks
> ---
>
WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal
permissions '0444'.
+static DEVICE_ATTR(fw_version, S_IRUGO, mxt_fw_version_show, NULL);
WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal
permissions '0444'.
+static
WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal
permissions '0444'.
+static DEVICE_ATTR(name, S_IRUGO, name ## _show, NULL);
WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal
permissions '0444'.
+static DEVICE_ATTR(pen_down, S_IRUGO,
Hi Morten
On 20/07/18 14:32, Morten Rasmussen wrote:
The SD_ASYM_CPUCAPACITY sched_domain flag is supposed to mark the
sched_domain in the hierarchy where all cpu capacities are visible for
any cpu's point of view on asymmetric cpu capacity systems. The
scheduler can then take to take capacity
ivers/mailbox/ti-msgmgr.c| 353
> +
> 2 files changed, 336 insertions(+), 67 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt
Jassi,
I dont see this in next-20180723. You'd asked
On Thu, Jul 19, 2018 at 11:19:54PM +0200, Peter Zijlstra wrote:
> --- a/include/uapi/linux/perf_event.h
> +++ b/include/uapi/linux/perf_event.h
> @@ -143,6 +143,8 @@ enum perf_event_sample_format {
> PERF_SAMPLE_PHYS_ADDR = 1U << 19,
>
> PERF_SAMPLE_MAX = 1U << 20,
To share codes between AMD and Hygon to mitigate Spectre V2 Retpoline
vulnerability, rename macros SPECTRE_V2_RETPOLINE_MINIMAL_AMD to
SPECTRE_V2_RETPOLINE_MINIMAL_LFENCE, and SPECTRE_V2_CMD_RETPOLINE_AMD
to SPECTRE_V2_CMD_RETPOLINE_LFENCE.
As Hygon processors is not affected by meltdown
On Mon, Jul 23, 2018 at 3:05 PM, Miklos Szeredi wrote:
>> wrote:
>>> Hello,
>>>
>>> syzbot found the following crash on:
>>>
>>> HEAD commit:d72e90f33aa4 Linux 4.18-rc6
>>> git tree: upstream
>>> console output:
On 07/23/2018 12:04 AM, Davidlohr Bueso wrote:
> On Wed, 18 Jul 2018, Waiman Long wrote:
>
>> The key here is that we don't want other incoming readers to observe
>> that there are waiters in the wait queue and hence have to go into the
>> slowpath until the single waiter in the queue is sure that
This is one of the default lcdif panel options for several imx
development boards. Now that we switched to CONFIG_DRM_MXSFB=y this
should be enabled as well.
Signed-off-by: Leonard Crestez
---
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
On 23-Jul 16:13, Peter Zijlstra wrote:
> On Mon, Jul 23, 2018 at 01:49:46PM +0100, Patrick Bellasi wrote:
> > On 23-Jul 11:49, Peter Zijlstra wrote:
> >
> > [...]
> >
> > > > -void __getparam_dl(struct task_struct *p, struct sched_attr *attr)
> > > > +void __getparam_dl(struct task_struct *p,
Stephen Rothwell writes:
> Hi all,
>
> Changes since 20180720:
>
> Dropped trees: xarray, ida (complex conflicts)
>
> The drm-msm tree gained a conflict against the drm tree and a build
> failure due to an interaction with the drm tree for which I added a
> merge fix patch.
>
> The kvm-arm tree
On 23 July 2018 00:28, Daniel Kurtz wrote:
> Some systems do not have software controllable regulators driving the
> DA7219's supplies, nor can they use device tree to create "always-on fixed
> regulators" to easily pretend like they do.
>
> On these systems the call to devm_regulator_bulk_get()
According to commit [1], dwarf2 unwinder had some issues that prevented the
fault injection stacktrace filter from working on x86-64.
Does anyone know whether this issue still exists 11 years later?
Are there any objections to revert this patch?
Gal
[1] 6d690dcac92a ("fault injection: disable
On Fri, Jul 20, 2018 at 2:35 PM, Andy Lutomirski wrote:
>
>> On Jul 16, 2018, at 6:05 AM, H.J. Lu wrote:
>>
>>> On Fri, Jul 13, 2018 at 7:08 PM, Andy Lutomirski
>>> wrote:
>>> I'm not at all convinced that this is the problem, but the series here
>>> will give a better diagnostic if the issue
On Sun, 22 Jul 2018 21:00:51 +0200
Marcus Folkesson wrote:
> Hi Jonathan,
>
> Thanks, all good catches.
>
> On Sun, Jul 22, 2018 at 09:08:38AM +0100, Jonathan Cameron wrote:
> > On Sat, 21 Jul 2018 23:19:48 +0200 (CEST)
> > Peter Meerwald-Stadler wrote:
> >
> > > Hello,
> > >
> > > >
On Thu, Mar 08, 2018 at 06:15:41PM -0800, kan.li...@linux.intel.com wrote:
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index ef47a418d819..86149b87cce8 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -2280,7 +2280,10 @@ static
On Wed, Jun 13, 2018 at 10:45:37AM -0500, Serge Hallyn wrote:
> On Thu, Jun 07, 2018 at 01:43:48PM +0200, Christian Brauner wrote:
> > When running in a container with a user namespace, if you call getxattr
> > with name = "system.posix_acl_access" and size % 8 != 4, then getxattr
> > silently
On Mon, 23 Jul 2018 14:25:31 +0200
Dominique Martinet wrote:
> Greg Kurz wrote on Mon, Jul 23, 2018:
> > The patch is quite big and I'm not sure I can find time to review it
> > carefully, but I'll try to help anyway.
>
> No worry, thanks for this already.
>
> > > Sorry for coming back to
Signed-off-by: Ivan Bornyakov
---
drivers/staging/gasket/gasket_page_table.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/gasket/gasket_page_table.c
b/drivers/staging/gasket/gasket_page_table.c
index 9f8116112e0a..3ffc8d67ec05 100644
---
This patch series resolves code style problems as reported by code analysis
tools.
Changes in v2:
- From the first version of patches, 2 patches are dropped in this
series.
- In the v1 patch set, 1/4 was not required as the issue is in
checkpatch.pl script and
This patch avoids getting irq number in xadc_remove function. Instead
store 'irq' in xadc struct and use xadc->irq wherever needed.
This patch also resolves a warning reported by coverity where it asks to
check return value of platform_get_irq() for any errors in xadc_remove.
Signed-off-by:
This patch adds check for return values from clock related functions.
This was reported by static code analysis tool.
Signed-off-by: Manish Narani
---
drivers/iio/adc/xilinx-xadc-core.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git
On Mon, Jul 23, 2018 at 04:59:44PM +0200, Peter Zijlstra wrote:
> On Thu, Mar 08, 2018 at 06:15:41PM -0800, kan.li...@linux.intel.com wrote:
> > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> > index ef47a418d819..86149b87cce8 100644
> > ---
This patch limits the xadc pcap clock frequency value to be less than
200MHz. This fixes the issue when zynq is booted at higher frequency
values, pcap crosses the maximum limit of 200MHz(Fmax) as it is derived
from IOPLL.
If this limit is crossed it is required to alter the WEDGE and REDGE
bits
Enabling the Interrupts before registering the irq handler is a bad
idea. This patch corrects the same for XADC driver.
Signed-off-by: Manish Narani
---
drivers/iio/adc/xilinx-xadc-core.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
On 20-Jul 18:23, Suren Baghdasaryan wrote:
> Hi Patrick,
Hi Sure,
thank!
> On Mon, Jul 16, 2018 at 1:29 AM, Patrick Bellasi
> wrote:
[...]
> > @@ -977,13 +991,21 @@ static inline void uclamp_cpu_get_id(struct
> > task_struct *p,
> > uc_grp = >uclamp.group[clamp_id][0];
> >
Hi Huacai,
On Sat, Jul 21, 2018 at 09:35:59AM +0800, 陈华才 wrote:
> SFB can improve the memory bandwidth as much as 30%, and we are
> planning to enable SFB by default. So, we want to control cpu_relax()
> under CONFIG_CPU_LOONGSON3, not under CONFIG_LOONGSON3_ENHANCEMENT.
OK, applied to mips-next
On Fri, Jul 20, 2018 at 07:02:39PM +0530, Balakrishna Godavarthi wrote:
> Redefinition of qca_uart_setup will help future Qualcomm Bluetooth
> SoC, to use the same function instead of duplicating the function.
> Added new arguments soc_type and soc_ver to the functions.
>
> These arguments will
On 7/23/2018 6:33 AM, Nishanth Menon wrote:
On 17:13-20180716, Nishanth Menon wrote:
Please find attached series to enable host-id as an optional dt property.
This is a minor update to V1 -> Mostly to pick up Greet's feedback and Rob's
Ack.
V1: https://patchwork.ozlabs.org/cover/931822/
The
On Mon, Jul 23, 2018 at 10:25:10AM -0700, Joe Perches wrote:
> On Mon, 2018-07-23 at 10:18 -0700, Dmitry Torokhov wrote:
> > On Mon, Jul 23, 2018 at 03:32:00PM +0200, Greg Kroah-Hartman wrote:
> > > On Mon, Jul 23, 2018 at 06:49:20PM +0530, dev-harsh1998 wrote:
> > > > WARNING: Symbolic
In most of cases, interrupt bits are set one by one but there are
also a lot of other cases that Aspeed I2C IP sends multiple
interrupt bits with combining master and slave events using a
single interrupt call. It happens much in multi-master environment
than single-master. For an example, when
There are use cases where it can be useful to have a cpus_read_trylock()
function to work around circular lock dependency problem involving
the cpu_hotplug_lock.
Signed-off-by: Waiman Long
---
include/linux/cpu.h | 2 ++
kernel/cpu.c| 6 ++
2 files changed, 8 insertions(+)
diff
This patchset works around a circular lock dependency issue in the
cpufreq driver reported by lockdep. The two locks involved are the
cpu_hotplup_lock and the reference count of a sysfs file.
The cpufreq_register_driver() function uses the lock sequence:
cpus_read_lock --> kn->count
Whereas
With lockdep turned on, the following circular lock dependency problem
was reported:
[ 57.470040] ==
[ 57.502900] WARNING: possible circular locking dependency detected
[ 57.535208] 4.18.0-0.rc3.1.el8+7.x86_64+debug #1 Tainted: G
[
The pin controller block of S5Pv210 for handling external wakeup
interrupts is different than in newer designs (Exynos).
Signed-off-by: Krzysztof Kozlowski
Cc: Tomasz Figa
Cc: Sylwester Nawrocki
Acked-by: Tomasz Figa
---
arch/arm/boot/dts/s5pv210.dtsi | 2 +-
1 file changed, 1 insertion(+),
Suspend and resume callbacks in Exynos/S5Pv210 pin controller drivers,
save and restore state of registers. This operations should be done for
all banks which have external interrupts (as denoted by using
EXYNOS_PIN_BANK_EINTG/EINTW macros).
Add all banks of Exynos5260 and Exynos5420. This is
The pinctrl driver defines an IRQ chip which handles external wakeup
interrupts, therefore from logical point of view, it is the owner of
external interrupt mask. The register controlling the mask belongs to
Power Management Unit address space so it has to be accessed with PMU
syscon regmap
Hi All,
Changes since v1
1. Add Tomasz's ack.
2. Reword description in patch 6/10.
Tests
=
This is both request for comments and requests for tests. Only basic
tests were done, including suspend to RAM on Odroid U3 (Exynos4412)
with max7768 RTC wakeup. Please kindly test it
Add missing documentation for suspend and resume members of struct
samsung_pin_ctrl and samsung_pinctrl_drv_data.
Signed-off-by: Krzysztof Kozlowski
Cc: Tomasz Figa
Cc: Sylwester Nawrocki
Acked-by: Tomasz Figa
---
drivers/pinctrl/samsung/pinctrl-samsung.h | 8
1 file changed, 8
Hardware (S5Pv210 and all Exynos SoCs) provides only 32 external
interrupts which can wakeup device from deep sleep modes. On S5Pv210
these are gph0-gph3. On all Exynos designs these are gpx0-gpx3.
There is only one 32-bit register for controlling the external wakeup
interrupt mask (masking and
The S5Pv210 external wakeup interrupts differ from Exynos therefore
separate compatible is needed. Duplicate existing flavor specific data
from exynos4210_wkup_irq_chip and add new compatible for S5Pv210.
At this point this new compatible does not bring anything new and works
exactly as existing
S5Pv210 and Exynos5433/Exynos7 have different address of
EINT_WAKEUP_MASK register. Rename existing S5P_EINT_WAKEUP_MASK to
avoid confusion and add new ones.
Signed-off-by: Krzysztof Kozlowski
Cc: Tomasz Figa
Cc: Sylwester Nawrocki
Acked-by: Tomasz Figa
---
arch/arm/mach-exynos/suspend.c
Since Exynos/S5Pv210 pin-controller driver is taking care about setting
the external wakeup interrupts mask, the legacy code can be removed.
Signed-off-by: Krzysztof Kozlowski
Cc: Tomasz Figa
Cc: Sylwester Nawrocki
Acked-by: Tomasz Figa
---
arch/arm/mach-exynos/common.h | 2 --
Remove the legacy, ugly API of exposing the static value of external
wakeup interrupts mask, because all arch-machine users where converted
to use generic implementation from pinctrl driver.
Signed-off-by: Krzysztof Kozlowski
Cc: Tomasz Figa
Cc: Sylwester Nawrocki
Acked-by: Tomasz Figa
---
Since Exynos/S5Pv210 pin-controller driver is taking care about setting
the external wakeup interrupts mask, the legacy code can be removed.
Signed-off-by: Krzysztof Kozlowski
Cc: Tomasz Figa
Cc: Sylwester Nawrocki
Acked-by: Tomasz Figa
---
arch/arm/mach-s5pv210/common.h | 1 -
On Fri, Jul 20, 2018 at 07:02:40PM +0530, Balakrishna Godavarthi wrote:
> In function qca_setup, we set initial and operating speeds for Qualcomm
> Bluetooth SoC's. This block of code is common across different
> Qualcomm Bluetooth SoC's. Instead of duplicating the code, created
> a wrapper
ish_dev_init() allocates 512*176 bytes memory for tx_buf and stores it at
>wr_free_list_head.link list on ish_probe().
But there is no deallocation of this memory in ish_remove() and in
ish_probe()
error path.
So current intel-ish-ipc provides 88 KB memory leak for each probe/release.
I have
On 21/07/18 12:47 AM, Julia Lawall wrote:
> From: kbuild test robot
>
> Use DEFINE_DEBUGFS_ATTRIBUTE rather than DEFINE_SIMPLE_ATTRIBUTE
> for debugfs files.
>
> Rationale: DEFINE_SIMPLE_ATTRIBUTE + debugfs_create_file()
> imposes some significant overhead as compared to
>
From: Ursula Braun
Date: Mon, 23 Jul 2018 13:53:07 +0200
> here are some small patches for SMC: Just the first patch contains a
> functional change. It allows to differ between the modes SMCR and SMCD
> on s390 when monitoring SMC sockets. The remaining patches are cleanups
> without functional
On 07/23/2018 01:01 PM, Mark Brown wrote:
On Fri, Jul 20, 2018 at 08:43:49PM -0400, Peter Geis wrote:
SW2 and SW4 use a shared table to provide voltage to the cpu core and
devices on Tegra hardware.
Added this table to the cpcap regulator driver as the first step to
supporting this device on
Good Afternoon,
I am re-sending the whole patch set due to my error of accidentally
converting the tabulation to spaces.
The CPCAP regulator driver can support various devices, but currently
only supports Omap4 devices.
Adds the sw2 and sw4 voltage tables, which power the Tegra core, and a
SW2 and SW4 use a shared table to provide voltage to the cpu core and
devices on Tegra hardware.
Added this table to the cpcap regulator driver as the first step to
supporting this device on Tegra.
Signed-off-by: Peter Geis
---
drivers/regulator/cpcap-regulator.c | 23 +++
Added support for the CPCAP power management regulator functions on
Tegra devices.
Added sw2_sw4 value tables, which provide power to the Tegra core and
aux devices.
Added the Tegra init tables and device tree compatibility match.
Signed-off-by: Peter Geis
---
Hi Paul & Vinod,
On Sat, Jul 21, 2018 at 01:06:25PM +0200, Paul Cercueil wrote:
> This is the version 3 of my jz4780-dma driver update patchset.
>
> Apologies to the DMA people, the v2 of this patchset did not make it to
> their mailing-list; see the bottom of this email for a description of
>
On Mon, Jul 09, 2018 at 11:43:01AM +0200, Esben Haabendal wrote:
> From: Esben Haabendal
>
> Make sure to call reinit_completion() before dma is started to avoid race
> condition where reinit_completion() is called after complete() and before
> wait_for_completion_timeout().
>
> Signed-off-by:
On 07/23/2018 10:48 AM, Jae Hyun Yoo wrote:
In most of cases, interrupt bits are set one by one but there are
also a lot of other cases that Aspeed I2C IP sends multiple
interrupt bits with combining master and slave events using a
single interrupt call. It happens much in multi-master
On 7/23/2018 10:36 AM, Qing Huang wrote:
>
> Hi Daniel/Parav,
>
> Have you got a chance to review this patch? Thanks!
Hi Qing, sorry for the delay, I just got back to the office today. I don't
agree with the proposed fix, I provided an alternative suggestion below.
>
>>> Or.
>>>
On Mon, Jul 23, 2018 at 01:58:26PM -0400, Peter Geis wrote:
> SW2 and SW4 use a shared table to provide voltage to the cpu core and
> devices on Tegra hardware.
> Added this table to the cpcap regulator driver as the first step to
> supporting this device on Tegra.
This also doesn't apply against
Thanks James for the review. Please see my inline answers.
On 7/23/2018 11:10 AM, James Feist wrote:
On 07/23/2018 10:48 AM, Jae Hyun Yoo wrote:
In most of cases, interrupt bits are set one by one but there are
also a lot of other cases that Aspeed I2C IP sends multiple
interrupt bits with
Hello,
I noticed this got merged, but I wanted to put my 2 cents in here:
On Wed, Dec 06, 2017 at 10:53:42AM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Restore the status to be compatible with legacy devices.
> Take Freescale eSPI boot for example, it copies (in 3 Byte
> addressing
Hi Daniel,
On 7/23/2018 11:11 AM, Daniel Jurgens wrote:
On 7/23/2018 10:36 AM, Qing Huang wrote:
Hi Daniel/Parav,
Have you got a chance to review this patch? Thanks!
Hi Qing, sorry for the delay, I just got back to the office today. I don't
agree with the proposed fix, I provided an
On Fri, 20 Jul 2018 at 03:04, Suzuki K Poulose wrote:
>
> Mathieu,
>
> On 19/07/18 21:36, Mathieu Poirier wrote:
> > On Tue, Jul 17, 2018 at 06:11:40PM +0100, Suzuki K Poulose wrote:
> >> In coresight perf mode, we need to prepare the sink before
> >> starting a session, which is done via
On Mon, Jul 23, 2018 at 10:25:10AM -0700, Joe Perches wrote:
> On Mon, 2018-07-23 at 10:18 -0700, Dmitry Torokhov wrote:
> > On Mon, Jul 23, 2018 at 03:32:00PM +0200, Greg Kroah-Hartman wrote:
> > > On Mon, Jul 23, 2018 at 06:49:20PM +0530, dev-harsh1998 wrote:
> > > > WARNING: Symbolic
Hi,
I'm a little late to this thread, but I recently noticed (and
complained about) commit: 59b356ffd0b0 ("mtd: m25p80: restore the
status of SPI flash when exiting").
On Mon, Apr 9, 2018 at 6:05 PM, NeilBrown wrote:
> On Mon, Apr 09 2018, Marek Vasut wrote:
>
>> On 04/08/2018 11:56 PM,
Use vzalloc instead of vmalloc followed by memset with 0.
Signed-off-by: Ivan Bornyakov
---
drivers/staging/gasket/gasket_page_table.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/gasket/gasket_page_table.c
On Mon, Jul 23, 2018 at 10:23:05AM -0700, Dmitry Torokhov wrote:
> On Mon, Jul 23, 2018 at 10:13:36AM -0700, Guenter Roeck wrote:
> > On Mon, Jul 23, 2018 at 07:48:57PM +0300, Anton Vasilyev wrote:
> > > static struct ro_vpd and rw_vpd are initialized by vpd_sections_init()
> > > in vpd_probe()
On Mon, 2018-07-23 at 11:24 -0700, Guenter Roeck wrote:
> There are much more urgent issues to fix there (such as, for example,
> converting the "offending" drivers to the latest API, which would
> magically cause most of the offenders to disappear).
Perhaps posting a list of desired hwmon
On 07/23/2018 02:13 PM, Mark Brown wrote:
On Mon, Jul 23, 2018 at 01:58:26PM -0400, Peter Geis wrote:
SW2 and SW4 use a shared table to provide voltage to the cpu core and
devices on Tegra hardware.
Added this table to the cpcap regulator driver as the first step to
supporting this device on
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