[PATCH] tty: serial: msm_geni_serial: Fix TX infinite loop

ail, both fixing the underflow and freeing up space for a smoother circular experience. Signed-off-by: Evan Green <evgr...@chromium.org> --- Note: This patch applies on top of Karthik's series of 8 fixup patches, which seem basically ready to go, at: https://www.spinics.net/lists/linux-arm-msm

Re: [PATCH v4 1/7] interconnect: Add generic on-chip interconnect API

Hi Georgi, On Fri, Mar 9, 2018 at 1:12 PM Georgi Djakov wrote: > This patch introduce a new API to get requirements and configure the > interconnect buses across the entire chipset to fit with the current > demand. > The API is using a consumer/provider-based model,

Re: [PATCH v4 5/7] interconnect: qcom: Add msm8916 interconnect provider driver

Hi Georgi, On Fri, Mar 9, 2018 at 1:11 PM Georgi Djakov wrote: > Add driver for the Qualcomm interconnect buses found in msm8916 based > platforms. > Signed-off-by: Georgi Djakov > --- >drivers/interconnect/Kconfig| 5 + >

Re: [PATCH v4 7/7] interconnect: Allow endpoints translation via DT

On Fri, Mar 9, 2018 at 1:10 PM Georgi Djakov wrote: > Currently we support only platform data for specifying the interconnect > endpoints. As now the endpoints are hard-coded into the consumer driver > this may leed to complications when a single driver is used by

Re: [PATCH v4 4/7] interconnect: qcom: Add RPM communication

On Fri, Mar 9, 2018 at 1:11 PM Georgi Djakov wrote: > On some Qualcomm SoCs, there is a remote processor, which controls some of > the Network-On-Chip interconnect resources. Other CPUs express their needs > by communicating with this processor. Add a driver to handle

Re: [PATCH v6 2/2] drivers: soc: Add LLCC driver

Hi Rishabh, On Tue, May 8, 2018 at 1:23 PM Rishabh Bhatnagar wrote: > LLCC (Last Level Cache Controller) provides additional cache memory > in the system. LLCC is partitioned into multiple slices and each > slice gets its own priority, size, ID and other config

Re: [PATCH RFC] mmc: sdhci: Don't get card-detect without preemption

On Wed, May 16, 2018 at 2:52 AM Adrian Hunter <adrian.hun...@intel.com> wrote: > On 02/05/18 02:47, Evan Green wrote: > > For a controller with SDHCI_QUIRK_NO_CARD_NO_RESET, there are several > > conditions where sdhci_do_reset is called under a spinlock with interrupts &

[PATCH] mmc: Allow non-sleeping GPIO cd

, and b) wire card detect up to a GPIO that doesn't sleep, this is a spurious warning. This change silences that warning, at the cost of pushing this problem down to users that have sleeping GPIOs and controllers with this quirk. Signed-off-by: Evan Green <evgr...@chromium.org> --- This

[PATCH v2] mmc: Allow non-sleeping GPIO cd

, and b) wire card detect up to a GPIO that doesn't sleep, this is a spurious warning. This change silences that warning, at the cost of pushing this problem down to users that have sleeping GPIOs and controllers with this quirk. Signed-off-by: Evan Green <evgr...@chromium.org> --- Changes si

Re: [PATCH V1 2/3] mmc: sdhci-msm: Add msm version specific ops and data structures

On Thu, May 24, 2018 at 5:35 AM Vijay Viswanath <vvisw...@codeaurora.org> wrote: > On 5/22/2018 11:40 PM, Evan Green wrote: > > On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath <vvisw...@codeaurora.org > > wrote: > > > >> In addition to offsets of ce

Re: [PATCH V1 3/3] mmc: host: Register changes for sdcc V5

On Thu, May 24, 2018 at 6:01 AM Vijay Viswanath <vvisw...@codeaurora.org> wrote: > On 5/22/2018 11:42 PM, Evan Green wrote: > > Hi Vijay. Thanks for this patch. > > > > On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath <vvisw...@codeaurora.org > > wrote:

Re: [PATCH] mmc: Allow non-sleeping GPIO cd

On Tue, May 22, 2018 at 5:08 AM Ulf Hansson wrote: > First, I thought I preferred this option, as it becomes clear of what > goes on. However I then realize, that it may not be worth it, because > in the end I guess the caller (sdhci), will not be able to deal with >

Re: [PATCH v7 2/2] drivers: soc: Add LLCC driver

ers/soc/qcom/llcc-slice.c > create mode 100644 include/linux/soc/qcom/llcc-qcom.h Thanks Rishabh. Reviewed-by: Evan Green <evgr...@chromium.org>

Re: [PATCH V1 1/3] mmc: sdhci-msm: Define new Register address map

Hi Vijay, On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath wrote: > From: Sayali Lokhande > For SDCC version 5.0.0, MCI registers are removed from SDCC > interface and some registers are moved to HC. > Define a new data structure where we can

Re: [PATCH V1 2/3] mmc: sdhci-msm: Add msm version specific ops and data structures

On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath wrote: > In addition to offsets of certain registers changing, the registers in > core_mem have been shifted to HC mem as well. To access these registers, > define msm version specific functions. These functions can be

Re: [PATCH V1 3/3] mmc: host: Register changes for sdcc V5

Hi Vijay. Thanks for this patch. On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath wrote: > From: Sayali Lokhande > For SDCC version 5.0.0 and higher, new compatible string > "qcom,sdhci-msm-v5" is added. > Based on the msm variant, pick the

Re: [PATCH] arm64: dts: qcom: Add pm8005 and pm8998 support

oot/dts/qcom/pm8998.dtsi | 55 > 2 files changed, 88 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/pm8005.dtsi > create mode 100644 arch/arm64/boot/dts/qcom/pm8998.dtsi > Reviewed-by: Evan Green

Re: [PATCH V2 1/4] mmc: sdhci-msm: Define new Register address map

ne a new data structure where we can statically define > > the address offsets for the registers in different SDCC versions. > > > > Signed-off-by: Sayali Lokhande > > Signed-off-by: Vijay Viswanath > > It would be prettier to line up the '=' and use BIT() not << but nevertheless: > > Acked-by: Adrian Hunter Reviewed-by: Evan Green

Re: [PATCH V2 2/4] mmc: sdhci-msm: Add msm version specific ops and data structures

On Tue, Jun 5, 2018 at 11:32 PM Adrian Hunter wrote: > > On 29/05/18 12:52, Vijay Viswanath wrote: > > In addition to offsets of certain registers changing, the registers in > > core_mem have been shifted to HC mem as well. To access these > > registers, define msm version specific functions.

Re: [PATCH V2 4/4] mmc: host: Register changes for sdcc V5

for register read/write to msm specific registers. > > > > Signed-off-by: Sayali Lokhande > > Signed-off-by: Vijay Viswanath > > Acked-by: Adrian Hunter Reviewed-by: Evan Green

[PATCH] pinctrl: msm: Pass along set_wake failures

] [] state_store+0xd4/0xf8 [ 54.091733] [] kobj_attr_store+0x18/0x28 [ 54.097396] [] sysfs_kf_write+0x5c/0x68 [ 54.102961] [] kernfs_fop_write+0x174/0x1b8 [ 54.108887] [] __vfs_write+0x58/0x160 [ 54.114276] [] vfs_write+0xcc/0x184 [ 54.119487] [] SyS_write+0x64/0xb4 Signed-off-by: Evan

[PATCH 4/7] scsi: ufs: sysfs: Document attribute writability

This change removes the read-only clauses from the documentation for UFS attributes, which are now writable. Signed-off-by: Evan Green --- Documentation/ABI/testing/sysfs-driver-ufs | 17 + 1 file changed, 1 insertion(+), 16 deletions(-) diff --git a/Documentation/ABI/testing

Re: [PATCH v4 1/7] interconnect: Add generic on-chip interconnect API

On Wed, Jun 6, 2018 at 11:09 AM Georgi Djakov wrote: > > Hi Evan, > > On 06/06/2018 05:59 PM, Georgi Djakov wrote: > >>> + > >>> +/** > >>> + * icc_node_create() - create a node > >>> + * @id: node id > >>> + * > >>> + * Return: icc_node pointer on success, or ERR_PTR() on error > >>> + */ > >>>

Re: [PATCH v5 6/8] interconnect: qcom: Add msm8916 interconnect provider driver

On Wed, Jun 20, 2018 at 5:11 AM Georgi Djakov wrote: > > Add driver for the Qualcomm interconnect buses found in msm8916 based > platforms. > > Signed-off-by: Georgi Djakov > --- > drivers/interconnect/Kconfig| 5 + > drivers/interconnect/Makefile | 1 + >

Re: [PATCH v5 4/8] interconnect: qcom: Add RPM communication

Hi Georgi, On Wed, Jun 20, 2018 at 5:11 AM Georgi Djakov wrote: > > On some Qualcomm SoCs, there is a remote processor, which controls some of > the Network-On-Chip interconnect resources. Other CPUs express their needs > by communicating with this processor. Add a driver to handle comminication

Re: [PATCH v7 3/4] phy: Add QMP phy based UFS phy support for sdm845

On Tue, Jun 19, 2018 at 1:38 AM Can Guo wrote: > > Add UFS PHY support to make SDM845 UFS work with common PHY framework. > > Signed-off-by: Can Guo > --- > drivers/phy/qualcomm/phy-qcom-qmp.c | 173 > +++- > drivers/phy/qualcomm/phy-qcom-qmp.h | 15 > 2

Re: [PATCH v7 2/4] phy: General struct and field cleanup

m/phy-qcom-qmp.c | 25 ++--- > 1 file changed, 14 insertions(+), 11 deletions(-) > I'm not a PHY expert, so I can't say much about the mechanics or ramifications of the is_dual_lane_phy change is, but for at least the sanity of the patch, here's my tag: Reviewed-by: Evan Green

Re: [PATCH v5 1/8] interconnect: Add generic on-chip interconnect API

Hi Georgi. Thanks for the new spin of this. On Wed, Jun 20, 2018 at 5:11 AM Georgi Djakov wrote: > > This patch introduce a new API to get requirements and configure the > interconnect buses across the entire chipset to fit with the current > demand. > > The API is using a

Re: [PATCH v5 6/8] interconnect: qcom: Add msm8916 interconnect provider driver

On Sun, Jul 1, 2018 at 5:12 AM Georgi Djakov wrote: > > Hi Evan, > > On 06/26/2018 11:48 PM, Evan Green wrote: > > On Wed, Jun 20, 2018 at 5:11 AM Georgi Djakov > > wrote: > > >> +static int qcom_icc_init(struct icc_node *node) > >>

[PATCH RFC] mmc: sdhci: Don't get card-detect without preemption

For a controller with SDHCI_QUIRK_NO_CARD_NO_RESET, there are several conditions where sdhci_do_reset is called under a spinlock with interrupts disabled. The card detect is often a GPIO, which might sleep. Avoid asking for the card detect status if interrupts are disabled to prevent a warning

Re: [PATCH v5 2/2] drivers: soc: Add LLCC driver

Hi Rishabh, On Mon, Apr 23, 2018 at 4:11 PM Rishabh Bhatnagar wrote: > LLCC (Last Level Cache Controller) provides additional cache memory > in the system. LLCC is partitioned into multiple slices and each > slice gets its own priority, size, ID and other config

Re: linux-next: build failure after merge of the qcom tree

On Wed, Apr 25, 2018 at 9:54 PM Stephen Rothwell <s...@canb.auug.org.au> wrote: > Hi Evan, > On Thu, 26 Apr 2018 03:39:25 +0000 Evan Green <evgr...@chromium.org> wrote: > > > > Guenter and I had a fix for compile test here, which had failures that > > look

Re: linux-next: build failure after merge of the qcom tree

On Wed, Apr 25, 2018 at 3:42 PM Stephen Rothwell wrote: > Hi Andy, > After merging the qcom tree, today's linux-next build (x86_64 > allmodconfig) failed like this: > ERROR: "geni_se_select_mode" [drivers/tty/serial/qcom_geni_serial.ko] undefined! > ERROR: "geni_se_init"

Re: [PATCH 1/2] arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP

Hi Rajendra, On Thu, Jan 25, 2018 at 8:32 AM, Rajendra Nayak wrote: > Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files > > Signed-off-by: Rajendra Nayak > --- > arch/arm64/boot/dts/qcom/Makefile| 1 + >

Re: [PATCH v2 09/10] drivers: qcom: rpmh: add support for batch RPMH request

Hello Lina, On Thu, Feb 15, 2018 at 9:35 AM, Lina Iyer wrote: > Platform drivers need make a lot of resource state requests at the same > time, say, at the start or end of an usecase. It can be quite > inefficient to send each request separately. Instead they can give the >

Re: [PATCH v2 07/10] drivers: qcom: rpmh: cache sleep/wake state requests

Hi Lina, On Thu, Feb 15, 2018 at 9:35 AM, Lina Iyer wrote: > Active state requests are sent immediately to the mailbox controller, > while sleep and wake state requests are cached in this driver to avoid > taxing the mailbox controller repeatedly. The cached values will be

Re: [PATCH v2 01/10] drivers: qcom: rpmh-rsc: add RPMH controller for QCOM SoCs

Hi Lina, On Thu, Feb 15, 2018 at 9:34 AM, Lina Iyer wrote: > Add controller driver for QCOM SoCs that have hardware based shared > resource management. The hardware IP known as RSC (Resource State > Coordinator) houses multiple Direct Resource Voter (DRV) for different >

Re: [PATCH v2 09/10] drivers: qcom: rpmh: add support for batch RPMH request

Hi Lina, On Thu, Feb 22, 2018 at 9:04 AM, Lina Iyer <il...@codeaurora.org> wrote: > On Wed, Feb 21 2018 at 23:25 +0000, Evan Green wrote: >> >> Hello Lina, >> >> On Thu, Feb 15, 2018 at 9:35 AM, Lina Iyer <il...@codeaurora.org> wrote: >>> >&g

Re: [PATCH v2 07/10] drivers: qcom: rpmh: cache sleep/wake state requests

Hi Lina, On Thu, Feb 22, 2018 at 8:58 AM, Lina Iyer <il...@codeaurora.org> wrote: > On Wed, Feb 21 2018 at 22:07 +0000, Evan Green wrote: >> >> Hi Lina, >> >> On Thu, Feb 15, 2018 at 9:35 AM, Lina Iyer <il...@codeaurora.org> wrote: > > [...] >

Re: [PATCH v2 05/10] drivers: qcom: rpmh-rsc: write sleep/wake requests to TCS

Hello Lina, On Thu, Feb 15, 2018 at 9:35 AM, Lina Iyer wrote: > Sleep and wake requests are sent when the application processor > subsystem of the SoC is entering deep sleep states like in suspend. > These requests help lower the system power requirements when the >

Re: [PATCH v7 2/2] cpufreq: qcom-hw: Add support for QCOM cpufreq HW driver

Hi Taniya, On Tue, Jul 24, 2018 at 3:44 AM Taniya Das wrote: > > The CPUfreq HW present in some QCOM chipsets offloads the steps necessary > for changing the frequency of CPUs. The driver implements the cpufreq > driver interface for this hardware engine. > > Signed-off-by: Saravana Kannan >

Re: [PATCH v7 6/8] interconnect: qcom: Add msm8916 interconnect provider driver

> drivers/interconnect/qcom/Kconfig | 9 + > drivers/interconnect/qcom/Makefile | 2 + > drivers/interconnect/qcom/msm8916.c | 510 > 5 files changed, 527 insertions(+) > create mode 100644 drivers/interconnect/qcom/msm8916.c > Reviewed-by: Evan Green

Re: [PATCH v7 1/8] interconnect: Add generic on-chip interconnect API

/interconnect/interconnect.rst > create mode 100644 drivers/interconnect/Kconfig > create mode 100644 drivers/interconnect/Makefile > create mode 100644 drivers/interconnect/core.c > create mode 100644 include/linux/interconnect-provider.h > create mode 100644 include/linux/interconnect.h > Thanks Georgi. This looks great! Reviewed-by: Evan Green

Re: [RFC PATCH v2 1/2] interconnect: qcom: Add sdm845 interconnect provider driver

Hi David, On Thu, Jul 26, 2018 at 4:30 PM David Dai wrote: > > Introduce Qualcomm SDM845 specific provider driver using the > interconnect framework. > > Signed-off-by: David Dai > --- > .../bindings/interconnect/qcom-sdm845.txt | 22 + > drivers/interconnect/qcom/Kconfig

Re: [PATCH v8 3/5] phy: Add QMP phy based UFS phy support for sdm845

On Tue, Jul 31, 2018 at 3:09 AM Can Guo wrote: > > Add UFS PHY support to make SDM845 UFS work with common PHY framework. > > Signed-off-by: Can Guo > --- > drivers/phy/qualcomm/phy-qcom-qmp.c | 172 > +++- > drivers/phy/qualcomm/phy-qcom-qmp.h | 15 > 2

Re: [PATCH v1 2/4] drivers: soc: Add support to register LLCC EDAC driver

On Wed, Aug 1, 2018 at 1:33 PM Venkata Narendra Kumar Gutta wrote: > > Cache error reporting controller is to detect and report single > and double bit errors on Last Level Cache Controller (LLCC) cache. > Add required support to register LLCC EDAC driver as platform driver, > from LLCC driver. >

Re: [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs

On Wed, Aug 1, 2018 at 1:34 PM Venkata Narendra Kumar Gutta wrote: > > From: Channagoud Kadabi > > Add error reporting driver for SBEs and DBEs. As of now, this driver > supports erp for Last Level Cache Controller (LLCC). This driver takes > care of dumping registers and adding config options

Re: [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs

On Fri, Aug 10, 2018 at 4:13 PM wrote: > > On 2018-08-10 10:23, Evan Green wrote: > > On Wed, Aug 1, 2018 at 1:34 PM Venkata Narendra Kumar Gutta > > wrote: > >> > >> From: Channagoud Kadabi > >> > >> Add error reporting driver for S

Re: [PATCH v7 8/8] interconnect: Allow endpoints translation via DT

erhaps most other frameworks are not quite as optional for a particular driver. Reviewed-by: Evan Green

Re: [PATCH v7 3/8] interconnect: Add debugfs support

> 1 file changed, 78 insertions(+) > Reviewed-by: Evan Green

Re: [PATCH v7 4/8] interconnect: qcom: Add RPM communication

rpm { > + interrupts = <0 168 1>; It would be nice if this interrupt example were more proper, somethine like . Other than that: Reviewed-by: Evan Green

Re: [PATCH RFC 4/4] arm64: dts: qcom: add wake up interrupts for GPIOs

On Tue, Jul 31, 2018 at 3:44 PM Lina Iyer wrote: > > GPIOs that are wakeup capable have interrupt lines that are routed to > the always-on interrupt controller (PDC) in parallel to the pinctrl. The > interrupts listed here are the wake up lines corresponding to GPIOs. > > Signed-off-by: Lina Iyer

Re: [PATCH v8 4/5] scsi: ufs: Power on phy after it is initialized

> -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project > > -- > To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Evan Green

Re: [PATCH v8 3/5] phy: Add QMP phy based UFS phy support for sdm845

On Thu, Aug 9, 2018 at 10:26 AM Vivek Gautam wrote: > > Hi Evan, > > > On 8/9/2018 3:25 AM, Evan Green wrote: > > On Tue, Jul 31, 2018 at 3:09 AM Can Guo wrote: > >> Add UFS PHY support to make SDM845 UFS work with common PHY framework. > >> > >>

Re: [PATCH v8 1/2] i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller

On Tue, Jul 31, 2018 at 12:20 PM Wolfram Sang wrote: > > On Mon, Jul 30, 2018 at 11:23:51AM -0600, Karthikeyan Ramasubramanian wrote: > > This bus driver supports the GENI based i2c hardware controller in the > > Qualcomm SOCs. The Qualcomm Generic Interface (GENI) is a programmable > > module

Re: [PATCH V9 1/2] scsi: ufs: set the device reference clock setting

On Tue, Aug 21, 2018 at 3:18 AM Sayali Lokhande wrote: > > From: Subhash Jadavani > > UFS host supplies the reference clock to UFS device and UFS device > specification allows host to provide one of the 4 frequencies (19.2 MHz, > 26 MHz, 38.4 MHz, 52 MHz) for reference clock. Host should set the

Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs

On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta wrote: > > From: Channagoud Kadabi > > Add error reporting driver for Single Bit Errors (SBEs) and Double Bit > Errors (DBEs). As of now, this driver supports erp for Last Level Cache > Controller (LLCC). This driver takes care of

Re: [PATCH v2 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC)

s/soc/qcom/llcc-slice.c | 55 > +++--- > include/linux/soc/qcom/llcc-qcom.h | 4 +-- > 2 files changed, 35 insertions(+), 24 deletions(-) > Reviewed-by: Evan Green

Re: [PATCH v2 2/4] drivers: soc: Add support to register LLCC EDAC driver

On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta wrote: > > Cache error reporting controller is to detect and report single Should be "Cache error reporting controller detects and reports single"... Other than that: Reviewed-by: Evan Green

Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs

On Thu, Aug 23, 2018 at 4:04 PM Evan Green wrote: > > On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta > wrote: > > > > From: Channagoud Kadabi Also checkpatch.pl complains a bit about this patch: WARNING: Non-standard signature: Co-develope

Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs

On Fri, Aug 24, 2018 at 11:32 AM wrote: > > On 2018-08-23 16:04, Evan Green wrote: > > On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta > > wrote: > >> > >> From: Channagoud Kadabi > >> > >> Add error reporting driver for Sin

Re: [PATCH v5 2/2] cpufreq: qcom-hw: Add support for QCOM cpufreq HW driver

Hi Taniya, On Thu, Jul 12, 2018 at 11:06 AM Taniya Das wrote: > > The CPUfreq HW present in some QCOM chipsets offloads the steps necessary > for changing the frequency of CPUs. The driver implements the cpufreq > driver interface for this hardware engine. > > Signed-off-by: Saravana Kannan >

[PATCH v3] scsi: ufs: Make sysfs attributes writable

This change makes the UFS controller's sysfs attributes writable, which will enable users to modify attributes. This can be useful during factory provisioning for setting up critical attributes like the reference clock frequency. Signed-off-by: Evan Green --- Configfs was determined

Re: [PATCH v7 1/4] phy: Update PHY power control sequence

t; > Signed-off-by: Can Guo > > --- > > drivers/phy/qualcomm/phy-qcom-qmp.c | 19 --- > > 1 file changed, 12 insertions(+), 7 deletions(-) > > Reviewed-by: Evan Green

Re: [PATCH] i2c: i2c-qcom-geni: Fix suspend clock handling

On Fri, Jul 13, 2018 at 3:21 PM Karthik Ramasubramanian wrote: > > > > On 7/9/2018 5:49 PM, Evan Green wrote: > > pm_runtime_suspended can return 0 even if the last runtime power > > management function called in the device was a suspend call. This > > trips up the

[PATCH] i2c: i2c-qcom-geni: Fix suspend clock handling

+0xd4/0xf8 [ 68.621014] [] kobj_attr_store+0x18/0x28 [ 68.626672] [] sysfs_kf_write+0x5c/0x68 [ 68.632240] [] kernfs_fop_write+0x174/0x1b8 [ 68.638177] [] __vfs_write+0x58/0x160 [ 68.643567] [] vfs_write+0xcc/0x184 [ 68.648780] [] SyS_write+0x64/0xb4 Signed-off-by: Evan Green

Re: [PATCH] pinctrl: msm: Pass along set_wake failures

On Mon, Jul 9, 2018 at 10:27 AM Bjorn Andersson wrote: > > Sorry for not getting back to you in a timely manner Evan, I wanted to > read up more on the details of how this is supposed to work. I still > haven't done so, but here's my concern: > > When we power down the SoC we're no longer

Re: [PATCH v6 1/8] interconnect: Add generic on-chip interconnect API

Ahoy Georgi! On Mon, Jul 9, 2018 at 8:51 AM Georgi Djakov wrote: > > This patch introduces a new API to get requirements and configure the > interconnect buses across the entire chipset to fit with the current > demand. > > The API is using a consumer/provider-based model, where the providers are

Re: [PATCH v6 6/8] interconnect: qcom: Add msm8916 interconnect provider driver

On Mon, Jul 9, 2018 at 8:51 AM Georgi Djakov wrote: > > Add driver for the Qualcomm interconnect buses found in msm8916 based > platforms. > > Signed-off-by: Georgi Djakov > --- > drivers/interconnect/Kconfig| 5 + > drivers/interconnect/Makefile | 1 + >

Re: [PATCH v6 4/8] interconnect: qcom: Add RPM communication

On Mon, Jul 9, 2018 at 8:51 AM Georgi Djakov wrote: > > On some Qualcomm SoCs, there is a remote processor, which controls some of > the Network-On-Chip interconnect resources. Other CPUs express their needs > by communicating with this processor. Add a driver to handle communication > with this

Re: [PATCH v6 7/8] dt-bindings: Introduce interconnect consumers bindings

On Mon, Jul 9, 2018 at 8:51 AM Georgi Djakov wrote: > > Add documentation for the interconnect consumer bindings, that will allow > to link a device node (consumer) to its interconnect controller hardware. > > Tha aim is to enable drivers to request a framework API to configure an > interconnect

Re: [PATCH] pinctrl: msm: Pass along set_wake failures

On Tue, Jul 10, 2018 at 1:38 PM Lina Iyer wrote: > > On Tue, Jul 10 2018 at 12:53 -0600, Evan Green wrote: > >On Mon, Jul 9, 2018 at 10:27 AM Bjorn Andersson > > wrote: > >> > >> Sorry for not getting back to you in a timely manner Evan, I wanted to >

Re: [PATCH 1/2] clk: qcom: clk-rpmh: Add QCOM RPMh clock driver

On Thu, Apr 5, 2018 at 4:17 PM Stephen Boyd wrote: > Quoting Taniya Das (2018-04-02 03:33:26) > > > > > > > >> + > > >> +#include "common.h" > > >> +#include "clk-regmap.h" > > >> + > > >> +#define CLK_RPMH_ARC_EN_OFFSET 0 > > >> +#define CLK_RPMH_VRM_EN_OFFSET 4 > > >>

Re: [PATCH v4 1/2] Documentation: Documentation for qcom, llcc

id of the client. > +For Example: > + venus { > + cache-slice-names = "vidsc0", "vidsc1"; > + cache-slices = < VIDSC0_ID>, < VIDSC1_ID>; My git complains about some whitespace weirdness on the line above. Other than that: Reviewed-by: Evan Green <evgr...@chromium.org> -Evan

Re: [PATCH v4 2/2] drivers: soc: Add LLCC driver

Hi Rishabh, On Tue, Apr 10, 2018 at 1:09 PM Rishabh Bhatnagar wrote: > LLCC (Last Level Cache Controller) provides additional cache memory > in the system. LLCC is partitioned into multiple slices and each > slice gets its own priority, size, ID and other config

[PATCH] clk: qcom: Base rcg parent rate off plan frequency

calculations is incorrect. For instance, if 150MHz was requested, but 200MHz was the match found, and that plan had a pre_div of 3, then the parent should be set to 600MHz, not 450MHz. Signed-off-by: Evan Green <evgr...@chromium.org> --- drivers/clk/qcom/clk-rcg2.c | 1 + 1 file changed, 1 ins

Re: [PATCH v7 [RESEND] 2/2] dt-bindings: introduce Command DB for QCOM SoCs

t to be called 'memory@85fe' because we prefer > generic node names. Another nit: the cmd-db region seems to need "no-map" to make the example actually work. Reviewed-by: Evan Green <evgr...@chromium.org> -Evan

Re: [PATCH v4 2/2] drivers: soc: Add LLCC driver

On Fri, Apr 13, 2018 at 4:08 PM <risha...@codeaurora.org> wrote: > On 2018-04-12 15:02, Evan Green wrote: > > Hi Rishabh, > > > > On Tue, Apr 10, 2018 at 1:09 PM Rishabh Bhatnagar > > <risha...@codeaurora.org> > > wrote: > > > >> LLCC (L

Re: [PATCH] soc: qcom: cmd-db: Make endian-agnostic

that we compare > the ids with a memcmp() because we already pad out the string 'id' field > to exactly 8 bytes with the strncpy() onto the stack. > Cc: Mahesh Sivasubramanian <msiva...@codeaurora.org> > Cc: Lina Iyer <il...@codeaurora.org> > Cc: Bjorn Andersson <bjorn

[PATCH] soc: Unconditionally include qcom Makefile

ed! ERROR: "geni_se_resources_off" [drivers/i2c/busses/i2c-qcom-geni.ko] undefined! ERROR: "geni_se_resources_on" [drivers/i2c/busses/i2c-qcom-geni.ko] undefined! make[1]: *** [scripts/Makefile.modpost:92: __modpost] Error 1 make: *** [Makefile:1237: modules] Error 2 [1] https://

Re: [PATCH v3 6/6] phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845

gau...@codeaurora.org> > --- > drivers/phy/qualcomm/phy-qcom-qusb2.c | 39 +++ > 1 file changed, 39 insertions(+) Reviewed-by: Evan Green <evgr...@chromium.org>

Re: [PATCH v3 2/6] phy: qcom-qusb2: Fix crash if nvmem cell not specified

ers/phy/qualcomm/phy-qcom-qusb2.c | 4 ++++ > 1 file changed, 4 insertions(+) Reviewed-by: Evan Green <evgr...@chromium.org>

Re: [PATCH v3 2/2] drivers: soc: Add LLCC driver

Hi Rishabh, On Tue, Mar 27, 2018 at 11:54 AM Rishabh Bhatnagar wrote: > LLCC (Last Level Cache Controller) provides additional cache memory > in the system. LLCC is partitioned into muliple slices and each > slice getting its own priority, size, ID and other config

Re: [PATCH v4 2/7] phy: qcom-qmp: Enable pipe_clk before PHY initialization

Hi Manu, On Thu, Mar 29, 2018 at 4:06 AM Manu Gautam wrote: > QMP PHY for USB/PCIE requires pipe_clk for locking of > retime buffers at the pipe interface. Driver checks for > PHY_STATUS without enabling pipe_clk due to which > phy_init() fails with initialization

Re: [PATCH 1/2] clk: qcom: clk-rpmh: Add QCOM RPMh clock driver

Hi Taniya, On Wed, Mar 28, 2018 at 11:19 PM Taniya Das wrote: > From: Amit Nischal > Add the RPMh clock driver to control the RPMh managed clock resources on > some of the Qualcomm Technologies, Inc. SoCs. > Signed-off-by: David Collins

Re: [PATCH 1/2] clk: qcom: clk-rpmh: Add QCOM RPMh clock driver

Hi Taniya, On Mon, Apr 2, 2018 at 3:33 AM Taniya Das <t...@codeaurora.org> wrote: > Hello Evan, > Thanks for the review comments. > On 3/30/2018 3:19 AM, Evan Green wrote: > > Hi Taniya, > > > > On Wed, Mar 28, 2018 at 11:19 PM Taniya Das <t...@codeau

Re: [PATCH 4/6] phy: qcom-qmp: Add QMP V3 USB3 UNI PHY support for sdm845

Hi Manu, On Fri, Mar 16, 2018 at 2:46 AM Manu Gautam wrote: > QMP V3 UNI PHY is a single lane USB3 PHY without support > for DisplayPort (DP). > Main difference from DP combo QMPv3 PHY is that UNI PHY > doesn't have dual RX/TX lanes and no separate DP_COM > block for

Re: [PATCH v4 07/10] drivers: qcom: rpmh: cache sleep/wake state requests

- Improve comments > --- > drivers/soc/qcom/rpmh.c | 203 +++- > include/soc/qcom/rpmh.h | 10 +++ > 2 files changed, 212 insertions(+), 1 deletion(-) Reviewed-by: Evan Green <evgr...@chromium.org>

Re: [PATCH v4 09/10] drivers: qcom: rpmh: add support for batch RPMH request

+++- > include/soc/qcom/rpmh.h | 8 +++ > 2 files changed, 162 insertions(+), 2 deletions(-) Reviewed-by: Evan Green <evgr...@chromium.org>

Re: [PATCH v4 05/10] drivers: qcom: rpmh-rsc: write sleep/wake requests to TCS

+++ >2 files changed, 128 insertions(+), 1 deletion(-) Reviewed-by: Evan Green <evgr...@chromium.org>

Re: [PATCH 4/6] phy: qcom-qmp: Add QMP V3 USB3 UNI PHY support for sdm845

On Tue, Mar 20, 2018 at 12:00 AM Manu Gautam <mgau...@codeaurora.org> wrote: > Hi, > On 3/19/2018 11:21 PM, Evan Green wrote: > > Hi Manu, > > > > On Fri, Mar 16, 2018 at 2:46 AM Manu Gautam <mgau...@codeaurora.org> wrote: > [snip] > >> inde

Re: [PATCH v3 07/10] drivers: qcom: rpmh: cache sleep/wake state requests

Hi Lina, On Fri, Mar 2, 2018 at 8:43 AM, Lina Iyer wrote: > Active state requests are sent immediately to the mailbox controller, > while sleep and wake state requests are cached in this driver to avoid > taxing the mailbox controller repeatedly. The cached values will be

[PATCH 1/2] arm64: dts: qcom: sdm845: add UFS controller

This change adds the UFS controller and PHY to SDM845. Signed-off-by: Evan Green Signed-off-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 66 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64

[PATCH 0/2] arm64: dts: qcom: sdm845: Add UFS DT nodes

. Can Guo (1): arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp Evan Green (1): arm64: dts: qcom: sdm845: add UFS controller arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 11 + arch/arm64/boot/dts/qcom/sdm845.dtsi| 66 + 2 files changed, 77 insertions

[PATCH 2/2] arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp

From: Can Guo This change enables the UFS host controller and PHY on sdm845-mtp. Signed-off-by: Can Guo Signed-off-by: Evan Green --- I was unable to test this on an MTP, if somebody could give this a try I would be grateful. This applies atop agross/for-next, since it needs the regulators

Re: [PATCH V2 2/2] mmc: sdhci-msm: Re-initialize DLL if MCLK is gated dynamically

On Mon, Oct 8, 2018 at 6:26 AM Veerabhadrarao Badiganti wrote: > > On few SDHCI-MSM controllers, the host controller's clock tuning > circuit may go out of sync if controller clocks are gated which > eventually will result in data CRC, command CRC/timeout errors. > To overcome this h/w

Re: [PATCH V3 1/3] mmc: sdhci: Allow platform controlled voltage switching

On Mon, Oct 8, 2018 at 6:22 AM Veerabhadrarao Badiganti wrote: > > From: Vijay Viswanath > > Some controllers can have internal mechanism to inform the SW that it > is ready for voltage switching. For such controllers, changing voltage > before the HW is ready can result in various issues. > >

[PATCH] clk: qcom: Remove unused arrays in SDM845 GCC

This change removes a parent map and parent name array that appear to be completely unreferenced. Signed-off-by: Evan Green --- drivers/clk/qcom/gcc-sdm845.c | 16 1 file changed, 16 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index

Re: [PATCH] clk: qcom: Remove unused arrays in SDM845 GCC

On Thu, Oct 18, 2018 at 3:29 PM Stephen Boyd wrote: > > Quoting Evan Green (2018-10-18 15:03:50) > > This change removes a parent map and parent name array that > > appear to be completely unreferenced. > > > > Signed-off-by: Evan Green > > --- > > Appli

[PATCH v2 5/5] arm64: dts: qcom: sdm845: Add USB PHY lane two

This change adds the second lane registers for the USB PHY, now that the QMP phy bindings have been updated. This way the driver can stop reaching beyond its register region to get at the second lane. Signed-off-by: Evan Green --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++-- 1 file

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