Re: [PATCH 00/15] Adding GAUDI NIC code to habanalabs driver
On 9/10/2020 1:32 PM, Oded Gabbay wrote: On Thu, Sep 10, 2020 at 11:28 PM Jakub Kicinski wrote: On Thu, 10 Sep 2020 23:16:22 +0300 Oded Gabbay wrote: On Thu, Sep 10, 2020 at 11:01 PM Jakub Kicinski wrote: On Thu, 10 Sep 2020 19:11:11 +0300 Oded Gabbay wrote: create mode 100644 drivers/misc/habanalabs/gaudi/gaudi_nic.c create mode 100644 drivers/misc/habanalabs/gaudi/gaudi_nic.h create mode 100644 drivers/misc/habanalabs/gaudi/gaudi_nic_dcbnl.c create mode 100644 drivers/misc/habanalabs/gaudi/gaudi_nic_debugfs.c create mode 100644 drivers/misc/habanalabs/gaudi/gaudi_nic_ethtool.c create mode 100644 drivers/misc/habanalabs/gaudi/gaudi_phy.c create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qpc0_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qpc0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qpc1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_rxb_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_rxe0_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_rxe0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_rxe1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_stat_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_tmr_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_txe0_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_txe0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_txe1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_txs0_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_txs0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_txs1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic1_qm0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic1_qm1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic2_qm0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic2_qm1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic3_qm0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic3_qm1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic4_qm0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic4_qm1_regs.h create mode 100644 drivers/misc/habanalabs/include/hw_ip/nic/nic_general.h The relevant code needs to live under drivers/net/(ethernet/). For one thing our automation won't trigger for drivers in random (/misc) part of the tree. Can you please elaborate on how to do this with a single driver that is already in misc ? As I mentioned in the cover letter, we are not developing a stand-alone NIC. We have a deep-learning accelerator with a NIC interface. Therefore, we don't have a separate PCI physical function for the NIC and I can't have a second driver registering to it. Is it not possible to move the files and still build them into a single module? hmm... I actually didn't try that as I thought it will be very strange and I'm not familiar with other drivers that build as a single ko but have files spread out in different subsystems. I don't feel it is a better option than what we did here. Will I need to split pull requests to different subsystem maintainers ? For the same driver ? Sounds to me this is not going to fly. Not necessarily, you can post your patches to all relevant lists and seek maintainer review/acked-by tags from the relevant maintainers. This is not unheard of with mlx5 for instance. Have you considered using notifiers to get your NIC driver registered while the NIC code lives in a different module? -- Florian
Re: [PATCH] PCI: Don't use Printk in raw_spinlocks
On 9/10/2020 12:20 PM, Bjorn Helgaas wrote:
On Thu, Sep 10, 2020 at 11:50:07AM -0700, Florian Fainelli wrote:
On 9/10/2020 11:46 AM, Bjorn Helgaas wrote:
On Thu, Sep 10, 2020 at 08:21:06AM -0600, Rob Herring wrote:
On Wed, Sep 9, 2020 at 8:07 PM Bjorn Helgaas wrote:
[+cc Mark, Florian, Rob, Scott]
On Sat, Aug 01, 2020 at 09:25:49AM +0800, Xingxing Su wrote:
Do not use printk in raw_spinlocks,
it will cause BUG: Invalid wait context.
The trace reported by lockdep follows.
[2.986113] =
[2.986115] [ BUG: Invalid wait context ]
[2.986116] 5.8.0-rc1+ #11 Not tainted
[2.986118] -
[2.986120] swapper/0/1 is trying to lock:
[2.986122] 80f5ddd8 (console_owner){}-{3:3}, at:
console_unlock+0x284/0x820
[2.986130] other info that might help us debug this:
[2.986132] context-{5:5}
[2.986134] 3 locks held by swapper/0/1:
[2.986135] #0: 9807fa03c990 (>mutex){}-{0:0}, at:
device_driver_attach+0x28/0x90
[2.986144] #1: 80fb83a8 (pci_lock){}-{2:2}, at:
pci_bus_write_config_word+0x60/0xb8
[2.986152] #2: 80f5ded0 (console_lock){+.+.}-{0:0}, at:
vprintk_emit+0x1b0/0x3b8
[2.986161] stack backtrace:
[2.986163] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.8.0-rc1+ #11
[2.986164] Stack : 1d67 9800030be9b0 0001
7b2aba74f6c4785b
[2.986172] 7b2aba74f6c4785b 9807f89cb438
80e7dc80
[2.986181] 0001 000a 0001
0001
[2.986189] 80f4e156 fffd 80cc2d98
f800
[2.986197] 2400 80f4
[2.986205] 9500cce0 80f5
81546318
[2.986213] 81c4c3c0 0018 bc00
[2.986221] 8134 9807f89c8000 9807f89cb430
9807f8a0
[2.986229] 806be568
[2.986237] 80211c1c
7b2aba74f6c4785b
[2.986245] ...
[2.986250] Call Trace:
[2.986251] [] show_stack+0x9c/0x130
[2.986253] [] dump_stack+0xe8/0x150
[2.986255] [] __lock_acquire+0x570/0x3250
[2.986257] [] lock_acquire+0x118/0x558
[2.986259] [] console_unlock+0x2e4/0x820
[2.986261] [] vprintk_emit+0x1c0/0x3b8
[2.986263] [] dev_vprintk_emit+0x1c8/0x210
[2.986265] [] dev_printk_emit+0x3c/0x60
[2.986267] [] _dev_warn+0x5c/0x80
[2.986269] [] pci_generic_config_write32+0x154/0x160
[2.986271] [] pci_bus_write_config_word+0x84/0xb8
[2.986273] [] pci_setup_device+0x22c/0x768
[2.986275] [] pci_scan_single_device+0xc8/0x100
[2.986277] [] pci_scan_slot+0xb0/0x178
[2.986279] [] pci_scan_child_bus_extend+0x5c/0x370
[2.986281] [] pci_scan_root_bus_bridge+0x6c/0xf0
[2.986283] [] pci_host_probe+0x1c/0xd8
[2.986285] [] platform_drv_probe+0x54/0xb8
[2.986287] [] really_probe+0x130/0x388
[2.986289] [] driver_probe_device+0x64/0xd8
[2.986291] [] device_driver_attach+0x84/0x90
[2.986293] [] __driver_attach+0xc8/0x128
[2.986295] [] bus_for_each_dev+0x74/0xd8
[2.986297] [] bus_add_driver+0x170/0x250
[2.986299] [] driver_register+0x84/0x150
[2.986301] [] do_one_initcall+0x98/0x458
[2.986303] [] kernel_init_freeable+0x2c0/0x36c
[2.986305] [] kernel_init+0x10/0x128
[2.986307] [] ret_from_kernel_thread+0x14/0x1c
Signed-off-by: Xingxing Su
---
drivers/pci/access.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 79c4a2e..b3fc164 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -160,9 +160,6 @@ int pci_generic_config_write32(struct pci_bus *bus,
unsigned int devfn,
* write happen to have any RW1C (write-one-to-clear) bits set, we
* just inadvertently cleared something we shouldn't have.
*/
- dev_warn_ratelimited(>dev, "%d-byte config write to %04x:%02x:%02x.%d
offset %#x may corrupt adjacent RW1C bits\n",
- size, pci_domain_nr(bus), bus->number,
- PCI_SLOT(devfn), PCI_FUNC(devfn), where);
We just changed this printk (see [1]), but I think we still have this
lockdep problem even after Mark's change. So I guess we need another
think about this.
Maybe we can print something when registering pci_ops that use
pci_generic_config_write32()?
That was my suggestion, but as Mark pointed out that doesn't work if
pci_generic_config_write32 is wrapped (which is 4 out of 8 cases).
Also, 3 of the cases are only for the root bus (bridge). Are 32-bit
writes to a bridge going to cause problems? For xgene, interestingly,
with DT _write32 is needed, but for ACPI it is no
Re: [PATCH v11 04/11] PCI: brcmstb: Add suspend and resume pm_ops
On 9/10/2020 12:05 PM, Jim Quinlan wrote:
On Thu, Sep 10, 2020 at 2:50 PM Rob Herring wrote:
On Thu, Sep 10, 2020 at 10:42 AM Jim Quinlan wrote:
On Thu, Sep 10, 2020 at 11:56 AM Rob Herring wrote:
On Mon, Aug 24, 2020 at 03:30:17PM -0400, Jim Quinlan wrote:
From: Jim Quinlan
Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
and resume. Now the PCIe driver may do so as well.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 47 +++
1 file changed, 47 insertions(+)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller/pcie-brcmstb.c
index c2b3d2946a36..3d588ab7a6dd 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -978,6 +978,47 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
brcm_pcie_bridge_sw_init_set(pcie, 1);
}
+static int brcm_pcie_suspend(struct device *dev)
+{
+ struct brcm_pcie *pcie = dev_get_drvdata(dev);
+
+ brcm_pcie_turn_off(pcie);
+ clk_disable_unprepare(pcie->clk);
+
+ return 0;
+}
+
+static int brcm_pcie_resume(struct device *dev)
+{
+ struct brcm_pcie *pcie = dev_get_drvdata(dev);
+ void __iomem *base;
+ u32 tmp;
+ int ret;
+
+ base = pcie->base;
+ clk_prepare_enable(pcie->clk);
+
+ /* Take bridge out of reset so we can access the SERDES reg */
+ brcm_pcie_bridge_sw_init_set(pcie, 0);
+
+ /* SERDES_IDDQ = 0 */
+ tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
+ u32p_replace_bits(, 0,
PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
+ writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
+
+ /* wait for serdes to be stable */
+ udelay(100);
Really needs to be a spinloop?
+
+ ret = brcm_pcie_setup(pcie);
+ if (ret)
+ return ret;
+
+ if (pcie->msi)
+ brcm_msi_set_regs(pcie->msi);
+
+ return 0;
+}
+
static void __brcm_pcie_remove(struct brcm_pcie *pcie)
{
brcm_msi_remove(pcie);
@@ -1087,12 +1128,18 @@ static int brcm_pcie_probe(struct platform_device *pdev)
MODULE_DEVICE_TABLE(of, brcm_pcie_match);
+static const struct dev_pm_ops brcm_pcie_pm_ops = {
+ .suspend_noirq = brcm_pcie_suspend,
+ .resume_noirq = brcm_pcie_resume,
Why do you need interrupts disabled? There's 39 cases of .suspend_noirq
and 1352 of .suspend in the tree.
I will test switching this to suspend_late/resume_early.
Why not just the 'regular' flavor suspend/resume?
Rob
We must have our PCIe driver suspend last and resume first because our
current driver turns off/on the power for the EPs. Note that this
code isn't in the driver as we are still figuring out a way to make it
upstreamable.
The suspend/resume ordering should be guaranteed by the Linux device
driver model though if not, this is a bug that ought to be fixed. The
PCI bridge sits at the top of the pci_device list and all EPs should be
child devices, so the suspend order should be from EPs down to the
bridge, and the resume the converse.
--
Florian
Re: [PATCH v11 04/11] PCI: brcmstb: Add suspend and resume pm_ops
On 9/10/2020 11:50 AM, Rob Herring wrote:
On Thu, Sep 10, 2020 at 10:42 AM Jim Quinlan wrote:
On Thu, Sep 10, 2020 at 11:56 AM Rob Herring wrote:
On Mon, Aug 24, 2020 at 03:30:17PM -0400, Jim Quinlan wrote:
From: Jim Quinlan
Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
and resume. Now the PCIe driver may do so as well.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 47 +++
1 file changed, 47 insertions(+)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller/pcie-brcmstb.c
index c2b3d2946a36..3d588ab7a6dd 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -978,6 +978,47 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
brcm_pcie_bridge_sw_init_set(pcie, 1);
}
+static int brcm_pcie_suspend(struct device *dev)
+{
+ struct brcm_pcie *pcie = dev_get_drvdata(dev);
+
+ brcm_pcie_turn_off(pcie);
+ clk_disable_unprepare(pcie->clk);
+
+ return 0;
+}
+
+static int brcm_pcie_resume(struct device *dev)
+{
+ struct brcm_pcie *pcie = dev_get_drvdata(dev);
+ void __iomem *base;
+ u32 tmp;
+ int ret;
+
+ base = pcie->base;
+ clk_prepare_enable(pcie->clk);
+
+ /* Take bridge out of reset so we can access the SERDES reg */
+ brcm_pcie_bridge_sw_init_set(pcie, 0);
+
+ /* SERDES_IDDQ = 0 */
+ tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
+ u32p_replace_bits(, 0,
PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
+ writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
+
+ /* wait for serdes to be stable */
+ udelay(100);
Really needs to be a spinloop?
+
+ ret = brcm_pcie_setup(pcie);
+ if (ret)
+ return ret;
+
+ if (pcie->msi)
+ brcm_msi_set_regs(pcie->msi);
+
+ return 0;
+}
+
static void __brcm_pcie_remove(struct brcm_pcie *pcie)
{
brcm_msi_remove(pcie);
@@ -1087,12 +1128,18 @@ static int brcm_pcie_probe(struct platform_device *pdev)
MODULE_DEVICE_TABLE(of, brcm_pcie_match);
+static const struct dev_pm_ops brcm_pcie_pm_ops = {
+ .suspend_noirq = brcm_pcie_suspend,
+ .resume_noirq = brcm_pcie_resume,
Why do you need interrupts disabled? There's 39 cases of .suspend_noirq
and 1352 of .suspend in the tree.
I will test switching this to suspend_late/resume_early.
Why not just the 'regular' flavor suspend/resume?
We must have inherited this from when the driver was not a
platform_device back in our 3.14 downstream kernel and we used
syscore_ops to do the system suspend/resume.
Later on, we sort of mechanically made those _noirq() to preserve the
semantics of syscore_ops, but in hindsight it should not be necessary,
the regular suspsend/resume should work and the device driver model
ordering between parent/child should take care of the bridge being
suspended last within the PCI bus type that is.
--
Florian
Re: [PATCH] PCI: Don't use Printk in raw_spinlocks
On 9/10/2020 11:46 AM, Bjorn Helgaas wrote:
On Thu, Sep 10, 2020 at 08:21:06AM -0600, Rob Herring wrote:
On Wed, Sep 9, 2020 at 8:07 PM Bjorn Helgaas wrote:
[+cc Mark, Florian, Rob, Scott]
On Sat, Aug 01, 2020 at 09:25:49AM +0800, Xingxing Su wrote:
Do not use printk in raw_spinlocks,
it will cause BUG: Invalid wait context.
The trace reported by lockdep follows.
[2.986113] =
[2.986115] [ BUG: Invalid wait context ]
[2.986116] 5.8.0-rc1+ #11 Not tainted
[2.986118] -
[2.986120] swapper/0/1 is trying to lock:
[2.986122] 80f5ddd8 (console_owner){}-{3:3}, at:
console_unlock+0x284/0x820
[2.986130] other info that might help us debug this:
[2.986132] context-{5:5}
[2.986134] 3 locks held by swapper/0/1:
[2.986135] #0: 9807fa03c990 (>mutex){}-{0:0}, at:
device_driver_attach+0x28/0x90
[2.986144] #1: 80fb83a8 (pci_lock){}-{2:2}, at:
pci_bus_write_config_word+0x60/0xb8
[2.986152] #2: 80f5ded0 (console_lock){+.+.}-{0:0}, at:
vprintk_emit+0x1b0/0x3b8
[2.986161] stack backtrace:
[2.986163] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.8.0-rc1+ #11
[2.986164] Stack : 1d67 9800030be9b0 0001
7b2aba74f6c4785b
[2.986172] 7b2aba74f6c4785b 9807f89cb438
80e7dc80
[2.986181] 0001 000a 0001
0001
[2.986189] 80f4e156 fffd 80cc2d98
f800
[2.986197] 2400 80f4
[2.986205] 9500cce0 80f5
81546318
[2.986213] 81c4c3c0 0018 bc00
[2.986221] 8134 9807f89c8000 9807f89cb430
9807f8a0
[2.986229] 806be568
[2.986237] 80211c1c
7b2aba74f6c4785b
[2.986245] ...
[2.986250] Call Trace:
[2.986251] [] show_stack+0x9c/0x130
[2.986253] [] dump_stack+0xe8/0x150
[2.986255] [] __lock_acquire+0x570/0x3250
[2.986257] [] lock_acquire+0x118/0x558
[2.986259] [] console_unlock+0x2e4/0x820
[2.986261] [] vprintk_emit+0x1c0/0x3b8
[2.986263] [] dev_vprintk_emit+0x1c8/0x210
[2.986265] [] dev_printk_emit+0x3c/0x60
[2.986267] [] _dev_warn+0x5c/0x80
[2.986269] [] pci_generic_config_write32+0x154/0x160
[2.986271] [] pci_bus_write_config_word+0x84/0xb8
[2.986273] [] pci_setup_device+0x22c/0x768
[2.986275] [] pci_scan_single_device+0xc8/0x100
[2.986277] [] pci_scan_slot+0xb0/0x178
[2.986279] [] pci_scan_child_bus_extend+0x5c/0x370
[2.986281] [] pci_scan_root_bus_bridge+0x6c/0xf0
[2.986283] [] pci_host_probe+0x1c/0xd8
[2.986285] [] platform_drv_probe+0x54/0xb8
[2.986287] [] really_probe+0x130/0x388
[2.986289] [] driver_probe_device+0x64/0xd8
[2.986291] [] device_driver_attach+0x84/0x90
[2.986293] [] __driver_attach+0xc8/0x128
[2.986295] [] bus_for_each_dev+0x74/0xd8
[2.986297] [] bus_add_driver+0x170/0x250
[2.986299] [] driver_register+0x84/0x150
[2.986301] [] do_one_initcall+0x98/0x458
[2.986303] [] kernel_init_freeable+0x2c0/0x36c
[2.986305] [] kernel_init+0x10/0x128
[2.986307] [] ret_from_kernel_thread+0x14/0x1c
Signed-off-by: Xingxing Su
---
drivers/pci/access.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 79c4a2e..b3fc164 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -160,9 +160,6 @@ int pci_generic_config_write32(struct pci_bus *bus,
unsigned int devfn,
* write happen to have any RW1C (write-one-to-clear) bits set, we
* just inadvertently cleared something we shouldn't have.
*/
- dev_warn_ratelimited(>dev, "%d-byte config write to %04x:%02x:%02x.%d
offset %#x may corrupt adjacent RW1C bits\n",
- size, pci_domain_nr(bus), bus->number,
- PCI_SLOT(devfn), PCI_FUNC(devfn), where);
We just changed this printk (see [1]), but I think we still have this
lockdep problem even after Mark's change. So I guess we need another
think about this.
Maybe we can print something when registering pci_ops that use
pci_generic_config_write32()?
That was my suggestion, but as Mark pointed out that doesn't work if
pci_generic_config_write32 is wrapped (which is 4 out of 8 cases).
Also, 3 of the cases are only for the root bus (bridge). Are 32-bit
writes to a bridge going to cause problems? For xgene, interestingly,
with DT _write32 is needed, but for ACPI it is not (only _read32). I
think xgene is practically dead though a few people still have
systems, but likely xgene with DT is really dead. The
Re: [PATCH v11 04/11] PCI: brcmstb: Add suspend and resume pm_ops
On 9/10/2020 8:56 AM, Rob Herring wrote:
On Mon, Aug 24, 2020 at 03:30:17PM -0400, Jim Quinlan wrote:
From: Jim Quinlan
Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
and resume. Now the PCIe driver may do so as well.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 47 +++
1 file changed, 47 insertions(+)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller/pcie-brcmstb.c
index c2b3d2946a36..3d588ab7a6dd 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -978,6 +978,47 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
brcm_pcie_bridge_sw_init_set(pcie, 1);
}
+static int brcm_pcie_suspend(struct device *dev)
+{
+ struct brcm_pcie *pcie = dev_get_drvdata(dev);
+
+ brcm_pcie_turn_off(pcie);
+ clk_disable_unprepare(pcie->clk);
+
+ return 0;
+}
+
+static int brcm_pcie_resume(struct device *dev)
+{
+ struct brcm_pcie *pcie = dev_get_drvdata(dev);
+ void __iomem *base;
+ u32 tmp;
+ int ret;
+
+ base = pcie->base;
+ clk_prepare_enable(pcie->clk);
+
+ /* Take bridge out of reset so we can access the SERDES reg */
+ brcm_pcie_bridge_sw_init_set(pcie, 0);
+
+ /* SERDES_IDDQ = 0 */
+ tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
+ u32p_replace_bits(, 0,
PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
+ writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
+
+ /* wait for serdes to be stable */
+ udelay(100);
Really needs to be a spinloop?
+
+ ret = brcm_pcie_setup(pcie);
+ if (ret)
+ return ret;
+
+ if (pcie->msi)
+ brcm_msi_set_regs(pcie->msi);
+
+ return 0;
+}
+
static void __brcm_pcie_remove(struct brcm_pcie *pcie)
{
brcm_msi_remove(pcie);
@@ -1087,12 +1128,18 @@ static int brcm_pcie_probe(struct platform_device *pdev)
MODULE_DEVICE_TABLE(of, brcm_pcie_match);
+static const struct dev_pm_ops brcm_pcie_pm_ops = {
+ .suspend_noirq = brcm_pcie_suspend,
+ .resume_noirq = brcm_pcie_resume,
Why do you need interrupts disabled? There's 39 cases of .suspend_noirq
and 1352 of .suspend in the tree.
Is doing a clk unprepare even safe in .suspend_noirq? IIRC,
prepare/unprepare can sleep.
Yes, it is safe, provided that your clock provider (clk-scmi.c in our
case) supports it, too. In our case the underlying mailbox driver has
its interrupts flagged with IRQF_NOSUSPEND such that they can still be
processed at _noirq time.
I think the rationale was to ensure that this would be done much later
after other subsystem have been made quiescent, but given the Linux
device driver model, the PCI bridge should be suspended after all
pci_device child device, so it should be safe not to use _noirq.
--
Florian
Re: [PATCH 1/4] dt-bindings: spi: Add compatible string for brcmstb SoCs
On 9/10/2020 8:25 AM, Ray Jui wrote: Add compatible string for brcmstb 7445 SoCs. Signed-off-by: Ray Jui Acked-by: Florian Fainelli -- Florian
Re: [PATCH 2/4] spi: bcm-qspi: Add compatible string for BRCMSTB 7445 SoCs
On 9/10/2020 8:25 AM, Ray Jui wrote: Add compatible string for BRCMSTB 7445 SoCs and indicate it has MSPI rev support. Signed-off-by: Ray Jui Acked-by: Florian Fainelli -- Florian
Re: [PATCH 4/4] spi: bcm-qspi: Clean up 7425, 7429, and 7435 settings
On 9/10/2020 8:25 AM, Ray Jui wrote: The Broadcom QSPI driver now falls back to no MSPI_DEV support as the default setting in the generic compatible string, explicit settings for STB chips 7425, 7429, and 7435 can be removed. Signed-off-by: Ray Jui Acked-by: Florian Fainelli -- Florian
Re: [PATCH 3/4] spi: bcm-qspi: Fix probe regression on iProc platforms
On 9/10/2020 8:25 AM, Ray Jui wrote:
iProc chips have QSPI controller that does not have the MSPI_REV
offset. Reading from that offset will cause a bus error. Fix it by
having MSPI_REV query disabled in the generic compatible string.
Fixes: 3a01f04d74ef ("spi: bcm-qspi: Handle lack of MSPI_REV offset")
Link:
https://lore.kernel.org/linux-arm-kernel/20200909211857.4144718-1-f.faine...@gmail.com/T/#u
Signed-off-by: Ray Jui
Acked-by: Florian Fainelli
--
Florian
Re: [GIT PULL 1/1] bcm2835-dt-next-2020-09-08
On 9/8/2020 11:54 AM, Nicolas Saenz Julienne wrote: Hi Florian, The following changes since commit 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5: Linux 5.9-rc1 (2020-08-16 13:04:57 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/nsaenz/linux-rpi.git tags/bcm2835-dt-next-2020-09-08 for you to fetch changes up to 4564363351e2680e55edc23c7953aebd2acb4ab7: ARM: dts: bcm2711: Enable the display pipeline (2020-09-08 18:28:23 +0200) Maxime Ripard enables vc4 on BCM2711 (RPi4), which among other things adds HDMI functionality (no 4K yet). Merged into devicetree/next, thanks Nicolas. -- Florian
Re: [PATCH 0/5] qspi binding and DTS fixes
On 8/27/2020 11:18 AM, Florian Fainelli wrote: Hi all, This patch series fixes incorrectly defined compatible strings for the Broadcom QSPI controller which resulted in the strings not being ordered from most to least compatible. We will need to apply some changes to the spi-bcm-qspi.c driver in the future to assume no revision register exist, and these patches are a preliminary step towards that goal. Series applied to devicetree/fixes, sending the PR shortly. -- Florian
Re: [PATCH 1/5] dt-bindings: spi: Fix spi-bcm-qspi compatible ordering
On 9/9/2020 1:41 PM, Rob Herring wrote:
On Thu, 27 Aug 2020 11:18:38 -0700, Florian Fainelli wrote:
The binding is currently incorrectly defining the compatible strings
from least specific to most specific instead of the converse. Re-order
them from most specific (left) to least specific (right) and fix the
examples as well.
Fixes: 5fc78f4c842a ("spi: Broadcom BRCMSTB, NSP, NS2 SoC bindings")
Signed-off-by: Florian Fainelli
---
.../bindings/spi/brcm,spi-bcm-qspi.txt | 16
1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Rob Herring
Thanks, and sorry about the nagging on IRC :)
--
Florian
[PATCH net-next v2] net: dsa: b53: Report VLAN table occupancy via devlink
We already maintain an array of VLANs used by the switch so we can
simply iterate over it to report the occupancy via devlink.
Signed-off-by: Florian Fainelli
---
Changes in v2:
- make count u64
- correct typo: s/PARMA/PARAM/
drivers/net/dsa/b53/b53_common.c | 60 ++--
drivers/net/dsa/b53/b53_priv.h | 1 +
drivers/net/dsa/bcm_sf2.c| 8 -
3 files changed, 66 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dsa/b53/b53_common.c b/drivers/net/dsa/b53/b53_common.c
index 26fcff85d881..6a5796c32721 100644
--- a/drivers/net/dsa/b53/b53_common.c
+++ b/drivers/net/dsa/b53/b53_common.c
@@ -977,6 +977,54 @@ int b53_get_sset_count(struct dsa_switch *ds, int port,
int sset)
}
EXPORT_SYMBOL(b53_get_sset_count);
+enum b53_devlink_resource_id {
+ B53_DEVLINK_PARAM_ID_VLAN_TABLE,
+};
+
+static u64 b53_devlink_vlan_table_get(void *priv)
+{
+ struct b53_device *dev = priv;
+ struct b53_vlan *vl;
+ unsigned int i;
+ u64 count = 0;
+
+ for (i = 0; i < dev->num_vlans; i++) {
+ vl = >vlans[i];
+ if (vl->members)
+ count++;
+ }
+
+ return count;
+}
+
+int b53_setup_devlink_resources(struct dsa_switch *ds)
+{
+ struct devlink_resource_size_params size_params;
+ struct b53_device *dev = ds->priv;
+ int err;
+
+ devlink_resource_size_params_init(_params, dev->num_vlans,
+ dev->num_vlans,
+ 1, DEVLINK_RESOURCE_UNIT_ENTRY);
+
+ err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
+ B53_DEVLINK_PARAM_ID_VLAN_TABLE,
+ DEVLINK_RESOURCE_ID_PARENT_TOP,
+ _params);
+ if (err)
+ goto out;
+
+ dsa_devlink_resource_occ_get_register(ds,
+ B53_DEVLINK_PARAM_ID_VLAN_TABLE,
+ b53_devlink_vlan_table_get, dev);
+
+ return 0;
+out:
+ dsa_devlink_resources_unregister(ds);
+ return err;
+}
+EXPORT_SYMBOL(b53_setup_devlink_resources);
+
static int b53_setup(struct dsa_switch *ds)
{
struct b53_device *dev = ds->priv;
@@ -992,8 +1040,10 @@ static int b53_setup(struct dsa_switch *ds)
b53_reset_mib(dev);
ret = b53_apply_config(dev);
- if (ret)
+ if (ret) {
dev_err(ds->dev, "failed to apply configuration\n");
+ return ret;
+ }
/* Configure IMP/CPU port, disable all other ports. Enabled
* ports will be configured with .port_enable
@@ -1012,7 +1062,12 @@ static int b53_setup(struct dsa_switch *ds)
*/
ds->vlan_filtering_is_global = true;
- return ret;
+ return b53_setup_devlink_resources(ds);
+}
+
+static void b53_teardown(struct dsa_switch *ds)
+{
+ dsa_devlink_resources_unregister(ds);
}
static void b53_force_link(struct b53_device *dev, int port, int link)
@@ -2141,6 +2196,7 @@ static int b53_get_max_mtu(struct dsa_switch *ds, int
port)
static const struct dsa_switch_ops b53_switch_ops = {
.get_tag_protocol = b53_get_tag_protocol,
.setup = b53_setup,
+ .teardown = b53_teardown,
.get_strings= b53_get_strings,
.get_ethtool_stats = b53_get_ethtool_stats,
.get_sset_count = b53_get_sset_count,
diff --git a/drivers/net/dsa/b53/b53_priv.h b/drivers/net/dsa/b53/b53_priv.h
index e942c60e4365..c55c0a9f1b47 100644
--- a/drivers/net/dsa/b53/b53_priv.h
+++ b/drivers/net/dsa/b53/b53_priv.h
@@ -328,6 +328,7 @@ void b53_br_set_stp_state(struct dsa_switch *ds, int port,
u8 state);
void b53_br_fast_age(struct dsa_switch *ds, int port);
int b53_br_egress_floods(struct dsa_switch *ds, int port,
bool unicast, bool multicast);
+int b53_setup_devlink_resources(struct dsa_switch *ds);
void b53_port_event(struct dsa_switch *ds, int port);
void b53_phylink_validate(struct dsa_switch *ds, int port,
unsigned long *supported,
diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
index 3263e8a0ae67..723820603107 100644
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
@@ -936,7 +936,12 @@ static int bcm_sf2_sw_setup(struct dsa_switch *ds)
b53_configure_vlan(ds);
bcm_sf2_enable_acb(ds);
- return 0;
+ return b53_setup_devlink_resources(ds);
+}
+
+static void bcm_sf2_sw_teardown(struct dsa_switch *ds)
+{
+ dsa_devlink_resources_unregister(ds);
}
/* The SWITCH_CORE register space is managed by b53 but operates on a page +
@@ -1073,6 +1078,7 @@ static int bcm_sf2_sw_get_sset_count(struct dsa_switch
*ds, int port,
static const struct dsa
[PATCH net-next] net: dsa: b53: Report VLAN table occupancy via devlink
We already maintain an array of VLANs used by the switch so we can
simply iterate over it to report the occupancy via devlink.
Signed-off-by: Florian Fainelli
---
drivers/net/dsa/b53/b53_common.c | 59 ++--
drivers/net/dsa/b53/b53_priv.h | 1 +
drivers/net/dsa/bcm_sf2.c| 8 -
3 files changed, 65 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dsa/b53/b53_common.c b/drivers/net/dsa/b53/b53_common.c
index 26fcff85d881..a1527665e817 100644
--- a/drivers/net/dsa/b53/b53_common.c
+++ b/drivers/net/dsa/b53/b53_common.c
@@ -977,6 +977,53 @@ int b53_get_sset_count(struct dsa_switch *ds, int port,
int sset)
}
EXPORT_SYMBOL(b53_get_sset_count);
+enum b53_devlink_resource_id {
+ B53_DEVLINK_PARMA_ID_VLAN_TABLE,
+};
+
+static u64 b53_devlink_vlan_table_get(void *priv)
+{
+ struct b53_device *dev = priv;
+ unsigned int i, count = 0;
+ struct b53_vlan *vl;
+
+ for (i = 0; i < dev->num_vlans; i++) {
+ vl = >vlans[i];
+ if (vl->members)
+ count++;
+ }
+
+ return count;
+}
+
+int b53_setup_devlink_resources(struct dsa_switch *ds)
+{
+ struct devlink_resource_size_params size_params;
+ struct b53_device *dev = ds->priv;
+ int err;
+
+ devlink_resource_size_params_init(_params, dev->num_vlans,
+ dev->num_vlans,
+ 1, DEVLINK_RESOURCE_UNIT_ENTRY);
+
+ err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
+ B53_DEVLINK_PARMA_ID_VLAN_TABLE,
+ DEVLINK_RESOURCE_ID_PARENT_TOP,
+ _params);
+ if (err)
+ goto out;
+
+ dsa_devlink_resource_occ_get_register(ds,
+ B53_DEVLINK_PARMA_ID_VLAN_TABLE,
+ b53_devlink_vlan_table_get, dev);
+
+ return 0;
+out:
+ dsa_devlink_resources_unregister(ds);
+ return err;
+}
+EXPORT_SYMBOL(b53_setup_devlink_resources);
+
static int b53_setup(struct dsa_switch *ds)
{
struct b53_device *dev = ds->priv;
@@ -992,8 +1039,10 @@ static int b53_setup(struct dsa_switch *ds)
b53_reset_mib(dev);
ret = b53_apply_config(dev);
- if (ret)
+ if (ret) {
dev_err(ds->dev, "failed to apply configuration\n");
+ return ret;
+ }
/* Configure IMP/CPU port, disable all other ports. Enabled
* ports will be configured with .port_enable
@@ -1012,7 +1061,12 @@ static int b53_setup(struct dsa_switch *ds)
*/
ds->vlan_filtering_is_global = true;
- return ret;
+ return b53_setup_devlink_resources(ds);
+}
+
+static void b53_teardown(struct dsa_switch *ds)
+{
+ dsa_devlink_resources_unregister(ds);
}
static void b53_force_link(struct b53_device *dev, int port, int link)
@@ -2141,6 +2195,7 @@ static int b53_get_max_mtu(struct dsa_switch *ds, int
port)
static const struct dsa_switch_ops b53_switch_ops = {
.get_tag_protocol = b53_get_tag_protocol,
.setup = b53_setup,
+ .teardown = b53_teardown,
.get_strings= b53_get_strings,
.get_ethtool_stats = b53_get_ethtool_stats,
.get_sset_count = b53_get_sset_count,
diff --git a/drivers/net/dsa/b53/b53_priv.h b/drivers/net/dsa/b53/b53_priv.h
index e942c60e4365..c55c0a9f1b47 100644
--- a/drivers/net/dsa/b53/b53_priv.h
+++ b/drivers/net/dsa/b53/b53_priv.h
@@ -328,6 +328,7 @@ void b53_br_set_stp_state(struct dsa_switch *ds, int port,
u8 state);
void b53_br_fast_age(struct dsa_switch *ds, int port);
int b53_br_egress_floods(struct dsa_switch *ds, int port,
bool unicast, bool multicast);
+int b53_setup_devlink_resources(struct dsa_switch *ds);
void b53_port_event(struct dsa_switch *ds, int port);
void b53_phylink_validate(struct dsa_switch *ds, int port,
unsigned long *supported,
diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
index 3263e8a0ae67..723820603107 100644
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
@@ -936,7 +936,12 @@ static int bcm_sf2_sw_setup(struct dsa_switch *ds)
b53_configure_vlan(ds);
bcm_sf2_enable_acb(ds);
- return 0;
+ return b53_setup_devlink_resources(ds);
+}
+
+static void bcm_sf2_sw_teardown(struct dsa_switch *ds)
+{
+ dsa_devlink_resources_unregister(ds);
}
/* The SWITCH_CORE register space is managed by b53 but operates on a page +
@@ -1073,6 +1078,7 @@ static int bcm_sf2_sw_get_sset_count(struct dsa_switch
*ds, int port,
static const struct dsa_switch_ops bcm_sf2_ops = {
.get_tag_protocol = b53_get_tag_protoco
Re: [PATCH stable 4.19 v2 0/2] arm64: entry: Place an SB sequence following an ERET instruction
On 8/24/2020 11:35 AM, Florian Fainelli wrote: Changes in v2: - included missing preliminary patch to define the SB barrier instruction Will Deacon (2): arm64: Add support for SB barrier and patch in over DSB; ISB sequences arm64: entry: Place an SB sequence following an ERET instruction Does anybody at ARM or Android care about those changes? If so, would you be willing to review these? Thanks arch/arm64/include/asm/assembler.h | 13 + arch/arm64/include/asm/barrier.h| 4 arch/arm64/include/asm/cpucaps.h| 3 ++- arch/arm64/include/asm/sysreg.h | 6 ++ arch/arm64/include/asm/uaccess.h| 3 +-- arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 12 arch/arm64/kernel/cpuinfo.c | 1 + arch/arm64/kernel/entry.S | 2 ++ arch/arm64/kvm/hyp/entry.S | 1 + arch/arm64/kvm/hyp/hyp-entry.S | 4 11 files changed, 47 insertions(+), 3 deletions(-) -- Florian
Re: [PATCH v11 00/11] PCI: brcmstb: enable PCIe for STB chips
On 9/7/2020 10:43 AM, Jim Quinlan wrote: On Mon, Sep 7, 2020 at 5:16 AM Lorenzo Pieralisi wrote: On Thu, Aug 27, 2020 at 09:29:59AM -0400, Jim Quinlan wrote: On Thu, Aug 27, 2020 at 2:35 AM Christoph Hellwig wrote: On Tue, Aug 25, 2020 at 10:40:27AM -0700, Florian Fainelli wrote: Hi, On 8/24/2020 12:30 PM, Jim Quinlan wrote: Patchset Summary: Enhance a PCIe host controller driver. Because of its unusual design we are foced to change dev->dma_pfn_offset into a more general role allowing multiple offsets. See the 'v1' notes below for more info. We are version 11 and counting, and it is not clear to me whether there is any chance of getting these patches reviewed and hopefully merged for the 5.10 merge window. There are a lot of different files being touched, so what would be the ideal way of routing those changes towards inclusion? FYI, I offered to take the dma-mapping bits through the dma-mapping tree. I have a bit of a backlog, but plan to review and if Jim is ok with that apply the current version. Sounds good to me. Hi Jim, is the dependency now solved ? Should we review/take this series as is for v5.10 through the PCI tree ? Hello Lorenzo, We are still working out a regression with the DMA offset commit on the RaspberryPi. Nicolas has found the root cause and we are now devising a solution. Maybe we can parallelize the PCIe driver review while the DMA changes are being worked on in Christoph's branch. Lorenzo, are you fine with the PCIe changes proper? -- Florian
[PATCH 1/2] dt-bindings: bus: Document breakpoint interrupt for gisb-arb
The GISB arbiter can have a third and optional interrupt to handle GISB breakpoints. Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt index 729def62f0c5..10f6d0a8159d 100644 --- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt +++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt @@ -10,7 +10,8 @@ Required properties: "brcm,bcm7038-gisb-arb" for 130nm chips - reg: specifies the base physical address and size of the registers - interrupts: specifies the two interrupts (timeout and TEA) to be used from - the parent interrupt controller + the parent interrupt controller. A third optional interrupt may be specified + for breakpoints. Optional properties: -- 2.25.1
[PATCH 2/2] bus: brcmstb_gisb: Add support for breakpoint interrupts
GISB breakpoint interrupts can be raised when a breakpoint has been
enabled to match a specific master and/or GISB register address. Being
able to print a message, similar to those done during target abort or
timeout greatly helps debug systems.
Signed-off-by: Florian Fainelli
---
drivers/bus/brcmstb_gisb.c | 96 +-
1 file changed, 95 insertions(+), 1 deletion(-)
diff --git a/drivers/bus/brcmstb_gisb.c b/drivers/bus/brcmstb_gisb.c
index 7579439971e3..7355fa2cb439 100644
--- a/drivers/bus/brcmstb_gisb.c
+++ b/drivers/bus/brcmstb_gisb.c
@@ -30,8 +30,22 @@
#define ARB_ERR_CAP_STATUS_WRITE (1 << 1)
#define ARB_ERR_CAP_STATUS_VALID (1 << 0)
+#define ARB_BP_CAP_CLEAR (1 << 0)
+#define ARB_BP_CAP_STATUS_PROT_SHIFT 14
+#define ARB_BP_CAP_STATUS_TYPE(1 << 13)
+#define ARB_BP_CAP_STATUS_RSP_SHIFT 10
+#define ARB_BP_CAP_STATUS_MASKGENMASK(1, 0)
+#define ARB_BP_CAP_STATUS_BS_SHIFT2
+#define ARB_BP_CAP_STATUS_WRITE (1 << 1)
+#define ARB_BP_CAP_STATUS_VALID (1 << 0)
+
enum {
ARB_TIMER,
+ ARB_BP_CAP_CLR,
+ ARB_BP_CAP_HI_ADDR,
+ ARB_BP_CAP_ADDR,
+ ARB_BP_CAP_STATUS,
+ ARB_BP_CAP_MASTER,
ARB_ERR_CAP_CLR,
ARB_ERR_CAP_HI_ADDR,
ARB_ERR_CAP_ADDR,
@@ -41,6 +55,11 @@ enum {
static const int gisb_offsets_bcm7038[] = {
[ARB_TIMER] = 0x00c,
+ [ARB_BP_CAP_CLR]= 0x014,
+ [ARB_BP_CAP_HI_ADDR]= -1,
+ [ARB_BP_CAP_ADDR] = 0x0b8,
+ [ARB_BP_CAP_STATUS] = 0x0c0,
+ [ARB_BP_CAP_MASTER] = -1,
[ARB_ERR_CAP_CLR] = 0x0c4,
[ARB_ERR_CAP_HI_ADDR] = -1,
[ARB_ERR_CAP_ADDR] = 0x0c8,
@@ -50,6 +69,11 @@ static const int gisb_offsets_bcm7038[] = {
static const int gisb_offsets_bcm7278[] = {
[ARB_TIMER] = 0x008,
+ [ARB_BP_CAP_CLR]= 0x01c,
+ [ARB_BP_CAP_HI_ADDR]= -1,
+ [ARB_BP_CAP_ADDR] = 0x220,
+ [ARB_BP_CAP_STATUS] = 0x230,
+ [ARB_BP_CAP_MASTER] = 0x234,
[ARB_ERR_CAP_CLR] = 0x7f8,
[ARB_ERR_CAP_HI_ADDR] = -1,
[ARB_ERR_CAP_ADDR] = 0x7e0,
@@ -59,6 +83,11 @@ static const int gisb_offsets_bcm7278[] = {
static const int gisb_offsets_bcm7400[] = {
[ARB_TIMER] = 0x00c,
+ [ARB_BP_CAP_CLR]= 0x014,
+ [ARB_BP_CAP_HI_ADDR]= -1,
+ [ARB_BP_CAP_ADDR] = 0x0b8,
+ [ARB_BP_CAP_STATUS] = 0x0c0,
+ [ARB_BP_CAP_MASTER] = 0x0c4,
[ARB_ERR_CAP_CLR] = 0x0c8,
[ARB_ERR_CAP_HI_ADDR] = -1,
[ARB_ERR_CAP_ADDR] = 0x0cc,
@@ -68,6 +97,11 @@ static const int gisb_offsets_bcm7400[] = {
static const int gisb_offsets_bcm7435[] = {
[ARB_TIMER] = 0x00c,
+ [ARB_BP_CAP_CLR]= 0x014,
+ [ARB_BP_CAP_HI_ADDR]= -1,
+ [ARB_BP_CAP_ADDR] = 0x158,
+ [ARB_BP_CAP_STATUS] = 0x160,
+ [ARB_BP_CAP_MASTER] = 0x164,
[ARB_ERR_CAP_CLR] = 0x168,
[ARB_ERR_CAP_HI_ADDR] = -1,
[ARB_ERR_CAP_ADDR] = 0x16c,
@@ -77,6 +111,11 @@ static const int gisb_offsets_bcm7435[] = {
static const int gisb_offsets_bcm7445[] = {
[ARB_TIMER] = 0x008,
+ [ARB_BP_CAP_CLR]= 0x010,
+ [ARB_BP_CAP_HI_ADDR]= -1,
+ [ARB_BP_CAP_ADDR] = 0x1d8,
+ [ARB_BP_CAP_STATUS] = 0x1e0,
+ [ARB_BP_CAP_MASTER] = 0x1e4,
[ARB_ERR_CAP_CLR] = 0x7e4,
[ARB_ERR_CAP_HI_ADDR] = 0x7e8,
[ARB_ERR_CAP_ADDR] = 0x7ec,
@@ -125,6 +164,16 @@ static u64 gisb_read_address(struct
brcmstb_gisb_arb_device *gdev)
return value;
}
+static u64 gisb_read_bp_address(struct brcmstb_gisb_arb_device *gdev)
+{
+ u64 value;
+
+ value = gisb_read(gdev, ARB_BP_CAP_ADDR);
+ value |= (u64)gisb_read(gdev, ARB_BP_CAP_HI_ADDR) << 32;
+
+ return value;
+}
+
static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
{
int offset = gdev->gisb_offsets[reg];
@@ -259,6 +308,41 @@ static irqreturn_t brcmstb_gisb_tea_handler(int irq, void
*dev_id)
return IRQ_HANDLED;
}
+static irqreturn_t brcmstb_gisb_bp_handler(int irq, void *dev_id)
+{
+ struct brcmstb_gisb_arb_device *gdev = dev_id;
+ const char *m_name;
+ u32 bp_status;
+ u64 arb_addr;
+ u32 master;
+ char m_fmt[11];
+
+ bp_status = gisb_read(gdev, ARB_BP_CAP_STATUS);
+
+ /* Invalid captured address, bail out */
+ if (!(bp_status & ARB_BP_CAP_STATUS_VALID))
+ return IRQ_HANDLED;
+
+ /* Read the address and master */
+ arb_addr = gisb_read_bp_address(gdev);
+ master = gisb_read(gdev, ARB_BP_CAP_MASTER);
+
+ m_name = brcmstb_gisb_master_to_str(gdev, master);
+ if (!m_name) {
+
[PATCH 0/2] bus: brcmstb_gisb: Add support for breakpoint interrupts
Hi all, This patch series adds support for GISB break point interrupts which can happen when a specific GISB range has been locked out by a security processor. Being able to get a debug message when such an access occurs greatly helps with debugging production software on Broadcom STB SoCs. Florian Fainelli (2): dt-bindings: bus: Document breakpoint interrupt for gisb-arb bus: brcmstb_gisb: Add support for breakpoint interrupts .../devicetree/bindings/bus/brcm,gisb-arb.txt | 3 +- drivers/bus/brcmstb_gisb.c| 96 ++- 2 files changed, 97 insertions(+), 2 deletions(-) -- 2.25.1
Re: [PATCH] MAINTAINERS: Add entry for Broadcom BDC driver
On 7/9/2020 8:48 PM, Florian Fainelli wrote: The Broadcom BDC driver did not have a MAINTAINERS entry which made it escape review from Al and myself, add an entry so the relevant mailing lists and people are copied. Signed-off-by: Florian Fainelli This patch still does not seem to have been picked up (not seeing it in linux-next), can this be applied so we have an accurate maintainer information for this driver? Thanks --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1d4aa7f942de..360d001b81b8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3434,6 +3434,14 @@ F: drivers/bus/brcmstb_gisb.c F:drivers/pci/controller/pcie-brcmstb.c N:brcmstb +BROADCOM BDC DRIVER +M: Al Cooper +L: linux-...@vger.kernel.org +L: bcm-kernel-feedback-l...@broadcom.com +S: Maintained +F: Documentation/devicetree/bindings/usb/brcm,bdc.txt +F: drivers/usb/gadget/udc/bdc/ + BROADCOM BMIPS CPUFREQ DRIVER M:Markus Mayer M:bcm-kernel-feedback-l...@broadcom.com -- Florian
Re: [PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates
On 9/4/2020 1:50 PM, Florian Fainelli wrote: This patch series adds support for two new STB chips: 72164 and 72165 and allows them to be tuned the same way other Brahma-B53 chips are. The last two changes are some minor configuration changes to the read-ahead cache logic to improve performance for Cortex-A72 based systems. Series applied to drivers/next, there was an incorrectly updated comment in the last patch that was removed. -- Florian
Re: [PATCH] ARM: brcmstb: Add debug UART entry for 72615
On 9/4/2020 1:42 PM, Florian Fainelli wrote: 72165 has the same memory map as 7278 and the same physical address for the UART, alias the definition accordingly. Signed-off-by: Florian Fainelli Applied to soc/next -- Florian
[PATCH net-next v2 1/2] of: Export of_remove_property() to modules
We will need to remove some OF properties in drivers/net/dsa/bcm_sf2.c
with a subsequent commit. Export of_remove_property() to modules so we
can keep bcm_sf2 modular and provide an empty stub for when CONFIG_OF is
disabled to maintain the ability to compile test.
Signed-off-by: Florian Fainelli
---
drivers/of/base.c | 1 +
include/linux/of.h | 5 +
2 files changed, 6 insertions(+)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index ea44fea99813..161a23631472 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1869,6 +1869,7 @@ int of_remove_property(struct device_node *np, struct
property *prop)
return rc;
}
+EXPORT_SYMBOL_GPL(of_remove_property);
int __of_update_property(struct device_node *np, struct property *newprop,
struct property **oldpropp)
diff --git a/include/linux/of.h b/include/linux/of.h
index 5cf7ae0465d1..481ec0467285 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -929,6 +929,11 @@ static inline int of_machine_is_compatible(const char
*compat)
return 0;
}
+static inline int of_remove_property(struct device_node *np, struct property
*prop)
+{
+ return 0;
+}
+
static inline bool of_console_check(const struct device_node *dn, const char
*name, int index)
{
return false;
--
2.25.1
[PATCH net-next v2 2/2] net: dsa: bcm_sf2: Ensure that MDIO diversion is used
Registering our slave MDIO bus outside of the OF infrastructure is
necessary in order to avoid creating double references of the same
Device Tree nodes, however it is not sufficient to guarantee that the
MDIO bus diversion is used because of_phy_connect() will still resolve
to a valid PHY phandle and it will connect to the PHY using its parent
MDIO bus which is still the SF2 master MDIO bus. The reason for that is
because BCM7445 systems were already shipped with a Device Tree blob
looking like this (irrelevant parts omitted for simplicity):
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
phy-mode = "rgmii-txid";
phy-handle = <>;
reg = <1>;
label = "rgmii_1";
};
...
mdio@403c0 {
...
phy0: ethernet-phy@0 {
broken-turn-around;
device_type = "ethernet-phy";
max-speed = <0x3e8>;
reg = <0>;
compatible = "brcm,bcm53125",
"ethernet-phy-ieee802.3-c22";
};
};
There is a hardware issue with chip revisions (Dx) that lead to the
development of the following commits:
461cd1b03e32 ("net: dsa: bcm_sf2: Register our slave MDIO bus")
536fab5bf582 ("net: dsa: bcm_sf2: Do not register slave MDIO bus with OF")
b8c6cd1d316f ("net: dsa: bcm_sf2: do not use indirect reads and writes for
7445E0")
There should have been an internal MDIO bus node created for the chip
revision (Dx) that suffers from this problem, but it did not happen back
then.
Had that happen, that we should have correctly parented phy@0 (bcm53125
below) as child node of the internal MDIO bus, but the production Device
Tree blob that was shipped with the firmware targeted the fixed version
of the chip, despite both the affected and corrected chips being shipped
into production.
The problem is that of_phy_connect() for port@1 will happily resolve the
'phy-handle' from the mdio@403c0 node, which bypasses the diversion
completely. This results in this double programming that the diversion
refers to and aims to avoid. In order to force of_phy_connect() to fail,
and have DSA call to dsa_slave_phy_connect(), we must deactivate
ethernet-phy@0 from mdio@403c0, and the best way to do that is by
removing the phandle property completely.
Signed-off-by: Florian Fainelli
---
drivers/net/dsa/bcm_sf2.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
index 1c7fbb6f0447..8e215c148487 100644
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
@@ -489,9 +489,11 @@ static void bcm_sf2_identify_ports(struct bcm_sf2_priv
*priv,
static int bcm_sf2_mdio_register(struct dsa_switch *ds)
{
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
- struct device_node *dn;
+ struct device_node *dn, *child;
+ struct phy_device *phydev;
+ struct property *prop;
static int index;
- int err;
+ int err, reg;
/* Find our integrated MDIO bus node */
dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
@@ -534,6 +536,31 @@ static int bcm_sf2_mdio_register(struct dsa_switch *ds)
priv->slave_mii_bus->parent = ds->dev->parent;
priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
+ /* We need to make sure that of_phy_connect() will not work by
+* removing the 'phandle' and 'linux,phandle' properties and
+* unregister the existing PHY device that was already registered.
+*/
+ for_each_available_child_of_node(dn, child) {
+ if (of_property_read_u32(child, "reg", ) ||
+ reg >= PHY_MAX_ADDR)
+ continue;
+
+ if (!(priv->indir_phy_mask & BIT(reg)))
+ continue;
+
+ prop = of_find_property(child, "phandle", NULL);
+ if (prop)
+ of_remove_property(child, prop);
+
+ prop = of_find_property(child, "linux,phandle", NULL);
+ if (prop)
+ of_remove_property(child, prop);
+
+ phydev = of_phy_find_device(child);
+ if (phydev)
+ phy_device_remove(phydev);
+ }
+
err = mdiobus_register(priv->slave_mii_bus);
if (err && dn)
of_node_put(dn);
--
2.25.1
[PATCH net-next v2 0/2] net: dsa: bcm_sf2: Ensure MDIO diversion is used
Changes in v2: - export of_update_property() to permit building bcm_sf2 as a module - provided a better explanation of the problem being solved after explaining it to Andrew during the v1 review Florian Fainelli (2): of: Export of_remove_property() to modules net: dsa: bcm_sf2: Ensure that MDIO diversion is used drivers/net/dsa/bcm_sf2.c | 31 +-- drivers/of/base.c | 1 + include/linux/of.h| 5 + 3 files changed, 35 insertions(+), 2 deletions(-) -- 2.25.1
Re: [PATCH v2 3/6] ARM: dts: NSP: Fix SP804 compatible node
On 9/3/2020 6:04 PM, André Przywara wrote:
On 02/09/2020 00:04, Florian Fainelli wrote:
Hi Florian,
sorry, the mail got swamped in my inbox...
On 8/28/2020 10:12 AM, Florian Fainelli wrote:
On 8/28/20 7:20 AM, Andre Przywara wrote:
The DT binding for SP804 requires to have an "arm,primecell" compatible
string.
Add this string so that the Linux primecell bus driver picks the device
up and activates the clock.
Fixes: a0efb0d28b77 ("ARM: dts: NSP: Add SP804 Support to DT")
Tested-by: Florian Fainelli
Signed-off-by: Andre Przywara
This looks fine, however there is a ccbtimer1 instance that you missed,
can you resubmit with it included?
With that:
Acked-by: Florian Fainelli
Andre are you going to resubmit a patch with the second instance
(ccbtimer1) fixed as well, or should I take care of that while applying
the patch? Either way is fine, just let me know.
So I was waiting for more comments, but there was nothing so far that
justifies a new version. So would you mind fixing this while applying? I
must have indeed missed this instance while diffing before and after.
Applied and fixed up the ccbtimer1 node, thanks.
--
Florian
[PATCH 3/4] soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2
Change the RAC prefetch distance from +/- 1 to +/- 2 for Cortex-A72 CPUs
since this provides an average of a 3.8% performance increase for
synthetic memcpy benchmarks.
Signed-off-by: Florian Fainelli
---
drivers/soc/bcm/brcmstb/biuctrl.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c
b/drivers/soc/bcm/brcmstb/biuctrl.c
index d448a89ceb27..28f69cc0df51 100644
--- a/drivers/soc/bcm/brcmstb/biuctrl.c
+++ b/drivers/soc/bcm/brcmstb/biuctrl.c
@@ -20,6 +20,8 @@
#define RACENDATA_SHIFT6
#define RAC_CPU_SHIFT 8
#define RACCFG_MASK0xff
+#define DPREF_LINE_2_SHIFT 24
+#define DPREF_LINE_2_MASK 0xff
/* Bitmask to enable instruction and data prefetching with a 256-bytes stride
*/
#define RAC_DATA_INST_EN_MASK (1 << RACPREFINST_SHIFT | \
@@ -50,6 +52,7 @@ enum cpubiuctrl_regs {
CPU_MCP_FLOW_REG,
CPU_WRITEBACK_CTRL_REG,
RAC_CONFIG0_REG,
+ RAC_CONFIG1_REG,
NUM_CPU_BIUCTRL_REGS,
};
@@ -58,7 +61,7 @@ static inline u32 cbc_readl(int reg)
int offset = cpubiuctrl_regs[reg];
if (offset == -1 ||
- (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg == RAC_CONFIG0_REG))
+ (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
return (u32)-1;
return readl_relaxed(cpubiuctrl_base + offset);
@@ -69,7 +72,7 @@ static inline void cbc_writel(u32 val, int reg)
int offset = cpubiuctrl_regs[reg];
if (offset == -1 ||
- (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg == RAC_CONFIG0_REG))
+ (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
return;
writel(val, cpubiuctrl_base + offset);
@@ -80,6 +83,7 @@ static const int b15_cpubiuctrl_regs[] = {
[CPU_MCP_FLOW_REG] = -1,
[CPU_WRITEBACK_CTRL_REG] = -1,
[RAC_CONFIG0_REG] = -1,
+ [RAC_CONFIG1_REG] = -1,
};
/* Odd cases, e.g: 7260A0 */
@@ -88,6 +92,7 @@ static const int b53_cpubiuctrl_no_wb_regs[] = {
[CPU_MCP_FLOW_REG] = 0x0b4,
[CPU_WRITEBACK_CTRL_REG] = -1,
[RAC_CONFIG0_REG] = 0x78,
+ [RAC_CONFIG1_REG] = 0x7c,
};
static const int b53_cpubiuctrl_regs[] = {
@@ -95,6 +100,7 @@ static const int b53_cpubiuctrl_regs[] = {
[CPU_MCP_FLOW_REG] = 0x0b4,
[CPU_WRITEBACK_CTRL_REG] = 0x22c,
[RAC_CONFIG0_REG] = 0x78,
+ [RAC_CONFIG1_REG] = 0x7c,
};
static const int a72_cpubiuctrl_regs[] = {
@@ -102,6 +108,7 @@ static const int a72_cpubiuctrl_regs[] = {
[CPU_MCP_FLOW_REG] = 0x1c,
[CPU_WRITEBACK_CTRL_REG] = 0x20,
[RAC_CONFIG0_REG] = 0x08,
+ [RAC_CONFIG1_REG] = 0x0c,
};
static int __init mcp_write_pairing_set(void)
@@ -167,7 +174,7 @@ static const u32 a72_b53_mach_compat[] = {
static void __init a72_b53_rac_enable_all(struct device_node *np)
{
unsigned int cpu;
- u32 enable = 0;
+ u32 enable = 0, pref_dist;
if (IS_ENABLED(CONFIG_CACHE_B15_RAC))
return;
@@ -175,10 +182,15 @@ static void __init a72_b53_rac_enable_all(struct
device_node *np)
if (WARN(num_possible_cpus() > 4, "RAC only supports 4 CPUs\n"))
return;
- for_each_possible_cpu(cpu)
+ pref_dist = cbc_readl(RAC_CONFIG1_REG);
+ for_each_possible_cpu(cpu) {
enable |= RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT);
+ if (cpubiuctrl_regs == a72_cpubiuctrl_regs)
+ pref_dist |= 1 << (cpu + DPREF_LINE_2_SHIFT);
+ }
cbc_writel(enable, RAC_CONFIG0_REG);
+ cbc_writel(pref_dist, RAC_CONFIG1_REG);
pr_info("%pOF: Broadcom %s read-ahead cache\n",
np, cpubiuctrl_regs == a72_cpubiuctrl_regs ?
--
2.25.1
[PATCH 4/4] soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines
Change the RACPREFDATA(x) setting to prefetch the next 256-byte line
after 4 consecutive lines have been used, instead of after 2 consecutive
lines. This does improve the synthetic memcpy benchmark by an additional
+0.5% on top of the previous change for Cortex-A72 CPUs.
Signed-off-by: Florian Fainelli
---
drivers/soc/bcm/brcmstb/biuctrl.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c
b/drivers/soc/bcm/brcmstb/biuctrl.c
index 28f69cc0df51..63864b6dea2e 100644
--- a/drivers/soc/bcm/brcmstb/biuctrl.c
+++ b/drivers/soc/bcm/brcmstb/biuctrl.c
@@ -23,7 +23,9 @@
#define DPREF_LINE_2_SHIFT 24
#define DPREF_LINE_2_MASK 0xff
-/* Bitmask to enable instruction and data prefetching with a 256-bytes stride
*/
+/* Bitmask to enable instruction and data prefetching with a 256-bytes stride,
+ * prefetch next 256-byte line after 4 consecutive lines used
+ */
#define RAC_DATA_INST_EN_MASK (1 << RACPREFINST_SHIFT | \
RACENPREF_MASK << RACENINST_SHIFT | \
1 << RACPREFDATA_SHIFT | \
@@ -174,7 +176,7 @@ static const u32 a72_b53_mach_compat[] = {
static void __init a72_b53_rac_enable_all(struct device_node *np)
{
unsigned int cpu;
- u32 enable = 0, pref_dist;
+ u32 enable = 0, pref_dist, shift;
if (IS_ENABLED(CONFIG_CACHE_B15_RAC))
return;
@@ -184,9 +186,13 @@ static void __init a72_b53_rac_enable_all(struct
device_node *np)
pref_dist = cbc_readl(RAC_CONFIG1_REG);
for_each_possible_cpu(cpu) {
+ shift = cpu * RAC_CPU_SHIFT + RACPREFDATA_SHIFT;
enable |= RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT);
- if (cpubiuctrl_regs == a72_cpubiuctrl_regs)
+ if (cpubiuctrl_regs == a72_cpubiuctrl_regs) {
+ enable &= ~(RACENPREF_MASK << shift);
+ enable |= 3 << shift;
pref_dist |= 1 << (cpu + DPREF_LINE_2_SHIFT);
+ }
}
cbc_writel(enable, RAC_CONFIG0_REG);
--
2.25.1
[PATCH 2/4] soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165
72165 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it
according to the existing values we have.
Signed-off-by: Florian Fainelli
---
drivers/soc/bcm/brcmstb/biuctrl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c
b/drivers/soc/bcm/brcmstb/biuctrl.c
index a4b01894a9ad..d448a89ceb27 100644
--- a/drivers/soc/bcm/brcmstb/biuctrl.c
+++ b/drivers/soc/bcm/brcmstb/biuctrl.c
@@ -131,6 +131,7 @@ static const u32 a72_b53_mach_compat[] = {
0x7211,
0x7216,
0x72164,
+ 0x72165,
0x7255,
0x7260,
0x7268,
--
2.25.1
[PATCH 2/4] soc: brcmstb: biuctrl: Tune MCP settings for 72165
72165 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it
according to the existing values we have.
Signed-off-by: Florian Fainelli
---
drivers/soc/bcm/brcmstb/biuctrl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c
b/drivers/soc/bcm/brcmstb/biuctrl.c
index a4b01894a9ad..d448a89ceb27 100644
--- a/drivers/soc/bcm/brcmstb/biuctrl.c
+++ b/drivers/soc/bcm/brcmstb/biuctrl.c
@@ -131,6 +131,7 @@ static const u32 a72_b53_mach_compat[] = {
0x7211,
0x7216,
0x72164,
+ 0x72165,
0x7255,
0x7260,
0x7268,
--
2.25.1
[PATCH 1/4] soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164
72164 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it
according to the existing values we have.
Signed-off-by: Florian Fainelli
---
drivers/soc/bcm/brcmstb/biuctrl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c
b/drivers/soc/bcm/brcmstb/biuctrl.c
index 95602ece51d4..a4b01894a9ad 100644
--- a/drivers/soc/bcm/brcmstb/biuctrl.c
+++ b/drivers/soc/bcm/brcmstb/biuctrl.c
@@ -130,6 +130,7 @@ static int __init mcp_write_pairing_set(void)
static const u32 a72_b53_mach_compat[] = {
0x7211,
0x7216,
+ 0x72164,
0x7255,
0x7260,
0x7268,
--
2.25.1
[PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates
This patch series adds support for two new STB chips: 72164 and 72165 and allows them to be tuned the same way other Brahma-B53 chips are. The last two changes are some minor configuration changes to the read-ahead cache logic to improve performance for Cortex-A72 based systems. Florian Fainelli (4): soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164 soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165 soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2 soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines drivers/soc/bcm/brcmstb/biuctrl.c | 30 +- 1 file changed, 25 insertions(+), 5 deletions(-) -- 2.25.1
[PATCH] ARM: brcmstb: Add debug UART entry for 72615
72165 has the same memory map as 7278 and the same physical address for the UART, alias the definition accordingly. Signed-off-by: Florian Fainelli --- arch/arm/include/debug/brcmstb.S | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S index 79223209d3f4..d693565af23c 100644 --- a/arch/arm/include/debug/brcmstb.S +++ b/arch/arm/include/debug/brcmstb.S @@ -33,6 +33,7 @@ #define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000) #define UARTA_7216 UARTA_7278 #define UARTA_72164UARTA_7278 +#define UARTA_72165UARTA_7278 #define UARTA_7364 REG_PHYS_ADDR(0x40b000) #define UARTA_7366 UARTA_7364 #define UARTA_74371REG_PHYS_ADDR(0x406b00) @@ -86,17 +87,18 @@ ARM_BE8(rev \rv, \rv ) 20:checkuart(\rp, \rv, 0x3390, 3390) 21:checkuart(\rp, \rv, 0x7216, 7216) 22:checkuart(\rp, \rv, 0x07216400, 72164) -23:checkuart(\rp, \rv, 0x7250, 7250) -24:checkuart(\rp, \rv, 0x7255, 7255) -25:checkuart(\rp, \rv, 0x7260, 7260) -26:checkuart(\rp, \rv, 0x7268, 7268) -27:checkuart(\rp, \rv, 0x7271, 7271) -28:checkuart(\rp, \rv, 0x7278, 7278) -29:checkuart(\rp, \rv, 0x7364, 7364) -30:checkuart(\rp, \rv, 0x7366, 7366) -31:checkuart(\rp, \rv, 0x07437100, 74371) -32:checkuart(\rp, \rv, 0x7439, 7439) -33:checkuart(\rp, \rv, 0x7445, 7445) +23:checkuart(\rp, \rv, 0x07216500, 72165) +24:checkuart(\rp, \rv, 0x7250, 7250) +25:checkuart(\rp, \rv, 0x7255, 7255) +26:checkuart(\rp, \rv, 0x7260, 7260) +27:checkuart(\rp, \rv, 0x7268, 7268) +28:checkuart(\rp, \rv, 0x7271, 7271) +29:checkuart(\rp, \rv, 0x7278, 7278) +30:checkuart(\rp, \rv, 0x7364, 7364) +31:checkuart(\rp, \rv, 0x7366, 7366) +32:checkuart(\rp, \rv, 0x07437100, 74371) +33:checkuart(\rp, \rv, 0x7439, 7439) +34:checkuart(\rp, \rv, 0x7445, 7445) /* No valid UART found */ 90:mov \rp, #0 -- 2.25.1
Re: [PATCH 00/10] dt-bindings: Convert SP805 to Json-schema (and fix users)
On 9/4/2020 8:35 AM, André Przywara wrote: On 04/09/2020 16:29, Florian Fainelli wrote: Hi, On 9/4/2020 1:58 AM, Linus Walleij wrote:>> On Fri, Aug 28, 2020 at 9:34 PM Florian Fainelli wrote: On 8/28/20 6:05 AM, Andre Przywara wrote: What is the plan for merging this series? Should Rob pick up all changes or since those are non critical changes, should we just leave it to the SoC maintainers to pick up the changes in their tree? What about André just send a pull request to the ARM SoC maintainers for the whole thing? I already applied some of the patches, if we got that route please CC me so I can drop them from my local queue. Thanks I would for sure drop these from any PR. Rob, are you happy with the actual binding conversion? If you are willing to take it as it is (Viresh has already acked), I could then split off the DT fixes and either chase the maintainers or send ARM SoC a PR. But this really depends on the binding being good. We had discussed this in an another leg of this thread that starts here: https://lore.kernel.org/linux-devicetree/cal_jsqkvcgaots6xl7pu+wm8x33plcqcuoaxymwra3j3odo...@mail.gmail.com/ -- Florian
Re: [PATCH 00/10] dt-bindings: Convert SP805 to Json-schema (and fix users)
On 9/4/2020 1:58 AM, Linus Walleij wrote: On Fri, Aug 28, 2020 at 9:34 PM Florian Fainelli wrote: On 8/28/20 6:05 AM, Andre Przywara wrote: What is the plan for merging this series? Should Rob pick up all changes or since those are non critical changes, should we just leave it to the SoC maintainers to pick up the changes in their tree? What about André just send a pull request to the ARM SoC maintainers for the whole thing? I already applied some of the patches, if we got that route please CC me so I can drop them from my local queue. Thanks -- Florian
Re: [PATCH net-next] net: dsa: bcm_sf2: Ensure that MDIO diversion is used
On 9/3/2020 3:03 PM, Andrew Lunn wrote: The firmware provides the Device Tree but here is the relevant section for you pasted below. The problematic device is a particular revision of the silicon (D0) which got later fixed (E0) however the Device Tree was created after the fixed platform, not the problematic one. Both revisions of the silicon are in production. There should have been an internal MDIO bus created for that chip revision such that we could have correctly parented phy@0 (bcm53125 below) as child node of the internal MDIO bus, but you have to realize that this was done back in 2014 when DSA was barely revived as an active subsystem. The BCM53125 node should have have been converted to an actual switch node at some point, I use a mdio_boardinfo overlay downstream to support the switch as a proper b53/DSA switch, anyway. I was expecting something like that. I think this patch needs a comment in the code explaining it is a workaround for a DT blob which cannot be changed. Maybe also make it conditional on the board compatible string? It is already targeted at the Broadcom pseudo PHY address (30) which is the one that needs diversion, I will update the patch description accordingly though. -- Florian
Re: [PATCH v2 01/11] usb: gadget: bdc: fix improper SPDX comment style for header file
On 9/3/2020 8:17 PM, Chunfeng Yun wrote: Hi Florian, On Thu, 2020-08-20 at 19:30 +0800, Chunfeng Yun wrote: For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used). Cc: Florian Fainelli Signed-off-by: Chunfeng Yun --- [snip] Would you please take a look at this series? I'll drop the patches that not fine with you. It all looks good to me, thanks and sorry for not responding earlier. -- Florian
Re: [PATCH v2 11/11] usb: gadget: bdc: fix checkpatch.pl repeated word warning
On 8/20/2020 4:30 AM, Chunfeng Yun wrote: fix the warning: WARNING:REPEATED_WORD: Possible repeated word: 'and' Cc: Florian Fainelli Signed-off-by: Chunfeng Yun Acked-by: Florian Fainelli -- Florian
Re: [PATCH v2 10/11] usb: gadget: bdc: fix checkpatch.pl spacing error
On 8/20/2020 4:30 AM, Chunfeng Yun wrote: fix checkpatch.pl error: ERROR:SPACING: space prohibited before that ',' Cc: Florian Fainelli Signed-off-by: Chunfeng Yun Acked-by: Florian Fainelli -- Florian
Re: [PATCH v2 08/11] usb: gadget: bdc: use the BIT macro to define bit filed
On 8/20/2020 4:30 AM, Chunfeng Yun wrote: Prefer using the BIT macro to define bit fileds Cc: Florian Fainelli Signed-off-by: Chunfeng Yun Acked-by: Florian Fainelli -- Florian
Re: [PATCH v2 09/11] usb: gadget: bdc: fix checkpatch.pl tab warning
On 8/20/2020 4:30 AM, Chunfeng Yun wrote: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements WARNING:TABSTOP: Statements should start on a tabstop Cc: Florian Fainelli Signed-off-by: Chunfeng Yun Acked-by: Florian Fainelli -- Florian
Re: [PATCH v2 07/11] usb: gadget: bdc: avoid precedence issues
On 8/20/2020 4:30 AM, Chunfeng Yun wrote: Add () around macro argument to avoid precedence issues Cc: Florian Fainelli Signed-off-by: Chunfeng Yun Acked-by: Florian Fainelli -- Florian
Re: [PATCH v2 05/11] usb: gadget: bdc: fix check warning of block comments alignment
On 8/20/2020 4:30 AM, Chunfeng Yun wrote: fix the warning: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line Cc: Florian Fainelli Signed-off-by: Chunfeng Yun Acked-by: Florian Fainelli -- Florian
Re: [PATCH v2 06/11] usb: gadget: bdc: add identifier name for function declaraion
On 8/20/2020 4:30 AM, Chunfeng Yun wrote: This is used to avoid the warning of function arguments, e.g. WARNING:FUNCTION_ARGUMENTS: function definition argument 'u32' should also have an identifier name Cc: Florian Fainelli Signed-off-by: Chunfeng Yun Acked-by: Florian Fainelli -- Florian
Re: [PATCH v2 03/11] usb: gadget: bdc: prefer pointer dereference to pointer type
On 8/20/2020 4:30 AM, Chunfeng Yun wrote: Prefer kzalloc(sizeof(*bd_table)...) over kzalloc(sizeof(struct bd_table) Cc: Florian Fainelli Signed-off-by: Chunfeng Yun Acked-by: Florian Fainelli -- Florian
Re: [PATCH v2 02/11] usb: gadget: bdc: remove bdc_ep_set_halt() declaration
On 8/20/2020 4:30 AM, Chunfeng Yun wrote: No definition for bdc_ep_set_halt(), so remove it. Cc: Florian Fainelli Signed-off-by: Chunfeng Yun Acked-by: Florian Fainelli -- Florian
Re: [PATCH v2 04/11] usb: gadget: bdc: fix warning of embedded function name
On 8/20/2020 4:30 AM, Chunfeng Yun wrote: Use '"%s...", __func__' to replace embedded function name Cc: Florian Fainelli Signed-off-by: Chunfeng Yun Acked-by: Florian Fainelli -- Florian
Re: [PATCH v2 01/11] usb: gadget: bdc: fix improper SPDX comment style for header file
On 8/20/2020 4:30 AM, Chunfeng Yun wrote: For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used). Cc: Florian Fainelli Signed-off-by: Chunfeng Yun Acked-by: Florian Fainelli -- Florian
Re: [PATCH net] net: phy: dp83867: Fix various styling and space issues
On 9/3/2020 9:41 AM, Dan Murphy wrote: Florian On 9/3/20 11:34 AM, Florian Fainelli wrote: On 9/3/2020 7:15 AM, Dan Murphy wrote: Fix spacing issues reported for misaligned switch..case and extra new lines. Also updated the file header to comply with networking commet style. Signed-off-by: Dan Murphy --- drivers/net/phy/dp83867.c | 47 ++- 1 file changed, 22 insertions(+), 25 deletions(-) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index cd7032628a28..f182a8d767c6 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -/* - * Driver for the Texas Instruments DP83867 PHY +/* Driver for the Texas Instruments DP83867 PHY * * Copyright (C) 2015 Texas Instruments Inc. */ @@ -35,7 +34,7 @@ #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6)) #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5) #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5) -#define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5) +#define DP83867_CFG4_SGMII_ANEG_TIMER_2US BIT(5) Now the definitions are inconsistent, you would want to drop this one and stick to the existing style. OK I was a little conflicted making that change due to the reasons you mentioned. But if that is an acceptable warning I am ok with it. IMHO, if the are no obvious incorrect styles, and using 1 << x is not, it just may not be the preferred style (and there is quite frankly a ton of those patterns in the kernel), then ignoring the checkpatch.pl warning is fine. After all this is a tool, not an absolute truth by any means, but again, others may disagree. -- Florian
Re: [PATCH net] net: phy: dp83867: Fix various styling and space issues
On 9/3/2020 7:15 AM, Dan Murphy wrote: Fix spacing issues reported for misaligned switch..case and extra new lines. Also updated the file header to comply with networking commet style. Signed-off-by: Dan Murphy --- drivers/net/phy/dp83867.c | 47 ++- 1 file changed, 22 insertions(+), 25 deletions(-) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index cd7032628a28..f182a8d767c6 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -/* - * Driver for the Texas Instruments DP83867 PHY +/* Driver for the Texas Instruments DP83867 PHY * * Copyright (C) 2015 Texas Instruments Inc. */ @@ -35,7 +34,7 @@ #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6)) #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5) #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5) -#define DP83867_CFG4_SGMII_ANEG_TIMER_2US(1 << 5) +#define DP83867_CFG4_SGMII_ANEG_TIMER_2USBIT(5) Now the definitions are inconsistent, you would want to drop this one and stick to the existing style. The rest of the changes look good, so with that fixed, and the subject correct to "net-next" (this is no bug fix material), you can add: Reviewed-by: Florian Fainelli -- Florian
Re: [PATCH net-next] net: dsa: bcm_sf2: Ensure that MDIO diversion is used
On 9/2/2020 6:13 PM, Andrew Lunn wrote:
On Wed, Sep 02, 2020 at 02:03:27PM -0700, Florian Fainelli wrote:
Registering our slave MDIO bus outside of the OF infrastructure is
necessary in order to avoid creating double references of the same
Device Tree nodes, however it is not sufficient to guarantee that the
MDIO bus diversion is used because of_phy_connect() will still resolve
to a valid PHY phandle and it will connect to the PHY using its parent
MDIO bus which is still the SF2 master MDIO bus.
Ensure that of_phy_connect() does not suceed by removing any phandle
reference for the PHY we need to divert. This forces the DSA code to use
the DSA slave_mii_bus that we register and ensures the MDIO diversion is
being used.
Hi Florian
Sorry, i don't get this explanation. Can you point me towards a device
tree i can look at to maybe understand what is going on.
The firmware provides the Device Tree but here is the relevant section
for you pasted below. The problematic device is a particular revision of
the silicon (D0) which got later fixed (E0) however the Device Tree was
created after the fixed platform, not the problematic one. Both
revisions of the silicon are in production.
There should have been an internal MDIO bus created for that chip
revision such that we could have correctly parented phy@0 (bcm53125
below) as child node of the internal MDIO bus, but you have to realize
that this was done back in 2014 when DSA was barely revived as an active
subsystem. The BCM53125 node should have have been converted to an
actual switch node at some point, I use a mdio_boardinfo overlay
downstream to support the switch as a proper b53/DSA switch, anyway.
The problem is that of_phy_connect() for port@1 will resolve the
phy-handle from the mdio@403c0 node, which bypasses the diversion
completely. This results in this double programming that the diversion
refers to. In order to force of_phy_connect() to fail, and have DSA call
to dsa_slave_phy_connect(), we must deactivate ethernet-phy@0 from
mdio@403c0, and the best way to do that is by removing the phandle
property completely.
Hope this clarifies the mess :)
switch_top@f0b0 {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "brcm,bcm7445-switch-top-v2.0\0simple-bus";
ranges = <0x00 0xf0b0 0x40804>;
ethernet_switch@0 {
#address-cells = <0x02>;
#size-cells = <0x00>;
brcm,num-acb-queues = <0x40>;
brcm,num-gphy = <0x01>;
brcm,num-rgmii-ports = <0x02>;
compatible =
"brcm,bcm7445-switch-v4.0\0brcm,bcm53012";
dsa,ethernet = <0x16>;
dsa,mii-bus = <0x17>;
resets = <0x18 0x1a>;
reset-names = "switch";
reg = <0x00 0x4 0x4 0x110 0x40340 0x30 0x40380 0x30 0x40400
0x34 0x40600 0x208>;
reg-names =
"core\0reg\0intrl2_0\0intrl2_1\0fcb\0acb";
interrupts = <0x00 0x18 0x04 0x00 0x19 0x04>;
interrupt-names = "switch_0\0switch_1";
brcm,fcb-pause-override;
brcm,acb-packets-inflight;
clocks = <0x0a 0x6d 0x0a 0x76>;
clock-names = "sw_switch\0sw_switch_mdiv";
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
phy-mode = "internal";
phy-handle = <0x29>;
linux,phandle = <0x2a>;
phandle = <0x2a>;
reg = <0x00>;
label = "gphy";
};
port@1 {
phy-mode = "rgmii-txid";
phy-handle = <0x2c>;
linux,phandle = <0x2d>;
phandle = <0x2d>;
reg = <0x01&g
[PATCH net-next] net: dsa: bcm_sf2: Ensure that MDIO diversion is used
Registering our slave MDIO bus outside of the OF infrastructure is
necessary in order to avoid creating double references of the same
Device Tree nodes, however it is not sufficient to guarantee that the
MDIO bus diversion is used because of_phy_connect() will still resolve
to a valid PHY phandle and it will connect to the PHY using its parent
MDIO bus which is still the SF2 master MDIO bus.
Ensure that of_phy_connect() does not suceed by removing any phandle
reference for the PHY we need to divert. This forces the DSA code to use
the DSA slave_mii_bus that we register and ensures the MDIO diversion is
being used.
Signed-off-by: Florian Fainelli
---
drivers/net/dsa/bcm_sf2.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
index 1c7fbb6f0447..8e215c148487 100644
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
@@ -489,9 +489,11 @@ static void bcm_sf2_identify_ports(struct bcm_sf2_priv
*priv,
static int bcm_sf2_mdio_register(struct dsa_switch *ds)
{
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
- struct device_node *dn;
+ struct device_node *dn, *child;
+ struct phy_device *phydev;
+ struct property *prop;
static int index;
- int err;
+ int err, reg;
/* Find our integrated MDIO bus node */
dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
@@ -534,6 +536,31 @@ static int bcm_sf2_mdio_register(struct dsa_switch *ds)
priv->slave_mii_bus->parent = ds->dev->parent;
priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
+ /* We need to make sure that of_phy_connect() will not work by
+* removing the 'phandle' and 'linux,phandle' properties and
+* unregister the existing PHY device that was already registered.
+*/
+ for_each_available_child_of_node(dn, child) {
+ if (of_property_read_u32(child, "reg", ) ||
+ reg >= PHY_MAX_ADDR)
+ continue;
+
+ if (!(priv->indir_phy_mask & BIT(reg)))
+ continue;
+
+ prop = of_find_property(child, "phandle", NULL);
+ if (prop)
+ of_remove_property(child, prop);
+
+ prop = of_find_property(child, "linux,phandle", NULL);
+ if (prop)
+ of_remove_property(child, prop);
+
+ phydev = of_phy_find_device(child);
+ if (phydev)
+ phy_device_remove(phydev);
+ }
+
err = mdiobus_register(priv->slave_mii_bus);
if (err && dn)
of_node_put(dn);
--
2.25.1
Re: [PATCH net] net: dp83867: Fix WoL SecureOn password
On 9/2/2020 12:27 PM, Dan Murphy wrote:
Fix the registers being written to as the values were being over written
when writing the same registers.
Fixes: caabee5b53f5 ("net: phy: dp83867: support Wake on LAN")
Signed-off-by: Dan Murphy
Reviewed-by: Florian Fainelli
--
Florian
Re: [RFT 06/11] mmc: sdhci-brcmstb: Simplify with optional clock and dev_err_probe()
On 9/2/2020 12:36 PM, Krzysztof Kozlowski wrote: Only -ENOENT from devm_clk_get() means that clock is not present in device tree. Other errors have their own meaning and should not be ignored. Simplify getting the clock which is in fact optional and also use dev_err_probe() for handling deferred. Signed-off-by: Krzysztof Kozlowski This is actually an open coded version of devm_clk_get_optional(), so this is fine: Acked-by: Florian Fainelli -- Florian
Re: [PATCH 01/11] mmc: bcm2835: Simplify with dev_err_probe()
On 9/2/2020 12:36 PM, Krzysztof Kozlowski wrote: Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski Acked-by: Florian Fainelli -- Florian
Re: [PATCH] net: bcmgenet: fix mask check in bcmgenet_validate_flow()
On 9/2/2020 4:18 AM, Denis Efremov wrote:
VALIDATE_MASK(eth_mask->h_source) is checked twice in a row in
bcmgenet_validate_flow(). Add VALIDATE_MASK(eth_mask->h_dest)
instead.
Fixes: 3e370952287c ("net: bcmgenet: add support for ethtool rxnfc flows")
Cc: sta...@vger.kernel.org
Signed-off-by: Denis Efremov
Acked-by: Florian Fainelli
--
Florian
Re: [PATCH 3/9] i2c: bcm2835: Simplify with dev_err_probe()
On 9/2/2020 8:06 AM, Krzysztof Kozlowski wrote: Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski Acked-by: Florian Fainelli -- Florian
Re: [PATCH v2 3/6] ARM: dts: NSP: Fix SP804 compatible node
On 8/28/2020 10:12 AM, Florian Fainelli wrote:
On 8/28/20 7:20 AM, Andre Przywara wrote:
The DT binding for SP804 requires to have an "arm,primecell" compatible
string.
Add this string so that the Linux primecell bus driver picks the device
up and activates the clock.
Fixes: a0efb0d28b77 ("ARM: dts: NSP: Add SP804 Support to DT")
Tested-by: Florian Fainelli
Signed-off-by: Andre Przywara
This looks fine, however there is a ccbtimer1 instance that you missed,
can you resubmit with it included?
With that:
Acked-by: Florian Fainelli
Andre are you going to resubmit a patch with the second instance
(ccbtimer1) fixed as well, or should I take care of that while applying
the patch? Either way is fine, just let me know.
--
Florian
[PATCH net-next 2/3] net: dsa: bcm_sf2: request and handle clocks
Fetch the corresponding clock resource and enable/disable it during
suspend/resume if and only if we have no ports defined for Wake-on-LAN.
Signed-off-by: Florian Fainelli
---
drivers/net/dsa/bcm_sf2.c | 20 ++--
drivers/net/dsa/bcm_sf2.h | 2 ++
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
index bafddb35f3a9..b8fa0a46c5c9 100644
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -750,6 +751,9 @@ static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
bcm_sf2_port_disable(ds, port);
}
+ if (!priv->wol_ports_mask)
+ clk_disable_unprepare(priv->clk);
+
return 0;
}
@@ -758,6 +762,9 @@ static int bcm_sf2_sw_resume(struct dsa_switch *ds)
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
int ret;
+ if (!priv->wol_ports_mask)
+ clk_prepare_enable(priv->clk);
+
ret = bcm_sf2_sw_rst(priv);
if (ret) {
pr_err("%s: failed to software reset switch\n", __func__);
@@ -1189,10 +1196,16 @@ static int bcm_sf2_sw_probe(struct platform_device
*pdev)
base++;
}
+ priv->clk = devm_clk_get_optional(>dev, "sw_switch");
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+
+ clk_prepare_enable(priv->clk);
+
ret = bcm_sf2_sw_rst(priv);
if (ret) {
pr_err("unable to software reset switch: %d\n", ret);
- return ret;
+ goto out_clk;
}
bcm_sf2_gphy_enable_set(priv->dev->ds, true);
@@ -1200,7 +1213,7 @@ static int bcm_sf2_sw_probe(struct platform_device *pdev)
ret = bcm_sf2_mdio_register(ds);
if (ret) {
pr_err("failed to register MDIO bus\n");
- return ret;
+ goto out_clk;
}
bcm_sf2_gphy_enable_set(priv->dev->ds, false);
@@ -1267,6 +1280,8 @@ static int bcm_sf2_sw_probe(struct platform_device *pdev)
out_mdio:
bcm_sf2_mdio_unregister(priv);
+out_clk:
+ clk_disable_unprepare(priv->clk);
return ret;
}
@@ -1280,6 +1295,7 @@ static int bcm_sf2_sw_remove(struct platform_device *pdev)
dsa_unregister_switch(priv->dev->ds);
bcm_sf2_cfp_exit(priv->dev->ds);
bcm_sf2_mdio_unregister(priv);
+ clk_disable_unprepare(priv->clk);
if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev))
reset_control_assert(priv->rcdev);
diff --git a/drivers/net/dsa/bcm_sf2.h b/drivers/net/dsa/bcm_sf2.h
index de386dd96d66..6dd69922e3f6 100644
--- a/drivers/net/dsa/bcm_sf2.h
+++ b/drivers/net/dsa/bcm_sf2.h
@@ -93,6 +93,8 @@ struct bcm_sf2_priv {
/* Mask of ports enabled for Wake-on-LAN */
u32 wol_ports_mask;
+ struct clk *clk;
+
/* MoCA port location */
int moca_port;
--
2.25.1
[PATCH net-next 3/3] net: dsa: bcm_sf2: recalculate switch clock rate based on ports
Whenever a port gets enabled/disabled, recalcultate the required switch
clock rate to make sure it always gets set to the expected rate
targeting our switch use case. This is only done for the BCM7445 switch
as there is no clocking profile available for BCM7278.
Signed-off-by: Florian Fainelli
---
drivers/net/dsa/bcm_sf2.c | 68 +--
drivers/net/dsa/bcm_sf2.h | 2 ++
2 files changed, 68 insertions(+), 2 deletions(-)
diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
index b8fa0a46c5c9..1c7fbb6f0447 100644
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
@@ -32,6 +32,49 @@
#include "b53/b53_priv.h"
#include "b53/b53_regs.h"
+/* Return the number of active ports, not counting the IMP (CPU) port */
+static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
+{
+ struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
+ unsigned int port, count = 0;
+
+ for (port = 0; port < ARRAY_SIZE(priv->port_sts); port++) {
+ if (dsa_is_cpu_port(ds, port))
+ continue;
+ if (priv->port_sts[port].enabled)
+ count++;
+ }
+
+ return count;
+}
+
+static void bcm_sf2_recalc_clock(struct dsa_switch *ds)
+{
+ struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
+ unsigned long new_rate;
+ unsigned int ports_active;
+ /* Frequenty in Mhz */
+ const unsigned long rate_table[] = {
+ 5922,
+ 6082,
+ 6250,
+ 6250,
+ };
+
+ ports_active = bcm_sf2_num_active_ports(ds);
+ if (ports_active == 0 || !priv->clk_mdiv)
+ return;
+
+ /* If we overflow our table, just use the recommended operational
+* frequency
+*/
+ if (ports_active > ARRAY_SIZE(rate_table))
+ new_rate = 9000;
+ else
+ new_rate = rate_table[ports_active - 1];
+ clk_set_rate(priv->clk_mdiv, new_rate);
+}
+
static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
{
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
@@ -83,6 +126,8 @@ static void bcm_sf2_imp_setup(struct dsa_switch *ds, int
port)
reg &= ~(RX_DIS | TX_DIS);
core_writel(priv, reg, CORE_G_PCTL_PORT(port));
}
+
+ priv->port_sts[port].enabled = true;
}
static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
@@ -168,6 +213,10 @@ static int bcm_sf2_port_setup(struct dsa_switch *ds, int
port,
if (!dsa_is_user_port(ds, port))
return 0;
+ priv->port_sts[port].enabled = true;
+
+ bcm_sf2_recalc_clock(ds);
+
/* Clear the memory power down */
reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
reg &= ~P_TXQ_PSM_VDD(port);
@@ -261,6 +310,10 @@ static void bcm_sf2_port_disable(struct dsa_switch *ds,
int port)
reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
reg |= P_TXQ_PSM_VDD(port);
core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
+
+ priv->port_sts[port].enabled = false;
+
+ bcm_sf2_recalc_clock(ds);
}
@@ -1202,10 +1255,18 @@ static int bcm_sf2_sw_probe(struct platform_device
*pdev)
clk_prepare_enable(priv->clk);
+ priv->clk_mdiv = devm_clk_get_optional(>dev, "sw_switch_mdiv");
+ if (IS_ERR(priv->clk_mdiv)) {
+ ret = PTR_ERR(priv->clk_mdiv);
+ goto out_clk;
+ }
+
+ clk_prepare_enable(priv->clk_mdiv);
+
ret = bcm_sf2_sw_rst(priv);
if (ret) {
pr_err("unable to software reset switch: %d\n", ret);
- goto out_clk;
+ goto out_clk_mdiv;
}
bcm_sf2_gphy_enable_set(priv->dev->ds, true);
@@ -1213,7 +1274,7 @@ static int bcm_sf2_sw_probe(struct platform_device *pdev)
ret = bcm_sf2_mdio_register(ds);
if (ret) {
pr_err("failed to register MDIO bus\n");
- goto out_clk;
+ goto out_clk_mdiv;
}
bcm_sf2_gphy_enable_set(priv->dev->ds, false);
@@ -1280,6 +1341,8 @@ static int bcm_sf2_sw_probe(struct platform_device *pdev)
out_mdio:
bcm_sf2_mdio_unregister(priv);
+out_clk_mdiv:
+ clk_disable_unprepare(priv->clk_mdiv);
out_clk:
clk_disable_unprepare(priv->clk);
return ret;
@@ -1295,6 +1358,7 @@ static int bcm_sf2_sw_remove(struct platform_device *pdev)
dsa_unregister_switch(priv->dev->ds);
bcm_sf2_cfp_exit(priv->dev->ds);
bcm_sf2_mdio_unregister(priv);
+ clk_disable_unprepare(priv->clk_mdiv);
clk_disable_unprepare(priv->clk);
if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev))
reset_control_assert(priv->rcdev);
diff --git a/d
[PATCH net-next 1/3] dt-bindings: net: Document Broadcom SF2 switch clocks
Describe the two possible clocks feeding into the Broadcom SF2 integrated Ethernet switch. BCM7445 systems have two clocks, one for the main switch core clock, and another for controlling the switch clock divider whereas BCM7278 systems only have the first kind. Signed-off-by: Florian Fainelli --- .../devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt | 7 +++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt b/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt index 88b57b0ca1f4..97ca62b0e14d 100644 --- a/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt +++ b/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt @@ -50,6 +50,13 @@ Optional properties: - reset-names: If the "reset" property is specified, this property should have the value "switch" to denote the switch reset line. +- clocks: when provided, the first phandle is to the switch's main clock and + is valid for both BCM7445 and BCM7278. The second phandle is only applicable + to BCM7445 and is to support dividing the switch core clock. + +- clock-names: when provided, the first phandle must be "sw_switch", and the + second must be named "sw_switch_mdiv". + Port subnodes: Optional properties: -- 2.25.1
[PATCH net-next 0/3] net: dsa: bcm_sf2: Clock support
Hi David, This patch series adds support for controlling the SF2 switch core and divider clock (where applicable). Florian Fainelli (3): dt-bindings: net: Document Broadcom SF2 switch clocks net: dsa: bcm_sf2: request and handle clocks net: dsa: bcm_sf2: recalculate switch clock rate based on ports .../bindings/net/brcm,bcm7445-switch-v4.0.txt | 7 ++ drivers/net/dsa/bcm_sf2.c | 84 ++- drivers/net/dsa/bcm_sf2.h | 4 + 3 files changed, 93 insertions(+), 2 deletions(-) -- 2.25.1
[PATCH net-next 0/3] net: systemport: Clock support
Hi David, This patch series makes the SYSTEMPORT driver request and manage its main and Wake-on-LAN clocks appropriately. Florian Fainelli (3): dt-bindings: net: Document Broadcom SYSTEMPORT clocks net: systemport: fetch and use clock resources net: systemport: Manage Wake-on-LAN clock .../bindings/net/brcm,systemport.txt | 5 +++ drivers/net/ethernet/broadcom/bcmsysport.c| 40 ++- drivers/net/ethernet/broadcom/bcmsysport.h| 2 + 3 files changed, 45 insertions(+), 2 deletions(-) -- 2.25.1
[PATCH net-next 1/3] dt-bindings: net: Document Broadcom SYSTEMPORT clocks
The Broadcom SYSTEMPORT adapters require the use of two clocks for
normal operations and during Wake-on-LAN, document those in the binding
document.
Signed-off-by: Florian Fainelli
---
Documentation/devicetree/bindings/net/brcm,systemport.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/brcm,systemport.txt
b/Documentation/devicetree/bindings/net/brcm,systemport.txt
index 83f29e0e11ba..745bb1776572 100644
--- a/Documentation/devicetree/bindings/net/brcm,systemport.txt
+++ b/Documentation/devicetree/bindings/net/brcm,systemport.txt
@@ -20,6 +20,11 @@ Optional properties:
- systemport,num-tier1-arb: number of tier 1 arbiters, an integer
- systemport,num-txq: number of HW transmit queues, an integer
- systemport,num-rxq: number of HW receive queues, an integer
+- clocks: When provided, must be two phandles to the functional clocks nodes of
+ the SYSTEMPORT block. The first phandle is the main SYSTEMPORT clock used
+ during normal operation, while the second phandle is the Wake-on-LAN clock.
+- clock-names: When provided, names of the functional clock phandles, first
+ name should be "sw_sysport" and second should be "sw_sysportwol".
Example:
ethernet@f04a {
--
2.25.1
[PATCH net-next 3/3] net: systemport: Manage Wake-on-LAN clock
It is necessary to manage the Wake-on-LAN clock to turn on the
appropriate blocks for MPD or CFP-based packet matching to work
otherwise we will not be able to reliably match packets during suspend.
Reported-by: Blair Prescott
Signed-off-by: Florian Fainelli
---
drivers/net/ethernet/broadcom/bcmsysport.c | 10 +-
drivers/net/ethernet/broadcom/bcmsysport.h | 1 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/broadcom/bcmsysport.c
b/drivers/net/ethernet/broadcom/bcmsysport.c
index 91eadba5540c..b25c70b74c92 100644
--- a/drivers/net/ethernet/broadcom/bcmsysport.c
+++ b/drivers/net/ethernet/broadcom/bcmsysport.c
@@ -2583,6 +2583,10 @@ static int bcm_sysport_probe(struct platform_device
*pdev)
if (!ret)
device_set_wakeup_capable(>dev, 1);
+ priv->wol_clk = devm_clk_get_optional(>dev, "sw_sysportwol");
+ if (IS_ERR(priv->wol_clk))
+ return PTR_ERR(priv->wol_clk);
+
/* Set the needed headroom once and for all */
BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8);
dev->needed_headroom += sizeof(struct bcm_tsb);
@@ -2772,8 +2776,10 @@ static int __maybe_unused bcm_sysport_suspend(struct
device *d)
bcm_sysport_fini_rx_ring(priv);
/* Get prepared for Wake-on-LAN */
- if (device_may_wakeup(d) && priv->wolopts)
+ if (device_may_wakeup(d) && priv->wolopts) {
+ clk_prepare_enable(priv->wol_clk);
ret = bcm_sysport_suspend_to_wol(priv);
+ }
clk_disable_unprepare(priv->clk);
@@ -2791,6 +2797,8 @@ static int __maybe_unused bcm_sysport_resume(struct
device *d)
return 0;
clk_prepare_enable(priv->clk);
+ if (priv->wolopts)
+ clk_disable_unprepare(priv->wol_clk);
umac_reset(priv);
diff --git a/drivers/net/ethernet/broadcom/bcmsysport.h
b/drivers/net/ethernet/broadcom/bcmsysport.h
index 51800053e88c..3a5cb6f128f5 100644
--- a/drivers/net/ethernet/broadcom/bcmsysport.h
+++ b/drivers/net/ethernet/broadcom/bcmsysport.h
@@ -771,6 +771,7 @@ struct bcm_sysport_priv {
u8 sopass[SOPASS_MAX];
unsigned intwol_irq_disabled:1;
struct clk *clk;
+ struct clk *wol_clk;
/* MIB related fields */
struct bcm_sysport_mib mib;
--
2.25.1
[PATCH net-next 2/3] net: systemport: fetch and use clock resources
We disable clocks shortly after probing the device to save as much power as
possible in case the interface is never used. When bcm_sysport_open() is
invoked, clocks are enabled, and disabled in bcm_sysport_stop().
A similar scheme is applied to the suspend/resume functions.
Signed-off-by: Florian Fainelli
---
drivers/net/ethernet/broadcom/bcmsysport.c | 30 +-
drivers/net/ethernet/broadcom/bcmsysport.h | 1 +
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/broadcom/bcmsysport.c
b/drivers/net/ethernet/broadcom/bcmsysport.c
index dfed9ade6950..91eadba5540c 100644
--- a/drivers/net/ethernet/broadcom/bcmsysport.c
+++ b/drivers/net/ethernet/broadcom/bcmsysport.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
@@ -186,6 +187,11 @@ static int bcm_sysport_set_features(struct net_device *dev,
netdev_features_t features)
{
struct bcm_sysport_priv *priv = netdev_priv(dev);
+ int ret;
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret)
+ return ret;
/* Read CRC forward */
if (!priv->is_lite)
@@ -197,6 +203,8 @@ static int bcm_sysport_set_features(struct net_device *dev,
bcm_sysport_set_rx_csum(dev, features);
bcm_sysport_set_tx_csum(dev, features);
+ clk_disable_unprepare(priv->clk);
+
return 0;
}
@@ -1940,6 +1948,8 @@ static int bcm_sysport_open(struct net_device *dev)
unsigned int i;
int ret;
+ clk_prepare_enable(priv->clk);
+
/* Reset UniMAC */
umac_reset(priv);
@@ -1970,7 +1980,8 @@ static int bcm_sysport_open(struct net_device *dev)
0, priv->phy_interface);
if (!phydev) {
netdev_err(dev, "could not attach to PHY\n");
- return -ENODEV;
+ ret = -ENODEV;
+ goto out_clk_disable;
}
/* Reset house keeping link status */
@@ -2048,6 +2059,8 @@ static int bcm_sysport_open(struct net_device *dev)
free_irq(priv->irq0, dev);
out_phy_disconnect:
phy_disconnect(phydev);
+out_clk_disable:
+ clk_disable_unprepare(priv->clk);
return ret;
}
@@ -2106,6 +2119,8 @@ static int bcm_sysport_stop(struct net_device *dev)
/* Disconnect from PHY */
phy_disconnect(dev->phydev);
+ clk_disable_unprepare(priv->clk);
+
return 0;
}
@@ -2487,6 +2502,10 @@ static int bcm_sysport_probe(struct platform_device
*pdev)
/* Initialize private members */
priv = netdev_priv(dev);
+ priv->clk = devm_clk_get_optional(>dev, "sw_sysport");
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+
/* Allocate number of TX rings */
priv->tx_rings = devm_kcalloc(>dev, txq,
sizeof(struct bcm_sysport_tx_ring),
@@ -2588,6 +2607,8 @@ static int bcm_sysport_probe(struct platform_device *pdev)
goto err_deregister_notifier;
}
+ clk_prepare_enable(priv->clk);
+
priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK;
dev_info(>dev,
"Broadcom SYSTEMPORT%s " REV_FMT
@@ -2596,6 +2617,8 @@ static int bcm_sysport_probe(struct platform_device *pdev)
(priv->rev >> 8) & 0xff, priv->rev & 0xff,
priv->irq0, priv->irq1, txq, rxq);
+ clk_disable_unprepare(priv->clk);
+
return 0;
err_deregister_notifier:
@@ -2752,6 +2775,8 @@ static int __maybe_unused bcm_sysport_suspend(struct
device *d)
if (device_may_wakeup(d) && priv->wolopts)
ret = bcm_sysport_suspend_to_wol(priv);
+ clk_disable_unprepare(priv->clk);
+
return ret;
}
@@ -2765,6 +2790,8 @@ static int __maybe_unused bcm_sysport_resume(struct
device *d)
if (!netif_running(dev))
return 0;
+ clk_prepare_enable(priv->clk);
+
umac_reset(priv);
/* Disable the UniMAC RX/TX */
@@ -2844,6 +2871,7 @@ static int __maybe_unused bcm_sysport_resume(struct
device *d)
out_free_tx_rings:
for (i = 0; i < dev->num_tx_queues; i++)
bcm_sysport_fini_tx_ring(priv, i);
+ clk_disable_unprepare(priv->clk);
return ret;
}
diff --git a/drivers/net/ethernet/broadcom/bcmsysport.h
b/drivers/net/ethernet/broadcom/bcmsysport.h
index 6d80735fbc7f..51800053e88c 100644
--- a/drivers/net/ethernet/broadcom/bcmsysport.h
+++ b/drivers/net/ethernet/broadcom/bcmsysport.h
@@ -770,6 +770,7 @@ struct bcm_sysport_priv {
u32 wolopts;
u8 sopass[SOPASS_MAX];
unsigned intwol_irq_disabled:1;
+ struct clk *clk;
/* MIB related fields */
struct bcm_sysport_mib mib;
--
2.25.1
Re: RFC: backport of commit a32c1c61212d
On 9/1/2020 9:06 AM, Doug Berger wrote:
On 9/1/2020 7:00 AM, Greg Kroah-Hartman wrote:
[snip]
Sorry for the confusion, but thanks for the reply.
There is functionality that exists in Linus' tree, but it is not the
result of a single commit that can be easily backported. I have been
unable to find anything in the documentation for submitting a patch to a
stable branch that covers this type of submission so I have sent this as
an RFC about process rather than a patch.
The upstream commit that ultimately results in the functional change is:
commit a32c1c61212d ("arm: simplify detection of memory zone boundaries")
That commit is dependent on other commits that aren't necessary for the
stable branches.
In my downstream kernel I would apply the single line patch included in
my original email, but it is not appropriate to apply that patch to
Linus' tree since the problem does not exist there.
This creates the situation where a simple patch could be applied to a
stable branch to improve its stability, but there is not a clear
upstream commit to reference.
My best guess at this point is to submit patches to the affected stable
branches like the one in my RFC and reference a32c1c61212d as the
upstream commit. This would be confusing to anyone that tried to compare
the submitted patch with the upstream patch since they
wouldn't look at all alike, but the fixes and upstream tags would define
the affected range in Linus' tree.
I would appreciate any guidance on how best to handle this kind of
situation.
You could submit various patches with [PATCH stable x.y] in the subject
to indicate they are targeting a specific stable branch, copy
sta...@vger.kernel.org as well as all recipients in this email and see
if that works.
Not sure if there is a more documented process than that.
--
Florian
Re: [PATCH 1/2] serial: 8250: Simplify with dev_err_probe()
On 9/1/2020 8:30 AM, Krzysztof Kozlowski wrote:
Common pattern of handling deferred probe can be simplified with
dev_err_probe(). Less code and the error value gets printed.
Signed-off-by: Krzysztof Kozlowski
---
drivers/tty/serial/8250/8250_bcm2835aux.c | 12 +++-
drivers/tty/serial/8250/8250_ingenic.c| 20 ++--
2 files changed, 9 insertions(+), 23 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_bcm2835aux.c
b/drivers/tty/serial/8250/8250_bcm2835aux.c
index 12d03e678295..fd95860cd661 100644
--- a/drivers/tty/serial/8250/8250_bcm2835aux.c
+++ b/drivers/tty/serial/8250/8250_bcm2835aux.c
@@ -110,12 +110,8 @@ static int bcm2835aux_serial_probe(struct platform_device
*pdev)
/* get the clock - this also enables the HW */
data->clk = devm_clk_get(>dev, NULL);
- ret = PTR_ERR_OR_ZERO(data->clk);
- if (ret) {
- if (ret != -EPROBE_DEFER)
- dev_err(>dev, "could not get clk: %d\n", ret);
- return ret;
- }
+ if (IS_ERR(data->clk))
+ return dev_err_probe(>dev, PTR_ERR(data->clk), "could not get
clk\n");
For 8250_bcm2835aux.c:
Acked-by: Florian Fainelli
--
Florian
Re: [PATCH 04/11] spi: bcm2835: Simplify with dev_err_probe()
On 9/1/2020 8:27 AM, Krzysztof Kozlowski wrote: Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski Acked-by: Florian Fainelli -- Florian
Re: [PATCH 1/1] ARM: dts: bcm2711: Enable ddr modes on emmc2 controller
On 8/29/2020 4:15 PM, Tobias Schramm wrote:
This patch enables ddr modes for eMMC and SD storage on emmc2,
doubling transfer speed. Previously only single data rate modes were
used, wasting half the available throughput.
The bcm2711 supports both SD and eMMC storage using ddr modes. Testing
show that pcb layout of the Raspberry Pi 4 can support them, too.
Signed-off-by: Tobias Schramm
This depends on Stefan's patch here:
https://lore.kernel.org/linux-arm-kernel/1598651234-29826-1-git-send-email-stefan.wah...@i2se.com/
I am fine with us taking the DTS patch, as long as they all land in 5.10
at some point.
---
arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
index 222d7825e1ab..8b61e258e906 100644
--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
@@ -191,6 +191,8 @@ {
vqmmc-supply = <_io_1v8_reg>;
vmmc-supply = <_vcc_reg>;
broken-cd;
+ mmc-ddr-3_3v;
+ sd-uhs-ddr50;
status = "okay";
};
--
Florian
Re: [PATCH 0/5] qspi binding and DTS fixes
On 8/27/2020 11:18 AM, Florian Fainelli wrote: Hi all, This patch series fixes incorrectly defined compatible strings for the Broadcom QSPI controller which resulted in the strings not being ordered from most to least compatible. We will need to apply some changes to the spi-bcm-qspi.c driver in the future to assume no revision register exist, and these patches are a preliminary step towards that goal. Rob, can I get your tag for this patch series so it can be sent out? Thanks! Florian Fainelli (5): dt-bindings: spi: Fix spi-bcm-qspi compatible ordering ARM: dts: bcm: HR2: Fixed QSPI compatible string ARM: dts: NSP: Fixed QSPI compatible string ARM: dts: BCM5301X: Fixed QSPI compatible string arm64: dts: ns2: Fixed QSPI compatible string .../bindings/spi/brcm,spi-bcm-qspi.txt | 16 arch/arm/boot/dts/bcm-hr2.dtsi | 2 +- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- arch/arm/boot/dts/bcm5301x.dtsi | 2 +- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 +- 5 files changed, 12 insertions(+), 12 deletions(-) -- Florian
Re: [PATCH 08/10] ARM: dts: Cygnus: Fix SP805 clocks
On 8/30/2020 8:55 PM, Florian Fainelli wrote: On Fri, 28 Aug 2020 14:06:00 +0100, Andre Przywara wrote: The SP805 DT binding requires two clocks to be specified, but the Broadcom Cygnus DT currently only specifies one clock. In practice, Linux would pick a clock named "apb_pclk" for the bus clock, and the Linux and U-Boot SP805 driver would use the first clock to derive the actual watchdog counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara --- Applied to qspi-fixes, thanks! Applied to devicetree/next actually, likewise for the next patch. -- Florian
Re: [PATCH 03/10] arm64: dts: broadcom: Fix SP805 clock-names
On Fri, 28 Aug 2020 14:05:55 +0100, Andre Przywara wrote: > The SP805 binding sets the name for the actual watchdog clock to > "wdog_clk" (with an underscore). > > Change the name in the DTs for Broadcom platforms to match that. The > Linux and U-Boot driver use the *first* clock for this purpose anyway, > so it does not break anything. > > Signed-off-by: Andre Przywara > --- Applied to devicetree-arm64/next, thanks! -- Florian
Re: [PATCH 09/10] ARM: dts: NSP: Fix SP805 clock-names
On Fri, 28 Aug 2020 14:06:01 +0100, Andre Przywara wrote: > The SP805 binding sets the name for the actual watchdog clock to > "wdog_clk" (with an underscore). > > Change the name in the DTs for the Broadcom NSP platform to match that. > The Linux and U-Boot driver use the *first* clock for this purpose > anyway, so it does not break anything. > > Signed-off-by: Andre Przywara > --- Applied to qspi-fixes, thanks! -- Florian
Re: [PATCH 08/10] ARM: dts: Cygnus: Fix SP805 clocks
On Fri, 28 Aug 2020 14:06:00 +0100, Andre Przywara wrote: > The SP805 DT binding requires two clocks to be specified, but the > Broadcom Cygnus DT currently only specifies one clock. > > In practice, Linux would pick a clock named "apb_pclk" for the bus > clock, and the Linux and U-Boot SP805 driver would use the first clock > to derive the actual watchdog counter frequency. > > Since currently both are the very same clock, we can just double the > clock reference, and add the correct clock-names, to match the binding. > > Signed-off-by: Andre Przywara > --- Applied to qspi-fixes, thanks! -- Florian
Re: [PATCH 00/10] dt-bindings: Convert SP805 to Json-schema (and fix users)
On 8/28/20 2:28 PM, Rob Herring wrote: > On Fri, Aug 28, 2020 at 1:34 PM Florian Fainelli wrote: >> >> On 8/28/20 6:05 AM, Andre Przywara wrote: >>> This is an attempt to convert the SP805 watchdog DT binding to yaml. >>> This is done in the first patch, the remaining nine fix some DT users. >>> >>> I couldn't test any of those DT files on actual machines, but tried >>> to make the changes in a way that would be transparent to at least the >>> Linux driver. The only other SP805 DT user I could find is U-Boot, which >>> seems to only use a very minimal subset of the binding (just the first >>> clock). >>> I only tried to fix those DTs that were easily and reliably fixable. >>> AFAICT, a missing primecell compatible string, for instance, would >>> prevent the Linux driver from probing the device at all, so I didn't >>> dare to touch those DTs at all. Missing clocks are equally fatal. >> >> What is the plan for merging this series? Should Rob pick up all changes >> or since those are non critical changes, should we just leave it to the >> SoC maintainers to pick up the changes in their tree? > > I don't take .dts files. Either subarch maintainers can pick up > individual patches or send a PR to SoC maintainers. OK, so we are fine, to say make sure this all lands in v5.10-rc1 at some point and the warnings should no longer exist by then? -- Florian
Re: [PATCH 00/10] dt-bindings: Convert SP805 to Json-schema (and fix users)
On 8/28/20 6:05 AM, Andre Przywara wrote: > This is an attempt to convert the SP805 watchdog DT binding to yaml. > This is done in the first patch, the remaining nine fix some DT users. > > I couldn't test any of those DT files on actual machines, but tried > to make the changes in a way that would be transparent to at least the > Linux driver. The only other SP805 DT user I could find is U-Boot, which > seems to only use a very minimal subset of the binding (just the first > clock). > I only tried to fix those DTs that were easily and reliably fixable. > AFAICT, a missing primecell compatible string, for instance, would > prevent the Linux driver from probing the device at all, so I didn't > dare to touch those DTs at all. Missing clocks are equally fatal. What is the plan for merging this series? Should Rob pick up all changes or since those are non critical changes, should we just leave it to the SoC maintainers to pick up the changes in their tree? Likewise for the SP804 timer series, what's the plan? -- Florian
Re: [PATCH 03/10] arm64: dts: broadcom: Fix SP805 clock-names
On 8/28/20 6:05 AM, Andre Przywara wrote: > The SP805 binding sets the name for the actual watchdog clock to > "wdog_clk" (with an underscore). > > Change the name in the DTs for Broadcom platforms to match that. The > Linux and U-Boot driver use the *first* clock for this purpose anyway, > so it does not break anything. Not that it really matters because the driver does a devm_clk_get(>dev, NULL), but yes, this should be fixed to conform to the binding. > > Signed-off-by: Andre Przywara Acked-by: Florian Fainelli -- Florian
Re: [PATCH 09/10] ARM: dts: NSP: Fix SP805 clock-names
On 8/28/20 6:06 AM, Andre Przywara wrote: > The SP805 binding sets the name for the actual watchdog clock to > "wdog_clk" (with an underscore). > > Change the name in the DTs for the Broadcom NSP platform to match that. > The Linux and U-Boot driver use the *first* clock for this purpose > anyway, so it does not break anything. > > Signed-off-by: Andre Przywara Acked-by: Florian Fainelli -- Florian
Re: [PATCH 08/10] ARM: dts: Cygnus: Fix SP805 clocks
On 8/28/20 6:06 AM, Andre Przywara wrote: > The SP805 DT binding requires two clocks to be specified, but the > Broadcom Cygnus DT currently only specifies one clock. > > In practice, Linux would pick a clock named "apb_pclk" for the bus > clock, and the Linux and U-Boot SP805 driver would use the first clock > to derive the actual watchdog counter frequency. > > Since currently both are the very same clock, we can just double the > clock reference, and add the correct clock-names, to match the binding. > > Signed-off-by: Andre Przywara Acked-by: Florian Fainelli -- Florian
Re: [PATCH 1/6] gpio: bcm-kona: Simplify with dev_err_probe()
On 8/27/20 1:08 PM, Krzysztof Kozlowski wrote: > Common pattern of handling deferred probe can be simplified with > dev_err_probe(). Less code and also it prints the error value. > > Signed-off-by: Krzysztof Kozlowski Acked-by: Florian Fainelli -- Florian
Re: [PATCH v2 3/6] ARM: dts: NSP: Fix SP804 compatible node
On 8/28/20 7:20 AM, Andre Przywara wrote:
> The DT binding for SP804 requires to have an "arm,primecell" compatible
> string.
> Add this string so that the Linux primecell bus driver picks the device
> up and activates the clock.
>
> Fixes: a0efb0d28b77 ("ARM: dts: NSP: Add SP804 Support to DT")
> Tested-by: Florian Fainelli
> Signed-off-by: Andre Przywara
This looks fine, however there is a ccbtimer1 instance that you missed,
can you resubmit with it included?
With that:
Acked-by: Florian Fainelli
--
Florian
Re: [PATCH 1/2] memory: brcmstb_dpfe: Simplify with dev_err_probe()
On 8/28/20 8:37 AM, Krzysztof Kozlowski wrote: > Common pattern of handling deferred probe can be simplified with > dev_err_probe(). Less code and the error value gets printed. > > Signed-off-by: Krzysztof Kozlowski Acked-by: Florian Fainelli -- Florian
Re: [PATCH] net: dsa: mt7530: fix advertising unsupported
On 8/27/2020 2:15 AM, Landen Chao wrote:
1000baseT_Half
Looks like this part of the commit subject spilled into the commit message.
Remove 1000baseT_Half to advertise correct hardware capability in
phylink_validate() callback function.
Fixes: 38f790a80560 ("net: dsa: mt7530: Add support for port 5")
Signed-off-by: Landen Chao
Reviewed-by: Florian Fainelli
--
Florian
[PATCH 5/5] arm64: dts: ns2: Fixed QSPI compatible string
The string was incorrectly defined before from least to most specific,
swap the compatible strings accordingly.
Fixes: ff73917d38a6 ("ARM64: dts: Add QSPI Device Tree node for NS2")
Signed-off-by: Florian Fainelli
---
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
index 15f7b0ed3836..39802066232e 100644
--- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
@@ -745,7 +745,7 @@ nand: nand@6646 {
};
qspi: spi@66470200 {
- compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
+ compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
reg = <0x66470200 0x184>,
<0x6647 0x124>,
<0x67017408 0x004>,
--
2.25.1
[PATCH 2/5] ARM: dts: bcm: HR2: Fixed QSPI compatible string
The string was incorrectly defined before from least to most specific,
swap the compatible strings accordingly.
Fixes: b9099ec754b5 ("ARM: dts: Add Broadcom Hurricane 2 DTS include file")
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm-hr2.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi
index cbebed5f050e..e8df458aad39 100644
--- a/arch/arm/boot/dts/bcm-hr2.dtsi
+++ b/arch/arm/boot/dts/bcm-hr2.dtsi
@@ -217,7 +217,7 @@ rng: rng@33000 {
};
qspi: spi@27200 {
- compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
+ compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
reg = <0x027200 0x184>,
<0x027000 0x124>,
<0x11c408 0x004>,
--
2.25.1
[PATCH 1/5] dt-bindings: spi: Fix spi-bcm-qspi compatible ordering
The binding is currently incorrectly defining the compatible strings
from least specific to most specific instead of the converse. Re-order
them from most specific (left) to least specific (right) and fix the
examples as well.
Fixes: 5fc78f4c842a ("spi: Broadcom BRCMSTB, NSP, NS2 SoC bindings")
Signed-off-by: Florian Fainelli
---
.../bindings/spi/brcm,spi-bcm-qspi.txt | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt
b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt
index f5e518d099f2..62d4ed2d7fd7 100644
--- a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt
+++ b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt
@@ -23,8 +23,8 @@ Required properties:
- compatible:
Must be one of :
-"brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs
-"brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+"brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs
+"brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI
BRCMSTB SoCs
"brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" :
Second Instance of MSPI
BRCMSTB SoCs
@@ -36,8 +36,8 @@ Required properties:
BRCMSTB SoCs
"brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" :
Second Instance of MSPI
BRCMSTB SoCs
-"brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : MSPI+BSPI on Cygnus, NSP
-"brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi" : NS2 SoCs
+"brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on Cygnus, NSP
+"brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi" : NS2 SoCs
- reg:
Define the bases and ranges of the associated I/O address spaces.
@@ -86,7 +86,7 @@ BRCMSTB SoC Example:
spi@f03e3400 {
#address-cells = <0x1>;
#size-cells = <0x0>;
- compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-qspi";
+ compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";
reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;
reg-names = "cs_reg", "mspi", "bspi";
interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
@@ -149,7 +149,7 @@ BRCMSTB SoC Example:
#address-cells = <1>;
#size-cells = <0>;
clocks = <_fixed>;
- compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-mspi";
+ compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";
reg = <0xf0416000 0x180>;
reg-names = "mspi";
interrupts = <0x14>;
@@ -160,7 +160,7 @@ BRCMSTB SoC Example:
iProc SoC Example:
qspi: spi@18027200 {
- compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
+ compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
reg = <0x18027200 0x184>,
<0x18027000 0x124>,
<0x1811c408 0x004>,
@@ -191,7 +191,7 @@ iProc SoC Example:
NS2 SoC Example:
qspi: spi@66470200 {
- compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
+ compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
reg = <0x66470200 0x184>,
<0x6647 0x124>,
<0x67017408 0x004>,
--
2.25.1
[PATCH 4/5] ARM: dts: BCM5301X: Fixed QSPI compatible string
The string was incorrectly defined before from least to most
specific, swap the compatible strings accordingly.
Fixes: 1c8f40650723 ("ARM: dts: BCM5301X: convert to iProc QSPI")
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm5301x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 2d9b4dd05830..0016720ce530 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -488,7 +488,7 @@ nand: nand@18028000 {
};
spi@18029200 {
- compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
+ compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
reg = <0x18029200 0x184>,
<0x18029000 0x124>,
<0x1811b408 0x004>,
--
2.25.1
[PATCH 0/5] qspi binding and DTS fixes
Hi all, This patch series fixes incorrectly defined compatible strings for the Broadcom QSPI controller which resulted in the strings not being ordered from most to least compatible. We will need to apply some changes to the spi-bcm-qspi.c driver in the future to assume no revision register exist, and these patches are a preliminary step towards that goal. Florian Fainelli (5): dt-bindings: spi: Fix spi-bcm-qspi compatible ordering ARM: dts: bcm: HR2: Fixed QSPI compatible string ARM: dts: NSP: Fixed QSPI compatible string ARM: dts: BCM5301X: Fixed QSPI compatible string arm64: dts: ns2: Fixed QSPI compatible string .../bindings/spi/brcm,spi-bcm-qspi.txt | 16 arch/arm/boot/dts/bcm-hr2.dtsi | 2 +- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- arch/arm/boot/dts/bcm5301x.dtsi | 2 +- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 +- 5 files changed, 12 insertions(+), 12 deletions(-) -- 2.25.1
[PATCH 3/5] ARM: dts: NSP: Fixed QSPI compatible string
The string was incorrectly defined before from least to most
specific, swap the compatible strings accordingly.
Fixes: 329f98c1974e ("ARM: dts: NSP: Add QSPI nodes to NSPI and bcm958625k
DTSes")
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm-nsp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 0346ea621f0f..c846fa3c244d 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -284,7 +284,7 @@ nand: nand@26000 {
};
qspi: spi@27200 {
- compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
+ compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
reg = <0x027200 0x184>,
<0x027000 0x124>,
<0x11c408 0x004>,
--
2.25.1
Re: [PATCH 3/6] ARM: dts: broadcom: Fix SP804 node
On 8/26/20 11:59 AM, Florian Fainelli wrote:
> On 8/26/20 11:53 AM, André Przywara wrote:
>> On 26/08/2020 19:42, Florian Fainelli wrote:
>>
>> Hi,
>>
>>> On 8/26/20 11:38 AM, Andre Przywara wrote:
>>>> The DT binding for SP804 requires to have an "arm,primecell" compatible
>>>> string.
>>>> Add this string so that the Linux primecell bus driver picks the device
>>>> up and activates the clock.
>>>>
>>>> Signed-off-by: Andre Przywara
>>>
>>> The commit subject should be:
>>>
>>> ARM: dts: NSP: Fix SP804 compatible node
>>>
>>> and we should probably have a Fixes tag that is:
>>>
>>> Fixes: a0efb0d28b77 ("ARM: dts: NSP: Add SP804 Support to DT")
>>>
>>> Could you please re-submit with those things corrected? Thanks
>>
>> Sure, will include that in a v2.
>>
>> Out of curiosity, do you have the hardware and can check the impact that
>> has?
>
> I have the hardware and could run some tests if you would like.
>
>> Not sure we actually create the device without the primecell compatible?
>> Or is the sp804 an exception here, compared to the other AMBA devices
>> (SP805, PL011)?
>
> No idea, I have never used those timers personally, and I doubt that
> anybody besides me within broadcom and hobbyists actually care about NSP
> these days.
Seems to be working fine for me with your patch applied, it probes:
# dmesg | grep sp804
[0.035363] clocksource: arm,sp804: mask: 0x max_cycles:
0x, max_idle_ns: 15290083572 ns
and it is usable:
# cat clocksource0/available_clocksource
arm_global_timer arm,sp804
and appears to work:
# echo "arm,sp804" > clocksource0/current_clocksource
[ 105.108547] clocksource: Switched to clocksource arm,sp804
# date; sleep 5; date
Thu Jan 1 00:01:51 UTC 1970
Thu Jan 1 00:01:56 UTC 1970
Feel free to add Tested-by: Florian Fainelli in
your v2, thanks André!
--
Florian
Re: [PATCH 3/6] ARM: dts: broadcom: Fix SP804 node
On 8/26/20 11:53 AM, André Przywara wrote:
> On 26/08/2020 19:42, Florian Fainelli wrote:
>
> Hi,
>
>> On 8/26/20 11:38 AM, Andre Przywara wrote:
>>> The DT binding for SP804 requires to have an "arm,primecell" compatible
>>> string.
>>> Add this string so that the Linux primecell bus driver picks the device
>>> up and activates the clock.
>>>
>>> Signed-off-by: Andre Przywara
>>
>> The commit subject should be:
>>
>> ARM: dts: NSP: Fix SP804 compatible node
>>
>> and we should probably have a Fixes tag that is:
>>
>> Fixes: a0efb0d28b77 ("ARM: dts: NSP: Add SP804 Support to DT")
>>
>> Could you please re-submit with those things corrected? Thanks
>
> Sure, will include that in a v2.
>
> Out of curiosity, do you have the hardware and can check the impact that
> has?
I have the hardware and could run some tests if you would like.
> Not sure we actually create the device without the primecell compatible?
> Or is the sp804 an exception here, compared to the other AMBA devices
> (SP805, PL011)?
No idea, I have never used those timers personally, and I doubt that
anybody besides me within broadcom and hobbyists actually care about NSP
these days.
--
Florian
Re: [PATCH 3/6] ARM: dts: broadcom: Fix SP804 node
On 8/26/20 11:38 AM, Andre Przywara wrote:
> The DT binding for SP804 requires to have an "arm,primecell" compatible
> string.
> Add this string so that the Linux primecell bus driver picks the device
> up and activates the clock.
>
> Signed-off-by: Andre Przywara
The commit subject should be:
ARM: dts: NSP: Fix SP804 compatible node
and we should probably have a Fixes tag that is:
Fixes: a0efb0d28b77 ("ARM: dts: NSP: Add SP804 Support to DT")
Could you please re-submit with those things corrected? Thanks
> ---
> arch/arm/boot/dts/bcm-nsp.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
> index 0346ea621f0f..1333ef8be0a2 100644
> --- a/arch/arm/boot/dts/bcm-nsp.dtsi
> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
> @@ -368,7 +368,7 @@
> };
>
> ccbtimer0: timer@34000 {
> - compatible = "arm,sp804";
> + compatible = "arm,sp804", "arm,primecell";
> reg = <0x34000 0x1000>;
> interrupts = ,
>;
>
--
Florian
Re: [PATCH 1/6] pwm: bcm2835: Simplify with dev_err_probe()
On 8/26/20 7:47 AM, Krzysztof Kozlowski wrote: > Common pattern of handling deferred probe can be simplified with > dev_err_probe(). Less code and also it prints the error value. > > Signed-off-by: Krzysztof Kozlowski Acked-by: Florian Fainelli -- Florian
Re: [PATCH v11 00/11] PCI: brcmstb: enable PCIe for STB chips
Hi, On 8/24/2020 12:30 PM, Jim Quinlan wrote: Patchset Summary: Enhance a PCIe host controller driver. Because of its unusual design we are foced to change dev->dma_pfn_offset into a more general role allowing multiple offsets. See the 'v1' notes below for more info. We are version 11 and counting, and it is not clear to me whether there is any chance of getting these patches reviewed and hopefully merged for the 5.10 merge window. There are a lot of different files being touched, so what would be the ideal way of routing those changes towards inclusion? Thanks! -- Florian
Re: [PATCH net-next 0/6] MAINTAINERS: Remove self from PHY LIBRARY
On 8/24/2020 6:21 PM, David Miller wrote: From: Florian Fainelli Date: Mon, 24 Aug 2020 17:43:37 -0700 On 8/24/2020 4:19 PM, David Miller wrote: From: Florian Fainelli Date: Sat, 22 Aug 2020 13:11:20 -0700 Hi David, Heiner, Andrew, Russell, This patch series aims at allowing myself to keep track of the Ethernet PHY and MDIO bus drivers that I authored or contributed to without being listed as a maintainer in the PHY library anymore. Thank you for the fish, I will still be around. I applied this to 'net' because I think it's important to MAINTAINERS information to be as uptodate as possible. Humm sure, however some of the paths defined in patches 4 and 5 assume that Andrew's series that moves PHY/MDIO/PCS to separate directories. I suppose this may be okay for a little while until you merge his patch series? Aha, I see. I think it's ok for now. I should have probably made it clearer that this depended on Andrew's patch series as opposed to simply building on top of it. -- Florian
Re: [PATCH net-next 0/6] MAINTAINERS: Remove self from PHY LIBRARY
On 8/24/2020 4:19 PM, David Miller wrote: From: Florian Fainelli Date: Sat, 22 Aug 2020 13:11:20 -0700 Hi David, Heiner, Andrew, Russell, This patch series aims at allowing myself to keep track of the Ethernet PHY and MDIO bus drivers that I authored or contributed to without being listed as a maintainer in the PHY library anymore. Thank you for the fish, I will still be around. I applied this to 'net' because I think it's important to MAINTAINERS information to be as uptodate as possible. Humm sure, however some of the paths defined in patches 4 and 5 assume that Andrew's series that moves PHY/MDIO/PCS to separate directories. I suppose this may be okay for a little while until you merge his patch series? -- Florian
Re: [PATCH v1] ata: ahci_brcm: Fix use of BCM7216 reset controller
Hi Jim,
On 8/24/20 1:40 PM, Jim Quinlan wrote:
> From: Jim Quinlan
>
> A reset controller "rescal" is shared between the AHCI driver and the PCIe
> driver for the BrcmSTB 7216 chip. Use
> devm_reset_control_get_optional_shared() to handle this sharing.
>
> Fixes: 272ecd60a636 ("ata: ahci_brcm: BCM7216 reset is self de-asserting")
> Fixes: c345ec6a50e9 ("ata: ahci_brcm: Support BCM7216 reset controller name")
> Signed-off-by: Jim Quinlan
> ---
> drivers/ata/ahci_brcm.c | 11 +++
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
> index 6853dbb4131d..d6115bc04b09 100644
> --- a/drivers/ata/ahci_brcm.c
> +++ b/drivers/ata/ahci_brcm.c
> @@ -428,7 +428,6 @@ static int brcm_ahci_probe(struct platform_device *pdev)
> {
> const struct of_device_id *of_id;
> struct device *dev = >dev;
> - const char *reset_name = NULL;
> struct brcm_ahci_priv *priv;
> struct ahci_host_priv *hpriv;
> struct resource *res;
> @@ -452,11 +451,10 @@ static int brcm_ahci_probe(struct platform_device *pdev)
>
> /* Reset is optional depending on platform and named differently */
> if (priv->version == BRCM_SATA_BCM7216)
> - reset_name = "rescal";
> + priv->rcdev =
> devm_reset_control_get_optional_shared(>dev, "rescal");
> else
> - reset_name = "ahci";
> + priv->rcdev = devm_reset_control_get_optional(>dev,
> "ahci");
>
> - priv->rcdev = devm_reset_control_get_optional(>dev, reset_name);
> if (IS_ERR(priv->rcdev))
> return PTR_ERR(priv->rcdev);
>
> @@ -479,10 +477,7 @@ static int brcm_ahci_probe(struct platform_device *pdev)
> break;
> }
>
> - if (priv->version == BRCM_SATA_BCM7216)
> - ret = reset_control_reset(priv->rcdev);
> - else
> - ret = reset_control_deassert(priv->rcdev);
> + ret = reset_control_deassert(priv->rcdev);
> if (ret)
> return ret;
We are missing an equivalent path in the brcm_ahci_resume() function,
with that fixed:
Acked-by: Florian Fainelli
--
Florian
Re: [PATCH 00/12] Convert WAR defines to config options
On 8/24/20 10:28 AM, Thomas Bogendoerfer wrote: > On Mon, Aug 24, 2020 at 10:10:07AM -0700, Florian Fainelli wrote: >> On 8/24/20 9:32 AM, Thomas Bogendoerfer wrote: >>> This patches convert workaround (WAR) defines into config options and >>> gets rid of mach-*/war.h files. >> >> Most (all but octeon?) of those platforms are not particularly popular >> or widespread, but is not this going to make it harder for distributions >> and people doing CI by having an explosion in the number of >> configurations to test? > > all options are only selected by arch/mips/Kconfig, so nothing should > change for any CI. OK, had missed that part, thanks. -- Florian
