Hi,
Dne sreda, 22. februar 2017 ob 16:18:50 CET je Icenowy Zheng napisal(a):
> Allwinner have a new "Display Engine 2.0" in there new SoCs, which comes
> in a new "Display Engine" (mixers instead of old backends and
> frontends).
>
> Add support for the mixer on Allwinner V3s SoC; it's the
Hi,
Dne sreda, 22. februar 2017 ob 21:17:29 CET je Icenowy Zheng napisal(a):
> 2017年2月23日 03:09于 Maxime Ripard 写道:
>
> > Hi,
> >
> > On Wed, Feb 22, 2017 at 11:18:48PM +0800, Icenowy Zheng wrote:
> > > +config SUNXI_DE2_CCU
> > > + bool "Support for the
Hi,
Dne petek, 24. februar 2017 ob 14:30:36 CET je Rob Herring napisal(a):
> On Wed, Feb 22, 2017 at 2:09 PM, Maxime Ripard
>
> wrote:
> > Hi,
> >
> > On Wed, Feb 22, 2017 at 11:23:06PM +0800, Icenowy Zheng wrote:
> >> Allwinner have a new "Display Engine 2.0"
left from you is for DE2. HDMI stuff is basically copied from Rockhip
> > driver (including EDID reading), TCON code is now reverted to the same as
> > it is in sunxi_display.c. I think it is worth to take a look at EDID code
> > and compare it.
>
> So is the
Dne sreda, 30. november 2016 ob 20:37:24 CET je Jean-Francois Moine
napisal(a):
> On Wed, 30 Nov 2016 20:14:11 +0100
>
> Jernej Škrabec <jernej.skra...@gmail.com> wrote:
> > Dne četrtek, 01. december 2016 ob 03:03:14 CET je Icenowy Zheng
napisal(a):
> > > 20
Hi,
Dne sreda, 29. marec 2017 ob 21:46:08 CEST je Icenowy Zheng napisal(a):
> Allwinner have a new "Display Engine 2.0" in their new SoCs, which comes
> with mixers to do graphic processing and feed data to TCON, like the old
> backends and frontends.
>
> Add support for the mixer on Allwinner
Hi Chen-Yu,
Dne ponedeljek, 31. julij 2017 ob 07:13:34 CEST je Chen-Yu Tsai napisal(a):
> Hi Jernej,
>
> On Mon, Jul 31, 2017 at 12:41 AM, Jernej Skrabec
>
> wrote:
> > During development of H3 HDMI driver, I found some issues with
> > setting video clock rate. It
Hi Chen-Yu,
Dne ponedeljek, 31. julij 2017 ob 07:02:18 CEST je Chen-Yu Tsai napisal(a):
> On Mon, Jul 31, 2017 at 12:41 AM, Jernej Skrabec
>
> wrote:
> > Currently ccu_frac_helper_set_rate() doesn't wait for a lock bit to be
> > set before returning. Because of that,
Hi,
Dne sreda, 02. avgust 2017 ob 07:02:39 CEST je icen...@aosc.io napisal(a):
> 在 2017-08-02 12:53,Jernej Škrabec 写道:
>
> > Hi Icenowy,
> >
> > Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng
> >
> > napisal(a):
> >> Allwinner H3 fe
Hi Icenowy,
Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng napisal(a):
> As we have already the support for the DE2 on Allwinner H3, add the
> display engine pipeline device tree nodes to its DTSI file.
>
> The H5 pipeline has some differences and will be enabled later.
>
>
Hi Icenowy,
Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng napisal(a):
> Allwinner H3 features a "Display Engine 2.0".
>
> Add device tree bindings for the following parts:
> - H3 TCONs
> - H3 Mixers
> - H3 Display engine
>
> Signed-off-by: Icenowy Zheng
> ---
>
Hi Chen-Yu,
Dne petek, 04. avgust 2017 ob 06:29:50 CEST je Chen-Yu Tsai napisal(a):
> On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng wrote:
> > 于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai 写到:
> >>Hi,
> >>
> >>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng
Hi Chen-Yu,
Dne petek, 04. avgust 2017 ob 11:27:33 CEST je Chen-Yu Tsai napisal(a):
> On Fri, Aug 4, 2017 at 4:59 PM, Jernej Škrabec <jernej.skra...@siol.net>
wrote:
> > Hi Chen-Yu,
> >
> > Dne petek, 04. avgust 2017 ob 06:29:50 CEST je Chen-Yu Tsai napisal(a):
> &
Hi,
Dne četrtek, 10. avgust 2017 ob 02:21:21 CEST je Rob Herring napisal(a):
> On Wed, Aug 02, 2017 at 09:06:26PM +0200, Jernej Škrabec wrote:
> > Hi,
> >
> > Dne sreda, 02. avgust 2017 ob 07:02:39 CEST je icen...@aosc.io napisal(a):
> > > 在 2017-08-02 12:53,Jernej
Hi,
Dne sreda, 17. maj 2017 ob 18:43:53 CEST je Icenowy Zheng napisal(a):
> As we have already the support for the TV encoder on Allwinner H3, add
> the display engine pipeline device tree nodes to its DTSI file.
>
> The H5 pipeline has some differences and will be enabled later.
>
> The
Hi,
Dne sreda, 17. maj 2017 ob 18:43:49 CEST je Icenowy Zheng napisal(a):
> The DE2 mixer can do color space correction needed by TV Encoder with
> its DCSC sub-engine.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
> ---
> drivers/gpu/drm/sun4i/sun8i_mixer.c | 35
>
Hi!
Dne petek, 09. junij 2017 ob 18:51:02 CEST je Icenowy Zheng napisal(a):
> 于 2017年6月10日 GMT+08:00 上午12:49:15, Maxime Ripard 写到:
> >On Wed, Jun 07, 2017 at 04:48:50PM +0800, Icenowy Zheng wrote:
> >> >> @@ -189,6 +211,8 @@ supported.
> >> >>
> >> >>
Hi,
Dne sobota, 20. maj 2017 ob 03:37:53 CEST je Chen-Yu Tsai napisal(a):
> On Sat, May 20, 2017 at 2:23 AM, Jernej Škrabec <jernej.skra...@siol.net>
wrote:
> > Hi,
> >
> > Dne petek, 19. maj 2017 ob 20:08:18 CEST je Icenowy Zheng napisal(a):
> >> 于 2017年5月20
写道:
> >>
> >> > On Mon, May 22, 2017 at 07:55:56PM +0200, Jernej Škrabec wrote:
> >> > > Hi,
> >> > >
> >> > > Dne sobota, 20. maj 2017 ob 03:37:53 CEST je Chen-Yu Tsai
> >
> >napisal(a):
> >> > > &
Hi,
Dne petek, 19. maj 2017 ob 20:08:18 CEST je Icenowy Zheng napisal(a):
> 于 2017年5月20日 GMT+08:00 上午2:03:30, Maxime Ripard 写到:
> >On Thu, May 18, 2017 at 12:43:50AM +0800, Icenowy Zheng wrote:
> >> Allwinner H3 features a TV encoder similar to the one in
Hi!
Dne petek, 19. maj 2017 ob 19:49:58 CEST je Icenowy Zheng napisal(a):
> 于 2017年5月20日 GMT+08:00 上午1:47:29, Maxime Ripard 写到:
> >On Thu, May 18, 2017 at 12:43:45AM +0800, Icenowy Zheng wrote:
> >> From: Icenowy Zheng
> >>
> >> Allwinner H3
Hi!
Dne sreda, 07. junij 2017 ob 16:38:27 CEST je Maxime Ripard napisal(a):
> On Wed, Jun 07, 2017 at 06:01:02PM +0800, Icenowy Zheng wrote:
> > >I have no idea what this is supposed to be doing either.
> > >
> > >I might be wrong, but I really feel like there's a big mismatch
> > >between your
Hi,
Dne nedelja, 04. junij 2017 ob 18:01:42 CEST je Icenowy Zheng napisal(a):
> From: Icenowy Zheng
>
> Allwinner H3 has two special TCONs, both come without channel0. And the
> TCON1 of H3 has no special clocks even for the channel1.
>
> Add support for these kinds of TCON.
Hi,
Dne sobota, 30. september 2017 ob 13:58:03 CEST je Alexey Kardashevskiy
napisal(a):
> On 21/09/17 06:01, Jernej Skrabec wrote:
> > [added media mailing list due to CEC question]
> >
> > This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now,
> > only video and CEC
Hi Maxime,
Dne ponedeljek, 27. november 2017 ob 16:41:29 CET je Maxime Ripard napisal(a):
> It seems like the mixer can only run properly when clocked at 150MHz. In
> order to have something more robust than simply a fire-and-forget
> assigned-clocks-rate, let's put that in the code.
>
>
Hi Maxime,
Dne ponedeljek, 27. november 2017 ob 16:41:35 CET je Maxime Ripard napisal(a):
> Add support for the A83T display pipeline.
>
> Reviewed-by: Chen-Yu Tsai
> Signed-off-by: Maxime Ripard
> ---
>
Hi,
Dne ponedeljek, 27. november 2017 ob 16:41:24 CET je Maxime Ripard napisal(a):
> Hi,
>
> Here is an attempt at supporting the LVDS output in our DRM driver. This
> has been tested on the A83T (with DE2), but since everything is basically
> in the TCON, it should also be usable on the older
Hi,
Dne torek, 28. november 2017 ob 10:02:23 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, Nov 27, 2017 at 05:01:49PM +0100, Jernej Škrabec wrote:
> > Dne ponedeljek, 27. november 2017 ob 16:41:35 CET je Maxime Ripard
napisal(a):
> > > Add support for t
Hi!
Dne torek, 28. november 2017 ob 16:54:42 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, Nov 27, 2017 at 09:57:34PM +0100, Jernej Skrabec wrote:
> > Since the time initial DE2 driver was written, some knowledge was gained
> > what setting are really necessary and what most of the magic
Hi!
Dne torek, 28. november 2017 ob 21:55:50 CET je Maxime Ripard napisal(a):
> On Mon, Nov 27, 2017 at 09:57:46PM +0100, Jernej Skrabec wrote:
> > DE2 have many CSC units - channel input CSC, channel output CSC and
> > mixer output CSC and maybe more.
> >
> > Fortunately, they have all same
Hi!
Dne torek, 28. november 2017 ob 09:58:26 CET je Maxime Ripard napisal(a):
> On Mon, Nov 27, 2017 at 05:07:04PM +0100, Jernej Škrabec wrote:
> > Hi Maxime,
> >
> > Dne ponedeljek, 27. november 2017 ob 16:41:29 CET je Maxime Ripard
napisal(a):
> > > It see
Hi!
Dne torek, 28. november 2017 ob 23:00:14 CET je Maxime Ripard napisal(a):
> On Tue, Nov 28, 2017 at 04:48:55PM +0100, Jernej Škrabec wrote:
> > > On Mon, Nov 27, 2017 at 05:01:49PM +0100, Jernej Škrabec wrote:
> > > > Dne ponedeljek, 27. november 2017 ob 16:41
Hi!
Dne torek, 28. november 2017 ob 22:00:01 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, Nov 27, 2017 at 09:57:41PM +0100, Jernej Skrabec wrote:
> > This commit adds basic support for VI planes. They are meant for video
> > overlay and because of that they support YUV formats too.
Hi,
Dne torek, 28. november 2017 ob 22:00:01 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, Nov 27, 2017 at 09:57:41PM +0100, Jernej Skrabec wrote:
> > This commit adds basic support for VI planes. They are meant for video
> > overlay and because of that they support YUV formats too.
Hi Julian,
Dne sreda, 29. november 2017 ob 22:48:34 CET je Julian Calaby napisal(a):
> Hi Jernej,
>
> On Tue, Nov 28, 2017 at 7:57 AM, Jernej Skrabec
wrote:
> > Calculate scaling parameters and call appropriate scaler set up
> > function.
> >
> > Signed-off-by: Jernej
Dne četrtek, 30. november 2017 ob 16:33:12 CET je Maxime Ripard napisal(a):
> On Tue, Nov 28, 2017 at 11:33:44PM +0100, Jernej Škrabec wrote:
> > Hi!
> >
> > Dne torek, 28. november 2017 ob 23:00:14 CET je Maxime Ripard napisal(a):
> > > On Tue, Nov 28, 2017 at 04
Hi,
Dne torek, 05. december 2017 ob 16:42:55 CET je Jernej Škrabec napisal(a):
> Hi Maxime,
>
> Dne torek, 05. december 2017 ob 16:10:21 CET je Maxime Ripard napisal(a):
> > Add support for the A83T display pipeline.
> >
> > Reviewed-by: Chen-Yu Tsai <w...@csie.
Hi Maxime,
Dne torek, 05. december 2017 ob 16:10:21 CET je Maxime Ripard napisal(a):
> Add support for the A83T display pipeline.
>
> Reviewed-by: Chen-Yu Tsai
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
>
Hi Maxime,
Dne torek, 05. december 2017 ob 11:36:18 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Fri, Dec 01, 2017 at 07:05:23AM +0100, Jernej Skrabec wrote:
> > Current DE2 driver is very basic and uses a lot of magic constants since
> > there is no documentation and knowledge about it was
Hi,
Dne petek, 18. maj 2018 ob 17:26:51 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote:
> > > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
> > > lookup pll-2 either.
> >
> > It is hi
Hi,
Dne nedelja, 20. maj 2018 ob 04:09:52 CEST je Julian Calaby napisal(a):
> Hi Jernej,
>
> On Sun, May 20, 2018 at 11:57 AM, Julian Calaby
wrote:
> > Hi Jernej,
> >
> > On Sun, May 20, 2018 at 4:31 AM, Jernej Skrabec
wrote:
> >> R40
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:12:53 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:24PM +0200, Jernej Skrabec wrote:
> > Expand HDMI PHY clock driver to support second clock parent.
> >
> > Signed-off-by: Jernej Skrabec
> > ---
> >
> >
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:01:47 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Sat, May 19, 2018 at 08:31:16PM +0200, Jernej Skrabec wrote:
> > TCON TOP main purpose is to configure whole display pipeline. It
> > determines relationships between mixers and TCONs, selects source TCON
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:05:17 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:17PM +0200, Jernej Skrabec wrote:
> > As already described in DT binding, TCON TOP is responsible for
> > configuring display pipeline. In this initial driver focus is on HDMI
> >
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:07:59 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:18PM +0200, Jernej Skrabec wrote:
> > If SoC has TCON TOP unit, it has to be configured from TCON, since it
> > has all information needed. Additionally, if it is TCON TV, it must also
>
Hi,
Dne četrtek, 24. maj 2018 ob 10:43:51 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, May 21, 2018 at 05:15:15PM +0200, Jernej Škrabec wrote:
> > > > + /*
> > > > +* Default register values might have some reserved bits set,
which
> >
Hi,
Dne petek, 18. maj 2018 ob 17:26:51 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote:
> > > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
> > > lookup pll-2 either.
> >
> > It is hi
Hi,
Dne petek, 18. maj 2018 ob 17:09:40 CEST je Sergey Suloev napisal(a):
> Hi, guys,
>
> On 05/18/2018 05:46 PM, Jernej Škrabec wrote:
> > Hi,
> >
> > Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
> >> On Fri, May 18, 2018 a
Hi,
Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
> > From: Jernej Skrabec
> >
> > Some SoCs with DW HDMI have multiple possible clock parents, like A64
> > and R40.
> >
> > Expand
Dne sreda, 13. junij 2018 ob 09:36:05 CEST je Maxime Ripard napisal(a):
> On Tue, Jun 12, 2018 at 10:00:33PM +0200, Jernej Skrabec wrote:
> > Function is useful when drm_of_find_possible_crtcs() can't be used and
> > custom parsing is needed. This can happen for example when there is a
> > node
Dne torek, 12. junij 2018 ob 22:00:29 CEST je Jernej Skrabec napisal(a):
> DW HDMI PHY driver and PHY clock driver share same registers. Make sure
> that DW HDMI PHY setup code doesn't change any clock related bits and
> set them to 0 during initialization.
>
> Signed-off-by: Jernej Skrabec
>
Hi,
Dne četrtek, 26. april 2018 ob 15:26:49 CEST je Jagan Teki napisal(a):
> On Wed, Apr 25, 2018 at 11:29 PM, Jernej Škrabec
>
> <jernej.skra...@siol.net> wrote:
> > Hi,
> >
> > Dne sreda, 25. april 2018 ob 12:34:09 CEST je Jagan Teki napisal(a):
> >&g
Hi Maxime,
Dne četrtek, 21. december 2017 ob 12:02:29 CET je Maxime Ripard napisal(a):
> Some clocks and resets supposed to drive the LVDS logic in the display
> engine have been overlooked when the driver was first introduced.
>
> Add those additional resources to the binding, and we'll deal
Hi,
Dne četrtek, 04. januar 2018 ob 15:45:18 CET je Chen-Yu Tsai napisal(a):
> On Sun, Dec 31, 2017 at 5:01 AM, Jernej Skrabec
wrote:
> > For example, A83T have nmp plls which are modelled as nkmp plls. Since k
> > is not specified, it has offset 0, shift 0 and lowest
Hi,
Dne petek, 05. januar 2018 ob 03:49:09 CET je Icenowy Zheng napisal(a):
> 于 2018年1月5日 GMT+08:00 上午2:52:10, Maxime Ripard <maxime.ripard@free-
electrons.com> 写到:
> >On Wed, Jan 03, 2018 at 10:32:26PM +0100, Jernej Škrabec wrote:
> >> Hi Rob,
> >>
> >&
Hi Laurent,
Dne torek, 09. januar 2018 ob 17:08:55 CET je Laurent Pinchart napisal(a):
> Hello,
>
> On Tuesday, 9 January 2018 17:58:46 EET Jernej Škrabec wrote:
> > Dne torek, 09. januar 2018 ob 11:43:08 CET je Archit Taneja napisal(a):
> > > On 12/31/2017 02:31
Hi Chen-Yu,
Dne ponedeljek, 08. januar 2018 ob 10:19:47 CET je Chen-Yu Tsai napisal(a):
> On Fri, Jan 5, 2018 at 3:28 AM, Jernej Škrabec <jernej.skra...@siol.net>
wrote:
> > Hi,
> >
> > Dne četrtek, 04. januar 2018 ob 15:45:18 CET je Chen-Yu Tsai napisal(a):
> >
Hi Archit,
Dne torek, 09. januar 2018 ob 11:43:08 CET je Archit Taneja napisal(a):
> On 12/31/2017 02:31 AM, Jernej Skrabec wrote:
> > Parts of PHY code could be useful also for custom PHYs. For example,
> > Allwinner A83T has custom PHY which is probably Synopsys gen2 PHY
> > with few additional
Hi Laurent,
Dne torek, 09. januar 2018 ob 14:30:22 CET je Laurent Pinchart napisal(a):
> Hi Jernej,
>
> Thank you for the patch.
>
> On Saturday, 30 December 2017 23:01:56 EET Jernej Skrabec wrote:
> > Parts of PHY code could be useful also for custom PHYs. For example,
> > Allwinner A83T has
Hi,
Dne torek, 09. januar 2018 ob 17:08:55 CET je Laurent Pinchart napisal(a):
> Hello,
>
> On Tuesday, 9 January 2018 17:58:46 EET Jernej Škrabec wrote:
> > Dne torek, 09. januar 2018 ob 11:43:08 CET je Archit Taneja napisal(a):
> > > On 12/31/2017 02:31 AM, Jernej Skr
Hi,
Dne četrtek, 18. januar 2018 ob 11:58:41 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Wed, Jan 17, 2018 at 09:14:11PM +0100, Jernej Skrabec wrote:
> > This commit changes formula from this:
> >
> > Freq = (parent_freq * N * K) / (M * P)
> >
> > to this:
> >
> > Freq = (parent_freq / M) *
Hi all,
Dne sreda, 10. januar 2018 ob 20:25:04 CET je Jernej Skrabec napisal(a):
> Parts of PHY code could be useful also for custom PHYs. For example,
> Allwinner A83T has custom PHY which is probably Synopsys gen2 PHY
> with few additional memory mapped registers, so most of the Synopsys PHY
>
Hi,
Dne ponedeljek, 29. januar 2018 ob 19:05:26 CET je Rob Herring napisal(a):
> On Wed, Jan 17, 2018 at 09:14:15PM +0100, Jernej Skrabec wrote:
> > This commit adds all necessary compatibles and descriptions needed to
> > implement A83T HDMI pipeline.
> >
> > Mixer is already properly
Dne četrtek, 08. februar 2018 ob 10:15:35 CET je Icenowy Zheng napisal(a):
> 在 2018-02-08 17:00,Maxime Ripard 写道:
>
> > On Tue, Feb 06, 2018 at 09:16:47PM +0800, Icenowy Zheng wrote:
> >> Banana Pi M2 Zero board is a H2+-based board by Sinovoip, with a form
> >> factor and GPIO holes similar to
Hi,
Dne torek, 02. januar 2018 ob 09:14:37 CET je Icenowy Zheng napisal(a):
> 在 2018年1月2日星期二 CST 下午4:11:04,Chen-Yu Tsai 写道:
>
> > On Sat, Dec 30, 2017 at 7:30 PM, Icenowy Zheng wrote:
> > > The H3/H5 SoCs have a HDMI output and a TV Composite output.
> > >
> > > Add simplefb
Hi Rob,
Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
> On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
> > This commit adds all necessary compatibles and descriptions needed to
> > implement A83T HDMI pipeline.
> >
> > Mixer is already properly described,
Dne četrtek, 26. julij 2018 ob 19:12:48 CEST je Icenowy Zheng napisal(a):
> From: Jagan Teki
>
> According to documentation and experience with other similar SoCs, video
> PLLs don't work stable if their output frequency is set below 192 MHz.
>
> Because of that, set minimal rate to both A64
Hi,
Dne ponedeljek, 05. marec 2018 ob 22:30:23 CET je Jernej Škrabec napisal(a):
> Hi,
>
> Dne petek, 02. marec 2018 ob 13:40:50 CET je Mark Brown napisal(a):
> > On Thu, Mar 01, 2018 at 11:23:57PM +0100, Jernej Škrabec wrote:
> > > I removed parts of the code fro
Hi,
Thank you for looking into it so quickly.
Dne četrtek, 08. marec 2018 ob 02:21:02 CET je Kuninori Morimoto napisal(a):
> Hi Jernej
>
> Thank you for your hard work
>
> > I found the issue. Commit be7ee5f32a9a ("ASoC: soc-generic-dmaengine-pcm:
> >
> > replace platform to component")
Hi all,
with todays linux-next (next-20180228), kernel on Allwinner H3 SoC crashes
with dmesg like that: https://pastebin.com/raw/0D5JeaJ8
I bisected the kernel and first offending commit is:
be7ee5f32a9a ("ASoC: soc-generic-dmaengine-pcm: replace platform to
component")
I know that crash
Hi Maxime,
Dne sreda, 28. februar 2018 ob 08:36:08 CET je Maxime Ripard napisal(a):
> On Tue, Feb 27, 2018 at 11:26:51PM +0100, Jernej Skrabec wrote:
> > TCON checks for LVDS properties even if it doesn't support it. Add a
> > check to skip that part of the code if TCON doesn't support channel 0.
Hi,
Dne sreda, 28. februar 2018 ob 08:34:40 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Tue, Feb 27, 2018 at 11:26:46PM +0100, Jernej Skrabec wrote:
> > Some NM PLLs doesn't work well when their output clock rate is set below
> > certain rate.
> >
> > Add support for that constrain.
> >
> >
Hi Maxime,
Dne torek, 27. februar 2018 ob 23:26:45 CET je Jernej Skrabec napisal(a):
> This series implements H3/H5 HDMI driver. It was tested on OrangePi 2 (H3),
> OrangePi Plus2e (H3) and OrangePi PC2 (H5) with many resolutions and it
> works well. Bug, which prevented correct operation for
which is set when clock rate is protected and unset
when it is unprotected. That way we could track if clk_rate_exclusive_put()
needs to be called or not.
Best regards,
Jernej
>
> regards,
> o.
>
> On Fri, Mar 09, 2018 at 01:13:14AM +0100, 'Ondřej Jirman' via linux-sunxi
wro
Hi,
Dne petek, 09. marec 2018 ob 00:49:18 CET je Kuninori Morimoto napisal(a):
> Hi Mark,Jernej
>
> > > Ahh.. indeed. Good catch !
> > > How about to add such flag ?
> > > This is just idea. No tested, No compiled, but can help you ?
> >
> > I think this makes sense as a patch. We might want
Hi,
Dne četrtek, 08. marec 2018 ob 23:47:17 CET je Ondřej Jirman napisal(a):
> Hi,
>
> On Thu, Mar 01, 2018 at 10:34:32PM +0100, Jernej Skrabec wrote:
> > Currently exclusive TCON clock lock is never released, which, for
> > example, prevents changing resolution on HDMI.
> >
> > In order to fix
Hi,
Dne torek, 24. april 2018 ob 15:34:21 CEST je Jagan Teki napisal(a):
> HDMI on Allwinner A64 has similar behavior like H3/H5, so
> reuse the same dts node details for A64.
>
> Signed-off-by: Jagan Teki
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 28
>
Hi,
Dne torek, 24. april 2018 ob 15:34:12 CEST je Jagan Teki napisal(a):
> Allwinner A64 has display engine pipeline like other Allwinner SOC's
> A83T/H3/H5.
>
> A64 DE2 behaviour similar to Allwinner A83T where mixer0, connected to tcon0
> with RGB, LVDS MIPI-DSI and mixer1, connected to tcon1
Hi all,
Dne sreda, 21. marec 2018 ob 03:18:13 CET je Icenowy Zheng napisal(a):
> 于 2018年3月21日 GMT+08:00 上午2:46:46, Maxime Ripard
写到:
> >On Sat, Mar 17, 2018 at 01:53:49AM +0800, Icenowy Zheng wrote:
> >> All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64
Hi,
Dne petek, 16. marec 2018 ob 15:02:13 CET je Icenowy Zheng napisal(a):
> The Allwinner H6 SoC has a CCU which has been largely rearranged.
>
> Add support for it in the sunxi-ng CCU framework.
>
> Signed-off-by: Icenowy Zheng
> Acked-by: Maxime Ripard
Hi Kuninori,
I'm responding to my own mail, since I didn't received yours for some reason
but I still saw your response in mailing list archive.
Dne sreda, 28. februar 2018 ob 22:02:09 CET je Jernej Škrabec napisal(a):
> Hi all,
>
> with todays linux-next (next-20180228), kernel on
Hi!
Dne ponedeljek, 05. marec 2018 ob 16:27:00 CET je Joonas Kylmälä napisal(a):
> Jernej Skrabec:
> > +_out {
> > + hdmi_out_con: endpoint {
> > + remote-endpoint = <_con_in>;
> > + };
> > +};
>
> This node is added to all the DTS files you enabled HDMI on. Is it
> something that
Hi,
Dne petek, 02. marec 2018 ob 13:40:50 CET je Mark Brown napisal(a):
> On Thu, Mar 01, 2018 at 11:23:57PM +0100, Jernej Škrabec wrote:
> > I removed parts of the code from the sun4i codec driver and interestingly
> > it doesn't crash if I remove following line
Hi,
Dne ponedeljek, 26. februar 2018 ob 10:38:00 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Sat, Feb 24, 2018 at 10:45:31PM +0100, Jernej Skrabec wrote:
> > Some NM PLLs doesn't work well when their output clock rate is set below
> > certain rate.
> >
> > Add support for that constrain.
>
>
Hi,
Dne ponedeljek, 26. februar 2018 ob 10:39:30 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Sat, Feb 24, 2018 at 10:45:38PM +0100, Jernej Skrabec wrote:
> > Current polarity configuration code is cleary wrong since it compares
> > same flag two times. However, even if flag name is fixed, it
Hi all,
Dne sobota, 24. februar 2018 ob 22:45:41 CET je Jernej Skrabec napisal(a):
> While A83T HDMI PHY seems to be just customized Synopsys HDMI PHY, H3
> HDMI PHY is completely custom PHY.
>
> However, they still have many things in common like clock and reset
> setup, setting sync polarity
Hi Julian,
Dne nedelja, 25. februar 2018 ob 09:11:34 CET je Julian Calaby napisal(a):
> Hi Jernej,
>
> On Sun, Feb 25, 2018 at 8:45 AM, Jernej Skrabec
wrote:
> > Enable HDMI output on all boards which have HDMI connector.
> >
> > Signed-off-by: Jernej Skrabec
Hi,
Dne ponedeljek, 26. februar 2018 ob 17:21:05 CET je Icenowy Zheng napisal(a):
> 于 2018年2月27日 GMT+08:00 上午12:16:44, "Jernej Škrabec"
<jernej.skra...@siol.net> 写到:
> >Hi Julian,
> >
> >Dne nedelja, 25. februar 2018 ob 09:11:34 CET je Julian Cal
Hi,
Dne sreda, 25. april 2018 ob 12:34:09 CEST je Jagan Teki napisal(a):
> On Tue, Apr 24, 2018 at 9:02 PM, Jernej Škrabec <jernej.skra...@siol.net>
wrote:
> > Hi,
> >
> > Dne torek, 24. april 2018 ob 15:34:12 CEST je Jagan Teki napisal(a):
> >> Allwinner
Hi,
Dne sreda, 25. april 2018 ob 15:55:48 CEST je Maxime Ripard napisal(a):
> On Wed, Apr 25, 2018 at 06:29:05PM +0530, Jagan Teki wrote:
> > On Tue, Apr 24, 2018 at 7:38 PM, Maxime Ripard
> >
> > wrote:
> > > On Tue, Apr 24, 2018 at 07:04:12PM +0530, Jagan Teki
Hi all,
with todays linux-next (next-20180228), kernel on Allwinner H3 SoC crashes
with dmesg like that: https://pastebin.com/raw/0D5JeaJ8
I bisected the kernel and first offending commit is:
be7ee5f32a9a ("ASoC: soc-generic-dmaengine-pcm: replace platform to
component")
I know that crash
Hi Maxime,
Dne torek, 27. februar 2018 ob 23:26:45 CET je Jernej Skrabec napisal(a):
> This series implements H3/H5 HDMI driver. It was tested on OrangePi 2 (H3),
> OrangePi Plus2e (H3) and OrangePi PC2 (H5) with many resolutions and it
> works well. Bug, which prevented correct operation for
Hi Maxime,
Dne sreda, 28. februar 2018 ob 08:36:08 CET je Maxime Ripard napisal(a):
> On Tue, Feb 27, 2018 at 11:26:51PM +0100, Jernej Skrabec wrote:
> > TCON checks for LVDS properties even if it doesn't support it. Add a
> > check to skip that part of the code if TCON doesn't support channel 0.
Hi,
Dne sreda, 28. februar 2018 ob 08:34:40 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Tue, Feb 27, 2018 at 11:26:46PM +0100, Jernej Skrabec wrote:
> > Some NM PLLs doesn't work well when their output clock rate is set below
> > certain rate.
> >
> > Add support for that constrain.
> >
> >
Hi Kuninori,
I'm responding to my own mail, since I didn't received yours for some reason
but I still saw your response in mailing list archive.
Dne sreda, 28. februar 2018 ob 22:02:09 CET je Jernej Škrabec napisal(a):
> Hi all,
>
> with todays linux-next (next-20180228), kernel on
Hi all,
Dne sreda, 21. marec 2018 ob 03:18:13 CET je Icenowy Zheng napisal(a):
> 于 2018年3月21日 GMT+08:00 上午2:46:46, Maxime Ripard
写到:
> >On Sat, Mar 17, 2018 at 01:53:49AM +0800, Icenowy Zheng wrote:
> >> All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64 SoC
> >
> >to
> >
> >> be
Hi,
Dne četrtek, 08. marec 2018 ob 23:47:17 CET je Ondřej Jirman napisal(a):
> Hi,
>
> On Thu, Mar 01, 2018 at 10:34:32PM +0100, Jernej Skrabec wrote:
> > Currently exclusive TCON clock lock is never released, which, for
> > example, prevents changing resolution on HDMI.
> >
> > In order to fix
which is set when clock rate is protected and unset
when it is unprotected. That way we could track if clk_rate_exclusive_put()
needs to be called or not.
Best regards,
Jernej
>
> regards,
> o.
>
> On Fri, Mar 09, 2018 at 01:13:14AM +0100, 'Ondřej Jirman' via linux-sunxi
wro
Hi,
Dne petek, 09. marec 2018 ob 00:49:18 CET je Kuninori Morimoto napisal(a):
> Hi Mark,Jernej
>
> > > Ahh.. indeed. Good catch !
> > > How about to add such flag ?
> > > This is just idea. No tested, No compiled, but can help you ?
> >
> > I think this makes sense as a patch. We might want
Hi,
Dne petek, 16. marec 2018 ob 15:02:13 CET je Icenowy Zheng napisal(a):
> The Allwinner H6 SoC has a CCU which has been largely rearranged.
>
> Add support for it in the sunxi-ng CCU framework.
>
> Signed-off-by: Icenowy Zheng
> Acked-by: Maxime Ripard
> ---
> Changes in v4:
> - Extract
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