On Mon, Aug 12, 2019 at 06:20:53PM +, Haiyang Zhang wrote:
> Currently in Azure cloud, for passthrough devices including GPU, the host
> sets the device instance ID's bytes 8 - 15 to a value derived from the host
> HWID, which is the same on all devices in a VM. So, the device instance
> ID's
git log --oneline --follow drivers/pci/controller/dwc/pci-layerscape.c
Do you see any commit with a $SUBJECT ending with a period ?
There is not. So remove it from yours too.
On Tue, Aug 13, 2019 at 02:28:39PM +0800, Xiaowei Bao wrote:
> The PCIe controller of layerscape just have 4 BARs, BAR0
You should fix your email client set-up to avoid sticking an [EXT]
tag to your emails $SUBJECT.
On Tue, Aug 13, 2019 at 07:39:48AM +, Xiaowei Bao wrote:
>
>
> > -Original Message-
> > From: Kishon Vijay Abraham I
> > Sent: 2019年8月13日 15:30
> > To: Xiaowei Bao ;
"PCI: dwc: al: Add support for DW based driver type"
Make $SUBJECT compliant with other host controllers patches.
On Tue, Jul 23, 2019 at 12:27:09PM +0300, Jonathan Chocron wrote:
> This driver is DT based and utilizes the DesignWare APIs.
> It allows using a smaller ECAM range for a larger bus
On Tue, Aug 06, 2019 at 11:52:11PM +, Haiyang Zhang wrote:
> Currently in Azure cloud, for passthrough devices including GPU, the
> host sets the device instance ID's bytes 8 - 15 to a value derived from
> the host HWID, which is the same on all devices in a VM. So, the device
> instance ID's
On Mon, Aug 12, 2019 at 10:39:00AM +, Xiaowei Bao wrote:
>
>
> > -Original Message-
> > From: Lorenzo Pieralisi
> > Sent: 2019年8月12日 18:12
> > To: Xiaowei Bao ; kis...@ti.com
> > Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.
First off:
Trim the CC list, you CC'ed maintainers (and mailing lists) for no
reasons whatsover.
Then, read this:
https://lore.kernel.org/linux-pci/20171026223701.ga25...@bhelgaas-glaptop.roam.corp.google.com/
and make your patches compliant please.
On Fri, Jun 28, 2019 at 09:38:25AM +0800,
On Fri, Jun 28, 2019 at 09:38:26AM +0800, Xiaowei Bao wrote:
> Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately.
>
> Signed-off-by: Xiaowei Bao
> ---
> v2:
> - No change.
> v3:
> - modify the commit message.
>
> drivers/pci/controller/dwc/Kconfig | 20 ++--
>
The generic ARM CPUidle driver includes by mistake.
Remove the topology header include.
Signed-off-by: Lorenzo Pieralisi
Acked-by: Daniel Lezcano
Reviewed-by: Ulf Hansson
Reviewed-by: Sudeep Holla
Cc: Ulf Hansson
Cc: Sudeep Holla
Cc: Daniel Lezcano
Cc: "Rafael J. Wysocki"
--
states.
Signed-off-by: Lorenzo Pieralisi
Reviewed-by: Ulf Hansson
Cc: Will Deacon
Cc: Ulf Hansson
Cc: Sudeep Holla
Cc: Daniel Lezcano
Cc: Catalin Marinas
Cc: Mark Rutland
Cc: "Rafael J. Wysocki"
---
arch/arm64/kernel/cpuidle.c | 7 ---
arch/arm64/kernel/psci.c | 4 ---
.
Signed-off-by: Lorenzo Pieralisi
Acked-by: Daniel Lezcano
Reviewed-by: Ulf Hansson
Reviewed-by: Sudeep Holla
Cc: Ulf Hansson
Cc: Sudeep Holla
Cc: Daniel Lezcano
Cc: Mark Rutland
Cc: "Rafael J. Wysocki"
---
MAINTAINERS| 8 ++
drivers/cpuidle/Kconfig.ar
rom the kernel, the generic and PSCI
CPUidle driver are left to co-exist.
Tested on Juno platform with both DT and ACPI boot firmwares.
Cc: Will Deacon
Cc: Shawn Guo
Cc: Ulf Hansson
Cc: Sudeep Holla
Cc: Daniel Lezcano
Cc: Catalin Marinas
Cc: Mark Rutland
Cc: "Rafael J. Wysocki"
Lorenzo
cpuidle_state.enter() function callback.
Signed-off-by: Lorenzo Pieralisi
Acked-by: Daniel Lezcano
Reviewed-by: Ulf Hansson
Reviewed-by: Sudeep Holla
Cc: Sudeep Holla
Cc: Mark Rutland
---
drivers/firmware/psci/psci_checker.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions
ate
parameters before handing them over to the PSCI firmware
interface to trigger PSCI.CPU_SUSPEND() calls.
Signed-off-by: Lorenzo Pieralisi
Acked-by: Daniel Lezcano
Reviewed-by: Ulf Hansson
Reviewed-by: Sudeep Holla
Cc: Will Deacon
Cc: Ulf Hansson
Cc: Sudeep Holla
Cc: Daniel Lezcano
Cc: Cata
Enable the PSCI CPUidle driver to replace the functionality
previously provided by the generic ARM CPUidle driver through
CPU operations.
Signed-off-by: Lorenzo Pieralisi
Cc: Will Deacon
Cc: Sudeep Holla
Cc: Catalin Marinas
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion
Enable the PSCI CPUidle driver to replace the functionality
previously provided by the generic ARM CPUidle driver.
Signed-off-by: Lorenzo Pieralisi
Cc: Shawn Guo
---
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig
b
not support CPUidle operations.
Signed-off-by: Lorenzo Pieralisi
Acked-by: Daniel Lezcano
Reviewed-by: Ulf Hansson
Reviewed-by: Sudeep Holla
Cc: Ulf Hansson
Cc: Sudeep Holla
Cc: Daniel Lezcano
Cc: "Rafael J. Wysocki"
---
drivers/cpuidle/cpuidle-arm.c | 12 +---
1 file
Side note, run:
git log --oneline on drivers/pci/controller/dwc existing files and
make sure commit subjects are in line with those.
Eg PCI: dw: should be PCI: dwc:
On Thu, Aug 08, 2019 at 09:30:05AM +, Chocron, Jonathan wrote:
> On Wed, 2019-08-07 at 17:36 +0100, Lorenzo Pieralisi wr
On Wed, Aug 07, 2019 at 09:27:45PM -0400, Sasha Levin wrote:
> On Wed, Aug 07, 2019 at 04:06:54PM +0100, Lorenzo Pieralisi wrote:
> > On Tue, Jul 23, 2019 at 04:21:07PM -0500, Bjorn Helgaas wrote:
> > > On Sat, Jul 13, 2019 at 11:03:53AM -0400, Sasha Levin wrote:
> > > &
On Tue, Jul 23, 2019 at 12:27:11PM +0300, Jonathan Chocron wrote:
> This basically aligns the usage of PCI_PROBE_ONLY and
> PCI_REASSIGN_ALL_BUS in dw_pcie_host_init() with the logic in
> pci_host_common_probe().
>
> Now it will be possible to control via the devicetree whether to just
> probe
On Tue, Jul 23, 2019 at 04:21:07PM -0500, Bjorn Helgaas wrote:
> On Sat, Jul 13, 2019 at 11:03:53AM -0400, Sasha Levin wrote:
> > On Fri, Jul 12, 2019 at 04:04:17PM +, Haiyang Zhang wrote:
> > > > -Original Message-
> > > > From: Randy Dunlap
> > > > Sent: Friday, July 12, 2019 11:53
On Fri, Jun 28, 2019 at 03:34:23PM +0800, Jianjun Wang wrote:
> These series patches modify pcie-mediatek.c and dt-bindings compatible
> string to support MT7629 PCIe host.
>
> Jianjun Wang (2):
> dt-bindings: PCI: Add support for MT7629
> PCI: mediatek: Add controller support for MT7629
>
>
On Tue, Aug 06, 2019 at 05:16:24PM +0100, Sudeep Holla wrote:
> On Mon, Jul 22, 2019 at 04:37:44PM +0100, Lorenzo Pieralisi wrote:
> > Allow selection of the PSCI CPUidle in the kernel by adding
> > the required Kconfig options.
> >
> > Remove PSCI callbacks fro
On Tue, Aug 06, 2019 at 05:10:33PM +0100, Sudeep Holla wrote:
> On Mon, Jul 22, 2019 at 04:37:43PM +0100, Lorenzo Pieralisi wrote:
> > PSCI firmware is the standard power management control for
> > all ARM64 based platforms and it is also deployed on some
> > ARM 32
On Fri, Jun 14, 2019 at 12:10:59PM +0200, Remi Pommarel wrote:
> PCI_EXP_RTCTL is used to activate PME interrupt only, so writing into it
> should not modify other interrupts' mask. The ISR mask polarity was also
> inverted, when PCI_EXP_RTCTL_PMEIE is set PCIE_MSG_PM_PME_MASK mask bit
> should
[trim the CC list please to keep only required maintainers]
On Mon, Jul 29, 2019 at 03:38:38PM +0800, Jianjun Wang wrote:
> On Fri, 2019-06-28 at 15:34 +0800, Jianjun Wang wrote:
> > MT7629 is an ARM platform SoC which has the same PCIe IP with MT7622.
> >
> > The HW default value of its Device
On Mon, Aug 05, 2019 at 10:24:42PM +0530, Vidya Sagar wrote:
[...]
> > > > IRQs are enabled when you call a suspend_noirq() callback, so the
> > > > blocking API can be used as long as the IRQ descriptor backing
> > > > the IRQ that will wake-up the blocked call is marked as
> > > >
On Fri, Aug 02, 2019 at 05:36:43PM +0530, Vidya Sagar wrote:
> On 7/30/2019 9:19 PM, Lorenzo Pieralisi wrote:
> > On Tue, Jul 23, 2019 at 08:14:08PM +0530, Vidya Sagar wrote:
> > > On 7/16/2019 4:52 PM, Lorenzo Pieralisi wrote:
> > > > On Sat, Jul 13, 2019 at 12:34
On Tue, Jul 23, 2019 at 08:14:08PM +0530, Vidya Sagar wrote:
> On 7/16/2019 4:52 PM, Lorenzo Pieralisi wrote:
> > On Sat, Jul 13, 2019 at 12:34:34PM +0530, Vidya Sagar wrote:
> >
> > [...]
> >
> > > > > > > +static int tegra_pcie_bpmp_set_ctrl
On Mon, Jul 29, 2019 at 03:38:38PM +0800, Jianjun Wang wrote:
> On Fri, 2019-06-28 at 15:34 +0800, Jianjun Wang wrote:
> > MT7629 is an ARM platform SoC which has the same PCIe IP with MT7622.
> >
> > The HW default value of its Device ID is invalid, fix its Device ID to
> > match the hardware
that we re-start the events before we start the PMU.
>
> That would be a fix for commit:
>
> da4e4f18afe0f372 ("drivers/perf: arm_pmu: implement CPU_PM notifier")
Yes that's correct, apologies. Probably we did not hit it because CPU PM
notifier entry failures are a pretty ra
On Tue, Jul 23, 2019 at 01:49:15PM +0200, Ulf Hansson wrote:
> On Mon, 22 Jul 2019 at 17:37, Lorenzo Pieralisi
> wrote:
> >
> > Current PSCI CPUidle driver is built on top of the generic ARM
> > CPUidle infrastructure that relies on the architectural back-end
> >
On Tue, Jul 23, 2019 at 01:46:56PM +0200, Ulf Hansson wrote:
> [...]
>
> > +++ b/drivers/cpuidle/cpuidle-psci.c
> > @@ -0,0 +1,150 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * PSCI CPU idle driver.
> > + *
> > + * Copyright (C)
ink: https://lore.kernel.org/linux-arm-kernel/20190613065410.GB16334@mwanda/
Reported-by: Dan Carpenter
Signed-off-by: Lorenzo Pieralisi
Cc: Dan Carpenter
Cc: Will Deacon
Cc: Hanjun Guo
Cc: Sudeep Holla
Cc: Catalin Marinas
Cc: Robin Murphy
---
drivers/acpi/arm64/iort.c | 4 ++--
1 file changed, 2 insert
d can lead
to subtle bugs.
Rename the local variable to prevent any issue.
Reported-by: Will Deacon
Signed-off-by: Lorenzo Pieralisi
Cc: Will Deacon
Cc: Hanjun Guo
Cc: Sudeep Holla
Cc: Catalin Marinas
Cc: Robin Murphy
Cc: Kefeng Wang
---
drivers/acpi/arm64/iort.c | 6 +++---
1 file changed, 3
The generic ARM CPUidle driver includes by mistake.
Remove the topology header include.
Signed-off-by: Lorenzo Pieralisi
Cc: Ulf Hansson
Cc: Sudeep Holla
Cc: Daniel Lezcano
Cc: "Rafael J. Wysocki"
---
drivers/cpuidle/cpuidle-arm.c | 1 -
1 file changed, 1 deletion(-)
diff --git
cpuidle_state.enter() function callback.
Signed-off-by: Lorenzo Pieralisi
Cc: Sudeep Holla
Cc: Mark Rutland
---
drivers/firmware/psci/psci_checker.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/firmware/psci/psci_checker.c
b/drivers/firmware/psci
not support CPUidle operations.
Signed-off-by: Lorenzo Pieralisi
Cc: Ulf Hansson
Cc: Sudeep Holla
Cc: Daniel Lezcano
Cc: "Rafael J. Wysocki"
---
drivers/cpuidle/cpuidle-arm.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/cpuidle/cpuidle-arm.c
ate
parameters before handing them over to the PSCI firmware
interface to trigger PSCI.CPU_SUSPEND() calls.
Signed-off-by: Lorenzo Pieralisi
Cc: Will Deacon
Cc: Ulf Hansson
Cc: Sudeep Holla
Cc: Daniel Lezcano
Cc: Catalin Marinas
Cc: Mark Rutland
Cc: "Rafael J. Wysocki"
---
arch
ael J. Wysocki"
Lorenzo Pieralisi (6):
ARM: cpuidle: Remove useless header include
ARM: cpuidle: Remove overzealous error logging
drivers: firmware: psci: Decouple checker from generic ARM CPUidle
ARM: psci: cpuidle: Introduce PSCI CPUidle driver
ARM: psci: cpuidle: Enable PSCI CPUi
states.
Update the affected defconfig files to guarantee seamingless
transition from the generic ARM CPUidle to the PSCI CPUidle
driver on arch/platforms using it.
Signed-off-by: Lorenzo Pieralisi
Cc: Will Deacon
Cc: Ulf Hansson
Cc: Sudeep Holla
Cc: Daniel Lezcano
Cc: Catalin Marinas
Cc: Mark
.
Signed-off-by: Lorenzo Pieralisi
Cc: Ulf Hansson
Cc: Sudeep Holla
Cc: Daniel Lezcano
Cc: Mark Rutland
Cc: "Rafael J. Wysocki"
---
MAINTAINERS| 8 ++
drivers/cpuidle/Kconfig.arm| 3 +
drivers/cpuidle/Makefile | 1 +
drivers/cpuidle/cpuidle-ps
ix this quite upsetting situation by limiting the vendor and device IDs
> to which the Relaxed Ordering quirk applies to the root ports in
> question, reported above.
>
> Signed-off-by: Vidya Sagar
> [lorenzo.pieral...@arm.com: completely rewrote the commit log/fixes tag]
>
On Mon, May 13, 2019 at 09:22:43PM +0200, Ulf Hansson wrote:
> From: Lina Iyer
>
> Update DT bindings to represent hierarchical CPU and CPU PM domain idle
> states for PSCI. Also update the PSCI examples to clearly show how
> flattened and hierarchical idle states can be represented in DT.
>
>
On Thu, Jul 18, 2019 at 11:49:11PM +0200, Ulf Hansson wrote:
> On Thu, 18 Jul 2019 at 19:41, Lina Iyer wrote:
> >
> > On Thu, Jul 18 2019 at 10:55 -0600, Ulf Hansson wrote:
> > >On Thu, 18 Jul 2019 at 15:31, Lorenzo Pieralisi
> > > wrote:
> > >>
&g
On Thu, Jul 18, 2019 at 01:43:44PM +0200, Ulf Hansson wrote:
[...]
> > > Anyway, as a suggestion to address your concern, how about this:
> > >
> > > 1. Move some things out to a PSCI cpuidle driver. We need to decide
> > > more exactly on what to move and find the right level for the
> > >
On Thu, Jul 18, 2019 at 12:35:07PM +0200, Ulf Hansson wrote:
> On Tue, 16 Jul 2019 at 17:53, Lorenzo Pieralisi
> wrote:
> >
> > On Mon, May 13, 2019 at 09:22:56PM +0200, Ulf Hansson wrote:
> > > When the hierarchical CPU topology layout is used in DT, let's allow the
&g
On Mon, May 13, 2019 at 09:22:56PM +0200, Ulf Hansson wrote:
> When the hierarchical CPU topology layout is used in DT, let's allow the
> CPU to be power managed through its PM domain, via deploying runtime PM
> support.
>
> To know for which idle states runtime PM reference counting is needed,
>
On Tue, Jul 16, 2019 at 10:45:49AM +0200, Ulf Hansson wrote:
[...]
> > > +static void psci_pd_convert_states(struct cpuidle_state *idle_state,
> > > + u32 *psci_state, struct genpd_power_state *state)
> > > +{
> > > + u32 *state_data = state->data;
> > > + u64
On Sat, Jul 13, 2019 at 12:34:34PM +0530, Vidya Sagar wrote:
[...]
> > > > > +static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
> > > > > + bool enable)
> > > > > +{
> > > > > + struct mrq_uphy_response resp;
> > > > > + struct
On Fri, Jul 12, 2019 at 09:02:49PM +0530, Vidya Sagar wrote:
[...]
> > > +static irqreturn_t tegra_pcie_irq_handler(int irq, void *arg)
> > > +{
> > > + struct tegra_pcie_dw *pcie = arg;
> > > +
> > > + if (pcie->mode == DW_PCIE_RC_TYPE)
> > > + return tegra_pcie_rp_irq_handler(pcie);
>
On Wed, Jul 10, 2019 at 11:52:12AM +0530, Vidya Sagar wrote:
[...]
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c
> b/drivers/pci/controller/dwc/pcie-tegra194.c
> new file mode 100644
> index ..189779edd976
> --- /dev/null
> +++
On Thu, Jul 11, 2019 at 10:12:35AM +0300, Shenhar, Talel wrote:
>
> On 7/10/2019 7:45 PM, Jonathan Chocron wrote:
> > Document Amazon's Annapurna Labs PCIe host bridge.
>
> That is the way! (best to keep same wordings (Amazon's)
Guys,
as a heads-up, the original posting, for whatever reason,
On Wed, Jul 10, 2019 at 11:52:12AM +0530, Vidya Sagar wrote:
[...]
> +#if defined(CONFIG_PCIEASPM)
> +static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
> +{
> + u32 val;
> +
> + val = dw_pcie_readl_dbi(>pci, pcie->cfg_link_cap_l1sub);
> + val &= ~PCI_L1SS_CAP_ASPM_L1_1;
> +
On Wed, Jul 10, 2019 at 11:52:08AM +0530, Vidya Sagar wrote:
> Some host controllers need to know the existence of clkreq signal routing to
> downstream devices to be able to advertise low power features like ASPM L1
> substates. Without clkreq signal routing being present, enabling ASPM L1 sub
>
On Wed, Jul 10, 2019 at 04:57:23PM +0530, Vidya Sagar wrote:
> On 7/10/2019 4:07 PM, Lorenzo Pieralisi wrote:
> > On Wed, Jul 10, 2019 at 11:52:05AM +0530, Vidya Sagar wrote:
> > > Add extended configuration space capability search API using struct
> > > dw_pcie *
>
On Wed, Jul 10, 2019 at 11:52:05AM +0530, Vidya Sagar wrote:
> Add extended configuration space capability search API using struct dw_pcie *
> pointer
Sentences are terminated with a period and this is v13 not v1, which
proves that you do not read the commit logs you write.
I need you guys to
On Fri, Jun 14, 2019 at 11:40:44PM +0800, YueHaibing wrote:
> Fix build error:
>
> drivers/pci/controller/dwc/pci-dra7xx.c:
> In function dra7xx_pcie_probe:
> drivers/pci/controller/dwc/pci-dra7xx.c:777:10:
> error: implicit declaration of function devm_gpiod_get_optional;
> did you mean
On Mon, May 13, 2019 at 09:22:52PM +0200, Ulf Hansson wrote:
> If the hierarchical CPU topology is used, but the OS initiated mode isn't
> supported, we need to rely solely on the regular cpuidle framework to
> manage the idle state selection, rather than using genpd and its governor.
>
> For
On Fri, Jul 05, 2019 at 05:56:28PM +0800, Hou Zhiqiang wrote:
> This patch set is to add fixes for Mobiveil PCIe Host driver.
> Splited #2, #3, #9 and #10 of v5 patches.
>
> Hou Zhiqiang (28):
> PCI: mobiveil: Unify register accessors
> PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
>
On Fri, Jun 14, 2019 at 11:40:44PM +0800, YueHaibing wrote:
> Fix build error:
>
> drivers/pci/controller/dwc/pci-dra7xx.c:
> In function dra7xx_pcie_probe:
> drivers/pci/controller/dwc/pci-dra7xx.c:777:10:
> error: implicit declaration of function devm_gpiod_get_optional;
> did you mean
On Fri, Jul 05, 2019 at 09:48:50AM +0100, Jon Hunter wrote:
> Commit 5e5e9c23f82a ("PCI: tegra: Add support for GPIO based PERST#")
> calls the function devm_gpiod_get_from_of_node() to request a GPIO.
> Unfortunately, around the same time this was merged, commit 025bf37725f1
> ("gpio: Fix return
On Thu, Jul 04, 2019 at 03:00:37AM +, Z.q. Hou wrote:
[...]
> > If you can manage to rebase patches on pci/mobiveil on top of v5.2-rc1,
> > send them separately so that I can merge them as a base for the subsequent
> > patches to be applied.
>
> You meant send the patches one by one, which
On Wed, Jul 03, 2019 at 04:19:05PM +0100, Lorenzo Pieralisi wrote:
> On Fri, Apr 12, 2019 at 08:35:24AM +, Z.q. Hou wrote:
> > From: Hou Zhiqiang
> >
> > Just format the code without functionality change.
> >
> > Signed-off-by: Hou Zhiqiang
> > Rev
On Fri, Apr 12, 2019 at 08:35:24AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> Just format the code without functionality change.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V5:
> - Retouched the subject.
>
> drivers/pci/controller/pcie-mobiveil.c | 261
On Fri, Apr 12, 2019 at 08:35:24AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> Just format the code without functionality change.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V5:
> - Retouched the subject.
>
> drivers/pci/controller/pcie-mobiveil.c | 261
On Fri, Apr 12, 2019 at 08:35:30AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> This patch corrects the returned error number by convention,
> and removes an unnecessary error check.
Two distinct changes, two patches, please split and repost.
Lorenzo
> Signed-off-by: Hou Zhiqiang
>
On Fri, Apr 12, 2019 at 08:35:11AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> This patch set is to add fixes for Mobiveil PCIe Host driver.
> And these patches are splited from the thread below:
> http://patchwork.ozlabs.org/project/linux-pci/list/?series=96417
>
> Hou Zhiqiang (20):
>
On Fri, Apr 12, 2019 at 08:36:12AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> In the loop block, there is not code to update the loop key,
> this patch updates the loop key by re-read the INTx status
> register.
>
> This patch also add the clearing of the handled INTx status.
This is two
On Fri, Apr 12, 2019 at 08:36:06AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> Outbound window routine:
> - Remove unused var definitions and register read operations.
> - Add the upper 32-bit cpu address setup of the window.
> - Instead of blindly write, only change the fields specified.
On Fri, Apr 12, 2019 at 08:36:00AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> The inbound windows have independent register set against outbound windows.
> This patch change the MEM inbound window to the first one.
You mean that windows 0 can be used as well as window 1 for inbound
windows
On Mon, Jun 17, 2019 at 10:34:35AM +, Z.q. Hou wrote:
[...]
> > There is nothing obvious. Write what you are fixing in the commit log and I
> > will
> > apply the patch, I won't write the commit log for you. Anyone should be able
> > to understand why a patch was needed by reading the
On Fri, Jun 28, 2019 at 12:29:45PM +0200, Arnd Bergmann wrote:
> linux/gpio.h is not the correct header for modern interfaces and
> causes a build failure without CONFIG_GPIOLIB:
>
> drivers/pci/controller/pci-tegra.c: In function 'tegra_pcie_port_reset':
>
On Thu, Jun 27, 2019 at 09:03:08PM +0530, Vidya Sagar wrote:
> On 6/27/2019 8:28 PM, Lorenzo Pieralisi wrote:
> > On Mon, Jun 24, 2019 at 02:44:56PM +0530, Vidya Sagar wrote:
> > > Remove multiple write enable and disable sequences of dbi registers as
> > > Tegra194
On Mon, Jun 24, 2019 at 02:44:56PM +0530, Vidya Sagar wrote:
> Remove multiple write enable and disable sequences of dbi registers as
> Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by
> DBI write-lock enable bit thereby not allowing any further writes to BAR-0
> register
On Mon, Jun 24, 2019 at 02:44:54PM +0530, Vidya Sagar wrote:
> Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
> features.
>
> Signed-off-by: Vidya Sagar
> Reviewed-by: Thierry Reding
> ---
> Changes since [v10]:
> * None
>
> Changes since [v9]:
> * None
>
> Changes
On Mon, Jun 17, 2019 at 01:43:36PM +0100, Lorenzo Pieralisi wrote:
> On Fri, Jun 14, 2019 at 12:10:59PM +0200, Remi Pommarel wrote:
> > PCI_EXP_RTCTL is used to activate PME interrupt only, so writing into it
> > should not modify other interrupts' mask. The ISR mask polarity was al
On Tue, Jun 25, 2019 at 02:52:36PM +0530, Vidya Sagar wrote:
> Add an API to group all the tasks to be done to de-initialize host which
> can then be called by any DesignWare core based driver implementations
> while adding .remove() support in their respective drivers.
>
> Signed-off-by: Vidya
On Sat, Jun 22, 2019 at 11:40:29PM +1000, Stephen Rothwell wrote:
> Hi all,
>
> In commit
>
> 46c1bfcfcd87 ("PCI: xilinx-nwl: Fix Multi MSI data programming")
>
> Fixes tag
>
> Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe
>
> has these problem(s):
>
> -
On Fri, Jun 21, 2019 at 04:39:59PM +0530, Vidya Sagar wrote:
> Cleanup DBI read and write APIs by removing "__" (underscore) from their
> names as there are no no-underscore versions and the underscore versions
> are already doing what no-underscore versions typically do. It also removes
> passing
On Wed, Jun 19, 2019 at 10:41:26AM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On 18/06/19 7:58 PM, Lorenzo Pieralisi wrote:
> > On Tue, Jun 18, 2019 at 04:21:17PM +0530, Vidya Sagar wrote:
> >
> > [...]
> >
> >>> 2) It is not related
gister_device(void)
> +{
> + return -ENODEV;
> +}
> +#endif /* CONFIG_ARM_SPE_PMU */
> +
> static int arm_pmu_acpi_parse_irqs(void)
> {
> int irq, cpu, irq_cpu, err;
> @@ -279,6 +352,8 @@ static int arm_pmu_acpi_init(void)
> if (acpi_disabled)
>
On Tue, Jun 18, 2019 at 04:21:17PM +0530, Vidya Sagar wrote:
[...]
> > 2) It is not related to this patch but I fail to see the reasoning
> > behind the __ in __dw_pci_read_dbi(), there is no no-underscore
> > equivalent so its definition is somewhat questionable, maybe
> > we should
On Tue, Jun 18, 2019 at 12:28:02PM +, Bharat Kumar Gogada wrote:
[...]
> > Applied to pci/xilinx for v5.3, please have a look and check if the commit
> > log
> > I wrote provides a clear description of the issue.
> >
> > Lorenzo
> Thanks Lorenzo and Marc.
> Lorenzo, can you please point to
On Tue, Jun 18, 2019 at 10:19:14AM +0530, Vidya Sagar wrote:
[...]
> Sorry for pinging again. Please let me know if these patches need to
> be sent again.
No problem. We can merge the code as-is even though I have a couple
of questions.
1) What about dbi2 interfaces (what an horrible name it
On Fri, Jun 14, 2019 at 10:19:02PM +, Dexuan Cui wrote:
> > -Original Message-
> > From: Michael Kelley
> > Sent: Friday, June 14, 2019 1:48 PM
> > To: Dexuan Cui ; linux-a...@vger.kernel.org;
> > r...@rjwysocki.net; l...@kernel.org; robert.mo...@intel.com;
> > erik.schma...@intel.com
On Fri, Jun 14, 2019 at 12:10:59PM +0200, Remi Pommarel wrote:
> PCI_EXP_RTCTL is used to activate PME interrupt only, so writing into it
> should not modify other interrupts' mask. The ISR mask polarity was also
> inverted, when PCI_EXP_RTCTL_PMEIE is set PCIE_MSG_PM_PME_MASK mask bit
> should
On Wed, Jun 12, 2019 at 02:42:00PM +0800, Ley Foon Tan wrote:
> This fix issue when access config from PCIe switch.
>
> Stratix 10 PCIe controller does not support Type 1 to Type 0 conversion
> as previous version (V1) does.
>
> The PCIe controller need to send Type 0 config TLP if the targeting
On Sat, Jun 15, 2019 at 01:30:39AM +, Z.q. Hou wrote:
> Hi Lorenzo,
>
> > -Original Message-
> > From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
> > Sent: 2019年6月12日 21:08
> > To: Z.q. Hou
> > Cc: linux-...@vger.kernel.org; linux-arm-ker
On Sat, Jun 15, 2019 at 05:03:33AM +, Z.q. Hou wrote:
> Hi Lorenzo,
>
> > -Original Message-
> > From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
> > Sent: 2019年6月13日 0:24
> > To: Z.q. Hou ; bhelg...@google.com
> > Cc: linu
On Sat, Jun 15, 2019 at 01:13:48AM +, Z.q. Hou wrote:
> Hi Lorenzo,
>
> > -Original Message-
> > From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
> > Sent: 2019年6月12日 21:54
> > To: Z.q. Hou
> > Cc: linux-...@vger.kernel.org; linux-arm-ker
On Wed, Jun 12, 2019 at 03:47:59PM +0530, Bharat Kumar Gogada wrote:
> The current Multi MSI data programming fails if multiple end points
> requesting MSI and multi MSI are connected with switch, i.e the current
> multi MSI data being given is not considering the number of vectors
> being
On Fri, Jun 14, 2019 at 10:19:10PM +0800, Yuehaibing wrote:
> Hi all,
>
> Friendly ping...
We should address Michael's question:
https://lore.kernel.org/linux-pci/byapr21mb12211eea95200f437c8e37ecd7...@byapr21mb1221.namprd21.prod.outlook.com/
Lorenzo
> On 2019/5/31 23:09, YueHaibing wrote:
>
Mitran
Ok I assume this means you tested it but according to what you
say above, are there still issues with this code path ? Should
we update the patch ?
Moreover:
https://kernelnewbies.org/PatchCulture
Please read it and never top-post.
Thanks,
Lorenzo
> On Wed, Jun 12, 2019 at
On Wed, May 22, 2019 at 11:33:49PM +0200, Remi Pommarel wrote:
> PCI_EXP_RTCTL is used to activate PME interrupt only, so writing into it
> should not modify other interrupts' mask (such as ISR0).
>
> Fixes: 6302bf3ef78d ("PCI: Init PCIe feature bits for managed host bridge
> alloc")
>
On Wed, Jun 12, 2019 at 02:01:56PM +0100, Marc Zyngier wrote:
> On Wed, 12 Jun 2019 11:17:59 +0100,
> Bharat Kumar Gogada wrote:
> >
> > The current Multi MSI data programming fails if multiple end points
> > requesting MSI and multi MSI are connected with switch, i.e the current
> > multi MSI
On Fri, Apr 12, 2019 at 08:37:00AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> Disable all inbound and outbound windows before set up the windows
> in kernel, in case transactions match the window set by bootloader.
There must be no PCI transactions ongoing at bootloader<->OS handover.
The
On Fri, Apr 12, 2019 at 08:35:54AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> As the .map_bus() use the WIN_NUM_0 for CFG transactions,
> it's better passing WIN_NUM_0 explicitly when initialize
> the CFG outbound window.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
>
On Fri, Apr 12, 2019 at 08:36:12AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> In the loop block, there is not code to update the loop key,
> this patch updates the loop key by re-read the INTx status
> register.
>
> This patch also add the clearing of the handled INTx status.
>
> Note:
On Fri, Apr 12, 2019 at 08:36:54AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> Sometimes there is not a PCIe Endpoint stalled in the slot,
> so do not exit when the PCIe link is not up. And degrade the
> print level of link up info.
So what's the point of probing if the link does not
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