[PATCH 1/3] Add BOOT_PARTITION_ENABLE definition to MMC EXT_CSD PART_CONFIG
Add bit mask for the BOOT_PARTITION_ENABLE values.
Signed-off-by: Neil Armstrong
---
include/linux/mmc/mmc.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index 50bcde3..eb5b361 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -347,6 +347,7 @@ struct _mmc_csd {
#define EXT_CSD_PART_CONFIG_ACC_BOOT0(0x1)
#define EXT_CSD_PART_CONFIG_ACC_RPMB(0x3)
#define EXT_CSD_PART_CONFIG_ACC_GP0(0x4)
+#define EXT_CSD_PART_CONFIG_EN_MASK(0x38)
#define EXT_CSD_PART_SUPPORT_PART_EN(0x1)
--
1.7.0.4
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[PATCH 0/3] Add boot_enable attribute to eMMC device for boot mode operation selection
Since eMMC 4.3 a special boot mode operation was introduced to retrieve data from the eMMC device with a very simple procedure. Since the Linux kernel exports these device boot partitions, it may be useful to select the boot partition from the user space. The patch has been tested on a Toshiba eMMC conforming with eMMC 4.5 specifications. Neil Armstrong (3): Add BOOT_PARTITION_ENABLE definition to MMC EXT_CSD PART_CONFIG Add boot_enable sysfs attribute to select MMC boot operation partition Add Documentation for MMC boot_enable attribute Documentation/mmc/mmc-dev-parts.txt |6 +++ drivers/mmc/card/block.c| 72 ++- include/linux/mmc/mmc.h |1 + 3 files changed, 78 insertions(+), 1 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/3] Add boot_enable sysfs attribute to select MMC boot operation partition
Add sysfs attribute to select the eMMC boot mode operation according to
the eMMC 4.5 specifications.
Valid values are : 0 for disabled, 1 for first boot partition, 2 for
second boot partition, 7 for user area.
Signed-off-by: Neil Armstrong
---
drivers/mmc/card/block.c | 72
+-
1 files changed, 71 insertions(+), 1 deletions(-)
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index 5bab73b..e11c42e 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -114,6 +114,7 @@ struct mmc_blk_data {
*/
unsigned intpart_curr;
struct device_attribute force_ro;
+struct device_attribute boot_enable;
struct device_attribute power_ro_lock;
intarea_type;
};
@@ -264,6 +265,23 @@ static ssize_t force_ro_show(struct device *dev,
struct device_attribute *attr,
return ret;
}
+static ssize_t boot_enable_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+int ret;
+struct mmc_card *card;
+struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev));
+
+md = mmc_blk_get(dev_to_disk(dev));
+card = md->queue.card;
+
+ret = snprintf(buf, PAGE_SIZE, "%d",
+(card->ext_csd.part_config &
+ EXT_CSD_PART_CONFIG_EN_MASK) >> 3);
+mmc_blk_put(md);
+return ret;
+}
+
static ssize_t force_ro_store(struct device *dev, struct
device_attribute *attr,
const char *buf, size_t count)
{
@@ -283,6 +301,48 @@ out:
return ret;
}
+static ssize_t boot_enable_store(struct device *dev,
+ struct device_attribute *attr, const char *buf,
+ size_t count)
+{
+int ret;
+char *end;
+u8 part_config;
+struct mmc_card *card;
+struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev));
+unsigned long set = simple_strtoul(buf, &end, 0);
+if (end == buf) {
+ret = -EINVAL;
+goto out;
+}
+
+md = mmc_blk_get(dev_to_disk(dev));
+card = md->queue.card;
+
+part_config = card->ext_csd.part_config;
+
+part_config &= EXT_CSD_PART_CONFIG_EN_MASK;
+part_config |= (set << 3) & EXT_CSD_PART_CONFIG_EN_MASK;
+
+mmc_claim_host(card->host);
+
+ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_PART_CONFIG, part_config,
+ card->ext_csd.part_time);
+
+mmc_release_host(card->host);
+
+if (ret)
+return ret;
+
+card->ext_csd.part_config = part_config;
+
+ret = count;
+out:
+mmc_blk_put(md);
+return ret;
+}
+
static int mmc_blk_open(struct block_device *bdev, fmode_t mode)
{
struct mmc_blk_data *md = mmc_blk_get(bdev->bd_disk);
@@ -2202,6 +2262,15 @@ static int mmc_add_disk(struct mmc_blk_data *md)
if (ret)
goto force_ro_fail;
+md->boot_enable.show = boot_enable_show;
+md->boot_enable.store = boot_enable_store;
+sysfs_attr_init(&md->boot_enable.attr);
+md->boot_enable.attr.name = "boot_enable";
+md->boot_enable.attr.mode = S_IRUGO | S_IWUSR;
+ret = device_create_file(disk_to_dev(md->disk), &md->boot_enable);
+if (ret)
+goto boot_enable_fail;
+
if ((md->area_type & MMC_BLK_DATA_AREA_BOOT) &&
card->ext_csd.boot_ro_lockable) {
umode_t mode;
@@ -2225,6 +2294,8 @@ static int mmc_add_disk(struct mmc_blk_data *md)
return ret;
power_ro_lock_fail:
+device_remove_file(disk_to_dev(md->disk), &md->boot_enable);
+boot_enable_fail:
device_remove_file(disk_to_dev(md->disk), &md->force_ro);
force_ro_fail:
del_gendisk(md->disk);
@@ -2434,4 +2505,3 @@ module_exit(mmc_blk_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Multimedia Card (MMC) block device driver");
-
--
1.7.0.4
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[PATCH 3/3] Add Documentation for MMC boot_enable attribute
Add documentation on the enable_boot sysfs attribute. Signed-off-by: Neil Armstrong --- Documentation/mmc/mmc-dev-parts.txt |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/Documentation/mmc/mmc-dev-parts.txt b/Documentation/mmc/mmc-dev-parts.txt index f08d078..78228de 100644 --- a/Documentation/mmc/mmc-dev-parts.txt +++ b/Documentation/mmc/mmc-dev-parts.txt @@ -38,3 +38,9 @@ feature has been disabled on the card, the file will be read-only. The boot partitions can also be locked permanently, but this feature is not accessible through sysfs in order to avoid accidental or malicious bricking. + +A special attribute named boot_enable is available to configure the +selected partition for the eMMC 4.3+ boot operation mode. +When selected between the two factory boot partitions and the main +user partition, at boot time a special sequence enables makes the +eMMC device to output the content of the selected partition. -- 1.7.0.4 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Add boot_enable attribute to eMMC device for boot mode operation selection
On 04/22/2013 06:55 AM, Namjae Jeon wrote: > 2013/4/19, Neil Armstrong : >> Since eMMC 4.3 a special boot mode operation was introduced to retrieve >> data from the eMMC device with a very simple procedure. Since the Linux >> kernel exports these device boot partitions, it may be useful to select >> the boot partition from the user space. >> >> The patch has been tested on a Toshiba eMMC conforming with eMMC 4.5 >> specifications. > Hi Neil. > We can be enable boot partition using mmc-utils. > See this address. > https://git.kernel.org/cgit/linux/kernel/git/cjb/mmc-utils.git/commit/?id=7bd1320b2cb38f040ab5cf017d17e283496690bf > > So, I don't think this patch is useful. > If you consider to be disable boot partition, you can try to update > mmc-utils base on the address I shared. > > Thanks. >> >> Neil Armstrong (3): >> Add BOOT_PARTITION_ENABLE definition to MMC EXT_CSD PART_CONFIG >> Add boot_enable sysfs attribute to select MMC boot operation >> partition >> Add Documentation for MMC boot_enable attribute >> >> Documentation/mmc/mmc-dev-parts.txt |6 +++ >> drivers/mmc/card/block.c| 72 >> ++- >> include/linux/mmc/mmc.h |1 + >> 3 files changed, 78 insertions(+), 1 deletions(-) >> >> >> > Hi, Thanks for the reply, I was not aware of the mmc-utils tools. I think the tool and the MMC_IOC_CMD interface should be documented in the kernel. Please ignore my patch. Regards, Neil -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 1/8] scpi: Add cmd indirection table to prepare for legacy commands
On 09/19/2016 04:41 PM, Sudeep Holla wrote:
> Hi Neil,
>
> On 07/09/16 16:34, Neil Armstrong wrote:
>> Add indirection table to permit multiple command values for legacy support.
>>
>
> I wrote the most of the patch and you changed the author too ;)
Sorry, forgot this ! v4 will have it !
>
>> Signed-off-by: Neil Armstrong
>> ---
>> drivers/firmware/arm_scpi.c | 145
>> ++--
>> 1 file changed, 127 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
>> index 4388937..9a87687 100644
>> --- a/drivers/firmware/arm_scpi.c
>> +++ b/drivers/firmware/arm_scpi.c
>
> [..]
>
>> @@ -161,6 +194,7 @@ struct scpi_drvinfo {
>> u32 protocol_version;
>> u32 firmware_version;
>> int num_chans;
>> +int *scpi_cmds;
>> atomic_t next_chan;
>> struct scpi_ops *scpi_ops;
>> struct scpi_chan *channels;
>> @@ -390,6 +424,19 @@ static u32 scpi_get_version(void)
>> return scpi_info->protocol_version;
>> }
>>
>> +static inline int check_cmd(unsigned int offset)
>> +{
>> +if (offset >= CMD_MAX_COUNT ||
>
> If we call scpi_send_message internally(as it's static) why is this
> check needed ?
>
>
>> +!scpi_info ||
>> +!scpi_info->scpi_cmds)
>
> Will be even reach to this point if above is true ?
>
>> +return -EINVAL;
>> +
>> +if (scpi_info->scpi_cmds[offset] < 0)
>> +return -EOPNOTSUPP;
>
> IMO just above couple of lines in the beginning of scpi_send_message
> will suffice. You can just add this to my original patch.
Will do.
>
>> static int
>> scpi_clk_get_range(u16 clk_id, unsigned long *min, unsigned long *max)
>> {
>> @@ -397,8 +444,13 @@ scpi_clk_get_range(u16 clk_id, unsigned long *min,
>> unsigned long *max)
>> struct clk_get_info clk;
>> __le16 le_clk_id = cpu_to_le16(clk_id);
>>
>> -ret = scpi_send_message(SCPI_CMD_GET_CLOCK_INFO, &le_clk_id,
>> -sizeof(le_clk_id), &clk, sizeof(clk));
>> +ret = check_cmd(CMD_GET_CLOCK_INFO);
>> +if (ret)
>> +return ret;
>> +
>
> It's totally unnecessary to add check in each and every function calling
> scpi_send_message, why not add it to scpi_send_message instead.
>
This was my first thought, I should have stayed at this !
Thanks,
Neil
Re: [PATCH] gpio: sx150x: Update OF configuration
On 06/18/2016 11:02 AM, Linus Walleij wrote: > On Fri, Jun 17, 2016 at 11:51 AM, Neil Armstrong > wrote: > >> In case of OF probing, the driver fails to initialize : >> - gpio_chip.base must be -1 >> - irq_summary must be either -1 or valid >> - There is no way to use the other configurations >> >> Add OF parsing function to complete the HW configuration, make >> OF configuration dynamic instead of static with #defines and >> update the DT bindings. >> >> Signed-off-by: Neil Armstrong > > As you can see from the result of the build robot, the removal > of #ifdef CONFIG_OF_GPIO does not play well with non-DT > configurarions. > > You need to figure something out here so that it builds for > both. OK, I'll find out. Thanks, Neil > Yours, > Linus Walleij >
Re: [PATCH 0/2] usb: phy: Add support for the Qualcomm HSIC USB PHY
On 06/17/2016 06:39 PM, Stephen Boyd wrote: > On 06/17/2016 03:25 AM, Neil Armstrong wrote: >> In order to support the Qualcomm MDM9615 in the Sierra Wireless WP8548 >> Modules, add the Qualcomm HSIC USB PHY used inside the MDM9615 SoC. >> >> This patchset is part of a global SoC + Module + Board support for the >> Sierra Wireless mangOH Board support with the WP8548 module. >> >> > > I've been working on an hsic driver for apq8074 which matches the same > hardware. I was going to send it out this week but got dragged down into > the HS phy part of it and fixing all the OTG handling. I'd prefer we > don't go down the route of your patches which ioremap the controller > address space in the phy driver. Instead we should use the ULPI bus that > was recently introduced. Care to take my patches for a spin[1]? I'll Cc > you on them once I send them out, which should be very soon. > > [1] > https://git.linaro.org/people/stephen.boyd/linux.git/shortlog/refs/heads/usb-hsic-8074 > Hi Stephen, No problem, my implementation was very basic and Host-mode only. I must check if it's still functional but yes, I'll take your patches. Neil
Re: [PATCH 5/5] regulator: qcom_rpm-regulator: Add support for pm8018 rpm regulator
On 06/17/2016 06:53 PM, Bjorn Andersson wrote:
> On Fri 17 Jun 03:22 PDT 2016, Neil Armstrong wrote:
>
>> In order to support eh Qualcomm MDM9615 SoC, add support for the
>> PM8018 RPM regulator in the qcom_rpm-regulator driver.
>>
>> Signed-off-by: Neil Armstrong
> [..]
>> diff --git a/drivers/regulator/qcom_rpm-regulator.c
>> b/drivers/regulator/qcom_rpm-regulator.c
> [..]
>> +/**
>> + * enum rpm_vreg_voltage_corner - possible voltage corner values
>> + *
>> + * These should be used in regulator_set_voltage and rpm_vreg_set_voltage
>> calls
>> + * for corner type regulators as if they had units of uV.
>> + */
>> +enum rpm_vreg_voltage_corner {
>> +RPM_VREG_CORNER_NONE = 1,
>> +RPM_VREG_CORNER_LOW,
>> +RPM_VREG_CORNER_NOMINAL,
>> +RPM_VREG_CORNER_HIGH,
>> +};
>> +
>> +static struct regulator_linear_range corner_ranges[] = {
>> +REGULATOR_LINEAR_RANGE(RPM_VREG_CORNER_NONE, 0,
>> +RPM_VREG_CORNER_HIGH, 1),
>> +};
>> +
>> static int rpm_reg_write(struct qcom_rpm_reg *vreg,
> [..]
>> +
>> +static const struct qcom_rpm_reg pm8018_corner = {
>> +.desc.linear_ranges = corner_ranges,
>> +.desc.n_linear_ranges = ARRAY_SIZE(corner_ranges),
>> +.desc.n_voltages = 4,
>> +.desc.ops = &uV_ops,
>> +.parts = &rpm8018_corner_parts,
>> +};
>> +
> [..]
>> +static const struct rpm_regulator_data rpm_pm8018_regulators[] = {
> [..]
>> +{ "dig_corner", QCOM_RPM_VOLTAGE_CORNER, &pm8018_corner,
>> + "vdd_dig_corner" },
>> +
>> +{ }
>> +};
>
> We have discussed the corners for a long time and I think we've
> concluded that they should be exposed as something like an OPP. What we
> have agreed on is that they should not be exposed as a regulator with
> voltages 1-4uV.
>
> So please drop the corner for now.
OK,
Thanks,
Neil
>
> Regards,
> Bjorn
>
[PATCH v2] gpio: sx150x: Update OF configuration
In case of OF probing, the driver fails to initialize :
- gpio_chip.base must be -1
- irq_summary must be either -1 or valid
- There is no way to use the other configurations
Add OF parsing function to complete the HW configuration, make
OF configuration dynamic instead of static with #defines and
update the DT bindings.
Signed-off-by: Neil Armstrong
---
Changes since v1 at
http://lkml.kernel.org/r/1466157063-10955-1-git-send-email-narmstr...@baylibre.com:
- Put back #ifdef CONFIG_OF_GPIO to remove OF code for non-of platforms
.../devicetree/bindings/gpio/gpio-sx150x.txt | 17 ++
drivers/gpio/gpio-sx150x.c | 67 --
2 files changed, 79 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/gpio-sx150x.txt
b/Documentation/devicetree/bindings/gpio/gpio-sx150x.txt
index c809acb..d2b5bb3 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-sx150x.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-sx150x.txt
@@ -22,6 +22,17 @@ Required properties:
- interrupt-controller: Marks the device as a interrupt controller.
+Optional Properties:
+- oscio-is-gpo: Boolean, Indicated the oscio pin can be used as additional
+ output gpo port.
+
+- pull-up-ports: Array of port numbers which must have pull-up enabled.
+- pull-down-ports: Array of port numbers which must have pull-down enabled.
+- open-drain-ports: Array of port numbers which must be configured as
open-drain,
+ Push-Pull mode is default.
+- polarity-invert-ports: Array of port numbers whih port polarity must be
inverted.
+- probe-reset: Boolean, Indicates the expander must be resetted.
+
The GPIO expander can optionally be used as an interrupt controller, in
which case it uses the default two cell specifier as described in
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
@@ -38,4 +49,10 @@ Example:
gpio-controller;
interrupt-controller;
+
+ pull-up-ports = <0 12>;
+ pull-down-ports = <1 8>;
+ open-drain-ports = <6 7 11>;
+ polarity-invert-ports = <3>;
+ probe-reset;
};
diff --git a/drivers/gpio/gpio-sx150x.c b/drivers/gpio/gpio-sx150x.c
index a177ebd..1226b5b 100644
--- a/drivers/gpio/gpio-sx150x.c
+++ b/drivers/gpio/gpio-sx150x.c
@@ -588,13 +588,16 @@ static void sx150x_init_chip(struct sx150x_chip *chip,
chip->gpio_chip.get = sx150x_gpio_get;
chip->gpio_chip.set = sx150x_gpio_set;
chip->gpio_chip.set_single_ended = sx150x_gpio_set_single_ended;
- chip->gpio_chip.base = pdata->gpio_base;
chip->gpio_chip.can_sleep= true;
chip->gpio_chip.ngpio= chip->dev_cfg->ngpios;
#ifdef CONFIG_OF_GPIO
- chip->gpio_chip.of_node = client->dev.of_node;
- chip->gpio_chip.of_gpio_n_cells = 2;
+ if (client->dev.of_node) {
+ chip->gpio_chip.of_node = client->dev.of_node;
+ chip->gpio_chip.of_gpio_n_cells = 2;
+ chip->gpio_chip.base = -1;
+ } else
#endif
+ chip->gpio_chip.base = pdata->gpio_base;
if (pdata->oscio_is_gpo)
++chip->gpio_chip.ngpio;
@@ -735,16 +738,70 @@ static int sx150x_install_irq_chip(struct sx150x_chip
*chip,
return err;
}
+#ifdef CONFIG_OF_GPIO
+static u16 sx150x_of_probe_pins(struct device *dev, char *attr_name)
+{
+ struct property *prop;
+ const __be32 *p;
+ u16 pins = 0;
+ u32 u;
+
+ if (!of_find_property(dev->of_node, attr_name, NULL))
+ return 0;
+
+ of_property_for_each_u32(dev->of_node, attr_name, prop, p, u)
+ if (u < 16)
+ pins |= BIT(u);
+
+ return pins;
+}
+
+static struct sx150x_platform_data *sx150x_of_probe(struct device *dev)
+{
+ struct sx150x_platform_data *pdata = devm_kzalloc(dev, sizeof(*pdata),
+ GFP_KERNEL);
+ /* gpio_base is not needed with OF */
+
+ pdata->oscio_is_gpo = of_property_read_bool(dev->of_node,
+ "oscio-is-gpo");
+
+ pdata->io_pullup_ena = sx150x_of_probe_pins(dev,
+ "pull-up-ports");
+
+ pdata->io_pulldn_ena = sx150x_of_probe_pins(dev,
+ "pull-down-ports");
+
+ pdata->io_polarity = sx150x_of_probe_pins(dev,
+ "polarity-invert-ports");
+
+ pdata->irq_summary = of_irq_get(dev->of_node, 0);
+
+ /* irq_base is not needed with OF */
+
+ pda
Re: [PATCH 4/4] ARM: dts: meson8b: Add Meson8b PWM Controller nodes
On 06/17/2016 08:21 PM, kbuild test robot wrote: > Hi, > > [auto build test ERROR on next-20160617] > [cannot apply to pwm/for-next robh/for-next v4.7-rc3 v4.7-rc2 v4.7-rc1 > v4.7-rc3] > [if your patch is applied to the wrong git tree, please drop us a note to > help improve the system] > > url: > https://github.com/0day-ci/linux/commits/Neil-Armstrong/pwm-Add-Amlogic-Meson-SoC-PWM-Controller/20160617-223758 > config: arm-multi_v7_defconfig (attached as .config) > compiler: arm-linux-gnueabi-gcc (Debian 5.3.1-8) 5.3.1 20160205 > reproduce: > wget > https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross > -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # save the attached .config to linux build tree > make.cross ARCH=arm > > All errors (new ones prefixed by >>): > >>> Error: arch/arm/boot/dts/meson8b.dtsi:167.17-18 syntax error >FATAL ERROR: Unable to parse input tree > > --- > 0-DAY kernel test infrastructureOpen Source Technology Center > https://lists.01.org/pipermail/kbuild-all Intel Corporation > I'll fix this for V2. Neil
Re: [RFC PATCH 0/2] scpi: Add SCPI framework to handle vendors variants
On 06/06/2016 07:10 PM, Sudeep Holla wrote: > > > On 30/05/16 09:30, Neil Armstrong wrote: >> On 05/27/2016 10:17 AM, Neil Armstrong wrote: > >> >> While looking for other ARMv8 based platform, I found that the RK3368 >> platform has the same SCPI implementation as Amlogic. >> >> They extended it with DDR, system and thermal commands. >> >> Look at : >> https://github.com/geekboxzone/mmallow_kernel/blob/geekbox/drivers/mailbox/scpi_cmd.h >> >> https://github.com/geekboxzone/mmallow_kernel/blob/geekbox/driver/mailbox/scpi_protocol.c >> >> So the SCPI must have a framework to allow different protocol >> versions, and must allow command extension. Grouping Rockchip and >> Amlogic should be done, thus needing a generic name like vendor_scpi >> or with a version. >> >> Sudeep, could you somehow find out which version of the protocol >> AmLogic and Rockchip based their SCPI development ? >> >> > > As Caesar Wang replied, they had a previous version of SCPI and I > suggested on how to extend the command set previously in private. > Not sure whats the progress on that This extension mechanism is OK for me. > > Anyways I had a look at geekbox driver and it looks mostly based on the > initial driver I wrote for initial SCPI versions. I am worried that your > extension might help people to develop their own protocol instead of > following the existing standards. SCPI is published now, so I vendors > use that rather than making up their own. Also ARM is trying to > standardize something in this area like PSCI, but that may take little > more time as it's under discussion with vendors. Sure, I understand ARM's point of view. But keep in mind that some vendors already diverted by using one of your initial out-of-tree code. This must be handled upstream whatever ARM business strategy is. My proposal was a first step, it can be simplified by removing the list stuff since we can consider there will be only one SCP interface. > > Though this initial version of SCPI is not published, I am sure it is > almost same as v1.0 except that the CMD is not part of payload like > v1.0. In v1.0 it's part of payload and the mailbox is used just for > doorbell mechanism. I hoped it would be this simple, but it touches core defines and structure that will over complicate the current driver. (i.e. the CMD indexes that differs, the CMD size shift, the high and low priority redirection or struct ordering) > IMO, we can add some compatible to indicate the pre v1.0 protocol > and add the support to the existing driver itself. Let me know your > thoughts. > My proposal is : - add a registry layer but with only a single scpi instance (no mode OF involved, remove drivers changes) - add a scpi_legacy.c driver that only supports the old SCPI like Amlogic and Rockchip, and add a disclaimer for new developed SoCs - add your extension capability to handle Amlogic's and Rockchip's extended commands If you agree, I'll post a new patchset for review with these changes. Thanks, Neil
Re: [Patch v6 0/2] Add Qualcomm ADM dmaengine driver
Andy Gross codeaurora.org> writes: > > This patch set introduces the dmaengine driver for the Qualcomm Application > Data Mover (ADM) DMA controller present on MSM8x60, APQ8064, and IPQ8064 > devices. > > The initial version of this driver will only support slave DMA operations > between system memory and peripherals. Flow control via the CRCI (client rate > control interface) is supported and can be configured via device tree > configuration. Flow control usage is required for some peripheral devices. > [...] Hi Andy, I'll need this patchset to support the NAND Controller on the MDM9615, what is the status ? Regards, Neil
[RFC PATCH v2 0/9] scpi: Add SCPI registry to handle legacy protocol
This patchset aims to support the legacy SCPI firmware implementation that was delivered as early technology preview for the JUNO platform. Finally a stable, maintained and public implementation for the SCPI protocol has been upstreamed part of the JUNO support and it is the recommended way of implementing SCP communication on ARMv8 platforms. The Amlogic GXBB platform is using this legacy protocol, as the RK3368 & RK3399 platforms. Only the GXBB example is provided here, but it's unclear if other Amlogic ARMv8 based SoCs uses this legacy procotol. In order to support the legacy protocol : - Move the scpi_get_ops to a thin registry layer - Change the arm_scpi.c to use the registry layer - Add a separate config option to build the registry layer - Add the legacy SCPI driver based on the new implementation - For example, add the Amlogic GXBB MHU and SCPI DT cpufreq & sensors nodes Initial RFC discution tread can be found at https://lkml.org/lkml/2016/5/26/111 Neil Armstrong (9): mailbox: Add Amlogic Meson Message-Handling-Unit dt-bindings: mailbox: Add Amlogic Meson MHU Bindings ARM64: dts: meson-gxbb: Add Meson MHU Node firmware: Add a SCPI registry to handle multiple implementations firmware: scpi: Switch arm_scpi to use new registry firmware: Add legacy SCPI protocol driver dt-bindings: arm: Update arm,scpi bindings with Meson GXBB SCPI ARM64: dts: meson-gxbb: Add SRAM node ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes Documentation/devicetree/bindings/arm/arm,scpi.txt | 8 +- .../devicetree/bindings/mailbox/meson-mhu.txt | 33 ++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi| 53 ++ drivers/firmware/Kconfig | 24 + drivers/firmware/Makefile | 2 + drivers/firmware/arm_scpi.c| 14 +- drivers/firmware/legacy_scpi.c | 644 + drivers/firmware/scpi.c| 94 +++ drivers/mailbox/Makefile | 2 + drivers/mailbox/meson_mhu.c| 199 +++ include/linux/scpi_protocol.h | 15 +- 11 files changed, 1075 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/mailbox/meson-mhu.txt create mode 100644 drivers/firmware/legacy_scpi.c create mode 100644 drivers/firmware/scpi.c create mode 100644 drivers/mailbox/meson_mhu.c -- 2.7.0
[RFC PATCH v2 3/9] ARM64: dts: meson-gxbb: Add Meson MHU Node
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 806b903..77381d0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -315,6 +315,14 @@
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
+
+ mailbox: mailbox@400 {
+ compatible = "amlogic,meson-gxbb-mhu";
+ reg = <0 0x400 0 0x4c>;
+ interrupts = <0 209 IRQ_TYPE_EDGE_RISING>,
+<0 210 IRQ_TYPE_EDGE_RISING>;
+ #mbox-cells = <1>;
+};
};
apb: apb@d000 {
--
2.7.0
[RFC PATCH v2 4/9] firmware: Add a SCPI registry to handle multiple implementations
Add a thin registry layer to store the current scpi_ops pointer out of the
arm_scpi.c location.
Add a register/unregister and devres managed unregister calls, and their
static inline disabled stubs.
Add the SCPI_FW config to enable the registry layer build.
Signed-off-by: Neil Armstrong
---
drivers/firmware/Kconfig | 4 ++
drivers/firmware/Makefile | 1 +
drivers/firmware/scpi.c | 94 +++
include/linux/scpi_protocol.h | 15 ++-
4 files changed, 113 insertions(+), 1 deletion(-)
create mode 100644 drivers/firmware/scpi.c
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index 6664f11..95b01f4 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -8,9 +8,13 @@ menu "Firmware Drivers"
config ARM_PSCI_FW
bool
+config SCPI_FW
+ bool
+
config ARM_SCPI_PROTOCOL
tristate "ARM System Control and Power Interface (SCPI) Message
Protocol"
depends on ARM_MHU
+ select SCPI_FW
help
System Control and Power Interface (SCPI) Message Protocol is
defined for the purpose of communication between the Application
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 474bada..b697462 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -2,6 +2,7 @@
# Makefile for the linux kernel.
#
obj-$(CONFIG_ARM_PSCI_FW) += psci.o
+obj-$(CONFIG_SCPI_FW) += scpi.o
obj-$(CONFIG_ARM_SCPI_PROTOCOL)+= arm_scpi.o
obj-$(CONFIG_DMI) += dmi_scan.o
obj-$(CONFIG_DMI_SYSFS)+= dmi-sysfs.o
diff --git a/drivers/firmware/scpi.c b/drivers/firmware/scpi.c
new file mode 100644
index 000..87a559a
--- /dev/null
+++ b/drivers/firmware/scpi.c
@@ -0,0 +1,94 @@
+/*
+ * System Control and Power Interface (SCPI) Message Protocol registry
+ *
+ * SCPI Message Protocol is used between the System Control Processor(SCP)
+ * and the Application Processors(AP). The Message Handling Unit(MHU)
+ * provides a mechanism for inter-processor communication between SCP's
+ * Cortex M3 and AP.
+ *
+ * SCP offers control and management of the core/cluster power states,
+ * various power domain DVFS including the core/cluster, certain system
+ * clocks configuration, thermal sensors and many others.
+ *
+ * Copyright (C) 2015 ARM Ltd.
+ * Copyright (C) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct scpi_ops *g_ops;
+
+struct scpi_ops *get_scpi_ops(void)
+{
+ return g_ops;
+}
+EXPORT_SYMBOL_GPL(get_scpi_ops);
+
+int scpi_ops_register(struct scpi_ops *ops)
+{
+ if (!ops)
+ return -EINVAL;
+
+ if (g_ops)
+ return -EEXIST;
+
+ g_ops = ops;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(scpi_ops_register);
+
+void scpi_ops_unregister(struct scpi_ops *ops)
+{
+ if (g_ops == ops)
+ g_ops = NULL;
+}
+EXPORT_SYMBOL_GPL(scpi_ops_unregister);
+
+static void devm_scpi_ops_unregister(struct device *dev, void *res)
+{
+ scpi_ops_unregister(*(struct scpi_ops **)res);
+}
+
+int devm_scpi_ops_register(struct device *dev,
+ struct scpi_ops *ops)
+{
+ struct scpi_ops **rcops;
+ int ret;
+
+ rcops = devres_alloc(devm_scpi_ops_unregister, sizeof(*ops),
+GFP_KERNEL);
+ if (!rcops)
+ return -ENOMEM;
+
+ ret = scpi_ops_register(ops);
+ if (!ret) {
+ *rcops = ops;
+ devres_add(dev, rcops);
+ } else
+ devres_free(rcops);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(devm_scpi_ops_register);
diff --git a/include/linux/scpi_protocol.h b/include/linux/scpi_protocol.h
index 35de50a..38c15d1 100644
--- a/include/linux/scpi_protocol.h
+++ b/include/linux/scpi_protocol.h
@@ -72,8 +72,21 @@ struct scpi_ops {
int (*sensor_get_value)(u16, u64 *);
};
-#if IS_REACHABLE(CONFIG_ARM_SCPI_PROTOCOL)
+#if IS_REACHABLE(CONFIG_SCPI_FW)
struct scpi_ops *get_scpi_ops(void);
+int scpi_ops_register(struct scpi_ops *drv);
+void scpi_ops_unregister(struct scpi_ops *drv);
+int devm_scpi_ops_register(struct device *dev, struct scpi_ops *drv);
#else
static inline struct scpi_ops *g
[RFC PATCH v2 7/9] dt-bindings: arm: Update arm,scpi bindings with Meson GXBB SCPI
Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/arm,scpi.txt | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt index 313dabd..fe58212 100644 --- a/Documentation/devicetree/bindings/arm/arm,scpi.txt +++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt @@ -7,7 +7,7 @@ by Linux to initiate various system control and power operations. Required properties: -- compatible : should be "arm,scpi" +- compatible : should be "arm,scpi" or "amlogic,meson-gxbb-scpi" - mboxes: List of phandle and mailbox channel specifiers All the channels reserved by remote SCP firmware for use by SCPI message protocol should be specified in any order @@ -60,7 +60,8 @@ A small area of SRAM is reserved for SCPI communication between application processors and SCP. Required properties: -- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM on Juno +- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM on Juno, + or "amlogic,meson-gxbb-sram" for Amlogic GXBB SoC. The rest of the properties should follow the generic mmio-sram description found in ../../sram/sram.txt @@ -70,7 +71,8 @@ Each sub-node represents the reserved area for SCPI. Required sub-node properties: - reg : The base offset and size of the reserved area with the SRAM - compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based - shared memory on Juno platforms + shared memory on Juno platforms or + "amlogic,meson-gxbb-scp-shmem" for Amlogic GXBB SoC. Sensor bindings for the sensors based on SCPI Message Protocol -- -- 2.7.0
[RFC PATCH v2 8/9] ARM64: dts: meson-gxbb: Add SRAM node
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 77381d0..913ba86 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -124,6 +124,15 @@
#size-cells = <2>;
ranges;
+ sram: sram@c800 {
+ compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
+ reg = <0x0 0xc800 0x0 0x14000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0xc800 0x14000>;
+ };
+
cbus: cbus@c110 {
compatible = "simple-bus";
reg = <0x0 0xc110 0x0 0x10>;
--
2.7.0
[RFC PATCH v2 5/9] firmware: scpi: Switch arm_scpi to use new registry
Change the arm_scpi.c to use the registry layer instead of returning it's
context ->ops pointer.
Signed-off-by: Neil Armstrong
---
drivers/firmware/arm_scpi.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
index 7e3e595..ba6bc53 100644
--- a/drivers/firmware/arm_scpi.c
+++ b/drivers/firmware/arm_scpi.c
@@ -162,7 +162,6 @@ struct scpi_drvinfo {
u32 firmware_version;
int num_chans;
atomic_t next_chan;
- struct scpi_ops *scpi_ops;
struct scpi_chan *channels;
struct scpi_dvfs_info *dvfs[MAX_DVFS_DOMAINS];
};
@@ -526,7 +525,7 @@ static int scpi_sensor_get_info(u16 sensor_id, struct
scpi_sensor_info *info)
return ret;
}
-int scpi_sensor_get_value(u16 sensor, u64 *val)
+static int scpi_sensor_get_value(u16 sensor, u64 *val)
{
__le16 id = cpu_to_le16(sensor);
struct sensor_value buf;
@@ -554,12 +553,6 @@ static struct scpi_ops scpi_ops = {
.sensor_get_value = scpi_sensor_get_value,
};
-struct scpi_ops *get_scpi_ops(void)
-{
- return scpi_info ? scpi_info->scpi_ops : NULL;
-}
-EXPORT_SYMBOL_GPL(get_scpi_ops);
-
static int scpi_init_versions(struct scpi_drvinfo *info)
{
int ret;
@@ -743,7 +736,10 @@ err:
FW_REV_MAJOR(scpi_info->firmware_version),
FW_REV_MINOR(scpi_info->firmware_version),
FW_REV_PATCH(scpi_info->firmware_version));
- scpi_info->scpi_ops = &scpi_ops;
+
+ ret = devm_scpi_ops_register(dev, &scpi_ops);
+ if (ret)
+ return ret;
ret = sysfs_create_groups(&dev->kobj, versions_groups);
if (ret)
--
2.7.0
[RFC PATCH v2 6/9] firmware: Add legacy SCPI protocol driver
Add legacy SCPI driver based on the latest SCPI driver but modified to behave like an earlier technology preview SCPI implementation that at least the Amlogic GXBB ARMv8 based platform uses in it's SCP firmware implementation. The main differences between the mainline, public and recommended SCPI implementation are : - virtual channels is not implemented - command word is passed by the MHU instead of the virtual channel ID - uses "sender id" in the command word for each commands groups - payload size shift in command word is different - command word is not in SRAM, so command queuing is not possible - command indexes are different - command data structures differs - commands are redirected to low or high priority channels by their indexes, so round-robin redirection is not possible A clear disclaimer is added to make it clear this implementation should not be used for new products and is only here to support already released SoCs. Signed-off-by: Neil Armstrong --- drivers/firmware/Kconfig | 20 ++ drivers/firmware/Makefile | 1 + drivers/firmware/legacy_scpi.c | 644 + 3 files changed, 665 insertions(+) create mode 100644 drivers/firmware/legacy_scpi.c diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 95b01f4..b9c2a33 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -31,6 +31,26 @@ config ARM_SCPI_PROTOCOL This protocol library provides interface for all the client drivers making use of the features offered by the SCP. +config LEGACY_SCPI_PROTOCOL + bool "Legacy System Control and Power Interface (SCPI) Message Protocol" + default y if ARCH_MESON + select ARM_SCPI_FW + help + System Control and Power Interface (SCPI) Message Protocol is + defined for the purpose of communication between the Application + Cores(AP) and the System Control Processor(SCP). The MHU peripheral + provides a mechanism for inter-processor communication between SCP + and AP. + + SCP controls most of the power managament on the Application + Processors. It offers control and management of: the core/cluster + power states, various power domain DVFS including the core/cluster, + certain system clocks configuration, thermal sensors and many + others. + + This protocol library provides interface for all the client drivers + making use of the features offered by the legacy SCP protocol. + config EDD tristate "BIOS Enhanced Disk Drive calls determine boot disk" depends on X86 diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index b697462..c2cac9c 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_ARM_PSCI_FW) += psci.o obj-$(CONFIG_SCPI_FW) += scpi.o obj-$(CONFIG_ARM_SCPI_PROTOCOL)+= arm_scpi.o +obj-$(CONFIG_LEGACY_SCPI_PROTOCOL) += legacy_scpi.o obj-$(CONFIG_DMI) += dmi_scan.o obj-$(CONFIG_DMI_SYSFS)+= dmi-sysfs.o obj-$(CONFIG_EDD) += edd.o diff --git a/drivers/firmware/legacy_scpi.c b/drivers/firmware/legacy_scpi.c new file mode 100644 index 000..4bd3ff7 --- /dev/null +++ b/drivers/firmware/legacy_scpi.c @@ -0,0 +1,644 @@ +/* + * Legacy System Control and Power Interface (SCPI) Message Protocol driver + * + * SCPI Message Protocol is used between the System Control Processor(SCP) + * and the Application Processors(AP). The Message Handling Unit(MHU) + * provides a mechanism for inter-processor communication between SCP's + * Cortex M3 and AP. + * + * SCP offers control and management of the core/cluster power states, + * various power domain DVFS including the core/cluster, certain system + * clocks configuration, thermal sensors and many others. + * + * Copyright (C) 2016 BayLibre, SAS. + * Author: Neil Armstrong + * + * Heavily based on arm_scpi.c from : + * Copyright (C) 2015 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * DISCLAIMER + * + * This SCPI implementation is based on a technology preview release + * and new ARMv8 SoCs implementations should use the standard SCPI + * implementation as defined in the ARM DUI 0922G and implemented + * in the arm_scpi.c driver. + */ + +#define pr_fmt(fmt) KBUILD_MODN
[RFC PATCH v2 9/9] ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes
Add the vcpu DVFS clock, the SCPU shared SRAM and the SCPI sensors nodes.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 36 +
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 913ba86..0f2596e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -61,6 +61,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
+ clocks = <&scpi_dvfs 0>;
};
cpu1: cpu@1 {
@@ -68,6 +69,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
+ clocks = <&scpi_dvfs 0>;
};
cpu2: cpu@2 {
@@ -75,6 +77,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
+ clocks = <&scpi_dvfs 0>;
};
cpu3: cpu@3 {
@@ -82,6 +85,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
+ clocks = <&scpi_dvfs 0>;
};
};
@@ -99,6 +103,28 @@
method = "smc";
};
+ scpi {
+ compatible = "amlogic,meson-gxbb-scpi";
+ mboxes = <&mailbox 0 &mailbox 1>;
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+ clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_dvfs: scpi_clocks@0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <1>;
+ clock-indices = <0>;
+ clock-output-names = "vcpu";
+ };
+ };
+
+ scpi_sensors: sensors {
+ compatible = "arm,scpi-sensors";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = ;
#size-cells = <1>;
ranges = <0 0x0 0xc800 0x14000>;
+
+ cpu_scp_lpri: scp-shmem@0 {
+ compatible = "amlogic,meson-gxbb-scp-shmem";
+ reg = <0x13000 0x400>;
+ };
+
+ cpu_scp_hpri: scp-shmem@200 {
+ compatible = "amlogic,meson-gxbb-scp-shmem";
+ reg = <0x13400 0x400>;
+ };
};
cbus: cbus@c110 {
--
2.7.0
[RFC PATCH v2 1/9] mailbox: Add Amlogic Meson Message-Handling-Unit
Add Amlogic Meson SoCs Message-Handling-Unit as mailbox controller
with 2 independent channels/links to communicate with a remote processor.
Signed-off-by: Neil Armstrong
---
drivers/mailbox/Makefile| 2 +
drivers/mailbox/meson_mhu.c | 199
2 files changed, 201 insertions(+)
create mode 100644 drivers/mailbox/meson_mhu.c
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 0be3e74..6aa9dbe 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -25,3 +25,5 @@ obj-$(CONFIG_TI_MESSAGE_MANAGER) += ti-msgmgr.o
obj-$(CONFIG_XGENE_SLIMPRO_MBOX) += mailbox-xgene-slimpro.o
obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o
+
+obj-$(CONFIG_ARCH_MESON) += meson_mhu.o
diff --git a/drivers/mailbox/meson_mhu.c b/drivers/mailbox/meson_mhu.c
new file mode 100644
index 000..0576b92
--- /dev/null
+++ b/drivers/mailbox/meson_mhu.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright (C) 2016 BayLibre SAS.
+ * Author: Neil Armstrong
+ * Heavily based on meson_mhu.c from :
+ * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Jassi Brar
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define INTR_SET_OFS 0x0
+#define INTR_STAT_OFS 0x4
+#define INTR_CLR_OFS 0x8
+
+#define MHU_LP_OFFSET 0x10
+#define MHU_HP_OFFSET 0x1c
+
+#define TX_REG_OFFSET 0x24
+
+#define MHU_CHANS 2
+
+struct meson_mhu_link {
+ unsigned int irq;
+ void __iomem *tx_reg;
+ void __iomem *rx_reg;
+};
+
+struct meson_mhu {
+ void __iomem *base;
+ struct meson_mhu_link mlink[MHU_CHANS];
+ struct mbox_chan chan[MHU_CHANS];
+ struct mbox_controller mbox;
+};
+
+static irqreturn_t meson_mhu_rx_interrupt(int irq, void *p)
+{
+ struct mbox_chan *chan = p;
+ struct meson_mhu_link *mlink = chan->con_priv;
+ u32 val;
+
+ val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
+ if (!val)
+ return IRQ_NONE;
+
+ mbox_chan_received_data(chan, (void *)&val);
+
+ writel_relaxed(~0, mlink->rx_reg + INTR_CLR_OFS);
+
+ return IRQ_HANDLED;
+}
+
+static bool meson_mhu_last_tx_done(struct mbox_chan *chan)
+{
+ struct meson_mhu_link *mlink = chan->con_priv;
+ u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
+
+ return (val == 0);
+}
+
+static int meson_mhu_send_data(struct mbox_chan *chan, void *data)
+{
+ struct meson_mhu_link *mlink = chan->con_priv;
+ u32 *arg = data;
+
+ writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
+
+ return 0;
+}
+
+static int meson_mhu_startup(struct mbox_chan *chan)
+{
+ struct meson_mhu_link *mlink = chan->con_priv;
+ int ret;
+
+ ret = request_irq(mlink->irq, meson_mhu_rx_interrupt,
+ IRQF_ONESHOT, "meson_mhu_link", chan);
+ if (ret) {
+ dev_err(chan->mbox->dev,
+ "Unable to acquire IRQ %d\n", mlink->irq);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void meson_mhu_shutdown(struct mbox_chan *chan)
+{
+ struct meson_mhu_link *mlink = chan->con_priv;
+
+ free_irq(mlink->irq, chan);
+}
+
+static const struct mbox_chan_ops meson_mhu_ops = {
+ .send_data = meson_mhu_send_data,
+ .startup = meson_mhu_startup,
+ .shutdown = meson_mhu_shutdown,
+ .last_tx_done = meson_mhu_last_tx_done,
+};
+
+static int meson_mhu_probe(struct platform_device *pdev)
+{
+ int i, err;
+ struct meson_mhu *mhu;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ int meson_mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET};
+
+ /* Allocate memory for device */
+ mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
+ if (!mhu)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ mhu->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(mhu->base)) {
+ dev_err(dev, "ioremap failed\n");
+ return PTR_ERR(mhu->base);
+ }
+
+ for (i = 0; i < MHU_CHANS; i++) {
+ mhu->chan[i].con_priv = &mhu->mlink[i];
+ mhu->mlink[i].irq = platform_get_irq(pdev, i);
+ if (mhu->mlink[i].irq < 0) {
+ dev_err(dev, &q
[RFC PATCH v2 2/9] dt-bindings: mailbox: Add Amlogic Meson MHU Bindings
Signed-off-by: Neil Armstrong
---
.../devicetree/bindings/mailbox/meson-mhu.txt | 33 ++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/meson-mhu.txt
diff --git a/Documentation/devicetree/bindings/mailbox/meson-mhu.txt
b/Documentation/devicetree/bindings/mailbox/meson-mhu.txt
new file mode 100644
index 000..4a80b44
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/meson-mhu.txt
@@ -0,0 +1,33 @@
+Amlogic Meson MHU Mailbox Driver
+
+
+The Amlogic's Meson SoCs Message-Handling-Unit (MHU) is a mailbox controller
+that has 2 independent channels/links to communicate with remote processor(s).
+MHU links are hardwired on a platform. A link raises interrupt for any
+received data. However, there is no specified way of knowing if the sent
+data has been read by the remote. This driver assumes the sender polls
+STAT register and the remote clears it after having read the data.
+
+Mailbox Device Node:
+
+
+Required properties:
+
+- compatible: Shall be "amlogic,meson-gxbb-mhu"
+- reg: Contains the mailbox register address range (base
+ address and length)
+- #mbox-cells Shall be 1 - the index of the channel needed.
+- interrupts: Contains the interrupt information corresponding to
+ each of the 2 links of MHU.
+
+Example:
+
+
+ mailbox: mailbox@c883c400 {
+ #mbox-cells = <1>;
+ compatible = "amlogic,meson-gxbb-mhu";
+ reg = <0 0xc883c400 0 0x4c>;
+ interrupts = <0 209 IRQ_TYPE_EDGE_RISING>,
+ <0 210 IRQ_TYPE_EDGE_RISING>;
+ #mbox-cells = <1>;
+ };
--
2.7.0
[PATCH v2] pinctrl: Add SX150X GPIO Extender Pinctrl Driver
Since the I2C sx150x GPIO expander driver uses platform_data to manage
the pins configurations, rewrite the driver as a pinctrl driver using
pinconf to get/set pin configurations from DT or debugfs.
The pinctrl driver is functionnally equivalent as the gpio-only driver
and can use DT for pinconf. The platform_data confirmation is dropped.
This patchset removed the gpio-only driver and selects the Pinctrl driver
config instead. This patchset also migrates the gpio dt-bindings to pinctrl
and add the pinctrl optional properties.
The driver was tested with a SX1509 device on a BeagleBone black with
interrupt support and on an X86_64 machine over an I2C to USB converter.
Signed-off-by: Neil Armstrong
---
This is a fixed version that builds and runs on non-OF platforms and on
arm based OF. The GPIO version is removed and the bindings are also moved
to the pinctrl bindings.
One remaining question, should i2c_driver remove be implemented ?
It would be quite hard to implement due to the interrupt controller.
Changes since v1 at
http://lkml.kernel.org/r/1473166599-29266-1-git-send-email-narmstr...@baylibre.com:
- Fix Kconfig descriptions on pinctrl and gpio
- Fix Kconfig dependency
- Remove oscio support for non-789 devices
- correct typo in dt bindings
- remove probe reset for non-789 devices
Changes since RFC at
http://lkml.kernel.org/r/1472130692-14404-1-git-send-email-narmstr...@baylibre.com:
- Put #ifdef CONFIG_OF/CONFIG_OF_GPIO to remove OF code for non-of platforms
- No more rely on OF_GPIO config
- Moved and enhanced bindings to pinctrl bindings
- Removed gpio-sx150x.c
- Temporary select PINCTRL_SX150X when GPIO_SX150X
- Temporary mark GPIO_SX150X as deprecated
.../gpio-sx150x.txt => pinctrl/pinctrl-sx150x.txt} | 46 +-
drivers/gpio/Kconfig | 13 +-
drivers/gpio/Makefile |1 -
drivers/pinctrl/Kconfig| 14 +
drivers/pinctrl/Makefile |1 +
.../gpio-sx150x.c => pinctrl/pinctrl-sx150x.c} | 1179
6 files changed, 782 insertions(+), 472 deletions(-)
rename Documentation/devicetree/bindings/{gpio/gpio-sx150x.txt =>
pinctrl/pinctrl-sx150x.txt} (40%)
rename drivers/{gpio/gpio-sx150x.c => pinctrl/pinctrl-sx150x.c} (24%)
diff --git a/Documentation/devicetree/bindings/gpio/gpio-sx150x.txt
b/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt
similarity index 40%
rename from Documentation/devicetree/bindings/gpio/gpio-sx150x.txt
rename to Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt
index c809acb..c293c8a 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-sx150x.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt
@@ -1,34 +1,54 @@
SEMTECH SX150x GPIO expander bindings
+Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
+../interrupt-controller/interrupts.txt for generic information regarding
+pin controller, GPIO, and interrupt bindings.
Required properties:
-
-- compatible: should be "semtech,sx1506q",
+- compatible: should be one of :
+ "semtech,sx1506q",
"semtech,sx1508q",
"semtech,sx1509q",
"semtech,sx1502q".
- reg: The I2C slave address for this device.
-- interrupt-parent: phandle of the parent interrupt controller.
-
-- interrupts: Interrupt specifier for the controllers interrupt.
-
- #gpio-cells: Should be 2. The first cell is the GPIO number and the
second cell is used to specify optional parameters:
bit 0: polarity (0: normal, 1: inverted)
- gpio-controller: Marks the device as a GPIO controller.
+Optional properties :
+- interrupt-parent: phandle of the parent interrupt controller.
+
+- interrupts: Interrupt specifier for the controllers interrupt.
+
- interrupt-controller: Marks the device as a interrupt controller.
+- semtech,probe-reset: Will trigger a reset of the GPIO expander on probe,
+ only for sx1508q and sx1509q
+
The GPIO expander can optionally be used as an interrupt controller, in
-which case it uses the default two cell specifier as described in
-Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
+which case it uses the default two cell specifier.
+
+Required properties for pin configuration sub-nodes:
+ - pins: List of pins to which the configuration applies.
+
+Optional properties for pin configuration sub-nodes:
+
+ - bias-disable: disable any pin bias, except the OSCIO pin
+ - bias-pull-up: pull up the pin, except the OSCIO pin
+ - bias-pull-down: pull down the pin, except the OSCIO pin
+ - bias-pull-pin-default: use pin-default pull state, except the OSCIO pin
+ - drive-push-pull: drive actively high and low
+ - drive-open-drain: drive with open drain only for sx1
[PATCH] ARM: qcom_defconfig: Fix MDM9515 LCC and GCC config
Correct prefix is MDM instead of MSM.
Fixes: 8aa788d3e59a ("ARM: configs: qualcomm: Add MDM9615 missing defconfigs")
Signed-off-by: Neil Armstrong
---
arch/arm/configs/qcom_defconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index c2dff4f..9f6d2a6 100644
--- a/arch/arm/configs/qcom_defconfig
+++ b/arch/arm/configs/qcom_defconfig
@@ -162,8 +162,8 @@ CONFIG_APQ_MMCC_8084=y
CONFIG_IPQ_LCC_806X=y
CONFIG_MSM_GCC_8660=y
CONFIG_MSM_LCC_8960=y
-CONFIG_MSM_GCC_9615=y
-CONFIG_MSM_LCC_9615=y
+CONFIG_MDM_GCC_9615=y
+CONFIG_MDM_LCC_9615=y
CONFIG_MSM_MMCC_8960=y
CONFIG_MSM_MMCC_8974=y
CONFIG_HWSPINLOCK_QCOM=y
--
1.9.1
[PATCH v3 4/8] scpi: Add support for Legacy match table for Amlogic GXBB SoC
Add new DT match table to setup the is_legacy boolean value across
the scpi functions.
Add the Amlogic GXBB SoC compatible for platform and as legacy match entry.
Signed-off-by: Neil Armstrong
---
drivers/firmware/arm_scpi.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
index 6a16100..60a76e63 100644
--- a/drivers/firmware/arm_scpi.c
+++ b/drivers/firmware/arm_scpi.c
@@ -979,6 +979,11 @@ static int scpi_alloc_xfer_list(struct device *dev, struct
scpi_chan *ch)
return 0;
}
+static const struct of_device_id legacy_scpi_of_match[] = {
+ {.compatible = "amlogic,meson-gxbb-scpi"},
+ {},
+};
+
static int scpi_probe(struct platform_device *pdev)
{
int count, idx, ret;
@@ -991,6 +996,9 @@ static int scpi_probe(struct platform_device *pdev)
if (!scpi_info)
return -ENOMEM;
+ if (of_match_device(legacy_scpi_of_match, &pdev->dev))
+ scpi_info->is_legacy = true;
+
count = of_count_phandle_with_args(np, "mboxes", "#mbox-cells");
if (count < 0) {
dev_err(dev, "no mboxes property in '%s'\n", np->full_name);
@@ -1097,6 +1105,7 @@ err:
static const struct of_device_id scpi_of_match[] = {
{.compatible = "arm,scpi"},
+ {.compatible = "amlogic,meson-gxbb-scpi"},
{},
};
--
1.9.1
[PATCH v3 5/8] scpi: grow MAX_DVFS_OPPS to 16 entries
Since Amlogic SoCs reports more than 8 OPPs per domains, grow the structure size to 16. Signed-off-by: Neil Armstrong --- drivers/firmware/arm_scpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c index 60a76e63..b422ad3 100644 --- a/drivers/firmware/arm_scpi.c +++ b/drivers/firmware/arm_scpi.c @@ -68,7 +68,7 @@ #define SCPI_SLOT 0 #define MAX_DVFS_DOMAINS 8 -#define MAX_DVFS_OPPS 8 +#define MAX_DVFS_OPPS 16 #define DVFS_LATENCY(hdr) (le32_to_cpu(hdr) >> 16) #define DVFS_OPP_COUNT(hdr)((le32_to_cpu(hdr) >> 8) & 0xff) -- 1.9.1
[PATCH v3 0/8] scpi: Add support for legacy SCPI protocol
This patchset aims to support the legacy SCPI firmware implementation that was delivered as early technology preview for the JUNO platform. Finally a stable, maintained and public implementation for the SCPI protocol has been upstreamed part of the JUNO support and it is the recommended way of implementing SCP communication on ARMv8 platforms. The Amlogic GXBB platform is using this legacy protocol, as the RK3368 & RK3399 platforms. This patchset will only add support for Amlogic GXBB SoC. This patchset add support for the legacy protocol in the arm_scpi.c file, avoiding code duplication. Last RFC discution tread can be found at : https://lkml.org/lkml/2016/8/9/210 Changes since v2 at : http://lkml.kernel.org/r/1471952816-30877-1-git-send-email-narmstr...@baylibre.com - Added command indirection table and use it in each commands - Added bitmap for high priority commands - Cleaned up legacy tx_prepare/handle_message to align to standard functions - Dropped legacy_scpi_ops Changes since v1 at : http://lkml.kernel.org/r/1471515066-3626-1-git-send-email-narmstr...@baylibre.com - Dropped vendor_send_message and rockchip vendor mechanism patches - Merged alternate functions into main functions using is_legacy boolean - Added DT match table to set is_legacy to true - Kept alternate scpi_ops structure for legacy Neil Armstrong (8): scpi: Add cmd indirection table to prepare for legacy commands scpi: Add alternative legacy structures, functions and macros scpi: Do not fail if get_capabilities is not implemented scpi: Add support for Legacy match table for Amlogic GXBB SoC scpi: grow MAX_DVFS_OPPS to 16 entries dt-bindings: Add support for Amlogic GXBB SCPI Interface ARM64: dts: meson-gxbb: Add SRAM node ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes Documentation/devicetree/bindings/arm/arm,scpi.txt | 8 +- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi| 45 +++ drivers/firmware/arm_scpi.c| 378 +++-- 3 files changed, 402 insertions(+), 29 deletions(-) -- 1.9.1
[PATCH v3 1/8] scpi: Add cmd indirection table to prepare for legacy commands
Add indirection table to permit multiple command values for legacy support.
Signed-off-by: Neil Armstrong
---
drivers/firmware/arm_scpi.c | 145 ++--
1 file changed, 127 insertions(+), 18 deletions(-)
diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
index 4388937..9a87687 100644
--- a/drivers/firmware/arm_scpi.c
+++ b/drivers/firmware/arm_scpi.c
@@ -99,6 +99,7 @@ enum scpi_error_codes {
SCPI_ERR_MAX
};
+/* SCPI Standard commands */
enum scpi_std_cmd {
SCPI_CMD_INVALID= 0x00,
SCPI_CMD_SCPI_READY = 0x01,
@@ -132,6 +133,38 @@ enum scpi_std_cmd {
SCPI_CMD_COUNT
};
+/* List all commands used by this driver, used as indexes */
+enum scpi_drv_cmds {
+ CMD_SCPI_CAPABILITIES = 0,
+ CMD_GET_CLOCK_INFO,
+ CMD_GET_CLOCK_VALUE,
+ CMD_SET_CLOCK_VALUE,
+ CMD_GET_DVFS,
+ CMD_SET_DVFS,
+ CMD_GET_DVFS_INFO,
+ CMD_SENSOR_CAPABILITIES,
+ CMD_SENSOR_INFO,
+ CMD_SENSOR_VALUE,
+ CMD_SET_DEVICE_PWR_STATE,
+ CMD_GET_DEVICE_PWR_STATE,
+ CMD_MAX_COUNT,
+};
+
+static int scpi_std_commands[CMD_MAX_COUNT] = {
+ SCPI_CMD_SCPI_CAPABILITIES,
+ SCPI_CMD_GET_CLOCK_INFO,
+ SCPI_CMD_GET_CLOCK_VALUE,
+ SCPI_CMD_SET_CLOCK_VALUE,
+ SCPI_CMD_GET_DVFS,
+ SCPI_CMD_SET_DVFS,
+ SCPI_CMD_GET_DVFS_INFO,
+ SCPI_CMD_SENSOR_CAPABILITIES,
+ SCPI_CMD_SENSOR_INFO,
+ SCPI_CMD_SENSOR_VALUE,
+ SCPI_CMD_SET_DEVICE_PWR_STATE,
+ SCPI_CMD_GET_DEVICE_PWR_STATE,
+};
+
struct scpi_xfer {
u32 slot; /* has to be first element */
u32 cmd;
@@ -161,6 +194,7 @@ struct scpi_drvinfo {
u32 protocol_version;
u32 firmware_version;
int num_chans;
+ int *scpi_cmds;
atomic_t next_chan;
struct scpi_ops *scpi_ops;
struct scpi_chan *channels;
@@ -390,6 +424,19 @@ static u32 scpi_get_version(void)
return scpi_info->protocol_version;
}
+static inline int check_cmd(unsigned int offset)
+{
+ if (offset >= CMD_MAX_COUNT ||
+ !scpi_info ||
+ !scpi_info->scpi_cmds)
+ return -EINVAL;
+
+ if (scpi_info->scpi_cmds[offset] < 0)
+ return -EOPNOTSUPP;
+
+ return 0;
+}
+
static int
scpi_clk_get_range(u16 clk_id, unsigned long *min, unsigned long *max)
{
@@ -397,8 +444,13 @@ scpi_clk_get_range(u16 clk_id, unsigned long *min,
unsigned long *max)
struct clk_get_info clk;
__le16 le_clk_id = cpu_to_le16(clk_id);
- ret = scpi_send_message(SCPI_CMD_GET_CLOCK_INFO, &le_clk_id,
- sizeof(le_clk_id), &clk, sizeof(clk));
+ ret = check_cmd(CMD_GET_CLOCK_INFO);
+ if (ret)
+ return ret;
+
+ ret = scpi_send_message(scpi_info->scpi_cmds[CMD_GET_CLOCK_INFO],
+ &le_clk_id, sizeof(le_clk_id),
+ &clk, sizeof(clk));
if (!ret) {
*min = le32_to_cpu(clk.min_rate);
*max = le32_to_cpu(clk.max_rate);
@@ -412,20 +464,32 @@ static unsigned long scpi_clk_get_val(u16 clk_id)
struct clk_get_value clk;
__le16 le_clk_id = cpu_to_le16(clk_id);
- ret = scpi_send_message(SCPI_CMD_GET_CLOCK_VALUE, &le_clk_id,
- sizeof(le_clk_id), &clk, sizeof(clk));
+ ret = check_cmd(CMD_GET_CLOCK_VALUE);
+ if (ret)
+ return ret;
+
+ ret = scpi_send_message(scpi_info->scpi_cmds[CMD_GET_CLOCK_VALUE],
+ &le_clk_id, sizeof(le_clk_id),
+ &clk, sizeof(clk));
+
return ret ? ret : le32_to_cpu(clk.rate);
}
static int scpi_clk_set_val(u16 clk_id, unsigned long rate)
{
+ int ret;
int stat;
struct clk_set_value clk = {
.id = cpu_to_le16(clk_id),
.rate = cpu_to_le32(rate)
};
- return scpi_send_message(SCPI_CMD_SET_CLOCK_VALUE, &clk, sizeof(clk),
+ ret = check_cmd(CMD_SET_CLOCK_VALUE);
+ if (ret)
+ return ret;
+
+ return scpi_send_message(scpi_info->scpi_cmds[CMD_SET_CLOCK_VALUE],
+&clk, sizeof(clk),
&stat, sizeof(stat));
}
@@ -434,17 +498,29 @@ static int scpi_dvfs_get_idx(u8 domain)
int ret;
u8 dvfs_idx;
- ret = scpi_send_message(SCPI_CMD_GET_DVFS, &domain, sizeof(domain),
+ ret = check_cmd(CMD_GET_DVFS);
+ if (ret)
+ return ret;
+
+ ret = scpi_send_message(scpi_info->scpi_cmds[CMD_GET_DVFS],
+ &domain, sizeof(domain),
&dvfs_idx, sizeof(dvfs_idx));
+
return ret ? ret : dvfs_idx;
}
static int scpi_dvfs_set_idx(u8 d
[PATCH v3 8/8] ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 36 +
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 2748007..257845a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -61,6 +61,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
+ clocks = <&scpi_dvfs 0>;
};
cpu1: cpu@1 {
@@ -68,6 +69,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
+ clocks = <&scpi_dvfs 0>;
};
cpu2: cpu@2 {
@@ -75,6 +77,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
+ clocks = <&scpi_dvfs 0>;
};
cpu3: cpu@3 {
@@ -82,6 +85,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
+ clocks = <&scpi_dvfs 0>;
};
};
@@ -99,6 +103,28 @@
method = "smc";
};
+ scpi {
+ compatible = "amlogic,meson-gxbb-scpi";
+ mboxes = <&mailbox 1 &mailbox 2>;
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+ clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_dvfs: scpi_clocks@0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <1>;
+ clock-indices = <0>;
+ clock-output-names = "vcpu";
+ };
+ };
+
+ scpi_sensors: sensors {
+ compatible = "arm,scpi-sensors";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = ;
#size-cells = <1>;
ranges = <0 0x0 0xc800 0x14000>;
+
+ cpu_scp_lpri: scp-shmem@0 {
+ compatible = "amlogic,meson-gxbb-scp-shmem";
+ reg = <0x13000 0x400>;
+ };
+
+ cpu_scp_hpri: scp-shmem@200 {
+ compatible = "amlogic,meson-gxbb-scp-shmem";
+ reg = <0x13400 0x400>;
+ };
};
cbus: cbus@c110 {
--
1.9.1
[PATCH v3 3/8] scpi: Do not fail if get_capabilities is not implemented
On Amlogic SCPI legacy implementation, the GET_CAPABILITIES is not supported, failover by using 0.0.0 version. Signed-off-by: Neil Armstrong --- drivers/firmware/arm_scpi.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c index 9ba1020..6a16100 100644 --- a/drivers/firmware/arm_scpi.c +++ b/drivers/firmware/arm_scpi.c @@ -891,6 +891,10 @@ static int scpi_init_versions(struct scpi_drvinfo *info) info->protocol_version = le32_to_cpu(caps.protocol_version); info->firmware_version = le32_to_cpu(caps.platform_version); } + /* Ignore error if not implemented */ + if (scpi_info->is_legacy && ret == -EOPNOTSUPP) + return 0; + return ret; } -- 1.9.1
[PATCH v3 2/8] scpi: Add alternative legacy structures, functions and macros
In order to support the legacy SCPI protocol variant, add back the structures
and macros that varies against the final specification.
Add indirection table for legacy commands.
Add bitmap field for channel selection
Add support for legacy in scpi_send_message.
Signed-off-by: Neil Armstrong
---
drivers/firmware/arm_scpi.c | 218 ++--
1 file changed, 211 insertions(+), 7 deletions(-)
diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
index 9a87687..9ba1020 100644
--- a/drivers/firmware/arm_scpi.c
+++ b/drivers/firmware/arm_scpi.c
@@ -50,11 +50,16 @@
#define CMD_TOKEN_ID_MASK 0xff
#define CMD_DATA_SIZE_SHIFT16
#define CMD_DATA_SIZE_MASK 0x1ff
+#define CMD_LEGACY_DATA_SIZE_SHIFT 20
+#define CMD_LEGACY_DATA_SIZE_MASK 0x1ff
#define PACK_SCPI_CMD(cmd_id, tx_sz) \
cmd_id) & CMD_ID_MASK) << CMD_ID_SHIFT) | \
(((tx_sz) & CMD_DATA_SIZE_MASK) << CMD_DATA_SIZE_SHIFT))
#define ADD_SCPI_TOKEN(cmd, token) \
((cmd) |= (((token) & CMD_TOKEN_ID_MASK) << CMD_TOKEN_ID_SHIFT))
+#define PACK_LEGACY_SCPI_CMD(cmd_id, tx_sz)\
+ cmd_id) & CMD_ID_MASK) << CMD_ID_SHIFT) | \
+ (((tx_sz) & CMD_LEGACY_DATA_SIZE_MASK) << CMD_LEGACY_DATA_SIZE_SHIFT))
#define CMD_SIZE(cmd) (((cmd) >> CMD_DATA_SIZE_SHIFT) & CMD_DATA_SIZE_MASK)
#define CMD_UNIQ_MASK (CMD_TOKEN_ID_MASK << CMD_TOKEN_ID_SHIFT | CMD_ID_MASK)
@@ -133,6 +138,61 @@ enum scpi_std_cmd {
SCPI_CMD_COUNT
};
+/* SCPI Legacy Commands */
+enum legacy_scpi_std_cmd {
+ LEGACY_SCPI_CMD_INVALID = 0x00,
+ LEGACY_SCPI_CMD_SCPI_READY = 0x01,
+ LEGACY_SCPI_CMD_SCPI_CAPABILITIES = 0x02,
+ LEGACY_SCPI_CMD_EVENT = 0x03,
+ LEGACY_SCPI_CMD_SET_CSS_PWR_STATE = 0x04,
+ LEGACY_SCPI_CMD_GET_CSS_PWR_STATE = 0x05,
+ LEGACY_SCPI_CMD_CFG_PWR_STATE_STAT = 0x06,
+ LEGACY_SCPI_CMD_GET_PWR_STATE_STAT = 0x07,
+ LEGACY_SCPI_CMD_SYS_PWR_STATE = 0x08,
+ LEGACY_SCPI_CMD_L2_READY= 0x09,
+ LEGACY_SCPI_CMD_SET_AP_TIMER= 0x0a,
+ LEGACY_SCPI_CMD_CANCEL_AP_TIME = 0x0b,
+ LEGACY_SCPI_CMD_DVFS_CAPABILITIES = 0x0c,
+ LEGACY_SCPI_CMD_GET_DVFS_INFO = 0x0d,
+ LEGACY_SCPI_CMD_SET_DVFS= 0x0e,
+ LEGACY_SCPI_CMD_GET_DVFS= 0x0f,
+ LEGACY_SCPI_CMD_GET_DVFS_STAT = 0x10,
+ LEGACY_SCPI_CMD_SET_RTC = 0x11,
+ LEGACY_SCPI_CMD_GET_RTC = 0x12,
+ LEGACY_SCPI_CMD_CLOCK_CAPABILITIES = 0x13,
+ LEGACY_SCPI_CMD_SET_CLOCK_INDEX = 0x14,
+ LEGACY_SCPI_CMD_SET_CLOCK_VALUE = 0x15,
+ LEGACY_SCPI_CMD_GET_CLOCK_VALUE = 0x16,
+ LEGACY_SCPI_CMD_PSU_CAPABILITIES= 0x17,
+ LEGACY_SCPI_CMD_SET_PSU = 0x18,
+ LEGACY_SCPI_CMD_GET_PSU = 0x19,
+ LEGACY_SCPI_CMD_SENSOR_CAPABILITIES = 0x1a,
+ LEGACY_SCPI_CMD_SENSOR_INFO = 0x1b,
+ LEGACY_SCPI_CMD_SENSOR_VALUE= 0x1c,
+ LEGACY_SCPI_CMD_SENSOR_CFG_PERIODIC = 0x1d,
+ LEGACY_SCPI_CMD_SENSOR_CFG_BOUNDS = 0x1e,
+ LEGACY_SCPI_CMD_SENSOR_ASYNC_VALUE = 0x1f,
+ LEGACY_SCPI_CMD_COUNT
+};
+
+/* List all commands that are required to go through the high priority link */
+static int legacy_hpriority_cmds[] = {
+ LEGACY_SCPI_CMD_GET_CSS_PWR_STATE,
+ LEGACY_SCPI_CMD_CFG_PWR_STATE_STAT,
+ LEGACY_SCPI_CMD_GET_PWR_STATE_STAT,
+ LEGACY_SCPI_CMD_SET_DVFS,
+ LEGACY_SCPI_CMD_GET_DVFS,
+ LEGACY_SCPI_CMD_SET_RTC,
+ LEGACY_SCPI_CMD_GET_RTC,
+ LEGACY_SCPI_CMD_SET_CLOCK_INDEX,
+ LEGACY_SCPI_CMD_SET_CLOCK_VALUE,
+ LEGACY_SCPI_CMD_GET_CLOCK_VALUE,
+ LEGACY_SCPI_CMD_SET_PSU,
+ LEGACY_SCPI_CMD_GET_PSU,
+ LEGACY_SCPI_CMD_SENSOR_CFG_PERIODIC,
+ LEGACY_SCPI_CMD_SENSOR_CFG_BOUNDS,
+};
+
/* List all commands used by this driver, used as indexes */
enum scpi_drv_cmds {
CMD_SCPI_CAPABILITIES = 0,
@@ -165,6 +225,21 @@ static int scpi_std_commands[CMD_MAX_COUNT] = {
SCPI_CMD_GET_DEVICE_PWR_STATE,
};
+static int scpi_legacy_commands[CMD_MAX_COUNT] = {
+ LEGACY_SCPI_CMD_SCPI_CAPABILITIES,
+ -1, /* GET_CLOCK_INFO */
+ LEGACY_SCPI_CMD_GET_CLOCK_VALUE,
+ LEGACY_SCPI_CMD_SET_CLOCK_VALUE,
+ LEGACY_SCPI_CMD_GET_DVFS,
+ LEGACY_SCPI_CMD_SET_DVFS,
+ LEGACY_SCPI_CMD_GET_DVFS_INFO,
+ LEGACY_SCPI_CMD_SENSOR_CAPABILITIES,
+ LEGACY_SCPI_CMD_SENSOR_INFO,
+ LEGACY_SCPI_CMD_SENSOR_VALUE,
+ -1, /* SET_DEVICE_PWR_STATE */
+ -1, /* GET_DEVICE_PWR_STATE */
+};
+
struct scpi_xfer {
[PATCH v3 7/8] ARM64: dts: meson-gxbb: Add SRAM node
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index bdbf6e7..2748007 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -124,6 +124,15 @@
#size-cells = <2>;
ranges;
+ sram: sram@c800 {
+ compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
+ reg = <0x0 0xc800 0x0 0x14000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0xc800 0x14000>;
+ };
+
cbus: cbus@c110 {
compatible = "simple-bus";
reg = <0x0 0xc110 0x0 0x10>;
--
1.9.1
[PATCH v3 6/8] dt-bindings: Add support for Amlogic GXBB SCPI Interface
Acked-by: Rob Herring Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/arm,scpi.txt | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt index faa4b44..04bc171 100644 --- a/Documentation/devicetree/bindings/arm/arm,scpi.txt +++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt @@ -7,7 +7,7 @@ by Linux to initiate various system control and power operations. Required properties: -- compatible : should be "arm,scpi" +- compatible : should be "arm,scpi" or "amlogic,meson-gxbb-scpi" - mboxes: List of phandle and mailbox channel specifiers All the channels reserved by remote SCP firmware for use by SCPI message protocol should be specified in any order @@ -60,7 +60,8 @@ A small area of SRAM is reserved for SCPI communication between application processors and SCP. Required properties: -- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM on Juno +- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM on Juno, + or "amlogic,meson-gxbb-sram" for Amlogic GXBB SoC. The rest of the properties should follow the generic mmio-sram description found in ../../sram/sram.txt @@ -70,7 +71,8 @@ Each sub-node represents the reserved area for SCPI. Required sub-node properties: - reg : The base offset and size of the reserved area with the SRAM - compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based - shared memory on Juno platforms + shared memory on Juno platforms or + "amlogic,meson-gxbb-scp-shmem" for Amlogic GXBB SoC. Sensor bindings for the sensors based on SCPI Message Protocol -- -- 1.9.1
Re: [PATCH 4/7] spi: meson: Add GXBB compatible
On 09/07/2016 08:58 PM, Mark Brown wrote: > On Wed, Sep 07, 2016 at 05:13:40PM +0200, Jerome Brunet wrote: >> From: Neil Armstrong >> >> Signed-off-by: Neil Armstrong >> --- > > I can't do anything with this, you've not provided a signoff. Please > resend with a signoff - see SubmittingPatches for details on what this > means and why it's important. > > I also only have patches 4 and 5 of this series and no cover letter, > what is going on there? > Hi Mark, Submitting patchsets for multiple subsystems is not straightforward, the cover-letter should also have been sent to linux-spi ML, lesson learned ! Jerome left my signoff because the patches were left untouched from my branch. Nevertheless, I will submit these patches 4 & 5 in a separate SPI serie, please ignore them in this patchset. Thanks, Neil
[PATCH 1/2] dt-bindings: spi-meson: Add GXBB Compatible string
Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/spi/spi-meson.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/spi-meson.txt b/Documentation/devicetree/bindings/spi/spi-meson.txt index bb52a86..dc6d031 100644 --- a/Documentation/devicetree/bindings/spi/spi-meson.txt +++ b/Documentation/devicetree/bindings/spi/spi-meson.txt @@ -7,7 +7,7 @@ NOR memories, without DMA support and a 64-byte unified transmit / receive buffer. Required properties: - - compatible: should be "amlogic,meson6-spifc" + - compatible: should be "amlogic,meson6-spifc" or "amlogic,meson-gxbb-spifc" - reg: physical base address and length of the controller registers - clocks: phandle of the input clock for the baud rate generator - #address-cells: should be 1 -- 1.9.1
[PATCH 2/2] spi: meson: Add GXBB compatible
Signed-off-by: Neil Armstrong
---
drivers/spi/spi-meson-spifc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-meson-spifc.c b/drivers/spi/spi-meson-spifc.c
index 2465259..616566e 100644
--- a/drivers/spi/spi-meson-spifc.c
+++ b/drivers/spi/spi-meson-spifc.c
@@ -442,6 +442,7 @@ static const struct dev_pm_ops meson_spifc_pm_ops = {
static const struct of_device_id meson_spifc_dt_match[] = {
{ .compatible = "amlogic,meson6-spifc", },
+ { .compatible = "amlogic,meson-gxbb-spifc", },
{ },
};
MODULE_DEVICE_TABLE(of, meson_spifc_dt_match);
--
1.9.1
[PATCH 0/2] spi: meson: Add Amlogic GXBB compatible
This patchset adds a specific compatible string in the Meson SPIFC driver for the Amlogic Meson GXBB SoC. This patchset is SPI-only respin from Jerome Brunet patchset at [1]. [1] http://lkml.kernel.org/r/1473261223-15412-1-git-send-email-jbru...@baylibre.com Neil Armstrong (2): dt-bindings: spi-meson: Add GXBB Compatible string spi: meson: Add GXBB compatible Documentation/devicetree/bindings/spi/spi-meson.txt | 2 +- drivers/spi/spi-meson-spifc.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) -- 1.9.1
Re: [PATCH 2/3] ARM64: dts: amlogic: Add basic support for Amlogic S905X
On 09/13/2016 08:14 AM, Carlo Caione wrote: > On Mon, Sep 12, 2016 at 11:43 PM, Andreas Färber wrote: > > [cut] >> I'm not arguing over the file name, where it perfectly makes sense to >> have a meson-gxl- prefix (already discussed), just about the compatible >> string where we don't have "amlogic,meson-gxl-s905x-p231" either because >> it is completely unnecessary and does _not_ add any value. >> >> Not that we're checking this string anywhere anyway... If you want to >> check for the GXL family you have to use "amlogic,meson-gxl"; if you >> want to check for the specific SoC you use "amlogic,s905x". Simple. We >> never match partial strings, so there is no sense in a hardcoded prefix >> that is duplicating information already available. > > Ok, then. Fine with me. > > Neil, do you want to resend my patch or you can take care of the fixes > for the whole patchset? > > Thanks, > Ok, I still need to synchronize with kevin for when and where to rebase from. Neil
[PATCH v2 0/3] ARM64: amlogic: Add support for GXL SoC Family
The new Amlogic GXL SoCs (S905X and S905D) are part of the Meson GX family and share some common features that can be described in a common GX dtsi file used by the Meson GXBB and Meson GXL Family dtsi. This patchset introduces the common GX dtsi and switches the GXBB to use the common GX dtsi. Then it introduces the GXL S905X SoC with the GXL common dtsi, then the S905D dtsi and the p212 board dts. Finally the GXL S905D SoC is introduced with a S905D dtsi using the GXL common and the p23x Board dtsi for the p231 and p230 development boards. Changes since v1 at http://lkml.kernel.org/r/20160903082227.30559-1-narmstr...@baylibre.com : - Add missing copyrigh in gx dtsi - Rename gxl SoCs compatibles to amlogic,s905x and amlogic,s905d Changes since RFC v1: - Merge GX common and GXBB changes in a single patch - Integrate GXL S905X patch - Add support for S905D and the p23x boards Note: This patchset integrates the patch "ARM64: dts: amlogic: Add basic support for Amlogic S905X" [1] from Carlo Caione. [1] http://lkml.kernel.org/r/1472382113-10754-1-git-send-email-ca...@caione.org Carlo Caione (1): ARM64: dts: amlogic: Add basic support for Amlogic S905X Neil Armstrong (2): ARM64: dts: amlogic: Add Meson GX dtsi from GXBB ARM64: dts: amlogic: Add basic support for Amlogic S905D Documentation/devicetree/bindings/arm/amlogic.txt | 11 + arch/arm64/boot/dts/amlogic/Makefile | 3 + arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 200 + arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi| 895 + .../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 51 ++ .../boot/dts/amlogic/meson-gxl-s905d-p231.dts | 51 ++ .../boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi | 64 ++ arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi | 48 ++ .../boot/dts/amlogic/meson-gxl-s905x-p212.dts | 69 ++ arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi | 48 ++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 48 ++ 11 files changed, 972 insertions(+), 516 deletions(-) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gx.dtsi create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi -- 2.7.0
[PATCH v2 3/3] ARM64: dts: amlogic: Add basic support for Amlogic S905D
This patch introduces the basic support for the Amlogic S905D (MesonGXL)
and for the Amlogic evaluation boards P230 and P231.
No documentation has been released yet for this SoC, so for now only the
bare minimum has been added in the DT.
Acked-by: Rob Herring
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/arm/amlogic.txt | 4 ++
arch/arm64/boot/dts/amlogic/Makefile | 2 +
.../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 51 +
.../boot/dts/amlogic/meson-gxl-s905d-p231.dts | 51 +
.../boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi | 64 ++
arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi | 48
6 files changed, 220 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt
b/Documentation/devicetree/bindings/arm/amlogic.txt
index 7edb635..fffc179 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -21,6 +21,10 @@ Boards with the Amlogic Meson GXL S905X SoC shall have the
following properties:
Required root node property:
compatible: "amlogic,s905x", "amlogic,meson-gxl";
+Boards with the Amlogic Meson GXL S905D SoC shall have the following
properties:
+ Required root node property:
+compatible: "amlogic,s905d", "amlogic,meson-gxl";
+
Board compatible values:
- "geniatech,atv1200" (Meson6)
- "minix,neo-x8" (Meson8)
diff --git a/arch/arm64/boot/dts/amlogic/Makefile
b/arch/arm64/boot/dts/amlogic/Makefile
index 1f78b07..57e0ae0 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -5,6 +5,8 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
new file mode 100644
index 000..3dfaa37
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905d-p23x.dtsi"
+
+/ {
+ compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl";
+ model = "Amlogic Meson GXL (S905D) P230 Devel
[PATCH v2 2/3] ARM64: dts: amlogic: Add basic support for Amlogic S905X
From: Carlo Caione
This patch introduces the basic support for the Amlogic S905X (Meson
GXL) and for the Amlogic evaluation board P212.
No documentation has been released yet for this SoC, so for now only the
bare minimum has been added in the DT.
Acked-by: Rob Herring
Reviewed-by: Andreas Färber
Signed-off-by: Carlo Caione
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/arm/amlogic.txt | 7 +++
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../boot/dts/amlogic/meson-gxl-s905x-p212.dts | 69 ++
arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi | 48 +++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 48 +++
5 files changed, 173 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt
b/Documentation/devicetree/bindings/arm/amlogic.txt
index fcc6f6c..7edb635 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -17,6 +17,10 @@ Boards with the Amlogic Meson GXBaby SoC shall have the
following properties:
Required root node property:
compatible: "amlogic,meson-gxbb";
+Boards with the Amlogic Meson GXL S905X SoC shall have the following
properties:
+ Required root node property:
+compatible: "amlogic,s905x", "amlogic,meson-gxl";
+
Board compatible values:
- "geniatech,atv1200" (Meson6)
- "minix,neo-x8" (Meson8)
@@ -28,3 +32,6 @@ Board compatible values:
- "hardkernel,odroid-c2" (Meson gxbb)
- "amlogic,p200" (Meson gxbb)
- "amlogic,p201" (Meson gxbb)
+ - "amlogic,p212" (Meson gxl s905x)
+ - "amlogic,p230" (Meson gxl s905d)
+ - "amlogic,p231" (Meson gxl s905d)
diff --git a/arch/arm64/boot/dts/amlogic/Makefile
b/arch/arm64/boot/dts/amlogic/Makefile
index 47ec703..1f78b07 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
new file mode 100644
index 000..9639f01
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905x.dtsi"
+
+/ {
+ compatible =
[PATCH v2 1/3] ARM64: dts: amlogic: Add Meson GX dtsi from GXBB
Move all non-gxbb specific nodes to a common GX dtsi.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 200 +++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 895
2 files changed, 579 insertions(+), 516 deletions(-)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gx.dtsi
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
new file mode 100644
index 000..a739d6a
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong
+ *
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione
+ *
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = ,
+,
+,
+;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = ,
+,
+,
+;
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+
Re: [PATCH 04/10] reset: meson: add driver Kconfig option
On 08/24/2016 03:28 PM, Philipp Zabel wrote: > Visible only if COMPILE_TEST is enabled, this allows to include the > driver in build tests. > > Cc: Neil Armstrong > Signed-off-by: Philipp Zabel > --- > drivers/reset/Kconfig | 6 ++ > drivers/reset/Makefile | 2 +- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig > index 8e33de2..fdf942d 100644 > --- a/drivers/reset/Kconfig > +++ b/drivers/reset/Kconfig > @@ -34,6 +34,12 @@ config RESET_LPC18XX > This enables the LPC18xx/43 reset driver that supports the reset > controllers on AR71xx SoCs. > > +config RESET_MESON > + bool "Meson Reset Driver" if COMPILE_TEST > + default ARCH_MESON > + help > + This enables the reset driver for Amlogic Meson SoCs. > + > config RESET_OXNAS > bool > > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index 25aa05a..1408cba 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -1,7 +1,6 @@ > obj-y += core.o > obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o > obj-$(CONFIG_MACH_PISTACHIO) += reset-pistachio.o > -obj-$(CONFIG_ARCH_MESON) += reset-meson.o > obj-$(CONFIG_ARCH_STM32) += reset-stm32.o > obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o > obj-$(CONFIG_ARCH_STI) += sti/ > @@ -10,6 +9,7 @@ obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq.o > obj-$(CONFIG_RESET_ATH79) += reset-ath79.o > obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o > obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o > +obj-$(CONFIG_RESET_MESON) += reset-meson.o > obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o > obj-$(CONFIG_TI_SYSCON_RESET) += reset-ti-syscon.o > obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o > Acked-by: Neil Armstrong
[RFC PATCH] pinctrl: Add SX150X GPIO Extender Pinctrl Driver
Since the I2C sx150x GPIO expander driver uses platform_data to managed
the pins configurations, rewrite the driver as a pinctrl driver using
pinconf to get pin configurations from DT.
The pinctrl driver is functionnally as the gpio-only driver equivalent
and can use DT for pinconf.
Signed-off-by: Neil Armstrong
---
drivers/pinctrl/Kconfig | 15 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-sx150x.c | 1056 ++
3 files changed, 1072 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-sx150x.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b3fe1d3..7ca2854 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -164,6 +164,21 @@ config PINCTRL_SIRF
select GENERIC_PINCONF
select GPIOLIB_IRQCHIP
+config PINCTRL_SX150X
+ bool "Semtech SX150x I2C GPIO expander pinctrl driver"
+ depends on GPIOLIB && I2C=y
+ select PINMUX
+ select PINCONF
+ select GENERIC_PINCONF
+ select GPIOLIB_IRQCHIP
+ select OF_GPIO
+ help
+ Say yes here to provide support for Semtech SX150-series I2C
+ GPIO expanders as pinctrl module.
+ Compatible models include:
+ - 8 bits: sx1508q, sx1502q
+ - 16 bits: sx1509q, sx1506q
+
config PINCTRL_PISTACHIO
def_bool y if MACH_PISTACHIO
depends on GPIOLIB
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 8ebd7b8..f7e748d 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
+obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o
obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o
diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c
new file mode 100644
index 000..6ace648
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-sx150x.c
@@ -0,0 +1,1056 @@
+/*
+ * Copyright (c) 2010, BayLibre, SAS. All rights reserved.
+ * Author: Neil Armstrong
+ *
+ * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Driver for Semtech SX150X I2C GPIO Expanders
+ *
+ * Author: Gregory Bean
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "core.h"
+#include "pinconf.h"
+#include "pinctrl-utils.h"
+
+/* The chip models of sx150x */
+enum {
+ SX150X_123 = 0,
+ SX150X_456,
+ SX150X_789,
+};
+
+struct sx150x_123_pri {
+ u8 reg_pld_mode;
+ u8 reg_pld_table0;
+ u8 reg_pld_table1;
+ u8 reg_pld_table2;
+ u8 reg_pld_table3;
+ u8 reg_pld_table4;
+ u8 reg_advance;
+};
+
+struct sx150x_456_pri {
+ u8 reg_pld_mode;
+ u8 reg_pld_table0;
+ u8 reg_pld_table1;
+ u8 reg_pld_table2;
+ u8 reg_pld_table3;
+ u8 reg_pld_table4;
+ u8 reg_advance;
+};
+
+struct sx150x_789_pri {
+ u8 reg_drain;
+ u8 reg_polarity;
+ u8 reg_clock;
+ u8 reg_misc;
+ u8 reg_reset;
+ u8 ngpios;
+};
+
+struct sx150x_device_data {
+ u8 model;
+ u8 reg_pullup;
+ u8 reg_pulldn;
+ u8 reg_dir;
+ u8 reg_data;
+ u8 reg_irq_mask;
+ u8 reg_irq_src;
+ u8 reg_sense;
+ u8 ngpios;
+ union {
+ struct sx150x_123_pri x123;
+ struct sx150x_456_pri x456;
+ struct sx150x_789_pri x789;
+ } pri;
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+};
+
+struct sx150x_pinctrl {
+ struct device *dev;
+ struct i2c_client *client;
+ struct pinctrl_dev *pctldev;
+ struct pinctrl_desc pinctrl_desc;
+ struct gpio_chip gpio;
+ struct irq_chip irq_chip;
+ struct {
+ int update;
+ u32 sense;
+ u32 masked;
+ u32 dev_sense;
+ u32 dev_masked;
+ } irq;
+ struct mutex lock;
+ const struct sx150x_device_data *data;
+};
+
+static const struct pinctrl_pin_desc sx150x_8_pins[] = {
+ PINCTRL_PIN(0, "gpio0"),
+ PINCTRL_PIN(1, "gpio1&qu
Re: [PATCH v2 0/7] scpi: Add support for legacy SCPI protocol
On 08/23/2016 01:46 PM, Neil Armstrong wrote: > This patchset aims to support the legacy SCPI firmware implementation that was > delivered as early technology preview for the JUNO platform. > > Finally a stable, maintained and public implementation for the SCPI protocol > has been upstreamed part of the JUNO support and it is the recommended way > of implementing SCP communication on ARMv8 platforms. > > The Amlogic GXBB platform is using this legacy protocol, as the RK3368 & > RK3399 > platforms. This patchset will only add support for Amlogic GXBB SoC. > > This patchset add support for the legacy protocol in the arm_scpi.c file, > avoiding code duplication. > > Last RFC discution tread can be found at : https://lkml.org/lkml/2016/8/9/210 > > The last patch depends on the "Platform MHU" dtsi patch. > > Changes since v1 at : > http://lkml.kernel.org/r/1471515066-3626-1-git-send-email-narmstr...@baylibre.com > - Dropped vendor_send_message and rockchip vendor mechanism patches > - Merged alternate functions into main functions using is_legacy boolean > - Added DT match table to set is_legacy to true > - Kept alternate scpi_ops structure for legacy > > Neil Armstrong (7): > scpi: Add alternative legacy structures, functions and macros > scpi: Use legacy variants command index calling scpi_send_message > scpi: Add support for Legacy match table for Amlogic GXBB SoC > scpi: grow MAX_DVFS_OPPS to 16 entries > dt-bindings: Add support for Amlogic GXBB SCPI Interface > ARM64: dts: meson-gxbb: Add SRAM node > ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes > > Documentation/devicetree/bindings/arm/arm,scpi.txt | 8 +- > arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi| 45 > drivers/firmware/arm_scpi.c| 279 > +++-- > 3 files changed, 302 insertions(+), 30 deletions(-) > Hi Sudeep, Sorry but I posted this V2 before you had time to look at my previous v1 replies... In this serie, I merged the scpi_send_message, but I must still evaluate how it's possible to use the list to queue commands. Here I used if(is_legacy) to stop duplicating functions, is this ok for you ? Thanks, Neil
[PATCH v5.1 0/2] tty/serial: meson_uart: add support for core clock handling
This patchset is a re-spin of Helmut Klein's v3 patchset at [0] and the v4/v5 patchset at [1] & [2]. Initially, the original patchset was made to enable usage on the non-AO UARTS not enabled by the Bootloader (uart_B and uart_C), but the patchset needed an overall change to have clean and stable DT bindings. The Amlogic Meson UART Driver did not have stable DT bindings and mismatched clock handling on non-AO UARTs since these "EE" UARTs needs a clock gate to be ungated to works correctly. In the same way, the AO UARTs does not need gating and can be used as Early Consoles. In the same time, the UART Interfaces can take clock input for the baudrate generate from either the external Xtal or the internal Bus Clock (clk81). So new bindings was necessary to meet these requirements and the DT maintainers requirements. The "legacy" binding actually used in the driver is left until all the DT files are switched to the new bindings. The GX DT has been tested, but the last 4 Meson6/Meson8/b are only compile-tested, and testing is welcome. Thus only the first 3 patches can be merged until the Meson6/Meson8/b are formally tested. It must be noted that the meson6 cannot work today except using an early console since the UART driver could not probe without a clocks property. Changes since v5 at [2]: - Dropped bindings and tty patch since merged by greg kh into tty next branch - Keep old bindings in DT files for retro-compatibility Changes since v4 at [1]: - Droped meson8/meson8b DT patches - Fixes copy/paste error in patch 2 - Refactored clock probing in patch 2 - merged meson6 patches together to avoid breaking bisect [0] http://lkml.kernel.org/r/20170331165437.26227-1-hgkr.kl...@gmail.com [1] http://lkml.kernel.org/r/1497001756-942-1-git-send-email-narmstr...@baylibre.com [2] http://lkml.kernel.org/r/1497428957-19942-1-git-send-email-narmstr...@baylibre.com Helmut Klein (1): ARM64: dts: meson-gx: use stable UART bindings with correct gate clock Neil Armstrong (1): ARM: dts: meson6: use stable UART bindings arch/arm/boot/dts/meson.dtsi| 8 arch/arm/boot/dts/meson6.dtsi | 28 arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 12 +--- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 25 + arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 25 + 5 files changed, 87 insertions(+), 11 deletions(-) -- 1.9.1
[PATCH v5.1 1/2] ARM64: dts: meson-gx: use stable UART bindings with correct gate clock
From: Helmut Klein
This patch switches to the stable UART bindings but also add the correct
gate clock to the non-AO UART nodes for GXBB and GXL SoCs.
Acked-by: Jerome Brunet
Signed-off-by: Helmut Klein
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 12 +---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 25 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 25 +
3 files changed, 55 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 35b8c88..1c6e4ed 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -225,7 +225,7 @@
};
uart_A: serial@84c0 {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson-gx-uart",
"amlogic,meson-uart";
reg = <0x0 0x84c0 0x0 0x14>;
interrupts = ;
clocks = <&xtal>;
@@ -233,7 +233,7 @@
};
uart_B: serial@84dc {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson-gx-uart",
"amlogic,meson-uart";
reg = <0x0 0x84dc 0x0 0x14>;
interrupts = ;
clocks = <&xtal>;
@@ -279,7 +279,7 @@
};
uart_C: serial@8700 {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson-gx-uart",
"amlogic,meson-uart";
reg = <0x0 0x8700 0x0 0x14>;
interrupts = ;
clocks = <&xtal>;
@@ -375,18 +375,16 @@
};
uart_AO: serial@4c0 {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart", "amlogic,meson-uart";
reg = <0x0 0x004c0 0x0 0x14>;
interrupts = ;
- clocks = <&xtal>;
status = "disabled";
};
uart_AO_B: serial@4e0 {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart", "amlogic,meson-uart";
reg = <0x0 0x004e0 0x0 0x14>;
interrupts = ;
- clocks = <&xtal>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 17d3efd..ea53cc2 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -682,6 +682,31 @@
clocks = <&clkc CLKID_SPI>;
};
+&uart_A {
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_AO {
+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_AO_B {
+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_B {
+ clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+ clock-names = "xtal", "core", "baud";
+};
+
+&uart_C {
+ clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
+ clock-names = "xtal", "core", "baud";
+};
+
&vpu {
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index 8d4f316..9e67444 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -623,6 +623,31 @@
clocks = <&clkc CLKID_SPI>;
};
+&uart_A {
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+ clock-names = "xtal", "core", "baud";
+};
+
+&uart_AO {
+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_AO_B {
+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_B {
+ clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+ clock-names = "xtal", "core", "baud";
+};
+
+&uart_C {
+ clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
+ clock-names = "xtal", "core", "baud";
+};
+
&vpu {
compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
};
--
1.9.1
[PATCH v5.1 2/2] ARM: dts: meson6: use stable UART bindings
The UART bindings needs specifying a SoC family, use the meson6 family
for the UART nodes like the other nodes.
Switch to the stable UART bindings for meson6 by adding a XTAL node and
using the proper compatible strings.
Signed-off-by: Neil Armstrong
---
arch/arm/boot/dts/meson.dtsi | 8
arch/arm/boot/dts/meson6.dtsi | 28
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 15204e4..1ce9aa0 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -86,14 +86,14 @@
};
uart_A: serial@84c0 {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson6-uart",
"amlogic,meson-uart";
reg = <0x84c0 0x18>;
interrupts = ;
status = "disabled";
};
uart_B: serial@84dc {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson6-uart",
"amlogic,meson-uart";
reg = <0x84dc 0x18>;
interrupts = ;
status = "disabled";
@@ -117,7 +117,7 @@
};
uart_C: serial@8700 {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson6-uart",
"amlogic,meson-uart";
reg = <0x8700 0x18>;
interrupts = ;
status = "disabled";
@@ -182,7 +182,7 @@
};
uart_AO: serial@4c0 {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson6-uart",
"amlogic,meson-ao-uart", "amlogic,meson-uart";
reg = <0x4c0 0x18>;
interrupts = ;
status = "disabled";
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index 8557b61..ef281d2 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -70,9 +70,37 @@
};
};
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
clk81: clk@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <2>;
};
}; /* end of / */
+
+
+&uart_AO {
+ clocks = <&xtal>, <&clk81>, <&clk81>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_A {
+ clocks = <&xtal>, <&clk81>, <&clk81>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_B {
+ clocks = <&xtal>, <&clk81>, <&clk81>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_C {
+ clocks = <&xtal>, <&clk81>, <&clk81>;
+ clock-names = "xtal", "pclk", "baud";
+};
--
1.9.1
Re: [PATCH 1/2] dt-bindings: spi: Document the STM32 SPI bindings
On 06/21/2017 04:32 PM, Amelie Delaunay wrote:
> This patch adds the documentation of device tree bindings
> for the STM32 SPI controller.
>
> Signed-off-by: Amelie Delaunay
> ---
> .../devicetree/bindings/spi/spi-stm32.txt | 60
> ++
> 1 file changed, 60 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/spi-stm32.txt
>
> diff --git a/Documentation/devicetree/bindings/spi/spi-stm32.txt
> b/Documentation/devicetree/bindings/spi/spi-stm32.txt
> new file mode 100644
> index 000..3958bf6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/spi-stm32.txt
> @@ -0,0 +1,60 @@
> +STMicroelectronics STM32 SPI Controller
> +
> +The STM32 SPI controller is used to communicate with external devices using
> +the Serial Peripheral Interface. It supports full-duplex, half-duplex and
> +simplex synchronous serial communication with external devices. It supports
> +from 4 to 32-bit data size. Although it can be configured as master or slave,
> +only master is supported by the driver.
> +
> +Required properties:
> +- compatible: Must be "st,stm32-spi".
Hi Amelie,
What about the gen1 SPI devices like the F4 ?
It should have been better to use SoC specific compatible, or specify the SPI
HW gen like gen1 or gen2.
Neil
> +- reg: Offset and length of the device's register set.
> +- interrupts: Must contain the interrupt id.
> +- clocks: Must contain an entry for spiclk (which feeds the internal clock
> + generator).
> +- #address-cells: Number of cells required to define a chip select address.
> +- #size-cells: Should be zero.
> +
> +Optional properties:
> +- resets: Must contain the phandle to the reset controller.
> +- A pinctrl state named "default" may be defined to set pins in mode of
> + operation for SPI transfer.
> +- dmas: DMA specifiers for tx and rx dma. DMA fifo mode must be used. See the
> + STM32 DMA bindings, Documentation/devicetree/bindings/dma/stm32-dma.txt.
> +- dma-names: DMA request names should include "tx" and "rx" if present.
> +- cs-gpios: list of GPIO chip selects. See the SPI bus bindings,
> + Documentation/devicetree/bindings/spi/spi-bus.txt
> +
> +
> +Child nodes represent devices on the SPI bus
> + See ../spi/spi-bus.txt
> +
> +Optional properties:
> +- st,spi-midi-ns: (Master Inter-Data Idleness) minimum time delay in
> + nanoseconds inserted between two consecutive data frames.
> +
> +
> +Example:
> + spi2: spi@40003800 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-spi";
> + reg = <0x40003800 0x400>;
> + interrupts = <36>;
> + clocks = <&rcc SPI2_CK>;
> + resets = <&rcc 1166>;
> + dmas = <&dmamux1 0 39 0x400 0x01>,
> +<&dmamux1 1 40 0x400 0x01>;
> + dma-names = "rx", "tx";
> + pinctrl-0 = <&spi2_pins_b>;
> + pinctrl-names = "default";
> + status = "okay";
> + cs-gpios = <&gpioa 11 0>;
> +
> + spidev@0 {
> + compatible = "spidev";
> + reg = <0>;
> + spi-max-frequency = <400>;
> + st,spi-midi = <4000>;
> + };
> + };
>
[PATCH] reset: meson: add level reset support for GX SoC family
The Amlogic GX SoC family embeds alternate registers to drive the reset
levels next to the pulse registers.
This patch adds support for level reset handling on the GX family only.
The Meson8 family has an alternate way to handle level reset.
Signed-off-by: Neil Armstrong
---
drivers/reset/reset-meson.c | 57 +
1 file changed, 53 insertions(+), 4 deletions(-)
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index a8b915e..d55e440 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -62,9 +62,11 @@
#include
#include
#include
+#include
#define REG_COUNT 8
#define BITS_PER_REG 32
+#define LEVEL_OFFSET 0x7c
struct meson_reset {
void __iomem *reg_base;
@@ -88,18 +90,61 @@ static int meson_reset_reset(struct reset_controller_dev
*rcdev,
return 0;
}
-static const struct reset_control_ops meson_reset_ops = {
+static int meson_reset_level(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct meson_reset *data =
+ container_of(rcdev, struct meson_reset, rcdev);
+ unsigned int bank = id / BITS_PER_REG;
+ unsigned int offset = id % BITS_PER_REG;
+ void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2);
+ u32 reg;
+
+ if (bank >= REG_COUNT)
+ return -EINVAL;
+
+ reg = readl(reg_addr);
+ if (assert)
+ writel(reg & ~BIT(offset), reg_addr);
+ else
+ writel(reg | BIT(offset), reg_addr);
+
+ return 0;
+}
+
+static int meson_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return meson_reset_level(rcdev, id, true);
+}
+
+static int meson_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return meson_reset_level(rcdev, id, false);
+}
+
+static const struct reset_control_ops meson_reset_meson8_ops = {
+ .reset = meson_reset_reset,
+};
+
+static const struct reset_control_ops meson_reset_gx_ops = {
.reset = meson_reset_reset,
+ .assert = meson_reset_assert,
+ .deassert = meson_reset_deassert,
};
static const struct of_device_id meson_reset_dt_ids[] = {
-{ .compatible = "amlogic,meson8b-reset", },
-{ .compatible = "amlogic,meson-gxbb-reset", },
+{ .compatible = "amlogic,meson8b-reset",
+ .data = (void *) &meson_reset_meson8_ops, },
+{ .compatible = "amlogic,meson-gxbb-reset",
+ .data = (void *) &meson_reset_gx_ops, },
{ /* sentinel */ },
};
static int meson_reset_probe(struct platform_device *pdev)
{
+ const struct reset_control_ops *ops;
struct meson_reset *data;
struct resource *res;
@@ -107,6 +152,10 @@ static int meson_reset_probe(struct platform_device *pdev)
if (!data)
return -ENOMEM;
+ ops = of_device_get_match_data(&pdev->dev);
+ if (!ops)
+ return -EINVAL;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
data->reg_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(data->reg_base))
@@ -116,7 +165,7 @@ static int meson_reset_probe(struct platform_device *pdev)
data->rcdev.owner = THIS_MODULE;
data->rcdev.nr_resets = REG_COUNT * BITS_PER_REG;
- data->rcdev.ops = &meson_reset_ops;
+ data->rcdev.ops = ops;
data->rcdev.of_node = pdev->dev.of_node;
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
--
2.7.4
[PATCH 2/2] clk: meson: gxbb: Add VPU and VAPB clocks data
The Amlogic Meson GX SoCs needs these two clocks to power up the
VPU power domain.
These two clocks are similar to the MALI clocks by having a glitch-free
mux and two similar clocks with gate, divider and muxes.
Signed-off-by: Neil Armstrong
---
drivers/clk/meson/gxbb.c | 292 +++
1 file changed, 292 insertions(+)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index b2d1e8e..a713744 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -1131,6 +1131,253 @@ static struct clk_gate gxbb_sd_emmc_c_clk0 = {
},
};
+/* VPU Clock */
+
+static u32 mux_table_vpu[] = {0, 1, 2, 3};
+static const char * const gxbb_vpu_parent_names[] = {
+ "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
+};
+
+static struct clk_mux gxbb_vpu_0_sel = {
+ .reg = (void *)HHI_VPU_CLK_CNTL,
+ .mask = 0x3,
+ .shift = 9,
+ .lock = &clk_lock,
+ .table = mux_table_vpu,
+ .hw.init = &(struct clk_init_data){
+ .name = "vpu_0_sel",
+ .ops = &clk_mux_ops,
+ /*
+* bits 9:10 selects from 4 possible parents:
+* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
+*/
+ .parent_names = gxbb_vpu_parent_names,
+ .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
+ .flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_divider gxbb_vpu_0_div = {
+ .reg = (void *)HHI_VPU_CLK_CNTL,
+ .shift = 0,
+ .width = 7,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "vpu_0_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "vpu_0_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_gate gxbb_vpu_0 = {
+ .reg = (void *)HHI_VPU_CLK_CNTL,
+ .bit_idx = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_0",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "vpu_0_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_mux gxbb_vpu_1_sel = {
+ .reg = (void *)HHI_VPU_CLK_CNTL,
+ .mask = 0x3,
+ .shift = 25,
+ .lock = &clk_lock,
+ .table = mux_table_vpu,
+ .hw.init = &(struct clk_init_data){
+ .name = "vpu_1_sel",
+ .ops = &clk_mux_ops,
+ /*
+* bits 25:26 selects from 4 possible parents:
+* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
+*/
+ .parent_names = gxbb_vpu_parent_names,
+ .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
+ .flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_divider gxbb_vpu_1_div = {
+ .reg = (void *)HHI_VPU_CLK_CNTL,
+ .shift = 16,
+ .width = 7,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "vpu_1_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "vpu_1_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_gate gxbb_vpu_1 = {
+ .reg = (void *)HHI_VPU_CLK_CNTL,
+ .bit_idx = 24,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_1",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "vpu_1_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_mux gxbb_vpu = {
+ .reg = (void *)HHI_VPU_CLK_CNTL,
+ .mask = 1,
+ .shift = 31,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "vpu",
+ .ops = &clk_mux_ops,
+ /*
+* bit 31 selects from 2 possible parents:
+* vpu_0 or vpu_1
+*/
+ .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+/* VAPB Clock */
+
+static u32 mux_table_vapb[] = {0, 1, 2, 3};
+static const char * const gxbb_vapb_parent_names[] = {
+ "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
+};
+
+static
[PATCH 0/2] clk: meson: gxbb: Add VPU and VAPB clocks
This patchset adds the VPU and VAPB clocks used to feed the Amlogic Meson GX SoC Video Processing Unit and it's power domain. Neil Armstrong (2): clk: meson: gxbb: Add VPU and VAPB clockids clk: meson: gxbb: Add VPU and VAPB clocks data drivers/clk/meson/gxbb.c | 292 ++ drivers/clk/meson/gxbb.h | 6 +- include/dt-bindings/clock/gxbb-clkc.h | 11 ++ 3 files changed, 308 insertions(+), 1 deletion(-) -- 2.7.4
[PATCH 1/2] clk: meson: gxbb: Add VPU and VAPB clockids
Add the clkids for the clocks feeding the Video Processing Unit. Signed-off-by: Neil Armstrong --- drivers/clk/meson/gxbb.h | 6 +- include/dt-bindings/clock/gxbb-clkc.h | 11 +++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index 5b1d4b3..aee6fbb 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -190,8 +190,12 @@ #define CLKID_SD_EMMC_B_CLK0_DIV 121 #define CLKID_SD_EMMC_C_CLK0_SEL 123 #define CLKID_SD_EMMC_C_CLK0_DIV 124 +#define CLKID_VPU_0_DIV 127 +#define CLKID_VPU_1_DIV 130 +#define CLKID_VAPB_0_DIV 134 +#define CLKID_VAPB_1_DIV 137 -#define NR_CLKS 126 +#define NR_CLKS 141 /* include the CLKIDs that have been made part of the DT binding */ #include diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h index c04a76d..7c5a6f3 100644 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -113,5 +113,16 @@ #define CLKID_SD_EMMC_A_CLK0 119 #define CLKID_SD_EMMC_B_CLK0 122 #define CLKID_SD_EMMC_C_CLK0 125 +#define CLKID_VPU_0_SEL126 +#define CLKID_VPU_0128 +#define CLKID_VPU_1_SEL129 +#define CLKID_VPU_1131 +#define CLKID_VPU 132 +#define CLKID_VAPB_0_SEL 133 +#define CLKID_VAPB_0 135 +#define CLKID_VAPB_1_SEL 136 +#define CLKID_VAPB_1 138 +#define CLKID_VAPB_SEL 139 +#define CLKID_VAPB 140 #endif /* __GXBB_CLKC_H */ -- 2.7.4
[PATCH 0/2] soc: amlogic: add support for Meson GX VPU Domains
On the Amlogic Gx SoCs (GXBB, GXL & GXM), the VPU power domain is initialized by the vendor U-Boot code, but running mainline U-boot has been possible on these SoCs. But lacking such init made the system lock at kernel boot. This patchset adds the Video Processing Unit power domain driver to enable the same power-on and power-down sequences and was designed to allow booting with the power domain already initialized or not. This driver has been tested on : - Odroid-C2 (GXBB) with Vendor and Mainline U-Boot - P212 (GXL) with Vendor and Mainline U-Boot - Khadas Vim (GXL) with Vendor U-Boot - Khadas Vim2 with (GXM) Vendor U-Boot Neil Armstrong (2): soc: amlogic: add Meson GX VPU Domains driver dt-bindings: power: add amlogic meeson power domain bindings .../bindings/power/amlogic,meson-gx-pwrc.txt | 65 ++ drivers/soc/amlogic/Kconfig| 10 + drivers/soc/amlogic/Makefile | 1 + drivers/soc/amlogic/meson-gx-pwrc-vpu.c| 234 + 4 files changed, 310 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt create mode 100644 drivers/soc/amlogic/meson-gx-pwrc-vpu.c -- 2.7.4
[PATCH 1/2] soc: amlogic: add Meson GX VPU Domains driver
The Video Processing Unit needs a specific Power Domain powering scheme
this driver handles this as a PM Power Domain driver.
Signed-off-by: Neil Armstrong
---
drivers/soc/amlogic/Kconfig | 10 ++
drivers/soc/amlogic/Makefile| 1 +
drivers/soc/amlogic/meson-gx-pwrc-vpu.c | 234
3 files changed, 245 insertions(+)
create mode 100644 drivers/soc/amlogic/meson-gx-pwrc-vpu.c
diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
index ef0b8f6..1621bb2 100644
--- a/drivers/soc/amlogic/Kconfig
+++ b/drivers/soc/amlogic/Kconfig
@@ -9,6 +9,16 @@ config MESON_GX_SOCINFO
Say yes to support decoding of Amlogic Meson GX SoC family
information about the type, package and version.
+config MESON_GX_PM_DOMAINS
+ bool "Amlogic Meson GX Power Domains driver"
+ depends on ARCH_MESON || COMPILE_TEST
+ default ARCH_MESON
+ select PM_GENERIC_DOMAINS
+ select PM_GENERIC_DOMAINS_OF
+ help
+ Say yes to expose Amlogic Meson GX Power Domains as
+ Generic Power Domains.
+
config MESON_MX_SOCINFO
bool "Amlogic Meson MX SoC Information driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile
index 1f5df50..8fa3218 100644
--- a/drivers/soc/amlogic/Makefile
+++ b/drivers/soc/amlogic/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
+obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o
diff --git a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
new file mode 100644
index 000..bf5190b
--- /dev/null
+++ b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ * Author: Neil Armstrong
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* AO Offsets */
+
+#define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
+
+#define GEN_PWR_VPU_HDMI BIT(8)
+#define GEN_PWR_VPU_HDMI_ISO BIT(9)
+
+/* HHI Offsets */
+
+#define HHI_MEM_PD_REG0(0x40 << 2)
+#define HHI_VPU_MEM_PD_REG0(0x41 << 2)
+#define HHI_VPU_MEM_PD_REG1(0x42 << 2)
+
+struct meson_gx_pwrc_vpu {
+ struct generic_pm_domain genpd;
+ struct regmap *regmap_ao;
+ struct regmap *regmap_hhi;
+ struct reset_control *rstc;
+ struct clk *vpu_clk;
+ struct clk *vapb_clk;
+ bool powered;
+};
+
+static inline
+struct meson_gx_pwrc_vpu *genpd_to_pd(struct generic_pm_domain *d)
+{
+ return container_of(d, struct meson_gx_pwrc_vpu, genpd);
+}
+
+static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
+{
+ struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
+ int i;
+
+ regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
+ GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
+ udelay(20);
+
+ /* Power Down Memories */
+ for (i = 0; i < 32; i += 2) {
+ regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
+ 0x2 << i, 0x3 << i);
+ udelay(5);
+ }
+ for (i = 0; i < 32; i += 2) {
+ regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
+ 0x2 << i, 0x3 << i);
+ udelay(5);
+ }
+ for (i = 8; i < 16; i++) {
+ regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
+ BIT(i), BIT(i));
+ udelay(5);
+ }
+ udelay(20);
+
+ regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
+ GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
+
+ msleep(20);
+
+ clk_disable_unprepare(pd->vpu_clk);
+ clk_disable_unprepare(pd->vapb_clk);
+
+ pd->powered = false;
+
+ return 0;
+}
+
+static int meson_gx_pwrc_vpu_setup_clk(struct meson_gx_pwrc_vpu *pd)
+{
+ int ret;
+
+ ret = clk_prepare_enable(pd->vpu_clk);
+ if (ret)
+ return ret;
+
+ return clk_prepare_enable(pd->vapb_clk);
+}
+
+static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
+{
+ struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
+ int ret;
+ int i;
+
+ regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
+ GEN_PWR_VPU_HDMI, 0);
+ udelay(20);
+
+ /* Power Up Memories */
+ for (i = 0; i < 32; i += 2) {
+ regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
+ 0x2 << i, 0);
+ udelay(5);
+ }
+
+ for (i = 0; i < 32; i +
[PATCH 2/2] dt-bindings: power: add amlogic meeson power domain bindings
Signed-off-by: Neil Armstrong
---
.../bindings/power/amlogic,meson-gx-pwrc.txt | 65 ++
1 file changed, 65 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
new file mode 100644
index 000..94c2474
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
@@ -0,0 +1,65 @@
+Amlogic Meson Power Controller
+==
+
+The Amlogic Meson SoCs embeds an internal Power domain controller.
+
+VPU Power Domain
+
+
+The Video Processing Unit power domain is controlled by this power controller,
+but the domain requires some external resources to meet the correct power
+sequences.
+The bindings must respect the power domain bindings as described in the file
+power_domain.txt
+
+Device Tree Bindings:
+-
+
+Required properties:
+- compatible: value should be different for each SoC family as :
+ - GXBB (S905) : "amlogic,meson-gxbb-vpu"
+ - GXL (S905X, S905D) : "amlogic,meson-gxl-vpu"
+ - GXM (S912) : "amlogic,meson-gxm-vpu"
+ followed by the common "amlogic,meson-gx-vpu"
+- #power-domain-cells: should be 0
+- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
+- resets: phandles to the reset lines needed for this power demain sequence
+ as described in ../reset/reset.txt
+- clocks: from common clock binding: handle to VPU and VAPB clocks
+- clock-names: from common clock binding: must contain "vpu", "vapb"
+ corresponding to entry in the clocks property.
+
+Parent node should have the following properties :
+- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
+- reg: base address and size of the AO system control register space.
+
+Example:
+---
+
+ao_sysctrl: sys-ctrl@0 {
+ compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
+ reg = <0x0 0x0 0x0 0x100>;
+
+ pwrc_vpu: power-controller-vpu {
+ compatible = "amlogic,meson-gx-pwrc-vpu";
+ #power-domain-cells = <0>;
+ amlogic,hhi-sysctrl = <&sysctrl>;
+ resets = <&reset RESET_VIU>,
+<&reset RESET_VENC>,
+<&reset RESET_VCBUS>,
+<&reset RESET_BT656>,
+<&reset RESET_DVIN_RESET>,
+<&reset RESET_RDMA>,
+<&reset RESET_VENCI>,
+<&reset RESET_VENCP>,
+<&reset RESET_VDAC>,
+<&reset RESET_VDI6>,
+<&reset RESET_VENCL>,
+<&reset RESET_VID_LOCK>;
+ clocks = <&clkc CLKID_VPU>,
+<&clkc CLKID_VAPB>;
+ clock-names = "vpu", "vapb";
+ };
+};
+
+
--
2.7.4
[PATCH 2/4] dt-bindings: display: amlogic,meson-dw-hdmi: Add optional HDMI 5V regulator
On reference boards and derivatives, the HDMI Logic is powered by an external 5V regulator. This regulator was set by the Vendor U-Boot, add optional support for it. Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt index 7f040ed..bf4a180 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt @@ -48,6 +48,10 @@ Required properties: Documentation/devicetree/bindings/reset/reset.txt, the reset-names should be "hdmitx_apb", "hdmitx", "hdmitx_phy" +Optional properties: +- hdmi-supply: Optional phandle to an external 5V regulator to power the HDMI + logic, as described in the file ../regulator/regulator.txt + Required nodes: The connections to the HDMI ports are modeled using the OF graph -- 2.7.4
[PATCH 0/4] drm/meson: power domain init related fixes
On the Amlogic Gx SoCs (GXBB, GXL & GXM), the VPU power domain is initialized by the vendor U-Boot code, but running mainline U-boot has been possible on these SoCs. But lacking such init made the system lock at kernel boot. A PM Power Domain driver has been pushed at [1] to solve the main issue. The following patches : - updates the DT bindings accordingly - adds support for missing regulators and registers init Neil Armstrong (4): dt-bindings: display: amlogic,meson-vpu: Add optional power domain property dt-bindings: display: amlogic,meson-dw-hdmi: Add optional HDMI 5V regulator drm/meson: dw_hdmi: Add support for an optional external 5V regulator drm/meson: Add missing VPU init .../devicetree/bindings/display/amlogic,meson-dw-hdmi.txt | 4 .../devicetree/bindings/display/amlogic,meson-vpu.txt | 4 drivers/gpu/drm/meson/meson_drv.c | 9 + drivers/gpu/drm/meson/meson_dw_hdmi.c | 13 + drivers/gpu/drm/meson/meson_registers.h | 4 5 files changed, 34 insertions(+) -- 2.7.4
[PATCH 1/4] dt-bindings: display: amlogic,meson-vpu: Add optional power domain property
The Video Processing Unit power domain was setup by the Vendor U-Boot, add support for an optional Power Domain phandle to setup it from the kernel. Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt index 00f74ba..057b813 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt +++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt @@ -64,6 +64,10 @@ Required properties: - reg-names: should contain the names of the previous memory regions - interrupts: should contain the VENC Vsync interrupt number +Optional properties: +- power-domains: Optional phandle to associated power domain as described in + the file ../power/power_domain.txt + Required nodes: The connections to the VPU output video ports are modeled using the OF graph -- 2.7.4
[PATCH 4/4] drm/meson: Add missing VPU init
The VPU init misses these configurations values.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_drv.c | 9 +
drivers/gpu/drm/meson/meson_registers.h | 4
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_drv.c
b/drivers/gpu/drm/meson/meson_drv.c
index 7742c7d..19a0d8d 100644
--- a/drivers/gpu/drm/meson/meson_drv.c
+++ b/drivers/gpu/drm/meson/meson_drv.c
@@ -150,6 +150,14 @@ static struct regmap_config meson_regmap_config = {
.max_register = 0x1000,
};
+static void meson_vpu_init(struct meson_drm *priv)
+{
+ writel_relaxed(0x21, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
+ writel_relaxed(0x1, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
+ writel_relaxed(0x90, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
+ writel_relaxed(0x2, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
+}
+
static int meson_drv_bind_master(struct device *dev, bool has_components)
{
struct platform_device *pdev = to_platform_device(dev);
@@ -221,6 +229,7 @@ static int meson_drv_bind_master(struct device *dev, bool
has_components)
/* Hardware Initialization */
+ meson_vpu_init(priv);
meson_venc_init(priv);
meson_vpp_init(priv);
meson_viu_init(priv);
diff --git a/drivers/gpu/drm/meson/meson_registers.h
b/drivers/gpu/drm/meson/meson_registers.h
index 2847381..bca8714 100644
--- a/drivers/gpu/drm/meson/meson_registers.h
+++ b/drivers/gpu/drm/meson/meson_registers.h
@@ -1363,6 +1363,10 @@
#define VPU_PROT3_STAT_1 0x277a
#define VPU_PROT3_STAT_2 0x277b
#define VPU_PROT3_REQ_ONOFF 0x277c
+#define VPU_RDARB_MODE_L1C1 0x2790
+#define VPU_RDARB_MODE_L1C2 0x2799
+#define VPU_RDARB_MODE_L2C1 0x279d
+#define VPU_WRARB_MODE_L2C1 0x27a2
/* osd super scale */
#define OSDSR_HV_SIZEIN 0x3130
--
2.7.4
[PATCH 3/4] drm/meson: dw_hdmi: Add support for an optional external 5V regulator
On reference boards and derivatives, the HDMI Logic is powered by an external
5V regulator.
This regulator was set by the Vendor U-Boot, add optional support for it.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_dw_hdmi.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c
b/drivers/gpu/drm/meson/meson_dw_hdmi.c
index cef4144..17de3af 100644
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
#include
#include
@@ -137,6 +138,7 @@ struct meson_dw_hdmi {
struct reset_control *hdmitx_phy;
struct clk *hdmi_pclk;
struct clk *venci_clk;
+ struct regulator *hdmi_supply;
u32 irq_stat;
};
#define encoder_to_meson_dw_hdmi(x) \
@@ -751,6 +753,17 @@ static int meson_dw_hdmi_bind(struct device *dev, struct
device *master,
dw_plat_data = &meson_dw_hdmi->dw_plat_data;
encoder = &meson_dw_hdmi->encoder;
+ meson_dw_hdmi->hdmi_supply = devm_regulator_get_optional(dev, "hdmi");
+ if (IS_ERR(meson_dw_hdmi->hdmi_supply)) {
+ if (PTR_ERR(meson_dw_hdmi->hdmi_supply) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+ meson_dw_hdmi->hdmi_supply = NULL;
+ } else {
+ ret = regulator_enable(meson_dw_hdmi->hdmi_supply);
+ if (ret)
+ return ret;
+ }
+
meson_dw_hdmi->hdmitx_apb = devm_reset_control_get_exclusive(dev,
"hdmitx_apb");
if (IS_ERR(meson_dw_hdmi->hdmitx_apb)) {
--
2.7.4
Re: [PATCH 2/2] dt-bindings: power: add amlogic meeson power domain bindings
On 17/10/2017 09:38, Neil Armstrong wrote:
> Signed-off-by: Neil Armstrong
> ---
> .../bindings/power/amlogic,meson-gx-pwrc.txt | 65
> ++
> 1 file changed, 65 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
>
> diff --git
> a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
> b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
> new file mode 100644
> index 000..94c2474
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
> @@ -0,0 +1,65 @@
> +Amlogic Meson Power Controller
> +==
> +
> +The Amlogic Meson SoCs embeds an internal Power domain controller.
> +
> +VPU Power Domain
> +
> +
> +The Video Processing Unit power domain is controlled by this power
> controller,
> +but the domain requires some external resources to meet the correct power
> +sequences.
> +The bindings must respect the power domain bindings as described in the file
> +power_domain.txt
> +
> +Device Tree Bindings:
> +-
> +
> +Required properties:
> +- compatible: value should be different for each SoC family as :
> + - GXBB (S905) : "amlogic,meson-gxbb-vpu"
> + - GXL (S905X, S905D) : "amlogic,meson-gxl-vpu"
> + - GXM (S912) : "amlogic,meson-gxm-vpu"
> + followed by the common "amlogic,meson-gx-vpu"
Oops, wrong compatibles, please ignore this patch, I'll repost it.
> +- #power-domain-cells: should be 0
> +- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
> +- resets: phandles to the reset lines needed for this power demain sequence
> + as described in ../reset/reset.txt
> +- clocks: from common clock binding: handle to VPU and VAPB clocks
> +- clock-names: from common clock binding: must contain "vpu", "vapb"
> + corresponding to entry in the clocks property.
> +
> +Parent node should have the following properties :
> +- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
> +- reg: base address and size of the AO system control register space.
> +
> +Example:
> +---
> +
> +ao_sysctrl: sys-ctrl@0 {
> + compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
> + reg = <0x0 0x0 0x0 0x100>;
> +
> + pwrc_vpu: power-controller-vpu {
> + compatible = "amlogic,meson-gx-pwrc-vpu";
> + #power-domain-cells = <0>;
> + amlogic,hhi-sysctrl = <&sysctrl>;
> + resets = <&reset RESET_VIU>,
> + <&reset RESET_VENC>,
> + <&reset RESET_VCBUS>,
> + <&reset RESET_BT656>,
> + <&reset RESET_DVIN_RESET>,
> + <&reset RESET_RDMA>,
> + <&reset RESET_VENCI>,
> + <&reset RESET_VENCP>,
> + <&reset RESET_VDAC>,
> + <&reset RESET_VDI6>,
> + <&reset RESET_VENCL>,
> + <&reset RESET_VID_LOCK>;
> + clocks = <&clkc CLKID_VPU>,
> + <&clkc CLKID_VAPB>;
> + clock-names = "vpu", "vapb";
> + };
> +};
> +
> +
>
[PATCH v2 1/2] soc: amlogic: add Meson GX VPU Domains driver
The Video Processing Unit needs a specific Power Domain powering scheme
this driver handles this as a PM Power Domain driver.
Signed-off-by: Neil Armstrong
---
drivers/soc/amlogic/Kconfig | 10 ++
drivers/soc/amlogic/Makefile| 1 +
drivers/soc/amlogic/meson-gx-pwrc-vpu.c | 234
3 files changed, 245 insertions(+)
create mode 100644 drivers/soc/amlogic/meson-gx-pwrc-vpu.c
diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
index ef0b8f6..1621bb2 100644
--- a/drivers/soc/amlogic/Kconfig
+++ b/drivers/soc/amlogic/Kconfig
@@ -9,6 +9,16 @@ config MESON_GX_SOCINFO
Say yes to support decoding of Amlogic Meson GX SoC family
information about the type, package and version.
+config MESON_GX_PM_DOMAINS
+ bool "Amlogic Meson GX Power Domains driver"
+ depends on ARCH_MESON || COMPILE_TEST
+ default ARCH_MESON
+ select PM_GENERIC_DOMAINS
+ select PM_GENERIC_DOMAINS_OF
+ help
+ Say yes to expose Amlogic Meson GX Power Domains as
+ Generic Power Domains.
+
config MESON_MX_SOCINFO
bool "Amlogic Meson MX SoC Information driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile
index 1f5df50..8fa3218 100644
--- a/drivers/soc/amlogic/Makefile
+++ b/drivers/soc/amlogic/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
+obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o
diff --git a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
new file mode 100644
index 000..bf5190b
--- /dev/null
+++ b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ * Author: Neil Armstrong
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* AO Offsets */
+
+#define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
+
+#define GEN_PWR_VPU_HDMI BIT(8)
+#define GEN_PWR_VPU_HDMI_ISO BIT(9)
+
+/* HHI Offsets */
+
+#define HHI_MEM_PD_REG0(0x40 << 2)
+#define HHI_VPU_MEM_PD_REG0(0x41 << 2)
+#define HHI_VPU_MEM_PD_REG1(0x42 << 2)
+
+struct meson_gx_pwrc_vpu {
+ struct generic_pm_domain genpd;
+ struct regmap *regmap_ao;
+ struct regmap *regmap_hhi;
+ struct reset_control *rstc;
+ struct clk *vpu_clk;
+ struct clk *vapb_clk;
+ bool powered;
+};
+
+static inline
+struct meson_gx_pwrc_vpu *genpd_to_pd(struct generic_pm_domain *d)
+{
+ return container_of(d, struct meson_gx_pwrc_vpu, genpd);
+}
+
+static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
+{
+ struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
+ int i;
+
+ regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
+ GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
+ udelay(20);
+
+ /* Power Down Memories */
+ for (i = 0; i < 32; i += 2) {
+ regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
+ 0x2 << i, 0x3 << i);
+ udelay(5);
+ }
+ for (i = 0; i < 32; i += 2) {
+ regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
+ 0x2 << i, 0x3 << i);
+ udelay(5);
+ }
+ for (i = 8; i < 16; i++) {
+ regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
+ BIT(i), BIT(i));
+ udelay(5);
+ }
+ udelay(20);
+
+ regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
+ GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
+
+ msleep(20);
+
+ clk_disable_unprepare(pd->vpu_clk);
+ clk_disable_unprepare(pd->vapb_clk);
+
+ pd->powered = false;
+
+ return 0;
+}
+
+static int meson_gx_pwrc_vpu_setup_clk(struct meson_gx_pwrc_vpu *pd)
+{
+ int ret;
+
+ ret = clk_prepare_enable(pd->vpu_clk);
+ if (ret)
+ return ret;
+
+ return clk_prepare_enable(pd->vapb_clk);
+}
+
+static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
+{
+ struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
+ int ret;
+ int i;
+
+ regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
+ GEN_PWR_VPU_HDMI, 0);
+ udelay(20);
+
+ /* Power Up Memories */
+ for (i = 0; i < 32; i += 2) {
+ regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
+ 0x2 << i, 0);
+ udelay(5);
+ }
+
+ for (i = 0; i < 32; i +
[PATCH v2 0/2] soc: amlogic: add support for Meson GX VPU Domains
On the Amlogic Gx SoCs (GXBB, GXL & GXM), the VPU power domain is initialized by the vendor U-Boot code, but running mainline U-boot has been possible on these SoCs. But lacking such init made the system lock at kernel boot. This patchset adds the Video Processing Unit power domain driver to enable the same power-on and power-down sequences and was designed to allow booting with the power domain already initialized or not. This driver has been tested on : - Odroid-C2 (GXBB) with Vendor and Mainline U-Boot - P212 (GXL) with Vendor and Mainline U-Boot - Khadas Vim (GXL) with Vendor U-Boot - Khadas Vim2 with (GXM) Vendor U-Boot Changes since v1: - fixed bindings compatible string Neil Armstrong (2): soc: amlogic: add Meson GX VPU Domains driver dt-bindings: power: add amlogic meson power domain bindings .../bindings/power/amlogic,meson-gx-pwrc.txt | 61 ++ drivers/soc/amlogic/Kconfig| 10 + drivers/soc/amlogic/Makefile | 1 + drivers/soc/amlogic/meson-gx-pwrc-vpu.c| 234 + 4 files changed, 306 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt create mode 100644 drivers/soc/amlogic/meson-gx-pwrc-vpu.c -- 2.7.4
[PATCH v2 2/2] dt-bindings: power: add amlogic meson power domain bindings
Signed-off-by: Neil Armstrong
---
.../bindings/power/amlogic,meson-gx-pwrc.txt | 61 ++
1 file changed, 61 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
new file mode 100644
index 000..95ec49a
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
@@ -0,0 +1,61 @@
+Amlogic Meson Power Controller
+==
+
+The Amlogic Meson SoCs embeds an internal Power domain controller.
+
+VPU Power Domain
+
+
+The Video Processing Unit power domain is controlled by this power controller,
+but the domain requires some external resources to meet the correct power
+sequences.
+The bindings must respect the power domain bindings as described in the file
+power_domain.txt
+
+Device Tree Bindings:
+-
+
+Required properties:
+- compatible: should be "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
+- #power-domain-cells: should be 0
+- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
+- resets: phandles to the reset lines needed for this power demain sequence
+ as described in ../reset/reset.txt
+- clocks: from common clock binding: handle to VPU and VAPB clocks
+- clock-names: from common clock binding: must contain "vpu", "vapb"
+ corresponding to entry in the clocks property.
+
+Parent node should have the following properties :
+- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
+- reg: base address and size of the AO system control register space.
+
+Example:
+---
+
+ao_sysctrl: sys-ctrl@0 {
+ compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
+ reg = <0x0 0x0 0x0 0x100>;
+
+ pwrc_vpu: power-controller-vpu {
+ compatible = "amlogic,meson-gx-pwrc-vpu";
+ #power-domain-cells = <0>;
+ amlogic,hhi-sysctrl = <&sysctrl>;
+ resets = <&reset RESET_VIU>,
+<&reset RESET_VENC>,
+<&reset RESET_VCBUS>,
+<&reset RESET_BT656>,
+<&reset RESET_DVIN_RESET>,
+<&reset RESET_RDMA>,
+<&reset RESET_VENCI>,
+<&reset RESET_VENCP>,
+<&reset RESET_VDAC>,
+<&reset RESET_VDI6>,
+<&reset RESET_VENCL>,
+<&reset RESET_VID_LOCK>;
+ clocks = <&clkc CLKID_VPU>,
+<&clkc CLKID_VAPB>;
+ clock-names = "vpu", "vapb";
+ };
+};
+
+
--
2.7.4
[PATCH 4/4] ARM64: dts: odroid-c2: Add HDMI and CEC Nodes
Now the VPU Power Domain has been fixed while boothing from Mainline U-Boot,
VPU and HDMI nodes can finally be added to the Odroid-C2 DTS.
Signed-off-by: Neil Armstrong
---
.../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index 1deaa53..ccf5640 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -135,6 +135,24 @@
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+};
+
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
};
ðmac {
@@ -177,6 +195,18 @@
};
};
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
&i2c_A {
status = "okay";
pinctrl-0 = <&i2c_a_pins>;
--
2.7.4
[PATCH 1/4] ARM64: dts: meson-gx: add VPU power domain
This patch adds support for the VPU Power Domain nodes, and attaches the
VPU power domain to the VPU node.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 11
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 43 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 43 +
3 files changed, 97 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index f175db8..80a0f2b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -371,6 +371,12 @@
compatible = "amlogic,meson-gx-ao-sysctrl",
"syscon", "simple-mfd";
reg = <0x0 0x0 0x0 0x100>;
+ pwrc_vpu: power-controller-vpu {
+ compatible =
"amlogic,meson-gx-pwrc-vpu";
+ #power-domain-cells = <0>;
+ amlogic,hhi-sysctrl = <&sysctrl>;
+ };
+
clkc_AO: clock-controller {
compatible = "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
@@ -448,6 +454,11 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
+ sysctrl: system-controller@0 {
+ compatible = "amlogic,meson-gx-hhi-sysctrl",
"syscon", "simple-mfd";
+ reg = <0 0 0 0x400>;
+ };
+
mailbox: mailbox@404 {
compatible = "amlogic,meson-gx-mhu",
"amlogic,meson-gxbb-mhu";
reg = <0 0x404 0 0x4c>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 3d41db9..512f3dd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -688,6 +688,48 @@
};
};
+&pwrc_vpu {
+ resets = <&reset RESET_VIU>,
+<&reset RESET_VENC>,
+<&reset RESET_VCBUS>,
+<&reset RESET_BT656>,
+<&reset RESET_DVIN_RESET>,
+<&reset RESET_RDMA>,
+<&reset RESET_VENCI>,
+<&reset RESET_VENCP>,
+<&reset RESET_VDAC>,
+<&reset RESET_VDI6>,
+<&reset RESET_VENCL>,
+<&reset RESET_VID_LOCK>;
+ clocks = <&clkc CLKID_VPU>,
+<&clkc CLKID_VAPB>;
+ clock-names = "vpu", "vapb";
+ /*
+* VPU clocking is provided by two identical clock paths
+* VPU_0 and VPU_1 muxed to a single clock by a glitch
+* free mux to safely change frequency while running.
+* Same for VAPB but with a final gate after the glitch free mux.
+*/
+ assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
+ <&clkc CLKID_VPU_0>,
+ <&clkc CLKID_VPU>, /* Glitch free mux */
+ <&clkc CLKID_VAPB_0_SEL>,
+ <&clkc CLKID_VAPB_0>,
+ <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+<0>, /* Do Nothing */
+<&clkc CLKID_VPU_0>,
+<&clkc CLKID_FCLK_DIV4>,
+<0>, /* Do Nothing */
+<&clkc CLKID_VAPB_0>;
+ assigned-clock-rates = <0>, /* Do Nothing */
+ <6>,
+ <0>, /* Do Nothing */
+ <0>, /* Do Nothing */
+ <25000>,
+ <0>; /* Do Nothing */
+};
+
&saradc {
compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
clocks = <&xtal>,
@@ -757,4 +799,5 @@
&vpu {
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
+ power-domains = <&pwrc_vpu>;
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index 19c001a..68f6564 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx
[PATCH 0/4] ARM64: dts: meson-gx: fix VPU init for non-vendor u-boot
On the Amlogic Gx SoCs (GXBB, GXL & GXM), the VPU power domain is initialized by the vendor U-Boot code, but running mainline U-boot has been possible on these SoCs. But lacking such init made the system lock at kernel boot. A PM Power Domain driver has been pushed at [1] to solve the main issue. This patchset depends on the the following patchsets : - [1] soc: amlogic: add support for Meson GX VPU Domains - [2] reset: meson: add level reset support for GX SoC family - [3] clk: meson: gxbb: Add VPU and VAPB clocks - [4] drm/meson: power domain init related fixes [1] https://lkml.kernel.org/r/1508228167-11753-1-git-send-email-narmstr...@baylibre.com [2] https://lkml.kernel.org/r/1508167573-17396-1-git-send-email-narmstr...@baylibre.com [3] https://lkml.kernel.org/r/1508168085-19032-1-git-send-email-narmstr...@baylibre.com [4] https://lkml.kernel.org/r/1508227664-11171-1-git-send-email-narmstr...@baylibre.com Neil Armstrong (4): ARM64: dts: meson-gx: add VPU power domain ARM64: dts: meson-gx: Add HDMI_5V regulator on selected boards ARM64: dts: meson-gx: grow reset controller memory zone ARM64: dts: odroid-c2: Add HDMI and CEC Nodes .../arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 12 ++ arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 13 ++- .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 30 +++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi| 43 ++ .../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 1 + .../dts/amlogic/meson-gxl-s905x-khadas-vim.dts | 1 + .../dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 12 ++ .../boot/dts/amlogic/meson-gxl-s905x-p212.dts | 1 + .../boot/dts/amlogic/meson-gxl-s905x-p212.dtsi | 11 ++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 43 ++ .../boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 12 ++ 11 files changed, 178 insertions(+), 1 deletion(-) -- 2.7.4
[PATCH 3/4] ARM64: dts: meson-gx: grow reset controller memory zone
Now the Amlogic Meson GX SoCs datasheet documents all the Reset registers,
grow the memory in the node to allow usage of the level registers.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 80a0f2b..9b19656 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -220,7 +220,7 @@
reset: reset-controller@4404 {
compatible = "amlogic,meson-gx-reset",
"amlogic,meson-gxbb-reset";
- reg = <0x0 0x04404 0x0 0x20>;
+ reg = <0x0 0x04404 0x0 0x9c>;
#reset-cells = <1>;
};
--
2.7.4
[PATCH 2/4] ARM64: dts: meson-gx: Add HDMI_5V regulator on selected boards
On reference boards and derivatives, the HDMI Logic is powered by an external
5V regulator.
This regulator was set by the Vendor U-Boot, add the regulator and phandle
property to the HDMI node.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 12
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 1 +
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts | 1 +
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 12
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts | 1 +
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi| 11 +++
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts| 12
7 files changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
index 7d4b95e..aa23185 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
@@ -59,6 +59,17 @@
reg = <0x0 0x0 0x0 0x8000>;
};
+ hdmi_5v: regulator-hdmi-5v {
+ compatible = "regulator-fixed";
+
+ regulator-name = "HDMI_5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+
+ gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
@@ -142,6 +153,7 @@
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
+ hdmi-supply = <&hdmi_5v>;
};
&hdmi_tx_tmds_port {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
index 6827f23..8bc540e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
@@ -135,6 +135,7 @@
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
+ hdmi-supply = <&hdmi_5v>;
};
&hdmi_tx_tmds_port {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
index 71a6e1c..d0f22aa 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
@@ -78,6 +78,7 @@
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
+ hdmi-supply = <&hdmi_5v>;
};
&hdmi_tx_tmds_port {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
index dc9c3b8..e6ba66c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
@@ -72,6 +72,17 @@
reg = <0x0 0x0 0x0 0x8000>;
};
+ hdmi_5v: regulator-hdmi-5v {
+ compatible = "regulator-fixed";
+
+ regulator-name = "HDMI_5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+
+ gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
@@ -143,6 +154,7 @@
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
+ hdmi-supply = <&hdmi_5v>;
};
&hdmi_tx_tmds_port {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
index 6e2bf85..4f6b1c9 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
@@ -88,6 +88,7 @@
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
+ hdmi-supply = <&hdmi_5v>;
};
&hdmi_tx_tmds_port {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
index ff09df1..a401126 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
@@ -
Re: [PATCH 0/4] drm/meson: power domain init related fixes
On 17/10/2017 11:06, Linus Lüssing wrote: > On Tue, Oct 17, 2017 at 10:07:40AM +0200, Neil Armstrong wrote: >> A PM Power Domain driver has been pushed at [1] to solve the main issue. > > URL to [1] missing? > Sorry, here it is : [1] https://lkml.kernel.org/r/1508228167-11753-1-git-send-email-narmstr...@baylibre.com
Re: [PATCH] reset: meson: add level reset support for GX SoC family
On 17/10/2017 12:08, Philipp Zabel wrote:
> Hi Neil,
>
> On Mon, 2017-10-16 at 17:26 +0200, Neil Armstrong wrote:
>> The Amlogic GX SoC family embeds alternate registers to drive the reset
>> levels next to the pulse registers.
>>
>> This patch adds support for level reset handling on the GX family only.
>>
>> The Meson8 family has an alternate way to handle level reset.
>>
>> Signed-off-by: Neil Armstrong
>
> thank you for the patch, comments below:
>
>> ---
>> drivers/reset/reset-meson.c | 57
>> +
>> 1 file changed, 53 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
>> index a8b915e..d55e440 100644
>> --- a/drivers/reset/reset-meson.c
>> +++ b/drivers/reset/reset-meson.c
>> @@ -62,9 +62,11 @@
>> #include
>> #include
>> #include
>> +#include
>>
>> #define REG_COUNT 8
>> #define BITS_PER_REG32
>> +#define LEVEL_OFFSET0x7c
>>
>> struct meson_reset {
>> void __iomem *reg_base;
>> @@ -88,18 +90,61 @@ static int meson_reset_reset(struct reset_controller_dev
>> *rcdev,
>> return 0;
>> }
>>
>> -static const struct reset_control_ops meson_reset_ops = {
>> +static int meson_reset_level(struct reset_controller_dev *rcdev,
>> +unsigned long id, bool assert)
>> +{
>> +struct meson_reset *data =
>> +container_of(rcdev, struct meson_reset, rcdev);
>> +unsigned int bank = id / BITS_PER_REG;
>> +unsigned int offset = id % BITS_PER_REG;
>> +void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2);
>> +u32 reg;
>> +
>> +if (bank >= REG_COUNT)
>> +return -EINVAL;
>
> This check is not necessary. The same check is in meson_reset_reset,
> which I didn't notice last time.
>
> of_reset_simple_xlate, the default rcdev->of_xlate implementation,
> already guarantees id < rcdev->nr_resets. And since nr_resets is set to
> REG_COUNT * BITS_PER_REG, we know that id < REG_COUNT * BITS_PER_REG and
> thus bank <= id / BITS_PER_REG < REG_COUNT.
Ok will remove.
>
>> +reg = readl(reg_addr);
>> +if (assert)
>> +writel(reg & ~BIT(offset), reg_addr);
>> +else
>> +writel(reg | BIT(offset), reg_addr);
>
> These read-modify-write operations must be protected by a spinlock.
Ok will add
>
>> +
>> +return 0;
>> +}
>> +
>> +static int meson_reset_assert(struct reset_controller_dev *rcdev,
>> + unsigned long id)
>> +{
>> +return meson_reset_level(rcdev, id, true);
>> +}
>> +
>> +static int meson_reset_deassert(struct reset_controller_dev *rcdev,
>> +unsigned long id)
>> +{
>> +return meson_reset_level(rcdev, id, false);
>> +}
>> +
>> +static const struct reset_control_ops meson_reset_meson8_ops = {
>> +.reset = meson_reset_reset,
>> +};
>> +
>> +static const struct reset_control_ops meson_reset_gx_ops = {
>> .reset = meson_reset_reset,
>> +.assert = meson_reset_assert,
>> +.deassert = meson_reset_deassert,
>> };
>>
>> static const struct of_device_id meson_reset_dt_ids[] = {
>> - { .compatible = "amlogic,meson8b-reset", },
>> - { .compatible = "amlogic,meson-gxbb-reset", },
>> + { .compatible = "amlogic,meson8b-reset",
>> + .data = (void *) &meson_reset_meson8_ops, },
>> + { .compatible = "amlogic,meson-gxbb-reset",
>> + .data = (void *) &meson_reset_gx_ops, },
>> { /* sentinel */ },
>> };
>
> of_device_id.data ist const void *, so there is no need to cast here.
Ok will remove then
>
>> static int meson_reset_probe(struct platform_device *pdev)
>> {
>> +const struct reset_control_ops *ops;
>> struct meson_reset *data;
>> struct resource *res;
>>
>> @@ -107,6 +152,10 @@ static int meson_reset_probe(struct platform_device
>> *pdev)
>> if (!data)
>> return -ENOMEM;
>>
>> +ops = of_device_get_match_data(&pdev->dev);
>> +if (!ops)
>> +return -EINVAL;
>> +
>> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> data->reg_base = devm_ioremap_resource(&pdev->dev, res);
>> if (IS_ERR(data->reg_base))
>> @@ -116,7 +165,7 @@ static int meson_reset_probe(struct platform_device
>> *pdev)
>>
>> data->rcdev.owner = THIS_MODULE;
>> data->rcdev.nr_resets = REG_COUNT * BITS_PER_REG;
>> -data->rcdev.ops = &meson_reset_ops;
>> +data->rcdev.ops = ops;
>> data->rcdev.of_node = pdev->dev.of_node;
>>
>> return devm_reset_controller_register(&pdev->dev, &data->rcdev);
>
> regards
> Philipp
>
Thanks,
Neil
[PATCH v2] reset: meson: add level reset support for GX SoC family
The Amlogic GX SoC family embeds alternate registers to drive the reset
levels next to the pulse registers.
This patch adds support for level reset handling on the GX family only.
The Meson8 family has an alternate way to handle level reset.
Signed-off-by: Neil Armstrong
---
drivers/reset/reset-meson.c | 62 ++---
1 file changed, 58 insertions(+), 4 deletions(-)
Changes since v1:
- protected read/change/modify with a spinlock
- removed unnedded check
- remove useless type conversion
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index a8b915e..f3b9d69 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -62,13 +62,16 @@
#include
#include
#include
+#include
#define REG_COUNT 8
#define BITS_PER_REG 32
+#define LEVEL_OFFSET 0x7c
struct meson_reset {
void __iomem *reg_base;
struct reset_controller_dev rcdev;
+ spinlock_t lock;
};
static int meson_reset_reset(struct reset_controller_dev *rcdev,
@@ -88,18 +91,63 @@ static int meson_reset_reset(struct reset_controller_dev
*rcdev,
return 0;
}
-static const struct reset_control_ops meson_reset_ops = {
+static int meson_reset_level(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct meson_reset *data =
+ container_of(rcdev, struct meson_reset, rcdev);
+ unsigned int bank = id / BITS_PER_REG;
+ unsigned int offset = id % BITS_PER_REG;
+ void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&data->lock, flags);
+
+ reg = readl(reg_addr);
+ if (assert)
+ writel(reg & ~BIT(offset), reg_addr);
+ else
+ writel(reg | BIT(offset), reg_addr);
+
+ spin_unlock_irqrestore(&data->lock, flags);
+
+ return 0;
+}
+
+static int meson_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return meson_reset_level(rcdev, id, true);
+}
+
+static int meson_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return meson_reset_level(rcdev, id, false);
+}
+
+static const struct reset_control_ops meson_reset_meson8_ops = {
.reset = meson_reset_reset,
};
+static const struct reset_control_ops meson_reset_gx_ops = {
+ .reset = meson_reset_reset,
+ .assert = meson_reset_assert,
+ .deassert = meson_reset_deassert,
+};
+
static const struct of_device_id meson_reset_dt_ids[] = {
-{ .compatible = "amlogic,meson8b-reset", },
-{ .compatible = "amlogic,meson-gxbb-reset", },
+{ .compatible = "amlogic,meson8b-reset",
+ .data = &meson_reset_meson8_ops, },
+{ .compatible = "amlogic,meson-gxbb-reset",
+ .data = &meson_reset_gx_ops, },
{ /* sentinel */ },
};
static int meson_reset_probe(struct platform_device *pdev)
{
+ const struct reset_control_ops *ops;
struct meson_reset *data;
struct resource *res;
@@ -107,6 +155,10 @@ static int meson_reset_probe(struct platform_device *pdev)
if (!data)
return -ENOMEM;
+ ops = of_device_get_match_data(&pdev->dev);
+ if (!ops)
+ return -EINVAL;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
data->reg_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(data->reg_base))
@@ -114,9 +166,11 @@ static int meson_reset_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, data);
+ spin_lock_init(&data->lock);
+
data->rcdev.owner = THIS_MODULE;
data->rcdev.nr_resets = REG_COUNT * BITS_PER_REG;
- data->rcdev.ops = &meson_reset_ops;
+ data->rcdev.ops = ops;
data->rcdev.of_node = pdev->dev.of_node;
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
--
2.7.4
[PATCH] reset: meson: remove unneeded check in meson_reset_reset
The if (bank >= REG_COUNT) is not need since already checked by the default rcdev->of_xlate implementation which guarantees that id < rcdev->nr_resets. Suggested-by: Philipp Zabel Signed-off-by: Neil Armstrong --- drivers/reset/reset-meson.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index f3b9d69..c419a37 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -83,9 +83,6 @@ static int meson_reset_reset(struct reset_controller_dev *rcdev, unsigned int offset = id % BITS_PER_REG; void __iomem *reg_addr = data->reg_base + (bank << 2); - if (bank >= REG_COUNT) - return -EINVAL; - writel(BIT(offset), reg_addr); return 0; -- 2.7.4
Re: [PATCH 3/4] ARM64: dts: meson-gx: grow reset controller memory zone
On 17/10/2017 10:29, Neil Armstrong wrote:
> Now the Amlogic Meson GX SoCs datasheet documents all the Reset registers,
> grow the memory in the node to allow usage of the level registers.
>
> Signed-off-by: Neil Armstrong
> ---
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> index 80a0f2b..9b19656 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> @@ -220,7 +220,7 @@
>
> reset: reset-controller@4404 {
> compatible = "amlogic,meson-gx-reset",
> "amlogic,meson-gxbb-reset";
> - reg = <0x0 0x04404 0x0 0x20>;
> + reg = <0x0 0x04404 0x0 0x9c>;
> #reset-cells = <1>;
> };
>
>
Kevin,
This one can be applied now since Philipp took my reset patch.
Neil
Re: [PATCH] mtd: spi-nor: Add support for Winbond w25q16dw
On 28/08/2017 15:11, Neil Armstrong wrote:
> Add JEDEC entry for the Winbond w25q16fw/w25q16dw with similar
> flags and format than the Winbond w25q32dw entry.
>
> Tested on a Khadas VIM2 SBC board with an Amlogic S912 SoC.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/mtd/spi-nor/spi-nor.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index cf1d4a1..2f74583 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1137,6 +1137,11 @@ static int spi_nor_is_locked(struct mtd_info *mtd,
> loff_t ofs, uint64_t len)
> { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
> { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
> { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
> + {
> + "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> + },
> { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
> { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
> { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
>
Hi Cyrille,
Did you had time to review this patch ?
Thanks,
Neil
[PATCH] ARM64: dts: meson-gx: Add SPICC nodes
Add nodes for the SPICC controller on GX common dtsi, GXBB and
GXL dtsi files.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 9 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 7 +++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 7 +++
3 files changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 436b875..613719d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -304,6 +304,15 @@
status = "disabled";
};
+ spicc: spi@8d80 {
+ compatible = "amlogic,meson-gx-spicc";
+ reg = <0x0 0x08d80 0x0 0x80>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
spifc: spi@8c80 {
compatible = "amlogic,meson-gx-spifc",
"amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 95a5d57..1734974 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -657,6 +657,13 @@
clock-names = "core", "clkin0", "clkin1";
};
+&spicc {
+ clocks = <&clkc CLKID_SPICC>;
+ clock-names = "core";
+ resets = <&reset RESET_PERIPHS_SPICC>;
+ num-cs = <1>;
+};
+
&spifc {
clocks = <&clkc CLKID_SPI>;
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index 42d78f0..567dde4 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -584,6 +584,13 @@
clock-names = "core", "clkin0", "clkin1";
};
+&spicc {
+ clocks = <&clkc CLKID_SPICC>;
+ clock-names = "core";
+ resets = <&reset RESET_PERIPHS_SPICC>;
+ num-cs = <1>;
+};
+
&spifc {
clocks = <&clkc CLKID_SPI>;
};
--
1.9.1
Re: [PATCH 5/5] pinctrl: meson-gxl: Add Ethernet PHY LEDS pins
On 05/29/2017 11:01 AM, Linus Walleij wrote: > On Wed, May 24, 2017 at 10:20 AM, Neil Armstrong > wrote: > >> The Amlogic Meson GXL SoCs embeds an 10/100 Ethernet PHY, this patchs enables >> the Link and Activity LEDs signals. >> >> Signed-off-by: Neil Armstrong > > Patch applied with Jerome's review tag. > > Yours, > Linus Walleij > Thanks Linus ! Neil
Re: [PATCH v5 07/10] drm/bridge/synopsys: dw-hdmi: Use bridge->mode_valid() callback
On 05/25/2017 04:19 PM, Jose Abreu wrote:
> Now that we have a callback to check if bridge supports a given mode
> we can use it in Synopsys Designware HDMI bridge so that we restrict
> the number of probbed modes to the ones we can actually display.
>
> Also, there is no need to use mode_fixup() callback as mode_valid()
> will handle the mode validation.
>
> NOTE: Only compile tested
> NOTE 2: I also had to change the pdata declaration of mode_valid
> custom callback so that the passed modes are const. I also changed
> in the platforms I found. Not even compiled it though.
>
> Signed-off-by: Jose Abreu
> Acked-by: Neil Armstrong
> Cc: Carlos Palminha
> Cc: Daniel Vetter
> Cc: Archit Taneja
> Cc: Andrzej Hajda
> Cc: Laurent Pinchart
> Cc: David Airlie
> Cc: Philipp Zabel
> Cc: Carlo Caione
> Cc: Kevin Hilman
> Cc: Mark Yao
> Cc: Heiko Stuebner
> ---
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 40
> +
> drivers/gpu/drm/imx/dw_hdmi-imx.c | 4 +--
> drivers/gpu/drm/meson/meson_dw_hdmi.c | 2 +-
> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +-
> include/drm/bridge/dw_hdmi.h| 2 +-
> 5 files changed, 17 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> index 8737de8..038dc43 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -1907,24 +1907,6 @@ static int dw_hdmi_connector_get_modes(struct
> drm_connector *connector)
> return ret;
> }
>
> -static enum drm_mode_status
> -dw_hdmi_connector_mode_valid(struct drm_connector *connector,
> - struct drm_display_mode *mode)
> -{
> - struct dw_hdmi *hdmi = container_of(connector,
> -struct dw_hdmi, connector);
> - enum drm_mode_status mode_status = MODE_OK;
> -
> - /* We don't support double-clocked modes */
> - if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> - return MODE_BAD;
> -
> - if (hdmi->plat_data->mode_valid)
> - mode_status = hdmi->plat_data->mode_valid(connector, mode);
> -
> - return mode_status;
> -}
> -
> static void dw_hdmi_connector_force(struct drm_connector *connector)
> {
> struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
> @@ -1950,7 +1932,6 @@ static void dw_hdmi_connector_force(struct
> drm_connector *connector)
>
> static const struct drm_connector_helper_funcs
> dw_hdmi_connector_helper_funcs = {
> .get_modes = dw_hdmi_connector_get_modes,
> - .mode_valid = dw_hdmi_connector_mode_valid,
> .best_encoder = drm_atomic_helper_best_encoder,
> };
>
> @@ -1973,18 +1954,21 @@ static int dw_hdmi_bridge_attach(struct drm_bridge
> *bridge)
> return 0;
> }
>
> -static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
> - const struct drm_display_mode *orig_mode,
> - struct drm_display_mode *mode)
> +static enum drm_mode_status dw_hdmi_bridge_mode_valid(struct drm_bridge
> *bridge,
> + const struct
> drm_display_mode *mode)
> {
> struct dw_hdmi *hdmi = bridge->driver_private;
> struct drm_connector *connector = &hdmi->connector;
> - enum drm_mode_status status;
> + enum drm_mode_status mode_status = MODE_OK;
>
> - status = dw_hdmi_connector_mode_valid(connector, mode);
> - if (status != MODE_OK)
> - return false;
> - return true;
> + /* We don't support double-clocked modes */
> + if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> + return MODE_BAD;
> +
> + if (hdmi->plat_data->mode_valid)
> + mode_status = hdmi->plat_data->mode_valid(connector, mode);
> +
> + return mode_status;
> }
>
> static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
> @@ -2028,7 +2012,7 @@ static void dw_hdmi_bridge_enable(struct drm_bridge
> *bridge)
> .enable = dw_hdmi_bridge_enable,
> .disable = dw_hdmi_bridge_disable,
> .mode_set = dw_hdmi_bridge_mode_set,
> - .mode_fixup = dw_hdmi_bridge_mode_fixup,
> + .mode_valid = dw_hdmi_bridge_mode_valid,
> };
>
> static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
> diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c
> b/drivers/gpu/drm/imx/dw_hdmi-imx.c
> index f039641..5f561c8 100644
> --- a/drivers/gpu/drm/imx/dw_hdmi-imx.c
> +++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c
[PATCH] drm/meson: Fix driver bind when only CVBS is available
While introducing HDMI support, component matching on connectors node
were bypassed since no driver would actually bind on the DT node.
But when only a CVBS connector is present, only a single node is found
in the graph, but ignored and a NULL match table is given to the
component code.
This code permits bypassing the components framework by binding directly
the DRM driver when no components needs to be loaded.
Fixes: a41e82e6c457 ("drm/meson: Add support for components")
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_drv.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_drv.c
b/drivers/gpu/drm/meson/meson_drv.c
index 75382f5..10b227d 100644
--- a/drivers/gpu/drm/meson/meson_drv.c
+++ b/drivers/gpu/drm/meson/meson_drv.c
@@ -152,7 +152,7 @@ static bool meson_vpu_has_available_connectors(struct
device *dev)
.max_register = 0x1000,
};
-static int meson_drv_bind(struct device *dev)
+static int meson_drv_bind_master(struct device *dev, bool has_components)
{
struct platform_device *pdev = to_platform_device(dev);
struct meson_drm *priv;
@@ -233,10 +233,12 @@ static int meson_drv_bind(struct device *dev)
if (ret)
goto free_drm;
- ret = component_bind_all(drm->dev, drm);
- if (ret) {
- dev_err(drm->dev, "Couldn't bind all components\n");
- goto free_drm;
+ if (has_components) {
+ ret = component_bind_all(drm->dev, drm);
+ if (ret) {
+ dev_err(drm->dev, "Couldn't bind all components\n");
+ goto free_drm;
+ }
}
ret = meson_plane_create(priv);
@@ -276,6 +278,11 @@ static int meson_drv_bind(struct device *dev)
return ret;
}
+static int meson_drv_bind(struct device *dev)
+{
+ return meson_drv_bind_master(dev, true);
+}
+
static void meson_drv_unbind(struct device *dev)
{
struct drm_device *drm = dev_get_drvdata(dev);
@@ -357,6 +364,9 @@ static int meson_drv_probe(struct platform_device *pdev)
count += meson_probe_remote(pdev, &match, np, remote);
}
+ if (count && !match)
+ return meson_drv_bind_master(&pdev->dev, false);
+
/* If some endpoints were found, initialize the nodes */
if (count) {
dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count);
--
1.9.1
Re: [PATCH v5 01/10] drm: Add drm_{crtc/encoder/connector}_mode_valid()
On 05/25/2017 04:19 PM, Jose Abreu wrote:
> Add a new helper to call crtc->mode_valid, connector->mode_valid
> and encoder->mode_valid callbacks.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Jose Abreu
> Reviewed-by: Daniel Vetter
> Reviewed-by: Andrzej Hajda
> Cc: Carlos Palminha
> Cc: Dave Airlie
>
> Changes v2->v3:
> - Move helpers to drm_probe_helper.c (Daniel)
> - Squeeze patches that introduce helpers into a single
> one (Daniel)
>
> Signed-off-by: Jose Abreu
> ---
> drivers/gpu/drm/drm_crtc_helper_internal.h | 13 ++
> drivers/gpu/drm/drm_probe_helper.c | 38
> ++
> 2 files changed, 51 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_crtc_helper_internal.h
> b/drivers/gpu/drm/drm_crtc_helper_internal.h
> index 28295e5..97dfe20 100644
> --- a/drivers/gpu/drm/drm_crtc_helper_internal.h
> +++ b/drivers/gpu/drm/drm_crtc_helper_internal.h
> @@ -26,7 +26,11 @@
> * implementation details and are not exported to drivers.
> */
>
> +#include
> +#include
> #include
> +#include
> +#include
>
> /* drm_fb_helper.c */
> #ifdef CONFIG_DRM_FBDEV_EMULATION
> @@ -62,4 +66,13 @@ static inline int drm_dp_aux_register_devnode(struct
> drm_dp_aux *aux)
> static inline void drm_dp_aux_unregister_devnode(struct drm_dp_aux *aux)
> {
> }
> +
> +/* drm_probe_helper.c */
> +enum drm_mode_status drm_crtc_mode_valid(struct drm_crtc *crtc,
> + const struct drm_display_mode *mode);
> +enum drm_mode_status drm_encoder_mode_valid(struct drm_encoder *encoder,
> + const struct drm_display_mode
> *mode);
> +enum drm_mode_status drm_connector_mode_valid(struct drm_connector
> *connector,
> + struct drm_display_mode *mode);
> +
> #endif
> diff --git a/drivers/gpu/drm/drm_probe_helper.c
> b/drivers/gpu/drm/drm_probe_helper.c
> index 1b0c14a..f01abdc 100644
> --- a/drivers/gpu/drm/drm_probe_helper.c
> +++ b/drivers/gpu/drm/drm_probe_helper.c
> @@ -38,6 +38,9 @@
> #include
> #include
> #include
> +#include
> +
> +#include "drm_crtc_helper_internal.h"
>
> /**
> * DOC: output probing helper overview
> @@ -113,6 +116,41 @@ static int drm_helper_probe_add_cmdline_mode(struct
> drm_connector *connector)
> return 1;
> }
>
> +enum drm_mode_status drm_crtc_mode_valid(struct drm_crtc *crtc,
> + const struct drm_display_mode *mode)
> +{
> + const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
> +
> + if (!crtc_funcs || !crtc_funcs->mode_valid)
> + return MODE_OK;
> +
> + return crtc_funcs->mode_valid(crtc, mode);
> +}
> +
> +enum drm_mode_status drm_encoder_mode_valid(struct drm_encoder *encoder,
> + const struct drm_display_mode *mode)
> +{
> + const struct drm_encoder_helper_funcs *encoder_funcs =
> + encoder->helper_private;
> +
> + if (!encoder_funcs || !encoder_funcs->mode_valid)
> + return MODE_OK;
> +
> + return encoder_funcs->mode_valid(encoder, mode);
> +}
> +
> +enum drm_mode_status drm_connector_mode_valid(struct drm_connector
> *connector,
> + struct drm_display_mode *mode)
> +{
> + const struct drm_connector_helper_funcs *connector_funcs =
> + connector->helper_private;
> +
> + if (!connector_funcs || !connector_funcs->mode_valid)
> + return MODE_OK;
> +
> + return connector_funcs->mode_valid(connector, mode);
> +}
> +
> #define DRM_OUTPUT_POLL_PERIOD (10*HZ)
> /**
> * drm_kms_helper_poll_enable - re-enable output polling.
>
Reviewed-by: Neil Armstrong
Re: [PATCH v5 02/10] drm: Introduce drm_bridge_mode_valid()
On 05/25/2017 04:19 PM, Jose Abreu wrote:
> Introduce a new helper function which calls mode_valid() callback
> for all bridges in an encoder chain.
>
> Signed-off-by: Jose Abreu
> Reviewed-by: Daniel Vetter
> Cc: Carlos Palminha
> Cc: Ville Syrjälä
> Cc: Dave Airlie
> Cc: Andrzej Hajda
> Cc: Archit Taneja
> Cc: Laurent Pinchart
> ---
> drivers/gpu/drm/drm_bridge.c | 33 +
> include/drm/drm_bridge.h | 2 ++
> 2 files changed, 35 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c
> index 86a7637..dc8cdfe 100644
> --- a/drivers/gpu/drm/drm_bridge.c
> +++ b/drivers/gpu/drm/drm_bridge.c
> @@ -206,6 +206,39 @@ bool drm_bridge_mode_fixup(struct drm_bridge *bridge,
> EXPORT_SYMBOL(drm_bridge_mode_fixup);
>
> /**
> + * drm_bridge_mode_valid - validate the mode against all bridges in the
> + * encoder chain.
> + * @bridge: bridge control structure
> + * @mode: desired mode to be validated
> + *
> + * Calls &drm_bridge_funcs.mode_valid for all the bridges in the encoder
> + * chain, starting from the first bridge to the last. If at least one bridge
> + * does not accept the mode the function returns the error code.
> + *
> + * Note: the bridge passed should be the one closest to the encoder.
> + *
> + * RETURNS:
> + * MODE_OK on success, drm_mode_status Enum error code on failure
> + */
> +enum drm_mode_status drm_bridge_mode_valid(struct drm_bridge *bridge,
> +const struct drm_display_mode *mode)
> +{
> + enum drm_mode_status ret = MODE_OK;
> +
> + if (!bridge)
> + return ret;
> +
> + if (bridge->funcs->mode_valid)
> + ret = bridge->funcs->mode_valid(bridge, mode);
> +
> + if (ret != MODE_OK)
> + return ret;
> +
> + return drm_bridge_mode_valid(bridge->next, mode);
> +}
> +EXPORT_SYMBOL(drm_bridge_mode_valid);
> +
> +/**
> * drm_bridge_disable - disables all bridges in the encoder chain
> * @bridge: bridge control structure
> *
> diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h
> index 00c6c36..8358eb3 100644
> --- a/include/drm/drm_bridge.h
> +++ b/include/drm/drm_bridge.h
> @@ -233,6 +233,8 @@ int drm_bridge_attach(struct drm_encoder *encoder, struct
> drm_bridge *bridge,
> bool drm_bridge_mode_fixup(struct drm_bridge *bridge,
> const struct drm_display_mode *mode,
> struct drm_display_mode *adjusted_mode);
> +enum drm_mode_status drm_bridge_mode_valid(struct drm_bridge *bridge,
> + const struct drm_display_mode *mode);
> void drm_bridge_disable(struct drm_bridge *bridge);
> void drm_bridge_post_disable(struct drm_bridge *bridge);
> void drm_bridge_mode_set(struct drm_bridge *bridge,
>
Reviewed-by: Neil Armstrong
Re: [PATCH v5 03/10] drm: Use new mode_valid() helpers in connector probe helper
if (mode->status == MODE_OK) > mode->status = drm_mode_validate_flag(mode, mode_flags); > > - if (mode->status == MODE_OK && connector_funcs->mode_valid) > - mode->status = connector_funcs->mode_valid(connector, > -mode); > + if (mode->status == MODE_OK) > + mode->status = drm_mode_validate_pipeline(mode, > + connector); > } > > prune: > Reviewed-by: Neil Armstrong
Re: [PATCH v5 05/10] drm: arcpgu: Use crtc->mode_valid() callback
On 05/25/2017 04:19 PM, Jose Abreu wrote:
> Now that we have a callback to check if crtc supports a given mode
> we can use it in arcpgu so that we restrict the number of probbed
> modes to the ones we can actually display.
>
> This is specially useful because arcpgu crtc is responsible to set
> a clock value in the commit() stage but unfortunatelly this clock
> does not support all the needed ranges.
>
> Also, remove the atomic_check() callback as mode_valid() callback
> will be called before.
>
> Signed-off-by: Jose Abreu
> Reviewed-by: Alexey Brodkin
> Cc: Carlos Palminha
> Cc: Alexey Brodkin
> Cc: Daniel Vetter
> Cc: Dave Airlie
> Cc: Laurent Pinchart
>
> Changes v4->v5:
> - Change commit message to "arcpgu" (Alexey)
> Changes v3->v4:
> - Do not use aux function (Laurent)
>
> ---
> drivers/gpu/drm/arc/arcpgu_crtc.c | 29 ++---
> 1 file changed, 14 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c
> b/drivers/gpu/drm/arc/arcpgu_crtc.c
> index ad9a959..99fbdae 100644
> --- a/drivers/gpu/drm/arc/arcpgu_crtc.c
> +++ b/drivers/gpu/drm/arc/arcpgu_crtc.c
> @@ -64,6 +64,19 @@ static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
> .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
> };
>
> +enum drm_mode_status arc_pgu_crtc_mode_valid(struct drm_crtc *crtc,
> + const struct drm_display_mode
> *mode)
> +{
> + struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
> + long rate, clk_rate = mode->clock * 1000;
> +
> + rate = clk_round_rate(arcpgu->clk, clk_rate);
> + if (rate != clk_rate)
> + return MODE_NOCLOCK;
> +
> + return MODE_OK;
> +}
> +
> static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
> {
> struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
> @@ -129,20 +142,6 @@ static void arc_pgu_crtc_disable(struct drm_crtc *crtc)
> ~ARCPGU_CTRL_ENABLE_MASK);
> }
>
> -static int arc_pgu_crtc_atomic_check(struct drm_crtc *crtc,
> - struct drm_crtc_state *state)
> -{
> - struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
> - struct drm_display_mode *mode = &state->adjusted_mode;
> - long rate, clk_rate = mode->clock * 1000;
> -
> - rate = clk_round_rate(arcpgu->clk, clk_rate);
> - if (rate != clk_rate)
> - return -EINVAL;
> -
> - return 0;
> -}
> -
> static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
> struct drm_crtc_state *state)
> {
> @@ -158,6 +157,7 @@ static void arc_pgu_crtc_atomic_begin(struct drm_crtc
> *crtc,
> }
>
> static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
> + .mode_valid = arc_pgu_crtc_mode_valid,
> .mode_set = drm_helper_crtc_mode_set,
> .mode_set_base = drm_helper_crtc_mode_set_base,
> .mode_set_nofb = arc_pgu_crtc_mode_set_nofb,
> @@ -165,7 +165,6 @@ static void arc_pgu_crtc_atomic_begin(struct drm_crtc
> *crtc,
> .disable= arc_pgu_crtc_disable,
> .prepare= arc_pgu_crtc_disable,
> .commit = arc_pgu_crtc_enable,
> - .atomic_check = arc_pgu_crtc_atomic_check,
> .atomic_begin = arc_pgu_crtc_atomic_begin,
> };
>
>
Reviewed-by: Neil Armstrong
Re: [PATCH v5 04/10] drm: Use mode_valid() in atomic modeset
funcs.mode_valid and > + *&drm_crtc_helper_funcs.mode_valid are called on the affected > components. > + * 5. &drm_bridge_funcs.mode_fixup is called on all encoder bridges. > + * 6. &drm_encoder_helper_funcs.atomic_check is called to validate any > encoder state. > *This function is only called when the encoder will be part of a > configured crtc, > *it must not be used for implementing connector property validation. > *If this function is NULL, &drm_atomic_encoder_helper_funcs.mode_fixup > is called > *instead. > - * 6. &drm_crtc_helper_funcs.mode_fixup is called last, to fix up the mode > with crtc constraints. > + * 7. &drm_crtc_helper_funcs.mode_fixup is called last, to fix up the mode > with crtc constraints. > * > * &drm_crtc_state.mode_changed is set when the input mode is changed. > * &drm_crtc_state.connectors_changed is set when a connector is added or > @@ -617,6 +683,10 @@ static int handle_conflicting_encoders(struct > drm_atomic_state *state, > return ret; > } > > + ret = mode_valid(state); > + if (ret) > + return ret; > + > return mode_fixup(state); > } > EXPORT_SYMBOL(drm_atomic_helper_check_modeset); > Reviewed-by: Neil Armstrong
Re: [PATCH v5 06/10] drm/bridge: analogix-anx78xx: Use bridge->mode_valid() callback
On 05/25/2017 04:19 PM, Jose Abreu wrote:
> Now that we have a callback to check if bridge supports a given mode
> we can use it in Analogix bridge so that we restrict the number of
> probbed modes to the ones we can actually display.
>
> Also, there is no need to use mode_fixup() callback as mode_valid()
> will handle the mode validation.
>
> NOTE: Only compile tested.
>
> Signed-off-by: Jose Abreu
> Cc: Carlos Palminha
> Cc: Daniel Vetter
> Cc: Archit Taneja
> Cc: Andrzej Hajda
> Cc: Laurent Pinchart
> Cc: David Airlie
> ---
> drivers/gpu/drm/bridge/analogix-anx78xx.c | 13 ++---
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.c
> b/drivers/gpu/drm/bridge/analogix-anx78xx.c
> index a2a8236..cf69a1c 100644
> --- a/drivers/gpu/drm/bridge/analogix-anx78xx.c
> +++ b/drivers/gpu/drm/bridge/analogix-anx78xx.c
> @@ -1061,18 +1061,17 @@ static int anx78xx_bridge_attach(struct drm_bridge
> *bridge)
> return 0;
> }
>
> -static bool anx78xx_bridge_mode_fixup(struct drm_bridge *bridge,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adjusted_mode)
> +enum drm_mode_status anx78xx_bridge_mode_valid(struct drm_bridge *bridge,
> +const struct drm_display_mode
> *mode)
> {
> if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> - return false;
> + return MODE_NO_INTERLACE;
>
> /* Max 1200p at 5.4 Ghz, one lane */
> if (mode->clock > 154000)
> - return false;
> + return MODE_CLOCK_HIGH;
>
> - return true;
> + return MODE_OK;
> }
>
> static void anx78xx_bridge_disable(struct drm_bridge *bridge)
> @@ -1129,7 +1128,7 @@ static void anx78xx_bridge_enable(struct drm_bridge
> *bridge)
>
> static const struct drm_bridge_funcs anx78xx_bridge_funcs = {
> .attach = anx78xx_bridge_attach,
> - .mode_fixup = anx78xx_bridge_mode_fixup,
> + .mode_valid = anx78xx_bridge_mode_valid,
> .disable = anx78xx_bridge_disable,
> .mode_set = anx78xx_bridge_mode_set,
> .enable = anx78xx_bridge_enable,
>
Reviewed-by: Neil Armstrong
Re: [PATCH v5 08/10] drm/arm: malidp: Use crtc->mode_valid() callback
On 05/25/2017 04:19 PM, Jose Abreu wrote:
> Now that we have a callback to check if crtc supports a given mode
> we can use it in malidp so that we restrict the number of probbed
> modes to the ones we can actually display.
>
> Also, remove the mode_fixup() callback as this is no longer needed
> because mode_valid() will be called before.
>
> NOTE: Not even compiled tested
>
> Signed-off-by: Jose Abreu
> Cc: Carlos Palminha
> Cc: Daniel Vetter
> Cc: Liviu Dudau
> Cc: Brian Starkey
> Cc: David Airlie
> ---
> drivers/gpu/drm/arm/malidp_crtc.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/arm/malidp_crtc.c
> b/drivers/gpu/drm/arm/malidp_crtc.c
> index 9446a67..4bb38a2 100644
> --- a/drivers/gpu/drm/arm/malidp_crtc.c
> +++ b/drivers/gpu/drm/arm/malidp_crtc.c
> @@ -22,9 +22,8 @@
> #include "malidp_drv.h"
> #include "malidp_hw.h"
>
> -static bool malidp_crtc_mode_fixup(struct drm_crtc *crtc,
> -const struct drm_display_mode *mode,
> -struct drm_display_mode *adjusted_mode)
> +static enum drm_mode_status malidp_crtc_mode_valid(struct drm_crtc *crtc,
> +const struct
> drm_display_mode *mode)
> {
> struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
> struct malidp_hw_device *hwdev = malidp->dev;
> @@ -40,11 +39,11 @@ static bool malidp_crtc_mode_fixup(struct drm_crtc *crtc,
> if (rate != req_rate) {
> DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n",
>req_rate);
> - return false;
> + return MODE_NOCLOCK;
> }
> }
>
> - return true;
> + return MODE_OK;
> }
>
> static void malidp_crtc_enable(struct drm_crtc *crtc)
> @@ -408,7 +407,7 @@ static int malidp_crtc_atomic_check(struct drm_crtc *crtc,
> }
>
> static const struct drm_crtc_helper_funcs malidp_crtc_helper_funcs = {
> - .mode_fixup = malidp_crtc_mode_fixup,
> + .mode_valid = malidp_crtc_mode_valid,
> .enable = malidp_crtc_enable,
> .disable = malidp_crtc_disable,
> .atomic_check = malidp_crtc_atomic_check,
>
Reviewed-by: Neil Armstrong
Re: [PATCH v5 09/10] drm/atmel-hlcdc: Use crtc->mode_valid() callback
On 05/25/2017 04:19 PM, Jose Abreu wrote:
> Now that we have a callback to check if crtc supports a given mode
> we can use it in atmel-hlcdc so that we restrict the number of probbed
> modes to the ones we can actually display.
>
> Also, remove the mode_fixup() callback as this is no longer needed
> because mode_valid() will be called before.
>
> NOTE: Not even compiled tested
>
> Signed-off-by: Jose Abreu
> Cc: Carlos Palminha
> Cc: Daniel Vetter
> Cc: Boris Brezillon
> Cc: David Airlie
> ---
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 9 -
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> index 53bfa56..bdfe74e 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> @@ -140,13 +140,12 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct
> drm_crtc *c)
> cfg);
> }
>
> -static bool atmel_hlcdc_crtc_mode_fixup(struct drm_crtc *c,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adjusted_mode)
> +static enum drm_mode_status atmel_hlcdc_crtc_mode_valid(struct drm_crtc *c,
> + const struct
> drm_display_mode *mode)
> {
> struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
>
> - return atmel_hlcdc_dc_mode_valid(crtc->dc, adjusted_mode) == MODE_OK;
> + return atmel_hlcdc_dc_mode_valid(crtc->dc, mode);
> }
>
> static void atmel_hlcdc_crtc_disable(struct drm_crtc *c)
> @@ -315,7 +314,7 @@ static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc
> *crtc,
> }
>
> static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = {
> - .mode_fixup = atmel_hlcdc_crtc_mode_fixup,
> + .mode_valid = atmel_hlcdc_crtc_mode_valid,
> .mode_set = drm_helper_crtc_mode_set,
> .mode_set_nofb = atmel_hlcdc_crtc_mode_set_nofb,
> .mode_set_base = drm_helper_crtc_mode_set_base,
>
Reviewed-by: Neil Armstrong
Re: [PATCH v5 10/10] drm: vc4: Use crtc->mode_valid() and encoder->mode_valid() callbacks
On 05/25/2017 04:19 PM, Jose Abreu wrote:
> Now that we have a callback to check if crtc and encoder supports a
> given mode we can use it in vc4 so that we restrict the number of
> probbed modes to the ones we can actually display.
>
> Also, remove the mode_fixup() calls as these are no longer needed
> because mode_valid() will be called before.
>
> NOTE: Not even compiled tested
>
> Signed-off-by: Jose Abreu
> Cc: Carlos Palminha
> Cc: Daniel Vetter
> Cc: Eric Anholt
> Cc: David Airlie
> ---
> drivers/gpu/drm/vc4/vc4_crtc.c | 13 ++---
> drivers/gpu/drm/vc4/vc4_dpi.c | 13 ++---
> 2 files changed, 12 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
> index 1b4dbe9..20703c8 100644
> --- a/drivers/gpu/drm/vc4/vc4_crtc.c
> +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
> @@ -542,18 +542,17 @@ static void vc4_crtc_enable(struct drm_crtc *crtc)
> drm_crtc_vblank_on(crtc);
> }
>
> -static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adjusted_mode)
> +static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
> + const struct drm_display_mode
> *mode)
> {
> /* Do not allow doublescan modes from user space */
> - if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
> + if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
> DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
> crtc->base.id);
> - return false;
> + return MODE_NO_DBLESCAN;
> }
>
> - return true;
> + return MODE_OK;
> }
>
> static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
> @@ -863,7 +862,7 @@ static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
> .mode_set_nofb = vc4_crtc_mode_set_nofb,
> .disable = vc4_crtc_disable,
> .enable = vc4_crtc_enable,
> - .mode_fixup = vc4_crtc_mode_fixup,
> + .mode_valid = vc4_crtc_mode_valid,
> .atomic_check = vc4_crtc_atomic_check,
> .atomic_flush = vc4_crtc_atomic_flush,
> };
> diff --git a/drivers/gpu/drm/vc4/vc4_dpi.c b/drivers/gpu/drm/vc4/vc4_dpi.c
> index c6d7039..61958ab 100644
> --- a/drivers/gpu/drm/vc4/vc4_dpi.c
> +++ b/drivers/gpu/drm/vc4/vc4_dpi.c
> @@ -330,20 +330,19 @@ static void vc4_dpi_encoder_enable(struct drm_encoder
> *encoder)
> }
> }
>
> -static bool vc4_dpi_encoder_mode_fixup(struct drm_encoder *encoder,
> -const struct drm_display_mode *mode,
> -struct drm_display_mode *adjusted_mode)
> +static enum drm_mode_status vc4_dpi_encoder_mode_valid(struct drm_encoder
> *encoder,
> +const struct
> drm_display_mode *mode)
> {
> - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> - return false;
> + if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> + return MODE_NO_INTERLACE;
>
> - return true;
> + return MODE_OK;
> }
>
> static const struct drm_encoder_helper_funcs vc4_dpi_encoder_helper_funcs = {
> .disable = vc4_dpi_encoder_disable,
> .enable = vc4_dpi_encoder_enable,
> - .mode_fixup = vc4_dpi_encoder_mode_fixup,
> + .mode_valid = vc4_dpi_encoder_mode_valid,
> };
>
> static const struct of_device_id vc4_dpi_dt_match[] = {
>
Reviewed-by: Neil Armstrong
Re: [PATCH] soc: amlogic: gx pm domain: add PM and OF dependencies
On 02/11/2017 23:42, Arnd Bergmann wrote:
> The new driver introduces harmless warnings:
>
> warning: (PM_RMOBILE && ARCH_RCAR_GEN1 && ARCH_RCAR_GEN2 && ARCH_R7S72100 &&
> MESON_GX_PM_DOMAINS) selects PM_GENERIC_DOMAINS which has unmet direct
> dependencies (PM)
> warning: (MESON_GX_PM_DOMAINS) selects PM_GENERIC_DOMAINS_OF which has unmet
> direct dependencies (PM_GENERIC_DOMAINS && OF)
>
> This adds CONFIG_OF and CONFIG_PM dependencies to ensure it
> will only be enabled in valid configurations.
>
> Fixes: 75fcb5ca4b46 ("soc: amlogic: add Meson GX VPU Domains driver")
> Signed-off-by: Arnd Bergmann
> ---
> drivers/soc/amlogic/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
> index 1621bb25a1ea..b04f6e4aedbc 100644
> --- a/drivers/soc/amlogic/Kconfig
> +++ b/drivers/soc/amlogic/Kconfig
> @@ -12,6 +12,7 @@ config MESON_GX_SOCINFO
> config MESON_GX_PM_DOMAINS
> bool "Amlogic Meson GX Power Domains driver"
> depends on ARCH_MESON || COMPILE_TEST
> + depends on PM && OF
> default ARCH_MESON
> select PM_GENERIC_DOMAINS
> select PM_GENERIC_DOMAINS_OF
>
Thanks for the fix
Acked-by: Neil Armstrong
[PATCH] soc: amlogic: meson-gx-pwrc-vpu: fix power-off when powered by bootloader
In the case the VPU power domain has been powered on by the bootloader
and no driver are attached to this power domain, the genpd will power it
off after a certain amount of time, but the clocks hasn't been enabled
by the kernel itself and the power-off will trigger some faults.
This patch enable the clocks to have a coherent state for an eventual
poweroff and switches to the pm_domain_always_on_gov governor.
Fixes: 75fcb5ca4b46 ("soc: amlogic: add Meson GX VPU Domains driver")
Signed-off-by: Neil Armstrong
---
drivers/soc/amlogic/meson-gx-pwrc-vpu.c | 29 +++--
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
index bf5190b..2bdeebc 100644
--- a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
+++ b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
@@ -34,7 +34,6 @@ struct meson_gx_pwrc_vpu {
struct reset_control *rstc;
struct clk *vpu_clk;
struct clk *vapb_clk;
- bool powered;
};
static inline
@@ -78,8 +77,6 @@ static int meson_gx_pwrc_vpu_power_off(struct
generic_pm_domain *genpd)
clk_disable_unprepare(pd->vpu_clk);
clk_disable_unprepare(pd->vapb_clk);
- pd->powered = false;
-
return 0;
}
@@ -91,7 +88,11 @@ static int meson_gx_pwrc_vpu_setup_clk(struct
meson_gx_pwrc_vpu *pd)
if (ret)
return ret;
- return clk_prepare_enable(pd->vapb_clk);
+ ret = clk_prepare_enable(pd->vapb_clk);
+ if (ret)
+ clk_disable_unprepare(pd->vpu_clk);
+
+ return ret;
}
static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
@@ -139,8 +140,6 @@ static int meson_gx_pwrc_vpu_power_on(struct
generic_pm_domain *genpd)
if (ret)
return ret;
- pd->powered = true;
-
return 0;
}
@@ -167,6 +166,8 @@ static int meson_gx_pwrc_vpu_probe(struct platform_device
*pdev)
struct reset_control *rstc;
struct clk *vpu_clk;
struct clk *vapb_clk;
+ bool powered_off;
+ int ret;
regmap_ao = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
if (IS_ERR(regmap_ao)) {
@@ -205,8 +206,17 @@ static int meson_gx_pwrc_vpu_probe(struct platform_device
*pdev)
vpu_hdmi_pd.vpu_clk = vpu_clk;
vpu_hdmi_pd.vapb_clk = vapb_clk;
- pm_genpd_init(&vpu_hdmi_pd.genpd, &simple_qos_governor,
- meson_gx_pwrc_vpu_get_power(&vpu_hdmi_pd));
+ powered_off = meson_gx_pwrc_vpu_get_power(&vpu_hdmi_pd);
+
+ /* If already powered, sync the clock states */
+ if (!powered_off) {
+ ret = meson_gx_pwrc_vpu_setup_clk(&vpu_hdmi_pd);
+ if (ret)
+ return ret;
+ }
+
+ pm_genpd_init(&vpu_hdmi_pd.genpd, &pm_domain_always_on_gov,
+ powered_off);
return of_genpd_add_provider_simple(pdev->dev.of_node,
&vpu_hdmi_pd.genpd);
@@ -214,8 +224,7 @@ static int meson_gx_pwrc_vpu_probe(struct platform_device
*pdev)
static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev)
{
- if (vpu_hdmi_pd.powered)
- meson_gx_pwrc_vpu_power_off(&vpu_hdmi_pd.genpd);
+ meson_gx_pwrc_vpu_power_off(&vpu_hdmi_pd.genpd);
}
static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = {
--
2.7.4
Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC
Hi Yixun, Le 04/11/2017 09:41, Yixun Lan a écrit : > > > On 11/04/17 02:17, Yixun Lan wrote: >> According to the datasheet, the clock gate bit for >> SARADC is bit[22] in Meson-GXBB/GXL series. >> >> Change-Id: Ic4fa58276d2a9ea273eef0a08541fc213ac5ac89 >> Signed-off-by: Yixun Lan >> --- >> drivers/clk/meson/gxbb.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c >> index b2d1e8ed7152..4f5b535fcd12 100644 >> --- a/drivers/clk/meson/gxbb.c >> +++ b/drivers/clk/meson/gxbb.c >> @@ -1139,7 +1139,6 @@ static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); >> static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); >> static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); >> static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); >> -static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10); >> static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); >> static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); >> static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); >> @@ -1149,6 +1148,7 @@ static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); >> static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17); >> static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18); >> static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); >> +static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 22); >> static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); >> static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); >> static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); >> > Hi Neil > I assume you will take this via the clk-meson tree.. > could you amend the commit msg and drop the 'Change-Id'? > (for other parts, please feel free to adjust if you see fit) > thanks Yes, I will push it as a fix. Can you check if the saradc driver is still functional when applied ? Neil > > Yixun >
Re: [PATCH v3] tty: serial: meson: allow baud-rates lower than 9600
Le 04/11/2017 14:13, Greg Kroah-Hartman a écrit : > On Sat, Nov 04, 2017 at 02:00:00PM +0100, V10lator wrote: >> Devices like DCF77 receivers need the baud-rate to be as low as 50. >> >> I have tested this on a Meson GXL device with uart_A. >> >> Cc: Greg Kroah-Hartman >> Cc: Jiri Slaby >> Cc: Carlo Caione >> Cc: Kevin Hilman >> Cc: linux-amlo...@lists.infradead.org >> Cc: linux-arm-ker...@lists.infradead.org >> Cc: linux-kernel@vger.kernel.org >> Signed-off-by: Thomas Rohloff >> --- >> drivers/tty/serial/meson_uart.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) > > What changed from v2? > > And I need a real name as the author of the patch :( > > > ___ > linux-amlogic mailing list > linux-amlo...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-amlogic > Hi Thomas, Make sure the "From" header of your mail matches the Signed-off-by tag, overwise use the --from option with "git send-email" to be sure, or generate the patch with the "git format-patch" with the "--from" option. Anyway : Reviewed-by: Neil Armstrong
Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA
On 06/11/2017 08:52, Yixun Lan wrote: > According to the datasheet, in Meson-GXBB/GXL series, > The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], > while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. > > Test passed at gxl_skt dev board. > > Tested-by: Xingyu Chen > Signed-off-by: Yixun Lan > > --- > I think this error was introduced by a copy & paste from meson8 code? > and we didn't notice them due to the SANA clock is also enabled by > DTS (so SAR_ADC works fine)? > --- > drivers/clk/meson/gxbb.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c > index b2d1e8ed7152..92168348ffa6 100644 > --- a/drivers/clk/meson/gxbb.c > +++ b/drivers/clk/meson/gxbb.c > @@ -1139,7 +1139,7 @@ static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); > static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); > static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); > static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); > -static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10); > +static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10); > static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); > static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); > static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); > @@ -1190,7 +1190,7 @@ static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, > 9); > static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); > static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); > static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); > -static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22); > +static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); > static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); > static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); > static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); > Hi Yixun, Can you precise how it affects the saradc driver ? from the DT and clk PoV ? Also, can you add a Fixes: tag on the patch ? Thanks, Neil
Re: [PATCH v5 8/9] drm/bridge/synopsys: dw-hdmi: Do not use device's drvdata
On 18/10/2017 14:09, Jeffy Chen wrote:
> Let plat drivers own the drvdata, so that they could cleanup resources
> in their unbind().
>
> Signed-off-by: Jeffy Chen
> ---
>
> Changes in v5: None
>
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 43
> ++---
> drivers/gpu/drm/imx/dw_hdmi-imx.c | 22 +--
> drivers/gpu/drm/meson/meson_dw_hdmi.c | 20 ++
> drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c | 14 --
> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 23 ---
> include/drm/bridge/dw_hdmi.h| 17 ++--
> 6 files changed, 77 insertions(+), 62 deletions(-)
>
[...]
> diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c
> b/drivers/gpu/drm/meson/meson_dw_hdmi.c
> index cef414466f9f..fc29f69f7108 100644
> --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
> +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
> @@ -138,6 +138,8 @@ struct meson_dw_hdmi {
> struct clk *hdmi_pclk;
> struct clk *venci_clk;
> u32 irq_stat;
> +
> + struct dw_hdmi *hdmi;
> };
> #define encoder_to_meson_dw_hdmi(x) \
> container_of(x, struct meson_dw_hdmi, encoder)
> @@ -526,7 +528,7 @@ static irqreturn_t dw_hdmi_top_thread_irq(int irq, void
> *dev_id)
> if (stat & HDMITX_TOP_INTR_HPD_RISE)
> hpd_connected = true;
>
> - dw_hdmi_setup_rx_sense(dw_hdmi->dev, hpd_connected,
> + dw_hdmi_setup_rx_sense(dw_hdmi->hdmi, hpd_connected,
> hpd_connected);
>
> drm_helper_hpd_irq_event(dw_hdmi->encoder.dev);
> @@ -865,9 +867,14 @@ static int meson_dw_hdmi_bind(struct device *dev, struct
> device *master,
> dw_plat_data->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
> dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709;
>
> - ret = dw_hdmi_bind(pdev, encoder, &meson_dw_hdmi->dw_plat_data);
> - if (ret)
> - return ret;
> + meson_dw_hdmi->hdmi = dw_hdmi_bind(pdev, encoder,
> +&meson_dw_hdmi->dw_plat_data);
> + if (IS_ERR(meson_dw_hdmi->hdmi)) {
> + encoder->funcs->destroy(encoder);
> + return PTR_ERR(meson_dw_hdmi->hdmi);
> + }
> +
> + dev_set_drvdata(dev, meson_dw_hdmi);
>
> DRM_DEBUG_DRIVER("HDMI controller initialized\n");
>
> @@ -877,7 +884,10 @@ static int meson_dw_hdmi_bind(struct device *dev, struct
> device *master,
> static void meson_dw_hdmi_unbind(struct device *dev, struct device *master,
> void *data)
> {
> - dw_hdmi_unbind(dev);
> + struct meson_dw_hdmi *meson_dw_hdmi = dev_get_drvdata(dev);
> +
> + dw_hdmi_unbind(meson_dw_hdmi->hdmi);
> + meson_dw_hdmi->encoder.funcs->destroy(&meson_dw_hdmi->encoder);
> }
>
> static const struct component_ops meson_dw_hdmi_ops = {
[...]
For meson/meson_dw_hdmi.c :
Reviewed-by: Neil Armstrong
[PATCH] ARM64: dts: meson-gxbb-odroidc2: fix usb1 power supply
Looking at the schematics, the USB Power Supply is shared between the
two USB interfaces,
If the usb0 fails to initialize, the second one won't have power.
Fixes: 5a0803bd5ae2 ("ARM64: dts: meson-gxbb-odroidc2: Enable USB Nodes")
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index 1deaa53..2e5ed59 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -301,6 +301,7 @@
&usb1_phy {
status = "okay";
+ phy-supply = <&usb_otg_pwr>;
};
&usb0 {
--
2.7.4
Re: [PATCH v4 2/2] crypto: stm32 - Support for STM32 CRYP crypto module
On 19/10/2017 15:01, Fabien DESSENNE wrote:
> Hi Corentin
>
>
> Thank you for your comments. I will fix according to them. See also me
> answers/questions below
>
> While we are at it, do you plan to deliver a new version of the
> crypto_engine update? (I had to remove the AEAD part of this new driver
> since it depends on that pending update)
>
> BR
>
> Fabien
>
>
> On 19/10/17 12:34, Corentin Labbe wrote:
>> Hello
>>
>> I have some minor comment below
>>
>> On Thu, Oct 19, 2017 at 11:03:59AM +0200, Fabien Dessenne wrote:
>>> This module registers block cipher algorithms that make use of the
>>> STMicroelectronics STM32 crypto "CRYP1" hardware.
>>> The following algorithms are supported:
>>> - aes: ecb, cbc, ctr
>>> - des: ecb, cbc
>>> - tdes: ecb, cbc
>>>
>>> Signed-off-by: Fabien Dessennie
>>> ---
>>> drivers/crypto/stm32/Kconfig |9 +
>>> drivers/crypto/stm32/Makefile |3 +-
>>> drivers/crypto/stm32/stm32-cryp.c | 1188
>>> +
>>> 3 files changed, 1199 insertions(+), 1 deletion(-)
>>> create mode 100644 drivers/crypto/stm32/stm32-cryp.c
>>>
>>> diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
>>> index 602332e..61ef00b 100644
>>> --- a/drivers/crypto/stm32/Kconfig
>>> +++ b/drivers/crypto/stm32/Kconfig
>> [...]
>>> +/* Bit [0] encrypt / decrypt */
>>> +#define FLG_ENCRYPT BIT(0)
>>> +/* Bit [8..1] algo & operation mode */
>>> +#define FLG_AES BIT(1)
>>> +#define FLG_DES BIT(2)
>>> +#define FLG_TDESBIT(3)
>>> +#define FLG_ECB BIT(4)
>>> +#define FLG_CBC BIT(5)
>>> +#define FLG_CTR BIT(6)
>>> +/* Mode mask = bits [15..0] */
>>> +#define FLG_MODE_MASK GENMASK(15, 0)
>>> +
>>> +/* Registers */
>>> +#define CRYP_CR 0x
>>> +#define CRYP_SR 0x0004
>>> +#define CRYP_DIN0x0008
>>> +#define CRYP_DOUT 0x000C
>>> +#define CRYP_DMACR 0x0010
>>> +#define CRYP_IMSCR 0x0014
>>> +#define CRYP_RISR 0x0018
>>> +#define CRYP_MISR 0x001C
>>> +#define CRYP_K0LR 0x0020
>>> +#define CRYP_K0RR 0x0024
>>> +#define CRYP_K1LR 0x0028
>>> +#define CRYP_K1RR 0x002C
>>> +#define CRYP_K2LR 0x0030
>>> +#define CRYP_K2RR 0x0034
>>> +#define CRYP_K3LR 0x0038
>>> +#define CRYP_K3RR 0x003C
>>> +#define CRYP_IV0LR 0x0040
>>> +#define CRYP_IV0RR 0x0044
>>> +#define CRYP_IV1LR 0x0048
>>> +#define CRYP_IV1RR 0x004C
>>> +
>>> +/* Registers values */
>>> +#define CR_DEC_NOT_ENC 0x0004
>>> +#define CR_TDES_ECB 0x
>>> +#define CR_TDES_CBC 0x0008
>>> +#define CR_DES_ECB 0x0010
>>> +#define CR_DES_CBC 0x0018
>>> +#define CR_AES_ECB 0x0020
>>> +#define CR_AES_CBC 0x0028
>>> +#define CR_AES_CTR 0x0030
>>> +#define CR_AES_KP 0x0038
>>> +#define CR_AES_UNKNOWN 0x
>>> +#define CR_ALGO_MASK0x00080038
>>> +#define CR_DATA32 0x
>>> +#define CR_DATA16 0x0040
>>> +#define CR_DATA80x0080
>>> +#define CR_DATA10x00C0
>>> +#define CR_KEY128 0x
>>> +#define CR_KEY192 0x0100
>>> +#define CR_KEY256 0x0200
>>> +#define CR_FFLUSH 0x4000
>>> +#define CR_CRYPEN 0x8000
>> Why not using BIT(x) ?
>
> Some values are not only 1 bit (then we may use BIT and BITGEN but this
> would be less readable), so I prefer to keep this values.
You can use GENMASK and the corresponding FIELD_PREP() and FIELD_GET().
It avoids manipulating the bits directly.
>
>> Why not using also directly FLG_XX since CR_XX are arbitray values ? like
>> using instead CR_AES_CBC = FLG_AES | FLG_CBC
>
> The CR_ values are used to write in the registers. FLG_ are arbitraty
> values, so we cannot mix them.
>
>>
>> [...]
>>> +static inline void stm32_cryp_wait_enable(struct stm32_cryp *cryp)
>>> +{
>>> + while (stm32_cryp_read(cryp, CRYP_CR) & CR_CRYPEN)
>>> + cpu_relax();
>>> +}
>> This function is not used, so you could remove it
>>
>>> +
>>> +static inline void stm32_cryp_wait_busy(struct stm32_cryp *cryp)
>>> +{
>>> + while (stm32_cryp_read(cryp, CRYP_SR) & SR_BUSY)
>>> + cpu_relax();
>>> +}
>> No timeout ?
>>
>>
>>> +
>>> +static inline void stm32_cryp_wait_output(struct stm32_cryp *cryp)
>>> +{
>>> + while (!(stm32_cryp_read(cryp, CRYP_SR) & SR_OFNE))
>>> + cpu_relax();
>>> +}
>> This function is not used, so you could remove it
>>
>> [...]
>>>
[RESEND PATCH v2 0/2] soc: amlogic: add support for Meson GX VPU Domains
[Resent with linux-pm in CC] On the Amlogic Gx SoCs (GXBB, GXL & GXM), the VPU power domain is initialized by the vendor U-Boot code, but running mainline U-boot has been possible on these SoCs. But lacking such init made the system lock at kernel boot. This patchset adds the Video Processing Unit power domain driver to enable the same power-on and power-down sequences and was designed to allow booting with the power domain already initialized or not. This driver has been tested on : - Odroid-C2 (GXBB) with Vendor and Mainline U-Boot - P212 (GXL) with Vendor and Mainline U-Boot - Khadas Vim (GXL) with Vendor U-Boot - Khadas Vim2 with (GXM) Vendor U-Boot Changes since v1: - fixed bindings compatible string Neil Armstrong (2): soc: amlogic: add Meson GX VPU Domains driver dt-bindings: power: add amlogic meson power domain bindings .../bindings/power/amlogic,meson-gx-pwrc.txt | 61 ++ drivers/soc/amlogic/Kconfig| 10 + drivers/soc/amlogic/Makefile | 1 + drivers/soc/amlogic/meson-gx-pwrc-vpu.c| 234 + 4 files changed, 306 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt create mode 100644 drivers/soc/amlogic/meson-gx-pwrc-vpu.c -- 2.7.4
[RESEND PATCH v2 2/2] dt-bindings: power: add amlogic meson power domain bindings
Acked-by: Rob Herring
Signed-off-by: Neil Armstrong
---
.../bindings/power/amlogic,meson-gx-pwrc.txt | 61 ++
1 file changed, 61 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
new file mode 100644
index 000..95ec49a
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
@@ -0,0 +1,61 @@
+Amlogic Meson Power Controller
+==
+
+The Amlogic Meson SoCs embeds an internal Power domain controller.
+
+VPU Power Domain
+
+
+The Video Processing Unit power domain is controlled by this power controller,
+but the domain requires some external resources to meet the correct power
+sequences.
+The bindings must respect the power domain bindings as described in the file
+power_domain.txt
+
+Device Tree Bindings:
+-
+
+Required properties:
+- compatible: should be "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
+- #power-domain-cells: should be 0
+- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
+- resets: phandles to the reset lines needed for this power demain sequence
+ as described in ../reset/reset.txt
+- clocks: from common clock binding: handle to VPU and VAPB clocks
+- clock-names: from common clock binding: must contain "vpu", "vapb"
+ corresponding to entry in the clocks property.
+
+Parent node should have the following properties :
+- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
+- reg: base address and size of the AO system control register space.
+
+Example:
+---
+
+ao_sysctrl: sys-ctrl@0 {
+ compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
+ reg = <0x0 0x0 0x0 0x100>;
+
+ pwrc_vpu: power-controller-vpu {
+ compatible = "amlogic,meson-gx-pwrc-vpu";
+ #power-domain-cells = <0>;
+ amlogic,hhi-sysctrl = <&sysctrl>;
+ resets = <&reset RESET_VIU>,
+<&reset RESET_VENC>,
+<&reset RESET_VCBUS>,
+<&reset RESET_BT656>,
+<&reset RESET_DVIN_RESET>,
+<&reset RESET_RDMA>,
+<&reset RESET_VENCI>,
+<&reset RESET_VENCP>,
+<&reset RESET_VDAC>,
+<&reset RESET_VDI6>,
+<&reset RESET_VENCL>,
+<&reset RESET_VID_LOCK>;
+ clocks = <&clkc CLKID_VPU>,
+<&clkc CLKID_VAPB>;
+ clock-names = "vpu", "vapb";
+ };
+};
+
+
--
2.7.4
