Re: [PATCH RFT 1/2] regulator: twl: Fix the formula to calculate vsel and voltage for twl6030ldo

[Rajendra Nayak]

Hi Axel,

My apologies for the delay in responding to this one.

On Monday 09 July 2012 04:31 PM, Axel Lin wrote:

於 一，2012-07-09 於 11:22 +0800，Axel Lin 提到：

In twl6030ldo_set_voltage, current code use below formula to calculate vsel:
 vsel = (min_uV/1000 - 1000)/100 + 1;
This is worng because when min_uV is 100 uV, vsel is 1.
It should be 0 in this case.


Why? Do you know of any documentation which states this?
I am referring to the twl6030 Top Functional spec version 1.18
and Table - 223 LDO Output Voltage Selection Code clearly
states that the vsel should be 1 when voltage expected is 100 uV.

Also refer to equation 3 LDO Output Voltage Selection Code in the
same document and you will see this mentioned..
Absolute Voltage value = 1.0V + 0.1V * (binary value – 0001)


Fix it by change the equation to: (This equation is common for linear mapping)
 vsel = DIV_ROUND_UP(min_uV - rdev-desc-min_uV, rdev-desc-uV_step);

In twl6030ldo_get_voltage, current code use below formula to calculate voltage:
 mV = 1000mv + 100mv * (vsel - 1)
This is worng because when vsel is 0, mV is 900mV. Note the min_uV is 1000mV.
Fix it by change the equation to: (This equation is common for linear mapping)
 return rdev-desc-min_uV + vsel * rdev-desc-uV_step;


While I'm thinking I need to rework this patch so that it doesn't use
rdev-desc-min_uV and rdev-desc-uV_step and then can be applied
to current Linus' tree.

But while I am tracking back to commit 3e3d3be79c
Author: Rajendra Nayakrna...@ti.com
Date:   Thu Apr 22 14:18:32 2010 +0530

 twl6030: regulator: Remove vsel tables and use formula for
calculation

 All twl6030 regulators can be programmed from 1.0v to 3.3v
 with 100mV steps.
 The below formula can be used to calculate the vsel values
 to be programmed in the VREG_VOLTAGE registers.

 Voltage(in mV) = 1000mv + 100mv * (vsel - 1)

 Ex: if vsel = 0x9, mV = 1000 + 100 * (9 -1) = 1800mV.

 This patch removes all existing VSEL tables for twl6030 adjustable
 regulators and just uses the formula directly for vsel calculations
 after verifing they fall in the allowed range.

 Signed-off-by: Rajendra Nayakrna...@ti.com

I found a problem that before commit 3e3d3be79c, the voltage tables were
not linear mapping. So why we can convert these voltage mapping table to
Voltage(in mV) = 1000mv + 100mv * (vsel - 1)?

Did I miss something?


All voltage tables before commit '3e3d3be79c' for twl6030 regulators
were clearly wrong. They assumed similarity with twl4030 regulators
which was not right.

regards,
Rajendra



Regards,
Axel




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Re: [PATCH RFT 1/2] regulator: twl: Fix checking voltage range in twl6030smps_set_voltage()

[Rajendra Nayak]

Copying Graeme and linux-omap list.

On Saturday 14 July 2012 11:07 AM, Axel Lin wrote:

The voltage selection logic is supposed to find the samllest voltage falls
within specified range. When using equation to calculate vsel, we need to
ensure the requested min_uV meet the range of using the equation.
Otherwise we may select a voltage that is out of specified range.

For example, in the case vsel = 62 means select voltage of 210uV.
What we want is to ensure the requested min_uV= 210 rather than checking
max_uV= 210. And this also means in the case min_uV  210, vsel = 62
does not meet the request.

Also calling twl6030smps_list_voltage() for all cases to ensure the selected
voltage still in bounds.

Signed-off-by: Axel Linaxel@gmail.com
---
  drivers/regulator/twl-regulator.c |   36 
  1 file changed, 16 insertions(+), 20 deletions(-)

diff --git a/drivers/regulator/twl-regulator.c 
b/drivers/regulator/twl-regulator.c
index 8f0bd56..03d0bea 100644
--- a/drivers/regulator/twl-regulator.c
+++ b/drivers/regulator/twl-regulator.c
@@ -760,32 +760,28 @@ twl6030smps_set_voltage(struct regulator_dev *rdev, int 
min_uV, int max_uV,
unsigned int *selector)
  {
struct twlreg_info  *info = rdev_get_drvdata(rdev);
-   int vsel = 0;
+   int vsel = 0, calc_uV;

switch (info-flags) {
case 0:
if (min_uV == 0)
vsel = 0;
else if ((min_uV= 60)  (min_uV= 130)) {
-   int calc_uV;
vsel = DIV_ROUND_UP(min_uV - 60, 12500);
vsel++;
-   calc_uV = twl6030smps_list_voltage(rdev, vsel);
-   if (calc_uV  max_uV)
-   return -EINVAL;
}
/* Values 1..57 for vsel are linear and can be calculated
 * values 58..62 are non linear.
 */
-   else if ((min_uV  190)  (max_uV= 210))
+   else if ((min_uV  190)  (min_uV= 210))
vsel = 62;
-   else if ((min_uV  180)  (max_uV= 190))
+   else if ((min_uV  180)  (min_uV= 190))
vsel = 61;
-   else if ((min_uV  150)  (max_uV= 180))
+   else if ((min_uV  150)  (min_uV= 180))
vsel = 60;
-   else if ((min_uV  135)  (max_uV= 150))
+   else if ((min_uV  135)  (min_uV= 150))
vsel = 59;
-   else if ((min_uV  130)  (max_uV= 135))
+   else if ((min_uV  130)  (min_uV= 135))
vsel = 58;
else
return -EINVAL;
@@ -794,25 +790,21 @@ twl6030smps_set_voltage(struct regulator_dev *rdev, int 
min_uV, int max_uV,
if (min_uV == 0)
vsel = 0;
else if ((min_uV= 70)  (min_uV= 142)) {
-   int calc_uV;
vsel = DIV_ROUND_UP(min_uV - 70, 12500);
vsel++;
-   calc_uV = twl6030smps_list_voltage(rdev, vsel);
-   if (calc_uV  max_uV)
-   return -EINVAL;
}
/* Values 1..57 for vsel are linear and can be calculated
 * values 58..62 are non linear.
 */
-   else if ((min_uV  190)  (max_uV= 210))
+   else if ((min_uV  190)  (min_uV= 210))
vsel = 62;
-   else if ((min_uV  180)  (max_uV= 190))
+   else if ((min_uV  180)  (min_uV= 190))
vsel = 61;
-   else if ((min_uV  135)  (max_uV= 180))
+   else if ((min_uV  135)  (min_uV= 180))
vsel = 60;
-   else if ((min_uV  135)  (max_uV= 150))
+   else if ((min_uV  135)  (min_uV= 150))
vsel = 59;
-   else if ((min_uV  130)  (max_uV= 135))
+   else if ((min_uV  130)  (min_uV= 135))
vsel = 58;
else
return -EINVAL;
@@ -828,13 +820,17 @@ twl6030smps_set_voltage(struct regulator_dev *rdev, int 
min_uV, int max_uV,
case SMPS_OFFSET_EN|SMPS_EXTENDED_EN:
if (min_uV == 0) {
vsel = 0;
-   } else if ((min_uV= 2161000)  (max_uV= 4321000)) {
+   } else if ((min_uV= 2161000)  (min_uV= 4321000)) {
vsel = DIV_ROUND_UP(min_uV - 2161000, 38600);
vsel++;
}
break;
}

+   calc_uV = twl6030smps_list_voltage(rdev, vsel);
+ 

Re: [PATCH RFT] regulator: twl: Fix list_voltate for twl6030ldo_ops

[Rajendra Nayak]

Axel,

On Monday 16 July 2012 04:01 PM, Axel Lin wrote:

According to the datasheet, the voltage for twl6030ldo_ops is not linear for
all cases. Linear mapping is only for the selection code from
0001 to 00011000.

Table 9. LDO Output Voltage Selection Code
CODE VOUT(V)COD  VOUT(V)CODE VOUT(V)CODE VOUT(V)
 0  1000 1.70001 2.500011000 3.3
0001 1.01001 1.800010001 2.600011001 Reserved
0010 1.11010 1.900010010 2.700011010 Reserved
0011 1.21011 2.000010011 2.800011011 Reserved
0100 1.31100 2.100010100 2.900011100 Reserved
0101 1.41101 2.200010101 3.000011101 Reserved
0110 1.51110 2.300010110 3.10000 Reserved
0111 1.6 2.400010111 3.20001 2.75

This patch implements the list_voltage callback based on above table.

Signed-off-by: Axel Linaxel@gmail.com


Seems to work fine on my 4460 Panda.

Without this fix..

[0.337341] V1V8: 1800 mV normal standby
[0.338531] V2V1: 2100 mV normal standby
[0.339813] VMMC: 1200 -- 3000 mV at 3100 mV normal standby

[0.341278] VPP: 1800 -- 2500 mV at 2000 mV normal standby
^
[0.343505] VCXIO: 1800 mV normal standby
[0.343597] VCXIO: supplied by V2V1
[0.345855] VDAC: 1800 mV normal standby
[0.345947] VDAC: supplied by V2V1
[0.347717] VAUX2_6030: 1200 -- 2800 mV at 1900 mV normal standby

[0.349212] VAUX3_6030: 1000 -- 3000 mV at 1300 mV normal standby


And with the fix..

[0.337707] V1V8: 1800 mV normal standby
[0.338897] V2V1: 2100 mV normal standby
[0.340179] VMMC: 1200 -- 3000 mV at 3000 mV normal standby
[0.341674] VPP: 1800 -- 2500 mV at 1900 mV normal standby
[0.343383] VCXIO: 1800 mV normal standby
[0.343475] VCXIO: supplied by V2V1
[0.345764] VDAC: 1800 mV normal standby
[0.345825] VDAC: supplied by V2V1
[0.347656] VAUX2_6030: 1200 -- 2800 mV at 1800 mV normal standby
[0.349121] VAUX3_6030: 1000 -- 3000 mV at 1200 mV normal standby

Thanks for the patch.

Tested-by: Rajendra Nayak rna...@ti.com


---
  drivers/regulator/twl-regulator.c |   31 ---
  1 file changed, 24 insertions(+), 7 deletions(-)

diff --git a/drivers/regulator/twl-regulator.c 
b/drivers/regulator/twl-regulator.c
index de99b78..242fe90 100644
--- a/drivers/regulator/twl-regulator.c
+++ b/drivers/regulator/twl-regulator.c
@@ -559,6 +559,27 @@ static struct regulator_ops twl6030coresmps_ops = {
.get_voltage= twl6030coresmps_get_voltage,
  };

+static int twl6030ldo_list_voltage(struct regulator_dev *rdev, unsigned sel)
+{
+   struct twlreg_info *info = rdev_get_drvdata(rdev);
+
+   switch (sel) {
+   case 0:
+   return 0;
+   case 1 ... 24:
+   /* Linear mapping from 0001 to 00011000:
+* Absolute voltage value = 1.0 V + 0.1 V × (sel – 0001)
+*/
+   return (info-min_mV + 100 * (sel - 1)) * 1000;
+   case 25 ... 30:
+   return -EINVAL;
+   case 31:
+   return 275;
+   default:
+   return -EINVAL;
+   }
+}
+
  static int
  twl6030ldo_set_voltage_sel(struct regulator_dev *rdev, unsigned selector)
  {
@@ -577,7 +598,7 @@ static int twl6030ldo_get_voltage_sel(struct regulator_dev 
*rdev)
  }

  static struct regulator_ops twl6030ldo_ops = {
-   .list_voltage   = regulator_list_voltage_linear,
+   .list_voltage   = twl6030ldo_list_voltage,

.set_voltage_sel = twl6030ldo_set_voltage_sel,
.get_voltage_sel = twl6030ldo_get_voltage_sel,
@@ -906,12 +927,10 @@ static struct twlreg_info TWL6030_INFO_##label = { \
.desc = { \
.name = #label, \
.id = TWL6030_REG_##label, \
-   .n_voltages = (max_mVolts - min_mVolts)/100 + 1, \
+   .n_voltages = 32, \
.ops =twl6030ldo_ops, \
.type = REGULATOR_VOLTAGE, \
.owner = THIS_MODULE, \
-   .min_uV = min_mVolts * 1000, \
-   .uV_step = 100 * 1000, \
}, \
}

@@ -923,12 +942,10 @@ static struct twlreg_info TWL6025_INFO_##label = { \
.desc = { \
.name = #label, \
.id = TWL6025_REG_##label, \
-   .n_voltages = ((max_mVolts - min_mVolts)/100) + 1, \
+   .n_voltages = 32, \
.ops =twl6030ldo_ops, \
.type = REGULATOR_VOLTAGE, \
.owner = THIS_MODULE, \
-   .min_uV = min_mVolts * 1000, \
-   .uV_step = 100

Re: [PATCH RFT] regulator: twl: Fix list_voltate for twl6030ldo_ops

[Rajendra Nayak]

Sorry, I seemed to have messed up with the underlining.

On Monday 16 July 2012 05:38 PM, Rajendra Nayak wrote:

[0.337341] V1V8: 1800 mV normal standby
[0.338531] V2V1: 2100 mV normal standby
[0.339813] VMMC: 1200 -- 3000 mV at 3100 mV normal standby
 


I meant 3100 mV normal standby was wrong.


[0.341278] VPP: 1800 -- 2500 mV at 2000 mV normal standby
 ^


2000 mV being wrong here.


[0.343505] VCXIO: 1800 mV normal standby
[0.343597] VCXIO: supplied by V2V1
[0.345855] VDAC: 1800 mV normal standby
[0.345947] VDAC: supplied by V2V1
[0.347717] VAUX2_6030: 1200 -- 2800 mV at 1900 mV normal standby
 


1900 mV here..


[0.349212] VAUX3_6030: 1000 -- 3000 mV at 1300 mV normal standby
 


and 1300 mV here.

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Re: [PATCH] clk: fix compile for OF !COMMON_CLK

[Rajendra Nayak]

Rob, Mike,

On Tuesday 17 July 2012 07:38 AM, Rob Herring wrote:

On 07/16/2012 07:12 PM, Mike Turquette wrote:

On 20120716-16:46, Rob Herring wrote:

From: Rob Herringrob.herr...@calxeda.com

With commit 766e6a4ec602d0c107 (clk: add DT clock binding support),
compiling with OF  !COMMON_CLK is broken.



Hi Rob,

Thanks for sending this quickly.

snip

@@ -313,19 +314,19 @@ int clk_add_alias(const char *alias, const char 
*alias_dev_name, char *id,
  struct device_node;
  struct of_phandle_args;

-#ifdef CONFIG_OF
+#if defined(CONFIG_OF)  defined(CONFIG_COMMON_CLK)
  struct clk *of_clk_get(struct device_node *np, int index);
  struct clk *of_clk_get_by_name(struct device_node *np, const char *name);
  struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec);
  #else
  static inline struct clk *of_clk_get(struct device_node *np, int index)
  {
-   return NULL;
+   return ERR_PTR(-EINVAL);


So how is this expected to work on platforms (like OMAP) which have 
CONFIG_OF enabled but not CONFIG_COMMON_CLK?


Archit has been seeing issues with failed clk_get's in the omap dss
driver on linux-next.
The clk_gets pass a valid dev pointer and an alias/con-id.

With the $Subject patch, the of_clk_get_by_name() for our builds always
returns a ERR_PTR(-EINVAL).

Even if we do get the right of_clk_get_by_name() built in,
there is another issue on OMAP where in we have CONFIG_OF
enabled/selected by default for all OMAP2+ builds, even when we
*do not* pass a dt blob to the kernel.

So would the below code fail in such cases because it expects a
valid of_node to be populated for a device (which also has clock
information in it)? if CONFIG_OF is set.

struct clk *clk_get(struct device *dev, const char *con_id)
{
const char *dev_id = dev ? dev_name(dev) : NULL;
struct clk *clk;

if (dev) {

Any reason why this isn't
if (dev-of_node) {

clk = of_clk_get_by_name(dev-of_node, con_id);
if (clk  __clk_get(clk))
return clk;
}

return clk_get_sys(dev_id, con_id);
}

regards,
Rajendra





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Re: [PATCH] clk: fix compile for OF !COMMON_CLK

[Rajendra Nayak]

On Tuesday 17 July 2012 06:49 PM, Rajendra Nayak wrote:

struct clk *clk_get(struct device *dev, const char *con_id)
{
 const char *dev_id = dev ? dev_name(dev) : NULL;
 struct clk *clk;

 if (dev) {

 Any reason why this isn't
 if (dev-of_node) {



Or rather,
if (dev  dev-of_node) {
as Archit just pointed out to me.
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Re: [PATCH] clk: fix compile for OF !COMMON_CLK

[Rajendra Nayak]

On Tuesday 17 July 2012 07:16 PM, Rob Herring wrote:

So how is this expected to work on platforms (like OMAP) which have
  CONFIG_OF enabled but not CONFIG_COMMON_CLK?


As I mentioned in my other reply, this really belongs with Shawn's patch
that changes the return value checking from NULL to err values.


ah, I seemed to have missed that. Just had a look at Shawn's patch and
that should work for OMAP too. thanks.
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Re: [RFC][PATCH 1/2] ARM: OMAP4: clock: Add device tree support for AUXCLKs

[Rajendra Nayak]

Hi Tony,

On Thursday 04 April 2013 05:12 AM, Tony Lindgren wrote:
 Hi,
 
[]..

 @@ -1663,6 +1664,40 @@ static struct omap_clk omap44xx_clks[] = {
  CLK(NULL,   cpufreq_ck,   dpll_mpu_ck,   CK_443X),
  };
  
 +static struct clk *scrm_clks[] = {
 +auxclk0_ck,
 +auxclk1_ck,
 +auxclk2_ck,
 +auxclk3_ck,
 +auxclk4_ck,
 +auxclk5_ck,
 +};
 
 Hmm I don't like the idea of specifying the auxclk both in the
 cclock44xx_data.c and in DT..
 
 +static struct clk_onecell_data scrm_data;
 +
 +#ifdef CONFIG_OF
 +int __init omap4_clk_init_dt(void)
 +{
 +struct device_node *np;
 +
 +np = of_find_compatible_node(NULL, NULL, ti,omap4-scrm);
 +if (np) {
 +scrm_data.clks = scrm_clks;
 +scrm_data.clk_num = ARRAY_SIZE(scrm_clks);
 +of_clk_add_provider(np, of_clk_src_onecell_get, scrm_data);
 +}
 +
 +return 0;
 +}
 +
 +#else
 +
 +int __init omap4_clk_init_dt(void)
 +{
 +return 0;
 +}
 +#endif /* CONFIG_OF */
 +
  int __init omap4xxx_clk_init(void)
  {
  u32 cpu_clkflg;
 
 .. and I'm not too keen on adding driver specific stuff to this file.
 
 How about just add a minimal drivers/clk/omap/clk-xyz.c that takes
 the configuration from DT and is based on the binding we already have in
 Documentation/devicetree/bindings/clock/clock-bindings.txt?
 
 Then as we add new bindings there we can drop them from current
 cclock44xx_data.c, no? That is after omap4 is DT only..

The patch just provides an alternative for clkdev mapping in case of DT.
Are you suggesting we move all *clock data* related to auxclks (and eventually
all clocks) into DT?
We have discussed this multiple times in the past, and moving 250 clock nodes
with each needing multiple register offsets, masks, shifts etc into DT makes it
completely un-readable. For me, having a way for devices to reference a clock 
that they
use for a device using DT makes sense, but not moving all clock data into dts 
files.

regards,
Rajendra

 
 Regards,
 
 Tony
 

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Re: [RFC][PATCH 1/2] ARM: OMAP4: clock: Add device tree support for AUXCLKs

[Rajendra Nayak]

[]..

 diff --git a/arch/arm/mach-omap2/board-generic.c 
 b/arch/arm/mach-omap2/board-generic.c
 index 0274ff7..23f2064 100644
 --- a/arch/arm/mach-omap2/board-generic.c
 +++ b/arch/arm/mach-omap2/board-generic.c
 @@ -158,7 +158,7 @@ DT_MACHINE_START(OMAP4_DT, Generic OMAP4 (Flattened 
 Device Tree))
   .init_irq   = omap_gic_of_init,
   .init_machine   = omap_generic_init,
   .init_late  = omap4430_init_late,
 - .init_time  = omap4_local_timer_init,
 + .init_time  = omap4_init_time,
   .dt_compat  = omap4_boards_compat,
   .restart= omap44xx_restart,
  MACHINE_END

[]..
 +#ifdef CONFIG_OF
 +int __init omap4_clk_init_dt(void)
 +{
 + struct device_node *np;
 +
 + np = of_find_compatible_node(NULL, NULL, ti,omap4-scrm);
 + if (np) {
 + scrm_data.clks = scrm_clks;
 + scrm_data.clk_num = ARRAY_SIZE(scrm_clks);
 + of_clk_add_provider(np, of_clk_src_onecell_get, scrm_data);
 + }
 +
 + return 0;
 +}

[]..
 +
 +void __init omap4_init_time(void)
 +{
 + omap4_clk_init_dt();
 + omap4_local_timer_init();
 +}

I guess you did all this because of_clk_add_provider() needs
slab to be initialized. With the below patch[1], now clk inits
happen within .init_timer already, so none of this would
be needed.

[1] http://www.spinics.net/lists/arm-kernel/msg231288.html

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Re: [RFC][PATCH 1/2] ARM: OMAP4: clock: Add device tree support for AUXCLKs

[Rajendra Nayak]

On Thursday 21 March 2013 07:24 PM, Roger Quadros wrote:
 On 03/21/2013 03:08 PM, Rajendra Nayak wrote:
 []..

 diff --git a/arch/arm/mach-omap2/board-generic.c 
 b/arch/arm/mach-omap2/board-generic.c
 index 0274ff7..23f2064 100644
 --- a/arch/arm/mach-omap2/board-generic.c
 +++ b/arch/arm/mach-omap2/board-generic.c
 @@ -158,7 +158,7 @@ DT_MACHINE_START(OMAP4_DT, Generic OMAP4 (Flattened 
 Device Tree))
 .init_irq   = omap_gic_of_init,
 .init_machine   = omap_generic_init,
 .init_late  = omap4430_init_late,
 -   .init_time  = omap4_local_timer_init,
 +   .init_time  = omap4_init_time,
 .dt_compat  = omap4_boards_compat,
 .restart= omap44xx_restart,
  MACHINE_END

 []..
 +#ifdef CONFIG_OF
 +int __init omap4_clk_init_dt(void)
 +{
 +   struct device_node *np;
 +
 +   np = of_find_compatible_node(NULL, NULL, ti,omap4-scrm);
 +   if (np) {
 +   scrm_data.clks = scrm_clks;
 +   scrm_data.clk_num = ARRAY_SIZE(scrm_clks);
 +   of_clk_add_provider(np, of_clk_src_onecell_get, scrm_data);
 +   }
 +
 +   return 0;
 +}

 []..
 +
 +void __init omap4_init_time(void)
 +{
 +   omap4_clk_init_dt();
 +   omap4_local_timer_init();
 +}

 I guess you did all this because of_clk_add_provider() needs
 slab to be initialized. With the below patch[1], now clk inits
 happen within .init_timer already, so none of this would
 be needed.

 [1] http://www.spinics.net/lists/arm-kernel/msg231288.html

 
 Right. I can then call omap4_clk_init_dt() from within omap4xxx_clk_init().
 
 Any comments about the main subject? Does the approach look fine?

It looks fine, except for the fact that I was wondering if the clock
provider needs to restrict itself to SCRM.
Nishant Menon brought up a need for specifying the mpu clock source
from within DT, to be able to use a generic cpufreq driver.
It could be a provider (not specific to scrm, but having only scrm
clocks for now) which we could add clocks as and when we see a need for
them to be specified from DT.

Btw, you need to copy Paul Walmsley for any clock related patches as
he is the OMAP clock maintainer.

 
 cheers,
 -roger
 

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Re: [PATCH 3/8] ARM: dts: omap: Add usb_otg and glue data

[Rajendra Nayak]

[]...



diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt 
b/Documentation/devicetree/bindings/usb/omap-usb.txt
index 29a043e..4688265 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -15,6 +15,7 @@ OMAP MUSB GLUE
 represents PERIPHERAL.
   - power : Should be 50. This signifies the controller can supply upto
 100mA when operating in host mode.
+ - usb-phy : the phandle for the PHY device

  SOC specific device node entry
  usb_otg_hs: usb_otg_hs@4a0ab000 {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts 
b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 3705a81..cb07583 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -107,3 +107,9 @@
 */
ti,pulldowns = 0x03a1c4;
  };
+
+usb_otg_hs {
+   interface_type = 0;
+   mode = 3;
+   power = 50;
+};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index e8ba1c2..afb9ba9 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -59,3 +59,9 @@
  twl_gpio {
ti,use-leds;
  };
+
+usb_otg_hs {
+   interface_type = 0;
+   mode = 3;
+   power = 50;
+};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi 
b/arch/arm/boot/dts/omap3-overo.dtsi
index 89808ce..4b3d157 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -55,3 +55,9 @@
  twl_gpio {
ti,use-leds;
  };
+
+usb_otg_hs {
+   interface_type = 0;
+   mode = 3;
+   power = 50;
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 1acc261..b6472f7 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -397,5 +397,17 @@
ti,timer-alwon;
ti,timer-secure;
};
+
+   usb_otg_hs: usb_otg_hs@480ab000 {
+   compatible = ti,omap3-musb;
+   reg = 0x480ab000 0x1000;
+   interrupts = 0 92 0x4, 0 93 0x4;
+   interrupt-names = mc, dma;
+   ti,hwmods = usb_otg_hs;
+   usb-phy = usb2_phy;
+   multipoint = 1;
+   num_eps = 16;
+   ram_bits = 12;


Where are these bindings documented? The general convention is to use
a '-' for property names and not '_'


+   };
};
  };
diff --git a/arch/arm/boot/dts/omap4-panda.dts 
b/arch/arm/boot/dts/omap4-panda.dts
index 4122efe..612c9bb 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -206,3 +206,9 @@
  twl_usb_comparator {
usb-supply = vusb;
  };
+
+usb_otg_hs {
+   interface_type = 1;
+   mode = 3;
+   power = 50;
+};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 43e5258..582d7ee 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -428,3 +428,9 @@
  twl_usb_comparator {
usb-supply = vusb;
  };
+
+usb_otg_hs {
+   interface_type = 1;
+   mode = 3;
+   power = 50;
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index c829d7e..5171739 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -542,5 +542,18 @@
reg-names = control_dev_conf, otghs_control;
ti,type = 1;
};
+
+   usb_otg_hs: usb_otg_hs@4a0ab000 {
+   compatible = ti,omap4-musb;
+   reg = 0x4a0ab000 0x7ff;
+   interrupts = 0 92 0x4, 0 93 0x4;
+   interrupt-names = mc, dma;
+   ti,hwmods = usb_otg_hs;
+   usb-phy = usb2_phy;
+   multipoint = 1;
+   num_eps = 16;
+   ram_bits = 12;
+   ti,has-mailbox;
+   };
};
  };
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index ed0bc95..398d2c3 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -67,7 +67,7 @@
#interrupt-cells = 1;
};

-   twl4030-usb {
+   usb2_phy: twl4030-usb {
compatible = ti,twl4030-usb;
interrupts = 10, 4;
usb1v5-supply = vusb1v5;



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Re: [PATCH] MMC/omap_hsmmc: handle failure of regulator_get better.

[Rajendra Nayak]

On Monday 30 July 2012 05:42 AM, NeilBrown wrote:


1/ if regulator_get fails, return an error.  This is important
if it failed with EPROBE_DEFER, as the probe needs to be
deferred.

2/ Don't set .set_power until the regulator has been found, or
the deferred probe will not bother calling omap_hsmmc_reg_get().


I am not very sure, but aren't the data structures re-allocated on a
re-probe (after it was deferred) causing .set_power to be lost anyway?



Signed-off-by: NeilBrownne...@suse.de

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 389a3ee..f052c29 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -299,12 +299,12 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host 
*host)
struct regulator *reg;
int ocr_value = 0;

-   mmc_slot(host).set_power = omap_hsmmc_set_power;
-
reg = regulator_get(host-dev, vmmc);
if (IS_ERR(reg)) {
dev_dbg(host-dev, vmmc regulator missing\n);
+   return PTR_ERR(reg);
} else {
+   mmc_slot(host).set_power = omap_hsmmc_set_power;
host-vcc = reg;
ocr_value = mmc_regulator_get_ocrmask(reg);
if (!mmc_slot(host).ocr_mask) {


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Re: [PATCH] MMC/omap_hsmmc: handle failure of regulator_get better.

[Rajendra Nayak]

On Monday 30 July 2012 11:54 AM, NeilBrown wrote:

On Mon, 30 Jul 2012 10:50:36 +0530 Rajendra Nayakrna...@ti.com  wrote:


On Monday 30 July 2012 05:42 AM, NeilBrown wrote:


1/ if regulator_get fails, return an error.  This is important
 if it failed with EPROBE_DEFER, as the probe needs to be
 deferred.

2/ Don't set .set_power until the regulator has been found, or
 the deferred probe will not bother calling omap_hsmmc_reg_get().


I am not very sure, but aren't the data structures re-allocated on a
re-probe (after it was deferred) causing .set_power to be lost anyway?



Apparently not - as I needed to make that change before the re-probe would
work.

Looking at the code to remind myself:

#define mmc_slot(host)  (host-pdata-slots[host-slot_id])

so the slot is inside the platform data which is allocated in
omap_hsmmc_init_one, called from omap_hsmmc_init.
This is all prior to the probing of the device.

So no: once set_power is set, it stays set.


Thanks for the explanation, makes sense.

Acked-by: Rajendra Nayak rna...@ti.com

Btw, is the support for re-probe/deferred probe already merged
now? or are you testing this with some out of tree patches.



Thanks,
NeilBrown



Signed-off-by: NeilBrownne...@suse.de

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 389a3ee..f052c29 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -299,12 +299,12 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host 
*host)
struct regulator *reg;
int ocr_value = 0;

-   mmc_slot(host).set_power = omap_hsmmc_set_power;
-
reg = regulator_get(host-dev, vmmc);
if (IS_ERR(reg)) {
dev_dbg(host-dev, vmmc regulator missing\n);
+   return PTR_ERR(reg);
} else {
+   mmc_slot(host).set_power = omap_hsmmc_set_power;
host-vcc = reg;
ocr_value = mmc_regulator_get_ocrmask(reg);
if (!mmc_slot(host).ocr_mask) {




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Re: [PATCH] regulator: twl-regulator: fix up VINTANA1/VINTANA2

[Rajendra Nayak]

On Wednesday 15 August 2012 03:40 AM, Aaro Koskinen wrote:

It seems commit 2098e95ce9bb039ff2e7bf836df358d18a176139 (regulator: twl:
adapt twl-regulator driver to dt) accidentally deleted VINTANA1. Also
the same commit defines VINTANA2 twice with TWL4030_ADJUSTABLE_LDO and
TWL4030_FIXED_LDO. This patch changes the fixed one to be VINTANA1.


Thanks for the fix, the commit does seem to have mixed up things.

Acked-by: Rajendra Nayak rna...@ti.com
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Re: [PATCH v1 01/11] drivers: usb: otg: add a new driver for omap usb2 phy

[Rajendra Nayak]

diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt 
b/Documentation/devicetree/bindings/usb/omap-usb.txt
new file mode 100644
index 000..80a28c9
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -0,0 +1,16 @@
+OMAP USB PHY
+
+OMAP USB2 PHY
+
+Required properties:
+ - compatible: Should be ti,omap-usb2
+ - reg : Address and length of the register set for the device. Also
+add the address of control module dev conf register until a driver for
+control module is added
+
+This is usually a subnode of ocp2scp to which it is connected.
+
+usb2phy@0x4a0ad080 {
+   compatible = ti,omap-usb2;
+   reg =0x4a0ad080 0x58;


Don;t you need a 'ti,hwmods' entry for this one?


--- /dev/null
+++ b/drivers/usb/otg/omap-usb2.c
@@ -0,0 +1,273 @@
+/*
+ * omap-usb2.c - USB PHY, talking to musb controller in OMAP.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com


Copyright (C) 2012? Same for the couple of headers below.


+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Author: Kishon Vijay Abraham Ikis...@ti.com
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+



+
+static int __devinit omap_usb2_probe(struct platform_device *pdev)
+{
+   struct omap_usb *phy;
+   struct usb_otg  *otg;
+   struct resource *res;
+
+   phy = devm_kzalloc(pdev-dev, sizeof(*phy), GFP_KERNEL);
+   if (!phy) {
+   dev_err(pdev-dev, unable to allocate memory for USB2 PHY\n);
+   return -ENOMEM;
+   }
+
+   otg = devm_kzalloc(pdev-dev, sizeof(*otg), GFP_KERNEL);
+   if (!otg) {
+   dev_err(pdev-dev, unable to allocate memory for USB OTG\n);
+   return -ENOMEM;
+   }
+
+   phy-dev =pdev-dev;
+
+   phy-phy.dev = phy-dev;
+   phy-phy.label   = omap-usb2;
+   phy-phy.set_suspend = omap_usb2_suspend;
+   phy-phy.otg = otg;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+
+   phy-control_dev_conf = devm_request_and_ioremap(pdev-dev, res);
+   if (phy-control_dev_conf == NULL) {
+   dev_err(pdev-dev, Failed to obtain io memory\n);
+   return -ENXIO;
+   }
+
+   phy-is_suspended= 1;
+   omap_usb_phy_power(phy, 0);
+
+   otg-set_host= omap_usb_set_host;
+   otg-set_peripheral  = omap_usb_set_peripheral;
+   otg-set_vbus= omap_usb_set_vbus;
+   otg-start_srp   = omap_usb_start_srp;
+   otg-phy =phy-phy;
+
+   phy-wkupclk = devm_clk_get(phy-dev, usb_phy_cm_clk32k);


Why not just use clk_get()? What does devm_clk_get() do?


+   if (IS_ERR(phy-wkupclk)) {
+   dev_err(pdev-dev, unable to get usb_phy_cm_clk32k\n);
+   return PTR_ERR(phy-wkupclk);
+   }
+   clk_prepare(phy-wkupclk);


Ideally clk_prepare() is an extension of clk_enable() and is expected
to be used that way. Not to be clubbed with clk_get(). Same with
clk_unprepare(). Do you do a clk_enable()/_disable() in interrupt/
atomic context?


+
+   usb_add_phy(phy-phy, USB_PHY_TYPE_USB2);
+
+   platform_set_drvdata(pdev, phy);
+
+   pm_runtime_enable(phy-dev);
+
+   return 0;
+}
+
+static int __devexit omap_usb2_remove(struct platform_device *pdev)
+{
+   struct omap_usb *phy = platform_get_drvdata(pdev);
+
+   clk_unprepare(phy-wkupclk);
+   usb_remove_phy(phy-phy);
+   platform_set_drvdata(pdev, NULL);
+
+   return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int omap_usb2_runtime_suspend(struct device *dev)
+{
+   struct platform_device  *pdev = to_platform_device(dev);
+   struct omap_usb *phy = platform_get_drvdata(pdev);
+
+   clk_disable(phy-wkupclk);
+
+   return 0;
+}
+
+static int omap_usb2_runtime_resume(struct device *dev)
+{
+   struct platform_device  *pdev = to_platform_device(dev);
+   struct omap_usb *phy = platform_get_drvdata(pdev);
+
+   clk_enable(phy-wkupclk);
+
+   return 0;
+}
+
+static const struct dev_pm_ops omap_usb2_pm_ops = {
+   SET_RUNTIME_PM_OPS(omap_usb2_runtime_suspend, omap_usb2_runtime_resume,
+   NULL)
+};
+
+#define DEV_PM_OPS (omap_usb2_pm_ops)
+#else
+#define DEV_PM_OPS NULL
+#endif
+
+#ifdef CONFIG_OF
+static const struct of_device_id omap_usb2_id_table[] = {
+   { .compatible = ti,omap-usb2 },
+   {}
+};
+MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
+#else
+#define omap_usb2_id_table NULL;
+#endif
+
+static 

Re: [PATCH v1 05/11] drivers: usb: twl6030: Add dt support for twl6030 usb

[Rajendra Nayak]

On Thursday 28 June 2012 05:21 PM, Kishon Vijay Abraham I wrote:

Add device tree support for twl6030 usb driver.
Update the Documentation with device tree binding information.

Signed-off-by: Kishon Vijay Abraham Ikis...@ti.com
---
  .../devicetree/bindings/usb/twl-usb.txt|   18 
  drivers/usb/otg/twl6030-usb.c  |   45 ++--
  2 files changed, 50 insertions(+), 13 deletions(-)
  create mode 100644 Documentation/devicetree/bindings/usb/twl-usb.txt

diff --git a/Documentation/devicetree/bindings/usb/twl-usb.txt 
b/Documentation/devicetree/bindings/usb/twl-usb.txt
new file mode 100644
index 000..f293271
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/twl-usb.txt
@@ -0,0 +1,18 @@
+USB COMPARATOR OF TWL CHIPS
+
+TWL6030 USB COMPARATOR
+ - compatible : Should be ti,twl6030-usb
+ - interrupts : Two interrupt numbers to the cpu should be specified. First
+   interrupt number is the otg interrupt number that raises ID interrupts when
+   the controller has to act as host and the second interrupt number is the
+   usb interrupt number that raises VBUS interrupts when the controller has to
+   act as device
+ - regulator :supply-name  can be vusb or ldousb
+ -supply-name-supply : phandle to the regulator device tree node
+
+twl6030-usb {
+   compatible = ti,twl6030-usb;
+   interrupts =  4 10;
+   regulator = vusb;
+   vusb-supply =vusb;


This doesn't seem right. Why do you ned a 'regulator' string along
with the phandle?


+};
diff --git a/drivers/usb/otg/twl6030-usb.c b/drivers/usb/otg/twl6030-usb.c
index 6a361d2..20b7abe 100644
--- a/drivers/usb/otg/twl6030-usb.c
+++ b/drivers/usb/otg/twl6030-usb.c
@@ -105,7 +105,7 @@ struct twl6030_usb {
u8  asleep;
boolirq_enabled;
boolvbus_enable;
-   unsigned long   features;
+   const char  *regulator;
  };

  #define   comparator_to_twl(x) container_of((x), struct twl6030_usb, 
comparator)
@@ -153,13 +153,6 @@ static int twl6030_start_srp(struct phy_companion 
*comparator)

  static int twl6030_usb_ldo_init(struct twl6030_usb *twl)
  {
-   char *regulator_name;
-
-   if (twl-features  TWL6025_SUBCLASS)
-   regulator_name = ldousb;
-   else
-   regulator_name = vusb;
-
/* Set to OTG_REV 1.3 and turn on the ID_WAKEUP_COMP */
twl6030_writeb(twl, TWL6030_MODULE_ID0 , 0x1, TWL6030_BACKUP_REG);

@@ -169,7 +162,7 @@ static int twl6030_usb_ldo_init(struct twl6030_usb *twl)
/* Program MISC2 register and set bit VUSB_IN_VBAT */
twl6030_writeb(twl, TWL6030_MODULE_ID0 , 0x10, TWL6030_MISC2);

-   twl-usb3v3 = regulator_get(twl-dev, regulator_name);
+   twl-usb3v3 = regulator_get(twl-dev, twl-regulator);
if (IS_ERR(twl-usb3v3))
return -ENODEV;

@@ -324,9 +317,9 @@ static int __devinit twl6030_usb_probe(struct 
platform_device *pdev)
  {
struct twl6030_usb  *twl;
int status, err;
-   struct twl4030_usb_data *pdata;
-   struct device *dev =pdev-dev;
-   pdata = dev-platform_data;
+   struct device_node  *np = pdev-dev.of_node;
+   struct device   *dev =pdev-dev;
+   struct twl4030_usb_data *pdata = dev-platform_data;

twl = devm_kzalloc(dev, sizeof *twl, GFP_KERNEL);
if (!twl)
@@ -335,13 +328,28 @@ static int __devinit twl6030_usb_probe(struct 
platform_device *pdev)
twl-dev =pdev-dev;
twl-irq1= platform_get_irq(pdev, 0);
twl-irq2= platform_get_irq(pdev, 1);
-   twl-features= pdata-features;
twl-linkstat= OMAP_MUSB_UNKNOWN;

twl-comparator.set_vbus = twl6030_set_vbus;
twl-comparator.start_srp= twl6030_start_srp;
omap_usb2_set_comparator(twl-comparator);

+   if (np) {
+   err = of_property_read_string(np, regulator,twl-regulator);
+   if (err  0) {
+   dev_err(pdev-dev, unable to get regulator\n);
+   return err;
+   }


Isn't there a better way for the driver to know which supply to use 
instead of DT passing the supply name?


regards,
Rajendra


+   } else if (pdata) {
+   if (pdata-features  TWL6025_SUBCLASS)
+   twl-regulator = ldousb;
+   else
+   twl-regulator = vusb;
+   } else {
+   dev_err(pdev-dev, twl6030 initialized without pdata\n);
+   return -EINVAL;
+   }
+
/* init spinlock for workqueue */
spin_lock_init(twl-lock);

@@ -403,12 +411,23 @@ static int __exit twl6030_usb_remove(struct 
platform_device *pdev)
return 0;
  }

+#ifdef CONFIG_OF
+static const struct of_device_id twl6030_usb_id_table[] = {
+   { .compatible = 

Re: [PATCH v1 07/11] drivers: usb: twl4030: Add device tree support for twl4030 usb

[Rajendra Nayak]

On Thursday 28 June 2012 05:21 PM, Kishon Vijay Abraham I wrote:

Add device tree support for twl6030 usb driver.


twl4030?


Update the Documentation with device tree binding information.

Signed-off-by: Kishon Vijay Abraham Ikis...@ti.com
---
  .../devicetree/bindings/usb/twl-usb.txt|   19 +
  drivers/usb/otg/twl4030-usb.c  |   28 +++
  2 files changed, 41 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/twl-usb.txt 
b/Documentation/devicetree/bindings/usb/twl-usb.txt
index f293271..2d069e4 100644
--- a/Documentation/devicetree/bindings/usb/twl-usb.txt
+++ b/Documentation/devicetree/bindings/usb/twl-usb.txt
@@ -16,3 +16,22 @@ twl6030-usb {
regulator = vusb;
vusb-supply =vusb;
  };
+
+TWL4030 USB PHY AND COMPARATOR
+ - compatible : Should be ti,twl4030-usb
+ - interrupts : The interrupt numbers to the cpu should be specified. First
+   interrupt number is the otg interrupt number that raises ID interrupts
+   and VBUS interrupts. The second interrupt number is optional.
+ -supply-name-supply : phandle to the regulator device tree node.
+supply-name  should be vusb1v5, vusb1v8 and vusb3v1
+ - usb_mode : The mode used by the phy to connect to the controller. 1
+   specifies ULPI mode and 2 specifies CEA2011_3PIN mode.


Are these standard usb phy modes or something specific to the twl4030
usb phy?


+
+twl4030-usb {
+   compatible = ti,twl4030-usb;
+   interrupts =  10 4;
+   vusb1v5-supply =vusb1v5;
+   vusb1v8-supply =vusb1v8;
+   vusb3v1-supply =vusb3v1;
+   usb_mode =1;
+};
diff --git a/drivers/usb/otg/twl4030-usb.c b/drivers/usb/otg/twl4030-usb.c
index 523cad5..a4e7434 100644
--- a/drivers/usb/otg/twl4030-usb.c
+++ b/drivers/usb/otg/twl4030-usb.c
@@ -585,23 +585,28 @@ static int __devinit twl4030_usb_probe(struct 
platform_device *pdev)
struct twl4030_usb  *twl;
int status, err;
struct usb_otg  *otg;
-
-   if (!pdata) {
-   dev_dbg(pdev-dev, platform_data not available\n);
-   return -EINVAL;
-   }
+   struct device_node  *np = pdev-dev.of_node;

twl = devm_kzalloc(pdev-dev, sizeof *twl, GFP_KERNEL);
if (!twl)
return -ENOMEM;

+   if (np)
+   of_property_read_u32(np, usb_mode,
+   (enum twl4030_usb_mode *)twl-usb_mode);
+   else if (pdata)
+   twl-usb_mode = pdata-usb_mode;
+   else {
+   dev_err(pdev-dev, twl4030 initialized without pdata\n);
+   return -EINVAL;
+   }
+
otg = devm_kzalloc(pdev-dev, sizeof *otg, GFP_KERNEL);
if (!otg)
return -ENOMEM;

twl-dev =pdev-dev;
twl-irq = platform_get_irq(pdev, 0);
-   twl-usb_mode= pdata-usb_mode;
twl-vbus_supplied   = false;
twl-asleep  = 1;
twl-linkstat= OMAP_MUSB_UNKNOWN;
@@ -690,12 +695,23 @@ static int __exit twl4030_usb_remove(struct 
platform_device *pdev)
return 0;
  }

+#ifdef CONFIG_OF
+static const struct of_device_id twl4030_usb_id_table[] = {
+   { .compatible = ti,twl4030-usb },
+   {}
+};
+MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
+#else
+#define twl4030_usb_id_table NULL
+#endif
+
  static struct platform_driver twl4030_usb_driver = {
.probe  = twl4030_usb_probe,
.remove = __exit_p(twl4030_usb_remove),
.driver = {
.name   = twl4030_usb,
.owner  = THIS_MODULE,
+   .of_match_table = twl4030_usb_id_table,


use of_match_ptr().


},
  };



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Re: [PATCH v1 08/11] arm/dts: Add twl4030-usb data

[Rajendra Nayak]

On Thursday 28 June 2012 05:21 PM, Kishon Vijay Abraham I wrote:

Add twl4030-usb data node in twl4030 device tree file.

Signed-off-by: Kishon Vijay Abraham Ikis...@ti.com
---
  arch/arm/boot/dts/twl4030.dtsi |   21 +
  1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index 22f4d13..66534a3 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -37,6 +37,18 @@
regulator-max-microvolt =315;
};

+   vusb1v5: regulator@3 {
+   compatible = ti,twl4030-vusb1v5;
+   };


These @3, @4 are actually wrong since the node do
not have a 'reg' property in it. This was commented on
by David Brown on my original series which added this but
it somehow slipped through the cracks. I understand that
you would have looked up what existed in the file and
extended, but what already exists in the file needs to
be fixed up too. I'll send in a patch to fix those up.

regards,
Rajendra


+
+   vusb1v8: regulator@4 {
+   compatible = ti,twl4030-vusb1v8;
+   };
+
+   vusb3v1: regulator@5 {
+   compatible = ti,twl4030-vusb3v1;
+   };
+
twl_gpio: gpio {
compatible = ti,twl4030-gpio;
gpio-controller;
@@ -44,4 +56,13 @@
interrupt-controller;
#interrupt-cells =1;
};
+
+   twl4030-usb {
+   compatible = ti,twl4030-usb;
+   interrupts =  10 4;
+   usb1v5-supply =vusb1v5;
+   usb1v8-supply =vusb1v8;
+   usb3v1-supply =vusb3v1;
+   usb_mode =1;
+   };
  };


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Re: [PATCH v1 10/11] arm/dts: omap: Add usb_otg and glue data

[Rajendra Nayak]

On Thursday 28 June 2012 05:21 PM, Kishon Vijay Abraham I wrote:

Add usb otg data node in omap4/omap3 device tree file. Also update
the node with board specific setting in omapx-board.dts file.

Signed-off-by: Kishon Vijay Abraham Ikis...@ti.com
---
  arch/arm/boot/dts/omap3-beagle.dts |6 ++
  arch/arm/boot/dts/omap3-evm.dts|6 ++
  arch/arm/boot/dts/omap3.dtsi   |8 
  arch/arm/boot/dts/omap4-panda.dts  |6 ++
  arch/arm/boot/dts/omap4-sdp.dts|6 ++
  arch/arm/boot/dts/omap4.dtsi   |8 
  6 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap3-beagle.dts 
b/arch/arm/boot/dts/omap3-beagle.dts
index 5b4506c..f3d7076 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -67,3 +67,9 @@
  mmc3 {
status = disable;
  };
+
+usb_otg_hs {
+   interface_type =0;
+   mode =3;
+   power =50;
+};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 2eee16e..8963b3d 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -18,3 +18,9 @@
reg =0x8000 0x1000; /* 256 MB */
};
  };
+
+usb_otg_hs {
+   interface_type =0;
+   mode =3;
+   power =50;
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 99474fa..2f565d6 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -215,5 +215,13 @@
compatible = ti,omap3-hsmmc;
ti,hwmods = mmc3;
};
+
+   usb_otg_hs: usb_otg_hs@4a0ab000 {
+   compatible = ti,musb-omap2430;


this compatible doesn't seem right in omap3.dtsi. Same with
the below entry in omap4.dtsi.
See other IP blocks which are reused across OMAP2/3/4 on
how the compatible for those are handled.


+   ti,hwmods = usb_otg_hs;
+   multipoint =1;
+   num_eps =16;
+   ram_bits =12;
+   };
};
  };
diff --git a/arch/arm/boot/dts/omap4-panda.dts 
b/arch/arm/boot/dts/omap4-panda.dts
index 1efe0c5..0825fa7 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -89,3 +89,9 @@
ti,non-removable;
bus-width =4;
  };
+
+usb_otg_hs {
+   interface_type =1;
+   mode =3;
+   power =50;
+};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index d08c4d1..5244d51 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -158,3 +158,9 @@
bus-width =4;
ti,non-removable;
  };
+
+usb_otg_hs {
+   interface_type =1;
+   mode =3;
+   power =50;
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 4d2dcc1..bc7b3c3 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -285,5 +285,13 @@
0x4a002300 0x1;
};
};
+
+   usb_otg_hs: usb_otg_hs@4a0ab000 {
+   compatible = ti,musb-omap2430;
+   ti,hwmods = usb_otg_hs;
+   multipoint =1;
+   num_eps =16;
+   ram_bits =12;
+   };
};
  };


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Re: [PATCH v1 11/11] arm: omap: phy: remove unused functions from omap-phy-internal.c

[Rajendra Nayak]

On Thursday 28 June 2012 05:21 PM, Kishon Vijay Abraham I wrote:

All the unnessary functions in omap-phy-internal is removed.
These functionality are now handled by omap-usb2 phy driver.

Cc: Felipe Balbiba...@ti.com
Signed-off-by: Kishon Vijay Abraham Ikis...@ti.com
Acked-by: Tony Lindgrent...@atomide.com
---
  arch/arm/mach-omap2/omap_phy_internal.c |  138 ---
  arch/arm/mach-omap2/twl-common.c|5 -
  arch/arm/mach-omap2/usb-musb.c  |3 -
  3 files changed, 0 insertions(+), 146 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_phy_internal.c 
b/arch/arm/mach-omap2/omap_phy_internal.c
index 4c90477..0c610b4 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -31,144 +31,6 @@
  #includeplat/usb.h
  #include control.h

-/* OMAP control module register for UTMI PHY */
-#define CONTROL_DEV_CONF   0x300
-#define PHY_PD 0x1
-
-#define USBOTGHS_CONTROL   0x33c
-#defineAVALID  BIT(0)
-#defineBVALID  BIT(1)
-#defineVBUSVALID   BIT(2)
-#defineSESSEND BIT(3)
-#defineIDDIG   BIT(4)
-
-static struct clk *phyclk, *clk48m, *clk32k;
-static void __iomem *ctrl_base;
-static int usbotghs_control;
-
-int omap4430_phy_init(struct device *dev)
-{
-   ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
-   if (!ctrl_base) {
-   pr_err(control module ioremap failed\n);
-   return -ENOMEM;
-   }
-   /* Power down the phy */
-   __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);


Just checking, but I hope your new driver handles this too.
You might not see any issues with it now, but not doing this could
gate OMAP hitting low power in idle.

regards,
Rajendra


-
-   if (!dev) {
-   iounmap(ctrl_base);
-   return 0;
-   }
-
-   phyclk = clk_get(dev, ocp2scp_usb_phy_ick);
-   if (IS_ERR(phyclk)) {
-   dev_err(dev, cannot clk_get ocp2scp_usb_phy_ick\n);
-   iounmap(ctrl_base);
-   return PTR_ERR(phyclk);
-   }
-
-   clk48m = clk_get(dev, ocp2scp_usb_phy_phy_48m);
-   if (IS_ERR(clk48m)) {
-   dev_err(dev, cannot clk_get ocp2scp_usb_phy_phy_48m\n);
-   clk_put(phyclk);
-   iounmap(ctrl_base);
-   return PTR_ERR(clk48m);
-   }
-
-   clk32k = clk_get(dev, usb_phy_cm_clk32k);
-   if (IS_ERR(clk32k)) {
-   dev_err(dev, cannot clk_get usb_phy_cm_clk32k\n);
-   clk_put(phyclk);
-   clk_put(clk48m);
-   iounmap(ctrl_base);
-   return PTR_ERR(clk32k);
-   }
-   return 0;
-}
-
-int omap4430_phy_set_clk(struct device *dev, int on)
-{
-   static int state;
-
-   if (on  !state) {
-   /* Enable the phy clocks */
-   clk_enable(phyclk);
-   clk_enable(clk48m);
-   clk_enable(clk32k);
-   state = 1;
-   } else if (state) {
-   /* Disable the phy clocks */
-   clk_disable(phyclk);
-   clk_disable(clk48m);
-   clk_disable(clk32k);
-   state = 0;
-   }
-   return 0;
-}
-
-int omap4430_phy_power(struct device *dev, int ID, int on)
-{
-   if (on) {
-   if (ID)
-   /* enable VBUS valid, IDDIG groung */
-   __raw_writel(AVALID | VBUSVALID, ctrl_base +
-   USBOTGHS_CONTROL);
-   else
-   /*
-* Enable VBUS Valid, AValid and IDDIG
-* high impedance
-*/
-   __raw_writel(IDDIG | AVALID | VBUSVALID,
-   ctrl_base + USBOTGHS_CONTROL);
-   } else {
-   /* Enable session END and IDIG to high impedance. */
-   __raw_writel(SESSEND | IDDIG, ctrl_base +
-   USBOTGHS_CONTROL);
-   }
-   return 0;
-}
-
-int omap4430_phy_suspend(struct device *dev, int suspend)
-{
-   if (suspend) {
-   /* Disable the clocks */
-   omap4430_phy_set_clk(dev, 0);
-   /* Power down the phy */
-   __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-
-   /* save the context */
-   usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL);
-   } else {
-   /* Enable the internel phy clcoks */
-   omap4430_phy_set_clk(dev, 1);
-   /* power on the phy */
-   if (__raw_readl(ctrl_base + CONTROL_DEV_CONF)  PHY_PD) {
-   __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-   mdelay(200);
-   

Re: [PATCH v1 05/11] drivers: usb: twl6030: Add dt support for twl6030 usb

[Rajendra Nayak]

On Tuesday 10 July 2012 11:58 AM, ABRAHAM, KISHON VIJAY wrote:

Hi,

On Tue, Jul 10, 2012 at 11:28 AM, Rajendra Nayakrna...@ti.com  wrote:

On Thursday 28 June 2012 05:21 PM, Kishon Vijay Abraham I wrote:


Add device tree support for twl6030 usb driver.
Update the Documentation with device tree binding information.

Signed-off-by: Kishon Vijay Abraham Ikis...@ti.com
---
   .../devicetree/bindings/usb/twl-usb.txt|   18 
   drivers/usb/otg/twl6030-usb.c  |   45
++--
   2 files changed, 50 insertions(+), 13 deletions(-)
   create mode 100644 Documentation/devicetree/bindings/usb/twl-usb.txt

diff --git a/Documentation/devicetree/bindings/usb/twl-usb.txt
b/Documentation/devicetree/bindings/usb/twl-usb.txt
new file mode 100644
index 000..f293271
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/twl-usb.txt
@@ -0,0 +1,18 @@
+USB COMPARATOR OF TWL CHIPS
+
+TWL6030 USB COMPARATOR
+ - compatible : Should be ti,twl6030-usb
+ - interrupts : Two interrupt numbers to the cpu should be specified.
First
+   interrupt number is the otg interrupt number that raises ID interrupts
when
+   the controller has to act as host and the second interrupt number is
the
+   usb interrupt number that raises VBUS interrupts when the controller
has to
+   act as device
+ - regulator :supply-name   can be vusb or ldousb
+ -supply-name-supply : phandle to the regulator device tree node
+
+twl6030-usb {
+   compatible = ti,twl6030-usb;
+   interrupts =   4 10;
+   regulator = vusb;
+   vusb-supply =vusb;



This doesn't seem right. Why do you ned a 'regulator' string along
with the phandle?


The original code was something like
if (twl-features  TWL6025_SUBCLASS)
regulator_name = ldousb;
else
regulator_name = vusb;

I wasn't sure how to handle this *TWL6025_SUBCLASS* stuff.




+};
diff --git a/drivers/usb/otg/twl6030-usb.c b/drivers/usb/otg/twl6030-usb.c
index 6a361d2..20b7abe 100644
--- a/drivers/usb/otg/twl6030-usb.c
+++ b/drivers/usb/otg/twl6030-usb.c
@@ -105,7 +105,7 @@ struct twl6030_usb {
 u8  asleep;
 boolirq_enabled;
 boolvbus_enable;
-   unsigned long   features;
+   const char  *regulator;
   };

   #define   comparator_to_twl(x) container_of((x), struct twl6030_usb,
comparator)
@@ -153,13 +153,6 @@ static int twl6030_start_srp(struct phy_companion
*comparator)

   static int twl6030_usb_ldo_init(struct twl6030_usb *twl)
   {
-   char *regulator_name;
-
-   if (twl-features   TWL6025_SUBCLASS)

-   regulator_name = ldousb;
-   else
-   regulator_name = vusb;
-
 /* Set to OTG_REV 1.3 and turn on the ID_WAKEUP_COMP */
 twl6030_writeb(twl, TWL6030_MODULE_ID0 , 0x1, TWL6030_BACKUP_REG);

@@ -169,7 +162,7 @@ static int twl6030_usb_ldo_init(struct twl6030_usb
*twl)
 /* Program MISC2 register and set bit VUSB_IN_VBAT */
 twl6030_writeb(twl, TWL6030_MODULE_ID0 , 0x10, TWL6030_MISC2);

-   twl-usb3v3 = regulator_get(twl-dev, regulator_name);
+   twl-usb3v3 = regulator_get(twl-dev, twl-regulator);
 if (IS_ERR(twl-usb3v3))
 return -ENODEV;

@@ -324,9 +317,9 @@ static int __devinit twl6030_usb_probe(struct
platform_device *pdev)
   {
 struct twl6030_usb  *twl;
 int status, err;
-   struct twl4030_usb_data *pdata;
-   struct device *dev =pdev-dev;

-   pdata = dev-platform_data;
+   struct device_node  *np = pdev-dev.of_node;
+   struct device   *dev =pdev-dev;

+   struct twl4030_usb_data *pdata = dev-platform_data;

 twl = devm_kzalloc(dev, sizeof *twl, GFP_KERNEL);
 if (!twl)
@@ -335,13 +328,28 @@ static int __devinit twl6030_usb_probe(struct
platform_device *pdev)
 twl-dev=pdev-dev;

 twl-irq1   = platform_get_irq(pdev, 0);
 twl-irq2   = platform_get_irq(pdev, 1);
-   twl-features   = pdata-features;
 twl-linkstat   = OMAP_MUSB_UNKNOWN;

 twl-comparator.set_vbus= twl6030_set_vbus;
 twl-comparator.start_srp   = twl6030_start_srp;
 omap_usb2_set_comparator(twl-comparator);

+   if (np) {
+   err = of_property_read_string(np,
regulator,twl-regulator);

+   if (err   0) {
+   dev_err(pdev-dev, unable to get regulator\n);
+   return err;
+   }



Isn't there a better way for the driver to know which supply to use instead
of DT passing the supply name?


The problem I see is this same driver is used for twl6030 and twl6025
and the regulator used is different for these two chips (And I think


hmm, so based on what chip is used on a board, shouldn't the board dts
file just map the right 

Re: [PATCH v1 01/11] drivers: usb: otg: add a new driver for omap usb2 phy

[Rajendra Nayak]

+
+static int __devinit omap_usb2_probe(struct platform_device *pdev)
+{
+   struct omap_usb *phy;
+   struct usb_otg  *otg;
+   struct resource *res;
+
+   phy = devm_kzalloc(pdev-dev, sizeof(*phy), GFP_KERNEL);
+   if (!phy) {
+   dev_err(pdev-dev, unable to allocate memory for USB2
PHY\n);
+   return -ENOMEM;
+   }
+
+   otg = devm_kzalloc(pdev-dev, sizeof(*otg), GFP_KERNEL);
+   if (!otg) {
+   dev_err(pdev-dev, unable to allocate memory for USB
OTG\n);
+   return -ENOMEM;
+   }
+
+   phy-dev=pdev-dev;

+
+   phy-phy.dev= phy-dev;
+   phy-phy.label  = omap-usb2;
+   phy-phy.set_suspend= omap_usb2_suspend;
+   phy-phy.otg= otg;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+
+   phy-control_dev_conf = devm_request_and_ioremap(pdev-dev, res);
+   if (phy-control_dev_conf == NULL) {
+   dev_err(pdev-dev, Failed to obtain io memory\n);
+   return -ENXIO;
+   }
+
+   phy-is_suspended   = 1;
+   omap_usb_phy_power(phy, 0);
+
+   otg-set_host   = omap_usb_set_host;
+   otg-set_peripheral = omap_usb_set_peripheral;
+   otg-set_vbus   = omap_usb_set_vbus;
+   otg-start_srp  = omap_usb_start_srp;
+   otg-phy=phy-phy;

+
+   phy-wkupclk = devm_clk_get(phy-dev, usb_phy_cm_clk32k);



Why not just use clk_get()? What does devm_clk_get() do?

It just associates the clk with the device. So whenever the the driver
gets detached, the devres will take care to do a clk_put() of the
clock.


ok, makes sense.





+   if (IS_ERR(phy-wkupclk)) {
+   dev_err(pdev-dev, unable to get usb_phy_cm_clk32k\n);
+   return PTR_ERR(phy-wkupclk);
+   }
+   clk_prepare(phy-wkupclk);



Ideally clk_prepare() is an extension of clk_enable() and is expected
to be used that way. Not to be clubbed with clk_get(). Same with
clk_unprepare(). Do you do a clk_enable()/_disable() in interrupt/
atomic context?


Currently it is called from a work queue. But Felipe wanted to remove
those work_queue from omap2430 glue. Then this would be called from
atomic context.
A query for you here. If pm_runtime_get_sync() is called in interrupt
context, will runtime resume of that device will also be called in the
same context?


Yes, it would. You also need to then tell the runtime pm framework about
it by calling a pm_runtime_irq_safe() api I guess.

regards,
Rajendra







+
+   usb_add_phy(phy-phy, USB_PHY_TYPE_USB2);
+
+   platform_set_drvdata(pdev, phy);
+
+   pm_runtime_enable(phy-dev);
+
+   return 0;
+}
+
+static int __devexit omap_usb2_remove(struct platform_device *pdev)
+{
+   struct omap_usb *phy = platform_get_drvdata(pdev);
+
+   clk_unprepare(phy-wkupclk);
+   usb_remove_phy(phy-phy);
+   platform_set_drvdata(pdev, NULL);
+
+   return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int omap_usb2_runtime_suspend(struct device *dev)
+{
+   struct platform_device  *pdev = to_platform_device(dev);
+   struct omap_usb *phy = platform_get_drvdata(pdev);
+
+   clk_disable(phy-wkupclk);
+
+   return 0;
+}
+
+static int omap_usb2_runtime_resume(struct device *dev)
+{
+   struct platform_device  *pdev = to_platform_device(dev);
+   struct omap_usb *phy = platform_get_drvdata(pdev);
+
+   clk_enable(phy-wkupclk);
+
+   return 0;
+}
+
+static const struct dev_pm_ops omap_usb2_pm_ops = {
+   SET_RUNTIME_PM_OPS(omap_usb2_runtime_suspend,
omap_usb2_runtime_resume,
+   NULL)
+};
+
+#define DEV_PM_OPS (omap_usb2_pm_ops)
+#else
+#define DEV_PM_OPS NULL
+#endif
+
+#ifdef CONFIG_OF
+static const struct of_device_id omap_usb2_id_table[] = {
+   { .compatible = ti,omap-usb2 },
+   {}
+};
+MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
+#else
+#define omap_usb2_id_table NULL;
+#endif
+
+static struct platform_driver omap_usb2_driver = {
+   .probe  = omap_usb2_probe,
+   .remove = __devexit_p(omap_usb2_remove),
+   .driver = {
+   .name   = omap-usb2,
+   .owner  = THIS_MODULE,
+   .pm = DEV_PM_OPS,
+   .of_match_table = omap_usb2_id_table,



Use of_match_ptr() instead.


Ok. And I'll remove #define omap_usb2_id_table NULL;.

Thanks
Kishon


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Re: [PATCH v1 07/11] drivers: usb: twl4030: Add device tree support for twl4030 usb

[Rajendra Nayak]

On Tuesday 10 July 2012 12:22 PM, ABRAHAM, KISHON VIJAY wrote:

+TWL4030 USB PHY AND COMPARATOR
  + - compatible : Should be ti,twl4030-usb
  + - interrupts : The interrupt numbers to the cpu should be specified.
  First
  +   interrupt number is the otg interrupt number that raises ID interrupts
  +   and VBUS interrupts. The second interrupt number is optional.
  + -supply-name-supply : phandle to the regulator device tree node.
  +supply-name   should be vusb1v5, vusb1v8 and vusb3v1
  + - usb_mode : The mode used by the phy to connect to the controller. 1
  +   specifies ULPI mode and 2 specifies CEA2011_3PIN mode.



  Are these standard usb phy modes or something specific to the twl4030
  usb phy?

These are standard modes used to connect the phy to the controller. I
think it's used by other chips other than twl4030 (Something in
am35xx??).


So would it make sense to document these bindings independent of a given
phy and a given controller, so it could be reused and not duplicated in
various forms for various different controllers.
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Re: [PATCH v1 01/11] drivers: usb: otg: add a new driver for omap usb2 phy

[Rajendra Nayak]

On Tuesday 10 July 2012 12:18 PM, ABRAHAM, KISHON VIJAY wrote:

Hi,

On Tue, Jul 10, 2012 at 11:33 AM, Venu Byravarasu
vbyravar...@nvidia.com  wrote:

+
+#ifdef CONFIG_PM


Should it not be CONFIG_PM_SLEEP instead of just CONFIG_PM?


Why? I think we should have CONFIG_PM_SLEEP only when we have
*suspend*, *resume* hooks. But this driver has only *runtime_suspend*
and *runtime_resume* hooks.


CONFIG_PM_RUNTIME maybe then?
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Re: [PATCH v1 10/11] arm/dts: omap: Add usb_otg and glue data

[Rajendra Nayak]

On Tuesday 10 July 2012 01:43 PM, ABRAHAM, KISHON VIJAY wrote:

Hi,

On Tue, Jul 10, 2012 at 11:57 AM, Rajendra Nayakrna...@ti.com  wrote:

On Thursday 28 June 2012 05:21 PM, Kishon Vijay Abraham I wrote:


Add usb otg data node in omap4/omap3 device tree file. Also update
the node with board specific setting in omapx-board.dts file.

Signed-off-by: Kishon Vijay Abraham Ikis...@ti.com
---
   arch/arm/boot/dts/omap3-beagle.dts |6 ++
   arch/arm/boot/dts/omap3-evm.dts|6 ++
   arch/arm/boot/dts/omap3.dtsi   |8 
   arch/arm/boot/dts/omap4-panda.dts  |6 ++
   arch/arm/boot/dts/omap4-sdp.dts|6 ++
   arch/arm/boot/dts/omap4.dtsi   |8 
   6 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap3-beagle.dts
b/arch/arm/boot/dts/omap3-beagle.dts
index 5b4506c..f3d7076 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -67,3 +67,9 @@
   mmc3 {
 status = disable;
   };
+
+usb_otg_hs {
+   interface_type =0;
+   mode =3;
+   power =50;
+};
diff --git a/arch/arm/boot/dts/omap3-evm.dts
b/arch/arm/boot/dts/omap3-evm.dts
index 2eee16e..8963b3d 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -18,3 +18,9 @@
 reg =0x8000 0x1000; /* 256 MB */
 };
   };
+
+usb_otg_hs {
+   interface_type =0;
+   mode =3;
+   power =50;
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 99474fa..2f565d6 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -215,5 +215,13 @@
 compatible = ti,omap3-hsmmc;
 ti,hwmods = mmc3;
 };
+
+   usb_otg_hs: usb_otg_hs@4a0ab000 {
+   compatible = ti,musb-omap2430;



this compatible doesn't seem right in omap3.dtsi. Same with
the below entry in omap4.dtsi.
See other IP blocks which are reused across OMAP2/3/4 on
how the compatible for those are handled.


Ok. So it should be like *ti,omap4-musb*, *ti,omap3-musb*?


Yes, that would be more appropriate.



Thanks
Kishon


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Re: [PATCH v1 11/11] arm: omap: phy: remove unused functions from omap-phy-internal.c

[Rajendra Nayak]

On Tuesday 10 July 2012 01:46 PM, ABRAHAM, KISHON VIJAY wrote:

Hi,

On Tue, Jul 10, 2012 at 11:59 AM, Rajendra Nayakrna...@ti.com  wrote:

On Thursday 28 June 2012 05:21 PM, Kishon Vijay Abraham I wrote:


All the unnessary functions in omap-phy-internal is removed.
These functionality are now handled by omap-usb2 phy driver.

Cc: Felipe Balbiba...@ti.com
Signed-off-by: Kishon Vijay Abraham Ikis...@ti.com
Acked-by: Tony Lindgrent...@atomide.com
---
   arch/arm/mach-omap2/omap_phy_internal.c |  138
---
   arch/arm/mach-omap2/twl-common.c|5 -
   arch/arm/mach-omap2/usb-musb.c  |3 -
   3 files changed, 0 insertions(+), 146 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_phy_internal.c
b/arch/arm/mach-omap2/omap_phy_internal.c
index 4c90477..0c610b4 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -31,144 +31,6 @@
   #includeplat/usb.h
   #include control.h

-/* OMAP control module register for UTMI PHY */
-#define CONTROL_DEV_CONF   0x300
-#define PHY_PD 0x1
-
-#define USBOTGHS_CONTROL   0x33c
-#defineAVALID  BIT(0)
-#defineBVALID  BIT(1)
-#defineVBUSVALID   BIT(2)
-#defineSESSEND BIT(3)
-#defineIDDIG   BIT(4)
-
-static struct clk *phyclk, *clk48m, *clk32k;
-static void __iomem *ctrl_base;
-static int usbotghs_control;
-
-int omap4430_phy_init(struct device *dev)
-{
-   ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
-   if (!ctrl_base) {
-   pr_err(control module ioremap failed\n);
-   return -ENOMEM;
-   }
-   /* Power down the phy */
-   __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);



Just checking, but I hope your new driver handles this too.
You might not see any issues with it now, but not doing this could
gate OMAP hitting low power in idle.


I power down the phy during probe in omap-usb2 phy driver.


ok, thanks, good to know.



Thanks
Kishon


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Re: [PATCH v4 23/23] mfd: omap-usb-host: Don't spam console on clk_set_parent failure

[Rajendra Nayak]

On Monday 10 December 2012 03:50 PM, Roger Quadros wrote:

clk_set_parent is expected to fail on OMAP3 platforms. We don't
consider that as fatal so don't spam console.


And what if it fails on a non-OMAP3 platform?



Signed-off-by: Roger Quadros rog...@ti.com
---
  drivers/mfd/omap-usb-host.c |   18 +-
  1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
index 0bb54393..344ce09 100644
--- a/drivers/mfd/omap-usb-host.c
+++ b/drivers/mfd/omap-usb-host.c
@@ -657,32 +657,32 @@ static int __devinit usbhs_omap_probe(struct 
platform_device *pdev)
}

if (is_ehci_phy_mode(pdata-port_mode[0])) {
-   /* for OMAP3 , the clk set paretn fails */
+   /* for OMAP3, clk_set_parent fails */
ret = clk_set_parent(omap-utmi_clk[0],
omap-xclk60mhsp1_ck);
if (ret != 0)
-   dev_err(dev, xclk60mhsp1_ck set parent
-   failed error:%d\n, ret);
+   dev_dbg(dev, xclk60mhsp1_ck set parent failed: %d\n,
+   ret);
} else if (is_ehci_tll_mode(pdata-port_mode[0])) {
ret = clk_set_parent(omap-utmi_clk[0],
omap-init_60m_fclk);
if (ret != 0)
-   dev_err(dev, init_60m_fclk set parent
-   failed error:%d\n, ret);
+   dev_dbg(dev, P0 init_60m_fclk set parent failed: %d\n,
+   ret);
}

if (is_ehci_phy_mode(pdata-port_mode[1])) {
ret = clk_set_parent(omap-utmi_clk[1],
omap-xclk60mhsp2_ck);
if (ret != 0)
-   dev_err(dev, xclk60mhsp2_ck set parent
-   failed error:%d\n, ret);
+   dev_dbg(dev, xclk60mhsp2_ck set parent failed: %d\n,
+   ret);
} else if (is_ehci_tll_mode(pdata-port_mode[1])) {
ret = clk_set_parent(omap-utmi_clk[1],
omap-init_60m_fclk);
if (ret != 0)
-   dev_err(dev, init_60m_fclk set parent
-   failed error:%d\n, ret);
+   dev_dbg(dev, P1 init_60m_fclk set parent failed: %d\n,
+   ret);
}

omap_usbhs_init(dev);



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Re: [PATCH 1/3] misc: Add crossbar driver

[Rajendra Nayak]

On Thursday 22 August 2013 05:03 PM, Sricharan R wrote:
  maps crossbar number-  to interrupt number and
  calls request_irq(int_no, crossbar_handler,..)

So will this mapping happen based on some data passed from DT or
just based on whats available when the device does a request_irq()?

If its based on whats available then I see an issue when you need
to remap something thats already mapped by default (and not used)
since you run out of all free ones.
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Re: [PATCH 1/3] misc: Add crossbar driver

[Rajendra Nayak]

On Friday 23 August 2013 11:41 AM, Sricharan R wrote:
 Hi,
 On Friday 23 August 2013 10:17 AM, Rajendra Nayak wrote:
 On Thursday 22 August 2013 05:03 PM, Sricharan R wrote:
  maps crossbar number-  to interrupt number and
  calls request_irq(int_no, crossbar_handler,..)
 So will this mapping happen based on some data passed from DT or
 just based on whats available when the device does a request_irq()?

 If its based on whats available then I see an issue when you need
 to remap something thats already mapped by default (and not used)
 since you run out of all free ones.
 Yes, when done based on what is available then there is a
 problem when we run out of free ones because we do not
 know which one to replace. I was thinking of something like
 this,
 1) DT would give a list of all free ones, and also if some are
 mapped as default and not used, mark those also as free.
 
  2) While mapping see if it has a default mapping and use it.
   otherwise, pick from free list.   
 
   This should be ok right ?

yeah, sounds ok.

 
 Regards,
  Sricharan
 

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Re: [PATCH] ARM: dts: OMAP5: Add i2c aliases

[Rajendra Nayak]

On Tuesday 15 October 2013 10:30 PM, Nishanth Menon wrote:
 Currently, i2c1 and i2c5 defer probe due to pinctrl dependencies.
 This changes the i2c ID each bus is registered with in i2c-dev
 interface.
 
 As a result of this, many userspace tools break and there is no
 consistent manner to fix the same if the i2c dev interface have no
 consistent numbering. Provide alias to allow ordering the i2c devices
 correctly.

This looks good Nishanth. Shouldn't we just go ahead and fix these for
all OMAPs/AMxx devices which would have the same problem as OMAP5 ;)

Acked-by: Rajendra Nayak rna...@ti.com 
 
 Signed-off-by: Nishanth Menon n...@ti.com
 ---
 
  arch/arm/boot/dts/omap5.dtsi |5 +
  1 file changed, 5 insertions(+)
 
 diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
 index e18ee7e..8970deb 100644
 --- a/arch/arm/boot/dts/omap5.dtsi
 +++ b/arch/arm/boot/dts/omap5.dtsi
 @@ -21,6 +21,11 @@
   interrupt-parent = gic;
  
   aliases {
 + i2c0 = i2c1;
 + i2c1 = i2c2;
 + i2c2 = i2c3;
 + i2c3 = i2c4;
 + i2c4 = i2c5;
   serial0 = uart1;
   serial1 = uart2;
   serial2 = uart3;
 

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Re: [PATCH V2 0/2] ARM: dts: OMAP2+: add i2c aliases

[Rajendra Nayak]

On Thursday 17 October 2013 01:51 AM, Nishanth Menon wrote:
 Add i2c aliases for OMAP and AM processor dts nodes to ensure proper
 i2c ordering. Based on Benoit's for_13/dts branch[1]
 
 Changes in V2:
   - Following Rajendra's suggestion, done for all OMAP and AM
 series SoCs, where i2c is defined.

Thanks Nishanth.
Acked-by: Rajendra Nayak rna...@ti.com

 
 V1: https://patchwork.kernel.org/patch/3046671/
 
 Nishanth Menon (2):
   ARM: dts: OMAP3+: Add i2c aliases
   ARM: dts: AM33xx+: Add i2c aliases
 
  arch/arm/boot/dts/am33xx.dtsi |3 +++
  arch/arm/boot/dts/am4372.dtsi |3 +++
  arch/arm/boot/dts/dra7.dtsi   |5 +
  arch/arm/boot/dts/omap3.dtsi  |3 +++
  arch/arm/boot/dts/omap4.dtsi  |4 
  arch/arm/boot/dts/omap5.dtsi  |5 +
  6 files changed, 23 insertions(+)
 
 [1] 
 https://git.kernel.org/cgit/linux/kernel/git/bcousson/linux-omap-dt.git/log/?h=for_3.13/dts
 

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Re: [PATCH V3 7/7] ARM: DRA: Enable Crossbar IP support for DRA7XX

[Rajendra Nayak]

On Tuesday 05 November 2013 06:44 PM, Sricharan R wrote:
 Enable the crossbar IP support for DRA7xx soc.
 
 Cc: Santosh Shilimkar santosh.shilim...@ti.com
 Cc: Rajendra Nayak rna...@ti.com
 Cc: Tony Lindgren t...@atomide.com
 Signed-off-by: Sricharan R r.sricha...@ti.com
 ---
  arch/arm/mach-omap2/Kconfig|1 +
  arch/arm/mach-omap2/omap4-common.c |4 
  2 files changed, 5 insertions(+)
 
 diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
 index b5fb5f7..2086c65 100644
 --- a/arch/arm/mach-omap2/Kconfig
 +++ b/arch/arm/mach-omap2/Kconfig
 @@ -141,6 +141,7 @@ config SOC_DRA7XX
   select ARM_GIC
   select HAVE_SMP
   select COMMON_CLK
 + select IRQ_CROSSBAR
  
  comment OMAP Core Type
   depends on ARCH_OMAP2
 diff --git a/arch/arm/mach-omap2/omap4-common.c 
 b/arch/arm/mach-omap2/omap4-common.c
 index 5791143..274cbfa 100644
 --- a/arch/arm/mach-omap2/omap4-common.c
 +++ b/arch/arm/mach-omap2/omap4-common.c
 @@ -22,6 +22,7 @@
  #include linux/of_platform.h
  #include linux/export.h
  #include linux/irqchip/arm-gic.h
 +#include linux/irqchip/irq-crossbar.h
  #include linux/of_address.h
  #include linux/reboot.h
  
 @@ -282,9 +283,12 @@ void __init omap_gic_of_init(void)
  
  skip_errata_init:
   omap_wakeupgen_init();
 + if (soc_is_dra7xx())
 + crossbar_init();

Its good if this is called irqcrossbar_init() to avoid confusion
with the dma crossbar which also exists in dra7 devices.

   irqchip_init();
  }
  
 +
  #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  static int omap4_twl6030_hsmmc_late_init(struct device *dev)
  {
 

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Re: [PATCH V4 1/6] clk: OMAP: introduce device tree binding to kernel clock data

[Rajendra Nayak]

On Wednesday 24 April 2013 09:58 PM, Mike Turquette wrote:
 Quoting Nishanth Menon (2013-04-14 14:19:17)
 Overall strategy introduced here is simple: a clock node described in
 device tree blob is used to identify the exact clock provided in the
 SoC specific data. This is then linked back using of_clk_add_provider
 to the device node to be accessible by of_clk_get.

 Based on discussion contributions from Roger Quadros, Grygorii Strashko
 and others.

 Cc: Kevin Hilman khil...@deeprootsystems.com
 Cc: Mike Turquette mturque...@linaro.org
 Cc: Paul Walmsley p...@pwsan.com
 [t...@atomide.com: co-developed]
 Signed-off-by: Tony Lindgren t...@atomide.com
 Signed-off-by: Nishanth Menon n...@ti.com
 
 I can take this into clk-next after the merge window.  Please refresh it
 for -rc1 as we discussed on irc.
 
 As an aside, will Tero's series for migrating to drivers/clk/omap[1] and
 Rajendra's patch for registering clocks late[2] be refreshed after the

[2] is already in mainline.

 merge window?  It would be nice to combine these efforts.
 
 Thanks,
 Mike
 
 [1] http://article.gmane.org/gmane.linux.ports.arm.omap/95948
 [2] http://www.spinics.net/lists/arm-kernel/msg231288.html
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 devicetree-disc...@lists.ozlabs.org
 https://lists.ozlabs.org/listinfo/devicetree-discuss
 

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Re: [PATCH] regulator: dts: Fix bindings description of regulator-boot-on

[Rajendra Nayak]

On Friday 11 October 2013 03:56 PM, Nishanth Menon wrote:
 Since regulator-boot-on property maps back to constraints-boot_on,
 current description of 'regulator-boot-on' property conflicts with
 description of 'boot-on' in include/linux/regulator/machine.h and the
 corresponding implementation in drivers/regulator/core.c.
 
 Ensure the description is more inline with the original intent.
 
 Cc: Rajendra Nayak rna...@ti.com
 
 Reported-by: Kishon Vijay Abraham I kis...@ti.com
 Signed-off-by: Nishanth Menon n...@ti.com
 ---
 
 Ref: my confusion in http://marc.info/?t=13814022884r=1w=2
 Based on v3.12-rc4 tag
 
  .../devicetree/bindings/regulator/regulator.txt|4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)
 
 diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt 
 b/Documentation/devicetree/bindings/regulator/regulator.txt
 index 2bd8f09..d999f096 100644
 --- a/Documentation/devicetree/bindings/regulator/regulator.txt
 +++ b/Documentation/devicetree/bindings/regulator/regulator.txt
 @@ -8,7 +8,9 @@ Optional properties:
  - regulator-min-microamp: smallest current consumers may set
  - regulator-max-microamp: largest current consumers may set
  - regulator-always-on: boolean, regulator should never be disabled
 -- regulator-boot-on: bootloader/firmware enabled regulator
 +- regulator-boot-on: regulator is enabled when the system is initially 
 started.
 +  If the regulator is not enabled by the hardware or bootloader then it will 
 be
 +  enabled when the constraints are applied.

Isn't this specific to how the linux regulator framework implements it?
why should it be documented in the generic bindings documentation which has
nothing Linux specific but more hardware details?

  - regulator-allow-bypass: allow the regulator to go into bypass mode
  - name-supply: phandle to the parent supply/regulator node
  - regulator-ramp-delay: ramp delay for regulator(in uV/uS)
 

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Re: [PATCH 1/3] crypto: omap-des: Add omap-des driver for OMAP4/AM43xx

[Rajendra Nayak]

[]..

 +
 +#define pr_fmt(fmt) %s:  fmt, __func__
 +
 +#ifdef DEBUG
 +#define prn(num) printk(#num =%d\n, num)
 +#define prx(num) printk(#num =%x\n, num)
 +#else
 +#define prn(num) do { } while (0)
 +#define prx(num)  do { } while (0)
 +#endif
 +
 +#include linux/err.h
 +#include linux/module.h
 +#include linux/init.h
 +#include linux/errno.h
 +#include linux/kernel.h
 +#include linux/platform_device.h
 +#include linux/scatterlist.h
 +#include linux/dma-mapping.h
 +#include linux/dmaengine.h
 +#include linux/omap-dma.h
 +#include linux/pm_runtime.h
 +#include linux/of.h
 +#include linux/of_device.h
 +#include linux/of_address.h
 +#include linux/io.h
 +#include linux/crypto.h
 +#include linux/interrupt.h
 +#include crypto/scatterwalk.h
 +#include crypto/des.h
 +
 +#define DST_MAXBURST 2
 +
 +#define DES_BLOCK_WORDS  (DES_BLOCK_SIZE  2)
 +
 +#define _calc_walked(inout) (dd-inout##_walk.offset - 
 dd-inout##_sg-offset)
 +
 +#define DES_REG_KEY(dd, x)   ((dd)-pdata-key_ofs - \
 + ((x ^ 0x01) * 0x04))
 +
 +#define DES_REG_IV(dd, x)((dd)-pdata-iv_ofs + ((x) * 0x04))
 +
 +#define DES_REG_CTRL(dd) ((dd)-pdata-ctrl_ofs)
 +#define DES_REG_CTRL_CBC (1  4)
 +#define DES_REG_CTRL_TDES(1  3)
 +#define DES_REG_CTRL_DIRECTION   (1  2)
 +#define DES_REG_CTRL_INPUT_READY (1  1)
 +#define DES_REG_CTRL_OUTPUT_READY(1  0)

Why not use bitops like you have done below.

 +
 +#define DES_REG_DATA_N(dd, x)((dd)-pdata-data_ofs + ((x) * 
 0x04))
 +
 +#define DES_REG_REV(dd)  ((dd)-pdata-rev_ofs)
 +
 +#define DES_REG_MASK(dd) ((dd)-pdata-mask_ofs)
 +
 +#define DES_REG_LENGTH_N(x)  (0x24 + ((x) * 0x04))
 +
 +#define DES_REG_IRQ_STATUS(dd) ((dd)-pdata-irq_status_ofs)
 +#define DES_REG_IRQ_ENABLE(dd) ((dd)-pdata-irq_enable_ofs)
 +#define DES_REG_IRQ_DATA_INBIT(1)
 +#define DES_REG_IRQ_DATA_OUT   BIT(2)
 +
 +#define FLAGS_MODE_MASK  0x000f
 +#define FLAGS_ENCRYPTBIT(0)
 +#define FLAGS_CBCBIT(1)
 +#define FLAGS_INIT   BIT(4)
 +#define FLAGS_BUSY   BIT(6)
 +

[]..

 +struct omap_des_pdata {
 + struct omap_des_algs_info   *algs_info;
 + unsigned intalgs_info_size;
 +
 + void(*trigger)(struct omap_des_dev *dd, int length);

Is this really used? How does a DT platform pass function pointers?

 +
 + u32 key_ofs;
 + u32 iv_ofs;
 + u32 ctrl_ofs;
 + u32 data_ofs;
 + u32 rev_ofs;
 + u32 mask_ofs;
 + u32 irq_enable_ofs;
 + u32 irq_status_ofs;
 +
 + u32 dma_enable_in;
 + u32 dma_enable_out;
 + u32 dma_start;
 +
 + u32 major_mask;
 + u32 major_shift;
 + u32 minor_mask;
 + u32 minor_shift;
 +};
 +
 +struct omap_des_dev {
 + struct list_headlist;
 + unsigned long   phys_base;
 + void __iomem*io_base;
 + struct omap_des_ctx *ctx;
 + struct device   *dev;
 + unsigned long   flags;
 + int err;
 +
 + /* spinlock used for queues */
 + spinlock_t  lock;
 + struct crypto_queue queue;
 +
 + struct tasklet_struct   done_task;
 + struct tasklet_struct   queue_task;
 +
 + struct ablkcipher_request   *req;
 + /*
 +  * total is used by PIO mode for book keeping so introduce
 +  * variable total_save as need it to calc page_order
 +  */
 + size_t  total;
 + size_t  total_save;
 +
 + struct scatterlist  *in_sg;
 + struct scatterlist  *out_sg;
 +
 + /* Buffers for copying for unaligned cases */
 + struct scatterlist  in_sgl;
 + struct scatterlist  out_sgl;
 + struct scatterlist  *orig_out;
 + int sgs_copied;
 +
 + struct scatter_walk in_walk;
 + struct scatter_walk out_walk;
 + int dma_in;
 + struct dma_chan *dma_lch_in;
 + int dma_out;
 + struct dma_chan *dma_lch_out;
 + int in_sg_len;
 + int out_sg_len;
 + int pio_only;
 + const struct omap_des_pdata *pdata;
 +};
 +
 +/* keep registered devices data here */
 +static LIST_HEAD(dev_list);
 +static DEFINE_SPINLOCK(list_lock);
 +

[]..

 +
 +static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
 +{
 + struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
 + crypto_ablkcipher_reqtfm(dd-req));
 + int err;
 +
 + 

Re: [PATCH v4 3/4] ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods

[Rajendra Nayak]

On Wednesday 18 June 2014 01:32 PM, Roger Quadros wrote:
 On 04/23/2014 08:35 PM, Roger Quadros wrote:
 From: Nikhil Devshatwar nikhil...@ti.com

 Add hwmods for ocp2scp3 and sata modules.

From what I see this is actually adding the ocp2scp3 data and fixing up some
of the sata data which is already added and erroneous.

It would help if this is split up and the changelog explains whats fixed up for
sata and why. Like for instance I see the opt clock data being removed but no
mention of why.
 

 [Roger Q] Clean up.

 CC: Benoit Cousson bcous...@baylibre.com
 CC: Paul Walmsley p...@pwsan.com
 Signed-off-by: Balaji T K balaj...@ti.com
 Signed-off-by: Nikhil Devshatwar nikhil...@ti.com
 Signed-off-by: Roger Quadros rog...@ti.com
 
 Tested-by: Roger Quadros rog...@ti.com
 against 3.16-rc1, no dependency patches needed.
 
 Nishant/Rajendra,
 
 Could you please review this? We need this for 3.16 SATA support and
 Paul won't take this in without your reviewed-by tag. Thanks.
 
 cheers,
 -roger
 
 ---
  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 
 ++-
  1 file changed, 26 insertions(+), 5 deletions(-)

 diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 
 b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 index 810c205..b02a4ab 100644
 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
  },
  };
  
 +/* ocp2scp3 */
 +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
 +
 +/* l4_cfg - ocp2scp3 */
 +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
 +.master = dra7xx_l4_cfg_hwmod,
 +.slave  = dra7xx_ocp2scp3_hwmod,
 +.clk= l4_root_clk_div,
 +.user   = OCP_USER_MPU | OCP_USER_SDMA,
 +};

All hwmod data files are organized in a certain way with all the hwmod/IP block 
info on top
and Interface structs at the bottom. Can we follow the same for ocp2scp3? It 
helps with better
readability.
 
 +
 +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
 +.name   = ocp2scp3,
 +.class  = dra7xx_ocp2scp_hwmod_class,
 +.clkdm_name = l3init_clkdm,

No main_clk?

regards,
Rajendra

 +.prcm = {
 +.omap4 = {
 +.clkctrl_offs = 
 DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
 +.context_offs = 
 DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
 +.modulemode   = MODULEMODE_HWCTRL,
 +},
 +},
 +};
 +
  /*
   * 'qspi' class
   *
 @@ -1268,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class 
 = {
  };
  
  /* sata */
 -static struct omap_hwmod_opt_clk sata_opt_clks[] = {
 -{ .role = ref_clk, .clk = sata_ref_clk },
 -};
  
  static struct omap_hwmod dra7xx_sata_hwmod = {
  .name   = sata,
 @@ -1278,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
  .clkdm_name = l3init_clkdm,
  .flags  = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
  .main_clk   = func_48m_fclk,
 +.mpu_rt_idx = 1,
  .prcm = {
  .omap4 = {
  .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
 @@ -1285,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
  .modulemode   = MODULEMODE_SWCTRL,
  },
  },
 -.opt_clks   = sata_opt_clks,
 -.opt_clks_cnt   = ARRAY_SIZE(sata_opt_clks),
  };
  
  /*
 @@ -2682,6 +2702,7 @@ static struct omap_hwmod_ocp_if 
 *dra7xx_hwmod_ocp_ifs[] __initdata = {
  dra7xx_l4_per1__mmc4,
  dra7xx_l4_cfg__mpu,
  dra7xx_l4_cfg__ocp2scp1,
 +dra7xx_l4_cfg__ocp2scp3,
  dra7xx_l3_main_1__qspi,
  dra7xx_l4_cfg__sata,
  dra7xx_l4_cfg__smartreflex_core,

 

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Re: [PATCH 1/2] ARM: DRA7: hwmod: Add OCP2SCP3 module

[Rajendra Nayak]

On Wednesday 18 June 2014 05:46 PM, Roger Quadros wrote:
 This module is needed for the SATA and PCIe PHYs.
 
 Signed-off-by: Roger Quadros rog...@ti.com
 Tested-by: Roger Quadros rog...@ti.com
 ---
  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 25 +
  1 file changed, 25 insertions(+)
 
 diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 
 b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 index 20b4398..cedef6b 100644
 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
   },
  };
  
 +/* ocp2scp3 */
 +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
 +
 +/* l4_cfg - ocp2scp3 */
 +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
 + .master = dra7xx_l4_cfg_hwmod,
 + .slave  = dra7xx_ocp2scp3_hwmod,
 + .clk= l4_root_clk_div,
 + .user   = OCP_USER_MPU | OCP_USER_SDMA,
 +};

is it not possible to move this down in the file where all interface
structs are defined?

 +
 +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
 + .name   = ocp2scp3,
 + .class  = dra7xx_ocp2scp_hwmod_class,
 + .clkdm_name = l3init_clkdm,
 + .prcm = {
 + .omap4 = {
 + .clkctrl_offs = 
 DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
 + .context_offs = 
 DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
 + .modulemode   = MODULEMODE_HWCTRL,
 + },
 + },
 +};
 +
  /*
   * 'qspi' class
   *
 @@ -2672,6 +2696,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] 
 __initdata = {
   dra7xx_l4_per1__mmc4,
   dra7xx_l4_cfg__mpu,
   dra7xx_l4_cfg__ocp2scp1,
 + dra7xx_l4_cfg__ocp2scp3,
   dra7xx_l3_main_1__qspi,
   dra7xx_l4_cfg__sata,
   dra7xx_l4_cfg__smartreflex_core,
 

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Re: [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems

[Rajendra Nayak]

On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
 Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
 
 Cc: Tony Lindgren t...@atomide.com
 Cc: Russell King li...@arm.linux.org.uk
 Cc: Paul Walmsley p...@pwsan.com
 Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
 Tested-by: Kishon Vijay Abraham I kis...@ti.com
 ---
 Changes from v1:
 * changed the clock domain to pcie_clkdm
 * Added PCIe as a slave port for l3_main.

Looks good to me,
Reviewed-by: Rajendra Nayak rna...@ti.com

 
 Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402/
 
  arch/arm/mach-omap2/omap_hwmod_7xx_data.c |   73 
 +
  1 file changed, 73 insertions(+)
 
 diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 
 b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 index 6ff40a6..2f37ca8 100644
 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 @@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
  };
  
  /*
 + * 'PCIE' class
 + *
 + */
 +
 +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
 + .name   = pcie,
 +};
 +
 +/* pcie1 */
 +static struct omap_hwmod dra7xx_pcie1_hwmod = {
 + .name   = pcie1,
 + .class  = dra7xx_pcie_hwmod_class,
 + .clkdm_name = pcie_clkdm,
 + .main_clk   = l4_root_clk_div,
 + .prcm = {
 + .omap4 = {
 + .clkctrl_offs   = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
 + .modulemode = MODULEMODE_SWCTRL,
 + },
 + },
 +};
 +
 +/* pcie2 */
 +static struct omap_hwmod dra7xx_pcie2_hwmod = {
 + .name   = pcie2,
 + .class  = dra7xx_pcie_hwmod_class,
 + .clkdm_name = pcie_clkdm,
 + .main_clk   = l4_root_clk_div,
 + .prcm = {
 + .omap4 = {
 + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
 + .modulemode   = MODULEMODE_SWCTRL,
 + },
 + },
 +};
 +
 +/*
   * 'PCIE PHY' class
   *
   */
 @@ -2448,6 +2485,38 @@ static struct omap_hwmod_ocp_if 
 dra7xx_l4_cfg__ocp2scp1 = {
   .user   = OCP_USER_MPU | OCP_USER_SDMA,
  };
  
 +/* l3_main_1 - pcie1 */
 +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
 + .master = dra7xx_l3_main_1_hwmod,
 + .slave  = dra7xx_pcie1_hwmod,
 + .clk= l3_iclk_div,
 + .user   = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/* l4_cfg - pcie1 */
 +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
 + .master = dra7xx_l4_cfg_hwmod,
 + .slave  = dra7xx_pcie1_hwmod,
 + .clk= l4_root_clk_div,
 + .user   = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/* l3_main_1 - pcie2 */
 +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
 + .master = dra7xx_l3_main_1_hwmod,
 + .slave  = dra7xx_pcie2_hwmod,
 + .clk= l3_iclk_div,
 + .user   = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/* l4_cfg - pcie2 */
 +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
 + .master = dra7xx_l4_cfg_hwmod,
 + .slave  = dra7xx_pcie2_hwmod,
 + .clk= l4_root_clk_div,
 + .user   = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
  /* l4_cfg - pcie1 phy */
  static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
   .master = dra7xx_l4_cfg_hwmod,
 @@ -2813,6 +2882,10 @@ static struct omap_hwmod_ocp_if 
 *dra7xx_hwmod_ocp_ifs[] __initdata = {
   dra7xx_l4_cfg__mpu,
   dra7xx_l4_cfg__ocp2scp1,
   dra7xx_l4_cfg__ocp2scp3,
 + dra7xx_l3_main_1__pcie1,
 + dra7xx_l4_cfg__pcie1,
 + dra7xx_l3_main_1__pcie2,
 + dra7xx_l4_cfg__pcie2,
   dra7xx_l4_cfg__pcie1_phy,
   dra7xx_l4_cfg__pcie2_phy,
   dra7xx_l3_main_1__qspi,
 

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Re: [PATCH 1/2] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy

[Rajendra Nayak]

On Wednesday 25 June 2014 11:32 PM, Kishon Vijay Abraham I wrote:
 Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
 Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
 for pcie1 phy and pcie2 phy.
 
 Cc: Tony Lindgren t...@atomide.com
 Cc: Russell King li...@arm.linux.org.uk
 Cc: Paul Walmsley p...@pwsan.com
 Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
 Tested-by: Kishon Vijay Abraham I kis...@ti.com

Looks good to me, feel free to add
Reviewed-by: Rajendra Nayak rna...@ti.com

 ---
 Please find the bootlog with these hwmod patches
 http://paste.ubuntu.com/7701601/
  arch/arm/mach-omap2/cm2_7xx.h |4 ++
  arch/arm/mach-omap2/omap_hwmod_7xx_data.c |   57 
 +
  arch/arm/mach-omap2/prm7xx.h  |4 ++
  3 files changed, 65 insertions(+)
 
 diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
 index 9ad7594..e966e3a 100644
 --- a/arch/arm/mach-omap2/cm2_7xx.h
 +++ b/arch/arm/mach-omap2/cm2_7xx.h
 @@ -357,6 +357,10 @@
  #define DRA7XX_CM_L3INIT_SATA_CLKCTRL
 DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
  #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET  0x00a0
  #define DRA7XX_CM_PCIE_STATICDEP_OFFSET  0x00a4
 +#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET  0x00b0
 +#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL 
 DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
 +#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET  0x00b8
 +#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL 
 DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
  #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET  0x00c0
  #define DRA7XX_CM_GMAC_STATICDEP_OFFSET  0x00c4
  #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
 diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 
 b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 index 3deb76e..6ff40a6 100644
 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 @@ -1290,6 +1290,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
  };
  
  /*
 + * 'PCIE PHY' class
 + *
 + */
 +
 +static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
 + .name   = pcie-phy,
 +};
 +
 +/* pcie1 phy */
 +static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
 + .name   = pcie1-phy,
 + .class  = dra7xx_pcie_phy_hwmod_class,
 + .clkdm_name = l3init_clkdm,
 + .main_clk   = l4_root_clk_div,
 + .prcm = {
 + .omap4 = {
 + .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
 + .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
 + .modulemode   = MODULEMODE_SWCTRL,
 + },
 + },
 +};
 +
 +/* pcie2 phy */
 +static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
 + .name   = pcie2-phy,
 + .class  = dra7xx_pcie_phy_hwmod_class,
 + .clkdm_name = l3init_clkdm,
 + .main_clk   = l4_root_clk_div,
 + .prcm = {
 + .omap4 = {
 + .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
 + .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
 + .modulemode   = MODULEMODE_SWCTRL,
 + },
 + },
 +};
 +
 +/*
   * 'qspi' class
   *
   */
 @@ -2409,6 +2448,22 @@ static struct omap_hwmod_ocp_if 
 dra7xx_l4_cfg__ocp2scp1 = {
   .user   = OCP_USER_MPU | OCP_USER_SDMA,
  };
  
 +/* l4_cfg - pcie1 phy */
 +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
 + .master = dra7xx_l4_cfg_hwmod,
 + .slave  = dra7xx_pcie1_phy_hwmod,
 + .clk= l4_root_clk_div,
 + .user   = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/* l4_cfg - pcie2 phy */
 +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
 + .master = dra7xx_l4_cfg_hwmod,
 + .slave  = dra7xx_pcie2_phy_hwmod,
 + .clk= l4_root_clk_div,
 + .user   = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
  static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
   {
   .pa_start   = 0x4b30,
 @@ -2758,6 +2813,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] 
 __initdata = {
   dra7xx_l4_cfg__mpu,
   dra7xx_l4_cfg__ocp2scp1,
   dra7xx_l4_cfg__ocp2scp3,
 + dra7xx_l4_cfg__pcie1_phy,
 + dra7xx_l4_cfg__pcie2_phy,
   dra7xx_l3_main_1__qspi,
   dra7xx_l4_cfg__sata,
   dra7xx_l4_cfg__smartreflex_core,
 diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
 index d92a840..4bb50fbf 100644
 --- a/arch/arm/mach-omap2/prm7xx.h
 +++ b/arch/arm/mach-omap2/prm7xx.h
 @@ -374,6 +374,10 @@
  #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET

Re: [PATCH 2/2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems

[Rajendra Nayak]

On Wednesday 25 June 2014 11:32 PM, Kishon Vijay Abraham I wrote:
 Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
 
 Cc: Tony Lindgren t...@atomide.com
 Cc: Russell King li...@arm.linux.org.uk
 Cc: Paul Walmsley p...@pwsan.com
 Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
 Tested-by: Kishon Vijay Abraham I kis...@ti.com
 ---
 Please find the bootlog with these hwmod patches
 http://paste.ubuntu.com/7701601/
  arch/arm/mach-omap2/omap_hwmod_7xx_data.c |   55 
 +
  1 file changed, 55 insertions(+)
 
 diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 
 b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 index 6ff40a6..934aa9d 100644
 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 @@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
  };
  
  /*
 + * 'PCIE' class
 + *
 + */
 +
 +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
 + .name   = pcie,
 +};
 +
 +/* pcie1 */
 +static struct omap_hwmod dra7xx_pcie1_hwmod = {
 + .name   = pcie1,
 + .class  = dra7xx_pcie_hwmod_class,
 + .clkdm_name = l3init_clkdm,

The TRM tells me it belongs to 'pcie_clkdm' instead. Can you please recheck?

 + .main_clk   = l4_root_clk_div,
 + .prcm = {
 + .omap4 = {
 + .clkctrl_offs   = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
 + .modulemode = MODULEMODE_SWCTRL,
 + },
 + },
 +};
 +
 +/* pcie2 */
 +static struct omap_hwmod dra7xx_pcie2_hwmod = {
 + .name   = pcie2,
 + .class  = dra7xx_pcie_hwmod_class,
 + .clkdm_name = l3init_clkdm,
 + .main_clk   = l4_root_clk_div,
 + .prcm = {
 + .omap4 = {
 + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
 + .modulemode   = MODULEMODE_SWCTRL,
 + },
 + },
 +};
 +
 +/*
   * 'PCIE PHY' class
   *
   */
 @@ -2448,6 +2485,22 @@ static struct omap_hwmod_ocp_if 
 dra7xx_l4_cfg__ocp2scp1 = {
   .user   = OCP_USER_MPU | OCP_USER_SDMA,
  };
  
 +/* l4_cfg - pcie1 */

There seems to be a slave port on l3_init as well which seems to be missing?

Refer to 'Figure 24-157. PCIe Controllers Integration' of TRM version P.

regards,
Rajendra

 +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
 + .master = dra7xx_l4_cfg_hwmod,
 + .slave  = dra7xx_pcie1_hwmod,
 + .clk= l4_root_clk_div,
 + .user   = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/* l4_cfg - pcie2 */
 +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
 + .master = dra7xx_l4_cfg_hwmod,
 + .slave  = dra7xx_pcie2_hwmod,
 + .clk= l4_root_clk_div,
 + .user   = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
  /* l4_cfg - pcie1 phy */
  static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
   .master = dra7xx_l4_cfg_hwmod,
 @@ -2813,6 +2866,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] 
 __initdata = {
   dra7xx_l4_cfg__mpu,
   dra7xx_l4_cfg__ocp2scp1,
   dra7xx_l4_cfg__ocp2scp3,
 + dra7xx_l4_cfg__pcie1,
 + dra7xx_l4_cfg__pcie2,
   dra7xx_l4_cfg__pcie1_phy,
   dra7xx_l4_cfg__pcie2_phy,
   dra7xx_l3_main_1__qspi,
 

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Re: [PATCH v2 1/2] ARM: DRA7: hwmod: Add OCP2SCP3 module

[Rajendra Nayak]

On Thursday 19 June 2014 01:20 AM, Roger Quadros wrote:
 This module is needed for the SATA and PCIe PHYs.
 
 Signed-off-by: Roger Quadros rog...@ti.com
 Tested-by: Roger Quadros rog...@ti.com

Reviewed-by: Rajendra Nayak rna...@ti.com

 ---
 v2:
 - added .main_clk to hwmod.
 - moved interface structure to the right place.
 
  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 24 
  1 file changed, 24 insertions(+)
 
 diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 
 b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 index 20b4398..c9daee4 100644
 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 @@ -1215,6 +1215,21 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
   },
  };
  
 +/* ocp2scp3 */
 +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
 + .name   = ocp2scp3,
 + .class  = dra7xx_ocp2scp_hwmod_class,
 + .clkdm_name = l3init_clkdm,
 + .main_clk   = l4_root_clk_div,
 + .prcm = {
 + .omap4 = {
 + .clkctrl_offs = 
 DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
 + .context_offs = 
 DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
 + .modulemode   = MODULEMODE_HWCTRL,
 + },
 + },
 +};
 +
  /*
   * 'qspi' class
   *
 @@ -2326,6 +2341,14 @@ static struct omap_hwmod_ocp_if 
 dra7xx_l4_cfg__ocp2scp1 = {
   .user   = OCP_USER_MPU | OCP_USER_SDMA,
  };
  
 +/* l4_cfg - ocp2scp3 */
 +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
 + .master = dra7xx_l4_cfg_hwmod,
 + .slave  = dra7xx_ocp2scp3_hwmod,
 + .clk= l4_root_clk_div,
 + .user   = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
  static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
   {
   .pa_start   = 0x4b30,
 @@ -2672,6 +2695,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] 
 __initdata = {
   dra7xx_l4_per1__mmc4,
   dra7xx_l4_cfg__mpu,
   dra7xx_l4_cfg__ocp2scp1,
 + dra7xx_l4_cfg__ocp2scp3,
   dra7xx_l3_main_1__qspi,
   dra7xx_l4_cfg__sata,
   dra7xx_l4_cfg__smartreflex_core,
 

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Re: [PATCH 2/2] ARM: DRA7: hwmod: Fixup SATA hwmod

[Rajendra Nayak]

On Wednesday 18 June 2014 05:46 PM, Roger Quadros wrote:
 Get rid of optional clock as that is now managed by the
 AHCI platform driver.

The optional clock info in hwmod is actually unused for a lot of
other modules too.
http://www.spinics.net/lists/arm-kernel/msg333025.html

 
 Correct .mpu_rt_idx to 1 as the module register space (SYSCONFIG..)
 is passed as the second memory resource in the device tree.
 
 Signed-off-by: Roger Quadros rog...@ti.com
 Tested-by: Roger Quadros rog...@ti.com

Reviewed-by: Rajendra Nayak rna...@ti.com

 ---
  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 6 +-
  1 file changed, 1 insertion(+), 5 deletions(-)
 
 diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 
 b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 index cedef6b..bc42eab 100644
 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 @@ -1292,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class 
 = {
  };
  
  /* sata */
 -static struct omap_hwmod_opt_clk sata_opt_clks[] = {
 - { .role = ref_clk, .clk = sata_ref_clk },
 -};
  
  static struct omap_hwmod dra7xx_sata_hwmod = {
   .name   = sata,
 @@ -1302,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
   .clkdm_name = l3init_clkdm,
   .flags  = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
   .main_clk   = func_48m_fclk,
 + .mpu_rt_idx = 1,
   .prcm = {
   .omap4 = {
   .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
 @@ -1309,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
   .modulemode   = MODULEMODE_SWCTRL,
   },
   },
 - .opt_clks   = sata_opt_clks,
 - .opt_clks_cnt   = ARRAY_SIZE(sata_opt_clks),
  };
  
  /*
 

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Re: [PATCH] clk: qcom: gdsc: Add GDSCs in apq8084 MMCC

[Rajendra Nayak]

On 03/25/2015 06:49 PM, Stephane Viau wrote:

Add the GDSC instances that exist as part of apq8084 MMCC block.

Signed-off-by: Stephane Viau sv...@codeaurora.org
---
  drivers/clk/qcom/Kconfig  |  1 +
  drivers/clk/qcom/mmcc-apq8084.c   | 56 ++-
  include/dt-bindings/clock/qcom,mmcc-apq8084.h |  8 
  3 files changed, 64 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 4dadfc9..89879e1 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -15,6 +15,7 @@ config APQ_GCC_8084
  config APQ_MMCC_8084
tristate APQ8084 Multimedia Clock Controller
select APQ_GCC_8084
+   select QCOM_GDSC
depends on COMMON_CLK_QCOM
help
  Support for the multimedia clock controller on apq8084 devices.
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
index 157139a..626adbd 100644
--- a/drivers/clk/qcom/mmcc-apq8084.c
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -1,5 +1,5 @@
  /*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   *
   * This software is licensed under the terms of the GNU General Public
   * License version 2, as published by the Free Software Foundation, and
@@ -26,6 +26,7 @@
  #include clk-rcg.h
  #include clk-branch.h
  #include reset.h
+#include gdsc.h

  #define P_XO  0
  #define P_MMPLL0  1
@@ -3075,6 +3076,48 @@ static const struct pll_config mmpll3_config = {
.aux_output_mask = BIT(1),
  };

+static struct gdsc venus0_gdsc = {
+   .gdscr = 0x1024,
+   .pd = {
+   .name = venus0,
+   },
+};
+
+static struct gdsc mdss_gdsc = {
+   .gdscr = 0x2304,
+   .pd = {
+   .name = mdss,
+   },
+};
+
+static struct gdsc camss_jpeg_gdsc = {
+   .gdscr = 0x35a4,
+   .pd = {
+   .name = camss_jpeg,
+   },
+};
+
+static struct gdsc camss_vfe_gdsc = {
+   .gdscr = 0x36a4,
+   .pd = {
+   .name = camss_vfe,
+   },
+};
+
+static struct gdsc oxili_gdsc = {
+   .gdscr = 0x4024,
+   .pd = {
+   .name = oxili,
+   },
+};
+
+static struct gdsc oxilicx_gdsc = {
+   .gdscr = 0x4034,
+   .pd = {
+   .name = oxilicx,
+   },
+};
+
  static struct clk_regmap *mmcc_apq8084_clocks[] = {
[MMSS_AHB_CLK_SRC] = mmss_ahb_clk_src.clkr,
[MMSS_AXI_CLK_SRC] = mmss_axi_clk_src.clkr,
@@ -3292,6 +3335,15 @@ static const struct qcom_reset_map mmcc_apq8084_resets[] 
= {
[MMSSNOCAXI_RESET] = { 0x5060 },
  };

+static struct generic_pm_domain *mmcc_apq8084_gdscs[] = {


With my v3, I changed this to an array of struct gdsc, I will
update this patch and include it in my gdsc series v4 repost, that I
will do shortly.

regards,
Rajendra


+   [VENUS0_GDSC] = venus0_gdsc.pd,
+   [MDSS_GDSC] = mdss_gdsc.pd,
+   [CAMSS_JPEG_GDSC] = camss_jpeg_gdsc.pd,
+   [CAMSS_VFE_GDSC] = camss_vfe_gdsc.pd,
+   [OXILI_GDSC] = oxili_gdsc.pd,
+   [OXILICX_GDSC] = oxilicx_gdsc.pd,
+};
+
  static const struct regmap_config mmcc_apq8084_regmap_config = {
.reg_bits   = 32,
.reg_stride = 4,
@@ -3306,6 +3358,8 @@ static const struct qcom_cc_desc mmcc_apq8084_desc = {
.num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
.resets = mmcc_apq8084_resets,
.num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
+   .gdscs = mmcc_apq8084_gdscs,
+   .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
  };

  static const struct of_device_id mmcc_apq8084_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,mmcc-apq8084.h 
b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
index d72b5b3..21fec5d 100644
--- a/include/dt-bindings/clock/qcom,mmcc-apq8084.h
+++ b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
@@ -180,4 +180,12 @@
  #define VPU_SLEEP_CLK 163
  #define VPU_VDP_CLK   164

+/* GDSCs */
+#define VENUS0_GDSC0
+#define MDSS_GDSC  1
+#define CAMSS_JPEG_GDSC2
+#define CAMSS_VFE_GDSC 3
+#define OXILI_GDSC 4
+#define OXILICX_GDSC   5
+
  #endif



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Re: [PATCH v6 7/9] nvmem: qfprom: Add bindings for qfprom

[Rajendra Nayak]

[]..


+Example:
+
+   qfprom: qfprom@0070 {
+   compatible  = qcom,qfprom;
+   reg = 0x0070 0x8000;
+   ...
+   /* Data cells */
+   tsens_calibration: calib@404 {
+   reg = 0x4404 0x10;
+   };
+   };
+
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+For example:
+
+   tsens {
+   ...
+   nvmem-cell = tsens_calibration;


Shouldn't this be nvmem-cells instead?


+   nvmem-cell-names = calibration;
+   };


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[PATCH] PM / Domains: Make pm_genpd_init() available to modules

[Rajendra Nayak]

Export symbol pm_genpd_init so it can be used in loadable
kernel modules

Signed-off-by: Rajendra Nayak rna...@codeaurora.org
Reported-by: Stephen Rothwell s...@canb.auug.org.au
---
 drivers/base/power/domain.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
index 0ee43c1..578d121 100644
--- a/drivers/base/power/domain.c
+++ b/drivers/base/power/domain.c
@@ -1952,6 +1952,7 @@ void pm_genpd_init(struct generic_pm_domain *genpd,
list_add(genpd-gpd_list_node, gpd_list);
mutex_unlock(gpd_list_lock);
 }
+EXPORT_SYMBOL_GPL(pm_genpd_init);
 
 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
 /*
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Re: [PATCH] PM / Domains: Make pm_genpd_init() available to modules

[Rajendra Nayak]

On 08/13/2015 11:41 PM, Stephen Boyd wrote:

On 08/13, Rajendra Nayak wrote:

Export symbol pm_genpd_init so it can be used in loadable
kernel modules

Signed-off-by: Rajendra Nayak rna...@codeaurora.org
Reported-by: Stephen Rothwell s...@canb.auug.org.au
---


I'd like to take this through the clk tree somehow so that we can
merge the rest of the GDSC series this coming cycle.


Ulf/Rafael, if you don't have any issues with the patch, and are fine
with Stephen taking this through the clk tree, would you be able to ack
this please? thanks.

regards,
Rajendra
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Re: [PATCH v9 0/9] Add simple NVMEM Framework via regmap.

[Rajendra Nayak]

On 07/27/2015 04:42 PM, Srinivas Kandagatla wrote:

Hi Greg/Kevin,

This patchset adds a new simple NVMEM framework to kernel, and it is tested
with various drivers like QCOM thermal sensors, QCOM cpr driver,
begal bone cape manager and few more on the way.

Can you please consider this as 4.3 material, AFAIK there are more than 3 
drivers
depending on this framework which are wating since last 2 merge windows.


I have been testing these with the qcom tsens driver, and did test v9
as well, so feel free to add my tested by for the entire series,

Tested-by: Rajendra Nayak rna...@codeaurora.org
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Re: [PATCH v2 2/2] clk: qcom: Make oxili GDSC parent of oxili_cx GDSC

[Rajendra Nayak]

On 11/13/2015 11:44 AM, Stephen Boyd wrote:
> On 11/13, Rajendra Nayak wrote:
>>
>> On 10/07/2015 01:02 AM, Stephen Boyd wrote:
>>> On 10/01, Stephen Boyd wrote:
>>>> The oxili_cx GDSC is inside the power domain of the oxili GDSC.
>>>> Add the dependency so that the CX domain can properly power up.
>>>>
>>>> Reported-by: Rob Clark <robdcl...@gmail.com>
>>>> Cc: Rajendra Nayak <rna...@codeaurora.org>
>>>> Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
>>>> ---
>>>
>>> Applied to clk-next
>>
>> I don't see this in clk-next. Was this dropped for some reason?
>>
> 
> Hm.. It's merged into Linus' tree now
> 
> b68f2c3b882202aba97a488c1fede0e99f7261e2
> 
> unless I missed something.

right, sorry, I seemed to be wrongly looking at the gcc driver instead
of mmcc.

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Re: [PATCH v2 2/2] clk: qcom: Make oxili GDSC parent of oxili_cx GDSC

[Rajendra Nayak]

On 10/07/2015 01:02 AM, Stephen Boyd wrote:
> On 10/01, Stephen Boyd wrote:
>> The oxili_cx GDSC is inside the power domain of the oxili GDSC.
>> Add the dependency so that the CX domain can properly power up.
>>
>> Reported-by: Rob Clark <robdcl...@gmail.com>
>> Cc: Rajendra Nayak <rna...@codeaurora.org>
>> Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
>> ---
> 
> Applied to clk-next

I don't see this in clk-next. Was this dropped for some reason?

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Re: [PATCH] clk: qcom: Make oxili GDSC parent of oxili_cx GDSC

[Rajendra Nayak]

On 09/24/2015 12:39 AM, Stephen Boyd wrote:

The oxili_cx GDSC is inside the power domain of the oxili GDSC.
Add the dependency so that the CX domain can properly power up.

Reported-by: Rob Clark <robdcl...@gmail.com>
Cc: Rajendra Nayak <rna...@codeaurora.org>
Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
---
  drivers/clk/qcom/mmcc-msm8974.c | 10 +-
  1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index fe8320dc41db..3613db0a73e3 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -2615,6 +2615,7 @@ MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
  static int mmcc_msm8974_probe(struct platform_device *pdev)
  {
struct regmap *regmap;
+   int ret;

regmap = qcom_cc_map(pdev, _msm8974_desc);
if (IS_ERR(regmap))
@@ -2623,7 +2624,14 @@ static int mmcc_msm8974_probe(struct platform_device 
*pdev)
clk_pll_configure_sr_hpm_lp(, regmap, _config, true);
clk_pll_configure_sr_hpm_lp(, regmap, _config, false);

-   return qcom_cc_really_probe(pdev, _msm8974_desc, regmap);
+   ret = qcom_cc_really_probe(pdev, _msm8974_desc, regmap);
+   if (ret)
+   return ret;
+
+   ret = pm_genpd_add_subdomain(_gdsc.pd, _gdsc.pd);


We'll need pm_genpd_add_subdomain() to be EXPORT_SYMBOL_GPL'ed so
clk-qcom can be built as a module.

It would also be nicer if this parent/child relationship can
somehow be represented in data (struct gdsc) that gets passed to
the gdsc driver which then sets it up, instead of individual
clock drivers doing it.


+   if (ret)
+   qcom_cc_remove(pdev);
+   return ret;
  }

  static int mmcc_msm8974_remove(struct platform_device *pdev)



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Re: [PATCH] clk: qcom: Make oxili GDSC parent of oxili_cx GDSC

[Rajendra Nayak]

[]...

>>> It would also be nicer if this parent/child relationship can
>>> somehow be represented in data (struct gdsc) that gets passed to
>>> the gdsc driver which then sets it up, instead of individual
>>> clock drivers doing it.
>>
>> Agreed. I'd rather that we do nothing besides register domains
>> and then let the core code handle hooking up domains and
>> subdomains.
> 
> A little closer inspection makes me want to skip this. PM domains
> can have multiple "master" domains, and pm_genpd_init() is the
> only API that would be able to do the linking. That API is mostly
> about initializing things to default values, so it doesn't seem
> like a good fit. I'll send a v2 with the remove part and the
> exports.

What I was suggesting is that the qcom gdsc driver handle this
instead of the qcom clock drivers.
Something like..

diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index da9fad8..00edb2d 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -226,6 +226,8 @@ int gdsc_register(struct device *dev, struct gdsc **scs, 
size_t num,
if (ret)
return ret;
data->domains[i] = [i]->pd;
+   if (scs[i]->parent)
+   pm_genpd_add_subdomain(scs[i]->parent, [i]->pd);
}
 
return of_genpd_add_provider_onecell(dev->of_node, data);
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 5ded268..bc5791f 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -49,6 +49,7 @@ struct gdsc {
struct reset_controller_dev *rcdev;
unsigned int*resets;
unsigned intreset_count;
+   struct generic_pm_domain*parent;
 };
 
 #ifdef CONFIG_QCOM_GDSC
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index fe8320d..51ad8de 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -2400,6 +2400,7 @@ static struct gdsc oxilicx_gdsc = {
.pd = {
.name = "oxilicx",
},
+   .parent = _gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
 };

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Re: [PATCH v2] arm64: dts: qcom: Add apq8096 dragonboard dts skeletons

[Rajendra Nayak]

On 12/02/2015 02:59 AM, Bryan Huntsman wrote:
> On 12/01/2015 08:11 AM, Rajendra Nayak wrote:
>> Add new dtsi and dts files for the apq8096 dragonboards with just
>> a serial device used as debug console
>>
>> While at it, also rearrange the Makefile so we have one dtb per line
>> so as to be consistent with whats done on other platforms.
>>
>> Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
>> ---
>>  arch/arm64/boot/dts/qcom/Makefile |  4 ++-
>>  arch/arm64/boot/dts/qcom/apq8096-dragonboard.dts  | 21 
>>  arch/arm64/boot/dts/qcom/apq8096-dragonboard.dtsi | 30 
>> +++
>>  3 files changed, 54 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/arm64/boot/dts/qcom/apq8096-dragonboard.dts
>>  create mode 100644 arch/arm64/boot/dts/qcom/apq8096-dragonboard.dtsi
> 
> One problem.  The board you have is not called a dragonboard.  Let's
> check with the marketing folks on what they're calling it now.  We need
> to explicitly avoid using dragonboard here as that name applies to a
> different class of products.  Thanks.

Thanks Bryan, I'll update with the new board name.

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Re: [PATCH v2 3/5] clk: qcom: Add MSM8996 Global Clock Control (GCC) driver

[Rajendra Nayak]

Stephen,

On 12/01/2015 07:01 AM, Stephen Boyd wrote:
> Add support for the global clock controller found on MSM8996
> based devices. This should allow most non-multimedia device
> drivers to probe and control their clocks.

On my 8096 board I see the following orphan clocks,

/sys/kernel/debug/clk # cat clk_orphan_summary
   clock enable_cnt  prepare_cntrate   accuracy 
  phase
---

-
 gcc_ufs_rx_symbol_1_clk  00   0  0 0
 gcc_ufs_rx_symbol_0_clk  00   0  0 0
 gcc_ufs_tx_symbol_0_clk  00   0  0 0
 gcc_pcie_2_pipe_clk  00   0  0 0
 gcc_pcie_1_pipe_clk  00   0  0 0
 gcc_pcie_0_pipe_clk  00   0  0 0
 gcc_usb3_phy_pipe_clk00   0  0 0

I was looking at some ufs clocks which lead me to this. something that needs to 
be fixed?

regards,
Rajendra

> 
> Signed-off-by: Stephen Boyd 
> ---
>  .../devicetree/bindings/clock/qcom,gcc.txt |1 +
>  drivers/clk/qcom/Kconfig   |8 +
>  drivers/clk/qcom/Makefile  |1 +
>  drivers/clk/qcom/gcc-msm8996.c | 3422 
> 
>  include/dt-bindings/clock/qcom,gcc-msm8996.h   |  339 ++
>  5 files changed, 3771 insertions(+)
>  create mode 100644 drivers/clk/qcom/gcc-msm8996.c
>  create mode 100644 include/dt-bindings/clock/qcom,gcc-msm8996.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt 
> b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> index 152dfaab2575..72f82f444091 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> @@ -13,6 +13,7 @@ Required properties :
>   "qcom,gcc-msm8974"
>   "qcom,gcc-msm8974pro"
>   "qcom,gcc-msm8974pro-ac"
> + "qcom,gcc-msm8996"
>  
>  - reg : shall contain base register location and length
>  - #clock-cells : shall contain 1
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index ee4c83aab4f4..fb2b499c647d 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -106,3 +106,11 @@ config MSM_MMCC_8974
> Support for the multimedia clock controller on msm8974 devices.
> Say Y if you want to support multimedia devices such as display,
> graphics, video encode/decode, camera, etc.
> +
> +config MSM_GCC_8996
> + tristate "MSM8996 Global Clock Controller"
> + depends on COMMON_CLK_QCOM
> + help
> +   Support for the global clock controller on msm8996 devices.
> +   Say Y if you want to use peripheral devices such as UART, SPI,
> +   i2c, USB, UFS, SD/eMMC, PCIe, etc.
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 472200040788..42dca6799414 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -21,5 +21,6 @@ obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
>  obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
>  obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
>  obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
> +obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
>  obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
>  obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
> diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
> new file mode 100644
> index ..16d7c323db49
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-msm8996.c
> @@ -0,0 +1,3422 @@
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +#include "common.h"
> +#include "clk-regmap.h"
> +#include "clk-alpha-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-branch.h"
> +#include "reset.h"
> +
> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
> +
> +enum {
> + P_XO,
> + P_GPLL0,
> + P_GPLL2,
> + P_GPLL3,
> + 

[PATCH 6/6] clk: qcom: mmcc8974: Use gdscs .parent and remove genpd calls

[Rajendra Nayak]

With gdsc driver capable of handling hierarchical power domains,
specify oxili_gdsc as parent of oxilicx_gdsc.

Remove all direct calls to genpd from the mmcc clock driver. The
adding and removing of subdomains is now handled from within
the gdsc driver.

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/mmcc-msm8974.c | 14 ++
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index 9d790bc..12cea42 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -2400,6 +2400,7 @@ static struct gdsc oxilicx_gdsc = {
.pd = {
.name = "oxilicx",
},
+   .parent = _gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
 };
 
@@ -2624,22 +2625,11 @@ static int mmcc_msm8974_probe(struct platform_device 
*pdev)
clk_pll_configure_sr_hpm_lp(, regmap, _config, true);
clk_pll_configure_sr_hpm_lp(, regmap, _config, false);
 
-   ret = qcom_cc_really_probe(pdev, _msm8974_desc, regmap);
-   if (ret)
-   return ret;
-
-   return pm_genpd_add_subdomain(_gdsc.pd, _gdsc.pd);
-}
-
-static int mmcc_msm8974_remove(struct platform_device *pdev)
-{
-   pm_genpd_remove_subdomain(_gdsc.pd, _gdsc.pd);
-   return 0;
+   return qcom_cc_really_probe(pdev, _msm8974_desc, regmap);
 }
 
 static struct platform_driver mmcc_msm8974_driver = {
.probe  = mmcc_msm8974_probe,
-   .remove = mmcc_msm8974_remove,
.driver = {
.name   = "mmcc-msm8974",
.of_match_table = mmcc_msm8974_match_table,
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[PATCH 0/6] Add support for MSM8996 GDSCs

[Rajendra Nayak]

This series adds support for GDSCs' which are part of gcc and mmcc
in QCOM msm8996 SoC. Series applies on top of the patches[1] which
adds support for MSM8996 clocks.

There are many more cases of gdscs within gdscs (hierarchical power
domains) in msm8996 (msm8974 has one such instance which is supported
upstream) and hence the series adds support within gdsc driver to
handle this.

Also msm8996 has gdscs with gds hw controllers within, for ensuring
slave device idleness before gdscs are powered off, hence the series
also adds support for gdscs with gds hw controllers.

ToDo: Series does not yet add support for gpu gdscs which are part
of mmcc.

Tested on apq8096 dragonboards to make sure all modelled gdscs can
be turned on/off successfully.

[1] https://lkml.org/lkml/2015/11/17/949 

Rajendra Nayak (6):
  clk: qcom: gdsc: Add support for hierarchical power domains
  clk: qcom: gdsc: Add support for gdscs with gds hw controller
  clk: qcom: gdsc: Add GDSCs in msm8996 GCC
  clk: qcom: gdsc: Add mmcc gdscs for msm8996 family
  clk: qcom: gdsc: Do not check for disabled status on votable gdscs
  clk: qcom: mmcc8974: Use gdscs .parent and remove genpd calls

 arch/arm64/boot/dts/qcom/msm8996.dtsi |   2 +
 drivers/clk/qcom/common.c |  14 ++-
 drivers/clk/qcom/gcc-msm8996.c|  92 +++
 drivers/clk/qcom/gdsc.c   |  69 ---
 drivers/clk/qcom/gdsc.h   |  34 --
 drivers/clk/qcom/mmcc-msm8974.c   |  14 +--
 drivers/clk/qcom/mmcc-msm8996.c   | 157 ++
 include/dt-bindings/clock/qcom,gcc-msm8996.h  |  11 ++
 include/dt-bindings/clock/qcom,mmcc-msm8996.h |  17 +++
 9 files changed, 363 insertions(+), 47 deletions(-)

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arm64: dts: qcom: Add apq8096 dragonboard dts skeletons

[Rajendra Nayak]

Add new dtsi and dts files for the apq8096 dragonboards with just
a serial device used as debug console

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
Patch applies on top of Stephens' patches to add msm8996 dtsi
https://lkml.org/lkml/2015/11/17/955

 arch/arm64/boot/dts/qcom/Makefile |  2 +-
 arch/arm64/boot/dts/qcom/apq8096-dragonboard.dts  | 21 
 arch/arm64/boot/dts/qcom/apq8096-dragonboard.dtsi | 30 +++
 3 files changed, 52 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/qcom/apq8096-dragonboard.dts
 create mode 100644 arch/arm64/boot/dts/qcom/apq8096-dragonboard.dtsi

diff --git a/arch/arm64/boot/dts/qcom/Makefile 
b/arch/arm64/boot/dts/qcom/Makefile
index fa1f661..bd992ef 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -1,5 +1,5 @@
 dtb-$(CONFIG_ARCH_QCOM)+= apq8016-sbc.dtb msm8916-mtp.dtb
-dtb-$(CONFIG_ARCH_QCOM)+= msm8996-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM)+= msm8996-mtp.dtb apq8096-dragonboard.dtb
 
 always := $(dtb-y)
 subdir-y   := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-dragonboard.dts 
b/arch/arm64/boot/dts/qcom/apq8096-dragonboard.dts
new file mode 100644
index 000..65f4a6a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8096-dragonboard.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "apq8096-dragonboard.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. APQ 8096 DragonBoard";
+   compatible = "qcom,apq8096-dragonboard";
+};
diff --git a/arch/arm64/boot/dts/qcom/apq8096-dragonboard.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-dragonboard.dtsi
new file mode 100644
index 000..9bab5c0
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8096-dragonboard.dtsi
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "msm8996.dtsi"
+
+/ {
+   aliases {
+   serial0 = _uart1;
+   };
+
+   chosen {
+   stdout-path = "serial0";
+   };
+
+   soc {
+   serial@75b {
+   status = "okay";
+   };
+   };
+};
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[PATCH 4/6] clk: qcom: gdsc: Add mmcc gdscs for msm8996 family

[Rajendra Nayak]

Add all gdsc data which are part of mmcc on msm8996 family

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi |   1 +
 drivers/clk/qcom/mmcc-msm8996.c   | 154 ++
 include/dt-bindings/clock/qcom,mmcc-msm8996.h |  17 +++
 3 files changed, 172 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 31e7bd9..0506fb8 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -252,6 +252,7 @@
compatible = "qcom,mmcc-msm8996";
#clock-cells = <1>;
#reset-cells = <1>;
+   #power-domain-cells = <1>;
reg = <0x8c 0x4>;
assigned-clocks = < MMPLL9_PLL>,
  < MMPLL1_PLL>,
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index 064f3ea..236acf5 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -32,6 +32,7 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "gdsc.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 
@@ -2917,6 +2918,141 @@ static struct clk_hw *mmcc_msm8996_hws[] = {
_div.hw,
 };
 
+struct gdsc mmagic_video_gdsc = {
+   .gdscr = 0x119c,
+   .gds_hw_ctrl = 0x120c,
+   .pd = {
+   .name = "mmagic_video",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc mmagic_mdss_gdsc = {
+   .gdscr = 0x247c,
+   .gds_hw_ctrl = 0x2480,
+   .pd = {
+   .name = "mmagic_mdss",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc mmagic_camss_gdsc = {
+   .gdscr = 0x3c4c,
+   .gds_hw_ctrl = 0x3c50,
+   .pd = {
+   .name = "mmagic_camss",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc venus_gdsc = {
+   .gdscr = 0x1024,
+   .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
+   .cxc_count = 3,
+   .pd = {
+   .name = "venus",
+   },
+   .parent = _video_gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc venus_core0_gdsc = {
+   .gdscr = 0x1040,
+   .cxcs = (unsigned int []){ 0x1048 },
+   .cxc_count = 1,
+   .pd = {
+   .name = "venus_core0",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc venus_core1_gdsc = {
+   .gdscr = 0x1044,
+   .cxcs = (unsigned int []){ 0x104c },
+   .cxc_count = 1,
+   .pd = {
+   .name = "venus_core1",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc camss_gdsc = {
+   .gdscr = 0x34a0,
+   .cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
+   .cxc_count = 2,
+   .pd = {
+   .name = "camss",
+   },
+   .parent = _camss_gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc vfe0_gdsc = {
+   .gdscr = 0x3664,
+   .cxcs = (unsigned int []){ 0x36a8 },
+   .cxc_count = 1,
+   .pd = {
+   .name = "vfe0",
+   },
+   .parent = _gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc vfe1_gdsc = {
+   .gdscr = 0x3674,
+   .cxcs = (unsigned int []){ 0x36ac },
+   .cxc_count = 1,
+   .pd = {
+   .name = "vfe0",
+   },
+   .parent = _gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc jpeg_gdsc = {
+   .gdscr = 0x35a4,
+   .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
+   .cxc_count = 4,
+   .pd = {
+   .name = "jpeg",
+   },
+   .parent = _gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc cpp_gdsc = {
+   .gdscr = 0x36d4,
+   .cxcs = (unsigned int []){ 0x36b0 },
+   .cxc_count = 1,
+   .pd = {
+   .name = "cpp",
+   },
+   .parent = _gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc fd_gdsc = {
+   .gdscr = 0x3b64,
+   .cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
+   .cxc_count = 2,
+   .pd = {
+   .name = "fd",
+   },
+   .parent = _gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc mdss_gdsc = {
+   .gdscr = 0x2304,
+   .cxcs = (unsigned int []){ 0x2310, 0x231c },
+   .cxc_count = 2,
+   .pd = {
+   .name = "mdss",
+   },
+   .parent = _mdss_gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
 static struct clk_regmap *mmcc_msm8996_clocks[] = {
[MMPLL0_EARLY] = _early.clkr,
[MMPLL0_PLL] = ,
@@ -3093,6 +3229,22 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = {
[FD_AHB_CLK] = _ahb_clk.clkr,
 };
 
+static struct gdsc *

Re: [PATCH 5/6] clk: qcom: gdsc: Do not check for disabled status on votable gdscs

[Rajendra Nayak]

On 12/01/2015 07:23 AM, Stephen Boyd wrote:
> On 11/26, Rajendra Nayak wrote:
>> Some gdscs might be controlled via voting registers and might not
>> really disable when the kernel intends to disable them (due to other
>> votes keeping them enabled)
>> Mark these gdscs with a flag for we do not check/wait on a disable
>> status for these gdscs within the kernel disable callback.
>>
>> Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
>> ---
>>  drivers/clk/qcom/gcc-msm8996.c  |  4 
>>  drivers/clk/qcom/gdsc.c |  4 
>>  drivers/clk/qcom/gdsc.h | 15 ---
>>  drivers/clk/qcom/mmcc-msm8996.c |  3 +++
>>  4 files changed, 19 insertions(+), 7 deletions(-)
> 
> We should have this patch before adding the gdscs that use it.
> Prevents any bisect hole.

yes, will rearrange to move this up in the series.

> 
>>  static struct gdsc usb30_gdsc = {
>> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
>> index fb2e43c..984537f 100644
>> --- a/drivers/clk/qcom/gdsc.c
>> +++ b/drivers/clk/qcom/gdsc.c
>> @@ -65,6 +65,10 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
>>  if (ret)
>>  return ret;
>>  
>> +/* If disabling votable gdscs, don't poll on status */
>> +if ((sc->flags & VOTABLE) && !en)
>> +return 0;
>> +
> 
> There's an explicit delay of 100uS on the disable path for
> votable gdscs in the downstream code. I don't see that here.

right, I just left it out as I did not see any issues testing
without it, when I did enable/disable the votable gdscs in
a tight loop. But maybe my testing was limited to only apss
voting for these so I can put it back in.

> 
>>  timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
>>  
>>  if (sc->gds_hw_ctrl) {
>> diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
>> index 66a43be..91cbb09 100644
>> --- a/drivers/clk/qcom/gdsc.h
>> +++ b/drivers/clk/qcom/gdsc.h
>> @@ -20,13 +20,6 @@
>>  struct regmap;
>>  struct reset_controller_dev;
>>  
>> -/* Powerdomain allowable state bitfields */
>> -#define PWRSTS_OFF  BIT(0)
>> -#define PWRSTS_RET  BIT(1)
>> -#define PWRSTS_ON   BIT(2)
>> -#define PWRSTS_OFF_ON   (PWRSTS_OFF | PWRSTS_ON)
>> -#define PWRSTS_RET_ON   (PWRSTS_RET | PWRSTS_ON)
>> -
>>  /**
>>   * struct gdsc - Globally Distributed Switch Controller
>>   * @pd: generic power domain
>> @@ -49,6 +42,14 @@ struct gdsc {
>>  unsigned int*cxcs;
>>  unsigned intcxc_count;
>>  const u8pwrsts;
>> +/* Powerdomain allowable state bitfields */
>> +#define PWRSTS_OFF  BIT(0)
>> +#define PWRSTS_RET  BIT(1)
>> +#define PWRSTS_ON   BIT(2)
>> +#define PWRSTS_OFF_ON   (PWRSTS_OFF | PWRSTS_ON)
>> +#define PWRSTS_RET_ON   (PWRSTS_RET | PWRSTS_ON)
> 
> Yes! We should have done this already. I guess I'm ok combining
> it with this patch.
> 
>> +const u8flags;
>> +#define VOTABLE BIT(0)
>>  struct reset_controller_dev *rcdev;
>>  unsigned int*resets;
>>  unsigned intreset_count;
> 

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Re: arm64: dts: qcom: Add apq8096 dragonboard dts skeletons

[Rajendra Nayak]

On 12/01/2015 05:18 AM, Stephen Boyd wrote:
> On 11/26, Rajendra Nayak wrote:
>> Add new dtsi and dts files for the apq8096 dragonboards with just
>> a serial device used as debug console
>>
>> Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
>> ---
>> Patch applies on top of Stephens' patches to add msm8996 dtsi
>> https://lkml.org/lkml/2015/11/17/955
>>
>>  arch/arm64/boot/dts/qcom/Makefile |  2 +-
>>  arch/arm64/boot/dts/qcom/apq8096-dragonboard.dts  | 21 
>>  arch/arm64/boot/dts/qcom/apq8096-dragonboard.dtsi | 30 
>> +++
>>  3 files changed, 52 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/arm64/boot/dts/qcom/apq8096-dragonboard.dts
>>  create mode 100644 arch/arm64/boot/dts/qcom/apq8096-dragonboard.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile 
>> b/arch/arm64/boot/dts/qcom/Makefile
>> index fa1f661..bd992ef 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -1,5 +1,5 @@
>>  dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb
>> -dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb apq8096-dragonboard.dtb
> 
> We should move to one dtb per line in this file. Other platforms
> are doing the same thing.

Sure, will repost with the change. I just saw the 8916/8016 ones were all in
a single line so did the same.

> 

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Re: [PATCH 2/6] clk: qcom: gdsc: Add support for gdscs with gds hw controller

[Rajendra Nayak]

On 12/01/2015 07:52 AM, Stephen Boyd wrote:
> On 11/26, Rajendra Nayak wrote:
>> @@ -58,30 +58,34 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
>>  {
>>  int ret;
>>  u32 val = en ? 0 : SW_COLLAPSE_MASK;
>> -u32 check = en ? PWR_ON_MASK : 0;
>>  unsigned long timeout;
>> +unsigned int status_reg = sc->gdscr;
>>  
>>  ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
>>  if (ret)
>>  return ret;
>>  
>>  timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
>> -do {
>> -ret = regmap_read(sc->regmap, sc->gdscr, );
>> -if (ret)
>> -return ret;
>>  
>> -if ((val & PWR_ON_MASK) == check)
>> +if (sc->gds_hw_ctrl) {
>> +status_reg = sc->gds_hw_ctrl;
>> +/*
>> + * The gds hw controller asserts/de-asserts the status bit soon
>> + * after it receives a power on/off request from a master.
>> + * The controller then takes around 8 xo cycles to start its internal
>> + * state machine and update the status bit. During this time, the
>> + * status bit does not reflect the true status of the core.
>> + * Add a delay of 1 us between writing to the SW_COLLAPSE bit and
>> + * polling the status bit
>> + */
> 
> Please indent this correctly to the udelay indent level.

will do.

> 
>> +udelay(1);
>> +}
>> +
>> +do {
>> +if (gdsc_is_enabled(sc, status_reg) == en)
>>  return 0;
>>  } while (time_before(jiffies, timeout));
>>  
>> -ret = regmap_read(sc->regmap, sc->gdscr, );
>> -if (ret)
>> -return ret;
>> -
>> -if ((val & PWR_ON_MASK) == check)
>> -return 0;
>> -
> 
> This opens a bug where we timeout and then the status bit changes
> after the timeout. One more check is good and should stay. We
> could also change this to ktime instead of jiffies. That would be
> a good improvement.

If the status bit does change after timeout maybe the timeout isn't
really enough and needs to be increased?

> 
>>  return -ETIMEDOUT;
>>  }
>>  
>> @@ -165,6 +169,7 @@ static int gdsc_init(struct gdsc *sc)
>>  {
>>  u32 mask, val;
>>  int on, ret;
>> +unsigned int reg;
>>  
>>  /*
>>   * Disable HW trigger: collapse/restore occur based on registers writes.
>> @@ -185,7 +190,8 @@ static int gdsc_init(struct gdsc *sc)
>>  return ret;
>>  }
>>  
>> -on = gdsc_is_enabled(sc);
>> +reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
>> +on = gdsc_is_enabled(sc, reg);
> 
> If the gdsc is voteable, then we need to make sure that the vote
> is from us when we boot up. Otherwise the kernel may think that
> the gdsc is enabled, but it gets turned off by some other master
> later on. I don't know if this causes some sort of problem for
> the power domain framework, but we can't rely on the status bit
> unless we're sure that we've actually set the register to enable
> it. In the normal enable/disable path we'll always know we set
> the register, so this really only matters once when we boot up.

right, thanks for catching this. However if we vote for a votable
GDSC just because its ON at boot (due to someone else having voted)
we won't ever remove the vote keeping it always enabled.

I think a safe way would be to consider all votable gdscs for which
*we* haven't voted explicitly to be disabled at boot?

> 

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Re: [PATCH 2/6] clk: qcom: gdsc: Add support for gdscs with gds hw controller

[Rajendra Nayak]

[]..

>> >>   return -ETIMEDOUT;
>> >>  }
>> >>
>> >> @@ -165,6 +169,7 @@ static int gdsc_init(struct gdsc *sc)
>> >>  {
>> >>   u32 mask, val;
>> >>   int on, ret;
>> >> + unsigned int reg;
>> >>
>> >>   /*
>> >>* Disable HW trigger: collapse/restore occur based on registers
>> writes.
>> >> @@ -185,7 +190,8 @@ static int gdsc_init(struct gdsc *sc)
>> >>   return ret;
>> >>   }
>> >>
>> >> - on = gdsc_is_enabled(sc);
>> >> + reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
>> >> + on = gdsc_is_enabled(sc, reg);
>> >
>> > If the gdsc is voteable, then we need to make sure that the vote
>> > is from us when we boot up. Otherwise the kernel may think that
>> > the gdsc is enabled, but it gets turned off by some other master
>> > later on. I don't know if this causes some sort of problem for
>> > the power domain framework, but we can't rely on the status bit
>> > unless we're sure that we've actually set the register to enable
>> > it. In the normal enable/disable path we'll always know we set
>> > the register, so this really only matters once when we boot up.
>>
>> right, thanks for catching this. However if we vote for a votable
>> GDSC just because its ON at boot (due to someone else having voted)
>> we won't ever remove the vote keeping it always enabled.
>>
>> I think a safe way would be to consider all votable gdscs for which
>> *we* haven't voted explicitly to be disabled at boot?
>>
>
> Agreed, when we boot we should consider GDSCs that are indicating
> they're enabled via the bit 31 status bit but without the sw
> enable mask set as "disabled" even though they're actually
> enabled by some other master in the SoC.

Thinking about this a bit more, your earlier suggestion of voting
for the GDSC explicitly seemed to work too, and also seemed cleaner.
genpd ends up removing the vote if there aren't any users as part
of genpd_poweroff_unused()

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[PATCH v2] arm64: dts: qcom: Add apq8096 dragonboard dts skeletons

[Rajendra Nayak]

Add new dtsi and dts files for the apq8096 dragonboards with just
a serial device used as debug console

While at it, also rearrange the Makefile so we have one dtb per line
so as to be consistent with whats done on other platforms.

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/Makefile |  4 ++-
 arch/arm64/boot/dts/qcom/apq8096-dragonboard.dts  | 21 
 arch/arm64/boot/dts/qcom/apq8096-dragonboard.dtsi | 30 +++
 3 files changed, 54 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/qcom/apq8096-dragonboard.dts
 create mode 100644 arch/arm64/boot/dts/qcom/apq8096-dragonboard.dtsi

diff --git a/arch/arm64/boot/dts/qcom/Makefile 
b/arch/arm64/boot/dts/qcom/Makefile
index fa1f661..0fd9a17 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -1,5 +1,7 @@
-dtb-$(CONFIG_ARCH_QCOM)+= apq8016-sbc.dtb msm8916-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM)+= apq8016-sbc.dtb
+dtb-$(CONFIG_ARCH_QCOM)+= msm8916-mtp.dtb
 dtb-$(CONFIG_ARCH_QCOM)+= msm8996-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM)+= apq8096-dragonboard.dtb
 
 always := $(dtb-y)
 subdir-y   := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-dragonboard.dts 
b/arch/arm64/boot/dts/qcom/apq8096-dragonboard.dts
new file mode 100644
index 000..65f4a6a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8096-dragonboard.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "apq8096-dragonboard.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. APQ 8096 DragonBoard";
+   compatible = "qcom,apq8096-dragonboard";
+};
diff --git a/arch/arm64/boot/dts/qcom/apq8096-dragonboard.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-dragonboard.dtsi
new file mode 100644
index 000..9bab5c0
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8096-dragonboard.dtsi
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "msm8996.dtsi"
+
+/ {
+   aliases {
+   serial0 = _uart1;
+   };
+
+   chosen {
+   stdout-path = "serial0";
+   };
+
+   soc {
+   serial@75b {
+   status = "okay";
+   };
+   };
+};
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[PATCH v2 3/6] clk: qcom: gdsc: Add support for votable gdscs

[Rajendra Nayak]

Some gdscs might be controlled via voting registers and might not
really disable when the kernel intends to disable them (due to other
votes keeping them enabled)
Mark these gdscs with a flag for we do not check/wait on a disable
status for these gdscs within the kernel disable callback.

Also at boot, if these GDSCs are found to be ON, we make sure we
vote for them before we inform the genpd framework about their
status. If genpd gets no users, it then disables (removes the vote)
them as part of genpd_poweroff_unused()

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/gdsc.c | 18 ++
 drivers/clk/qcom/gdsc.h | 15 ---
 2 files changed, 26 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 9f530b7..f12d7b2 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -66,6 +66,17 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
if (ret)
return ret;
 
+   /* If disabling votable gdscs, don't poll on status */
+   if ((sc->flags & VOTABLE) && !en) {
+   /*
+* Add a short delay here to ensure that an enable
+* right after it was disabled does not put it in an
+* unknown state
+*/
+   udelay(TIMEOUT_US);
+   return 0;
+   }
+
if (sc->gds_hw_ctrl) {
status_reg = sc->gds_hw_ctrl;
/*
@@ -199,6 +210,13 @@ static int gdsc_init(struct gdsc *sc)
if (on < 0)
return on;
 
+   /*
+* Votable GDSCs can be ON due to Vote from other masters.
+* If a Votable GDSC is ON, make sure we have a Vote.
+*/
+   if ((sc->flags & VOTABLE) && on)
+   gdsc_enable(>pd);
+
if (on || (sc->pwrsts & PWRSTS_RET))
gdsc_force_mem_on(sc);
else
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 66a43be..3bf497c 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -20,13 +20,6 @@
 struct regmap;
 struct reset_controller_dev;
 
-/* Powerdomain allowable state bitfields */
-#define PWRSTS_OFF BIT(0)
-#define PWRSTS_RET BIT(1)
-#define PWRSTS_ON  BIT(2)
-#define PWRSTS_OFF_ON  (PWRSTS_OFF | PWRSTS_ON)
-#define PWRSTS_RET_ON  (PWRSTS_RET | PWRSTS_ON)
-
 /**
  * struct gdsc - Globally Distributed Switch Controller
  * @pd: generic power domain
@@ -49,6 +42,14 @@ struct gdsc {
unsigned int*cxcs;
unsigned intcxc_count;
const u8pwrsts;
+/* Powerdomain allowable state bitfields */
+#define PWRSTS_OFF BIT(0)
+#define PWRSTS_RET BIT(1)
+#define PWRSTS_ON  BIT(2)
+#define PWRSTS_OFF_ON  (PWRSTS_OFF | PWRSTS_ON)
+#define PWRSTS_RET_ON  (PWRSTS_RET | PWRSTS_ON)
+   const u8flags;
+#define VOTABLEBIT(0)
struct reset_controller_dev *rcdev;
unsigned int*resets;
unsigned intreset_count;
-- 
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[PATCH v2 1/6] clk: qcom: gdsc: Add support for hierarchical power domains

[Rajendra Nayak]

Some qcom SoCs' can have hierarchical power domains. Let the gdsc structs
specify the parents (if any) and the driver add genpd subdomains for them.

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/common.c | 14 +-
 drivers/clk/qcom/gdsc.c   | 27 +--
 drivers/clk/qcom/gdsc.h   | 17 -
 3 files changed, 46 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index c112eba..4a34329 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -185,6 +185,7 @@ int qcom_cc_really_probe(struct platform_device *pdev,
struct clk **clks;
struct qcom_reset_controller *reset;
struct qcom_cc *cc;
+   struct gdsc_desc *scd;
size_t num_clks = desc->num_clks;
struct clk_regmap **rclks = desc->clks;
 
@@ -230,15 +231,18 @@ int qcom_cc_really_probe(struct platform_device *pdev,
devm_add_action(dev, qcom_cc_reset_unregister, >rcdev);
 
if (desc->gdscs && desc->num_gdscs) {
-   ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs,
-   >rcdev, regmap);
+   scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
+   if (!scd)
+   return -ENOMEM;
+   scd->dev = dev;
+   scd->scs = desc->gdscs;
+   scd->num = desc->num_gdscs;
+   ret = gdsc_register(scd, >rcdev, regmap);
if (ret)
return ret;
+   devm_add_action(dev, qcom_cc_gdsc_unregister, scd);
}
 
-   devm_add_action(dev, qcom_cc_gdsc_unregister, dev);
-
-
return 0;
 }
 EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index da9fad8..bfab75b 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -201,11 +201,14 @@ static int gdsc_init(struct gdsc *sc)
return 0;
 }
 
-int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
+int gdsc_register(struct gdsc_desc *desc,
  struct reset_controller_dev *rcdev, struct regmap *regmap)
 {
int i, ret;
struct genpd_onecell_data *data;
+   struct device *dev = desc->dev;
+   struct gdsc **scs = desc->scs;
+   size_t num = desc->num;
 
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
@@ -228,10 +231,30 @@ int gdsc_register(struct device *dev, struct gdsc **scs, 
size_t num,
data->domains[i] = [i]->pd;
}
 
+   /* Add subdomains */
+   for (i = 0; i < num; i++) {
+   if (!scs[i])
+   continue;
+   if (scs[i]->parent)
+   pm_genpd_add_subdomain(scs[i]->parent, [i]->pd);
+   }
+
return of_genpd_add_provider_onecell(dev->of_node, data);
 }
 
-void gdsc_unregister(struct device *dev)
+void gdsc_unregister(struct gdsc_desc *desc)
 {
+   int i;
+   struct device *dev = desc->dev;
+   struct gdsc **scs = desc->scs;
+   size_t num = desc->num;
+
+   /* Remove subdomains */
+   for (i = 0; i < num; i++) {
+   if (!scs[i])
+   continue;
+   if (scs[i]->parent)
+   pm_genpd_remove_subdomain(scs[i]->parent, [i]->pd);
+   }
of_genpd_del_provider(dev->of_node);
 }
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 5ded268..4e9dfc1 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -41,6 +41,7 @@ struct reset_controller_dev;
  */
 struct gdsc {
struct generic_pm_domainpd;
+   struct generic_pm_domain*parent;
struct regmap   *regmap;
unsigned intgdscr;
unsigned int*cxcs;
@@ -51,18 +52,24 @@ struct gdsc {
unsigned intreset_count;
 };
 
+struct gdsc_desc {
+   struct device *dev;
+   struct gdsc **scs;
+   size_t num;
+};
+
 #ifdef CONFIG_QCOM_GDSC
-int gdsc_register(struct device *, struct gdsc **, size_t n,
- struct reset_controller_dev *, struct regmap *);
-void gdsc_unregister(struct device *);
+int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
+ struct regmap *);
+void gdsc_unregister(struct gdsc_desc *desc);
 #else
-static inline int gdsc_register(struct device *d, struct gdsc **g, size_t n,
+static inline int gdsc_register(struct gdsc_desc *desc,
struct reset_controller_dev *rcdev,
struct regmap *r)
 {
return -ENOSYS;
 }
 
-static inline void gdsc_unregister(struct device *d) {};
+static inline void gdsc_unregister(struct gdsc_desc *desc) {};
 #endif /* CONFIG_QCOM_GDSC */
 #end

[PATCH v2 4/6] clk: qcom: gdsc: Add GDSCs in msm8996 GCC

[Rajendra Nayak]

Add all data for the GDSCs which are part of msm8996 GCC block

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi|  1 +
 drivers/clk/qcom/gcc-msm8996.c   | 92 
 include/dt-bindings/clock/qcom,gcc-msm8996.h | 11 
 3 files changed, 104 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 2c2736d..31e7bd9 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -147,6 +147,7 @@
compatible = "qcom,gcc-msm8996";
#clock-cells = <1>;
#reset-cells = <1>;
+   #power-domain-cells = <1>;
reg = <0x30 0x9>;
};
 
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 16d7c32..bb8c61f 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -30,6 +30,7 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "gdsc.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 
@@ -3059,6 +3060,83 @@ static struct clk_hw *gcc_msm8996_hws[] = {
_ice_core_postdiv_clk_src.hw,
 };
 
+static struct gdsc aggre0_noc_gdsc = {
+   .gdscr = 0x81004,
+   .gds_hw_ctrl = 0x81028,
+   .pd = {
+   .name = "aggre0_noc",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+   .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
+   .gdscr = 0x7d024,
+   .pd = {
+   .name = "hlos1_vote_aggre0_noc",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+   .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
+   .gdscr = 0x7d034,
+   .pd = {
+   .name = "hlos1_vote_lpass_adsp",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+   .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_lpass_core_gdsc = {
+   .gdscr = 0x7d038,
+   .pd = {
+   .name = "hlos1_vote_lpass_core",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+   .flags = VOTABLE,
+};
+
+static struct gdsc usb30_gdsc = {
+   .gdscr = 0xf004,
+   .pd = {
+   .name = "usb30",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc pcie0_gdsc = {
+   .gdscr = 0x6b004,
+   .pd = {
+   .name = "pcie0",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc pcie1_gdsc = {
+   .gdscr = 0x6d004,
+   .pd = {
+   .name = "pcie1",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc pcie2_gdsc = {
+   .gdscr = 0x6e004,
+   .pd = {
+   .name = "pcie2",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc ufs_gdsc = {
+   .gdscr = 0x75004,
+   .pd = {
+   .name = "ufs",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
 static struct clk_regmap *gcc_msm8996_clocks[] = {
[GPLL0_EARLY] = _early.clkr,
[GPLL0] = ,
@@ -3245,6 +3323,18 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
[GCC_RX1_USB2_CLKREF_CLK] = _rx1_usb2_clkref_clk.clkr,
 };
 
+static struct gdsc *gcc_msm8996_gdscs[] = {
+   [AGGRE0_NOC_GDSC] = _noc_gdsc,
+   [HLOS1_VOTE_AGGRE0_NOC_GDSC] = _vote_aggre0_noc_gdsc,
+   [HLOS1_VOTE_LPASS_ADSP_GDSC] = _vote_lpass_adsp_gdsc,
+   [HLOS1_VOTE_LPASS_CORE_GDSC] = _vote_lpass_core_gdsc,
+   [USB30_GDSC] = _gdsc,
+   [PCIE0_GDSC] = _gdsc,
+   [PCIE1_GDSC] = _gdsc,
+   [PCIE2_GDSC] = _gdsc,
+   [UFS_GDSC] = _gdsc,
+};
+
 static const struct qcom_reset_map gcc_msm8996_resets[] = {
[GCC_SYSTEM_NOC_BCR] = { 0x4000 },
[GCC_CONFIG_NOC_BCR] = { 0x5000 },
@@ -3363,6 +3453,8 @@ static const struct qcom_cc_desc gcc_msm8996_desc = {
.num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
.resets = gcc_msm8996_resets,
.num_resets = ARRAY_SIZE(gcc_msm8996_resets),
+   .gdscs = gcc_msm8996_gdscs,
+   .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
 };
 
 static const struct of_device_id gcc_msm8996_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h 
b/include/dt-bindings/clock/qcom,gcc-msm8996.h
index 888e75c..6f814db 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8996.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -336,4 +336,15 @@
 #define GCC_MSS_Q6_BCR 99
 #define GCC_QREFS_VBG_CAL_BCR  100
 
+/* Indexes for GDSCs */
+#define AGGRE0_NOC_GDSC0
+#define HLOS1_VOTE_AGGRE0_NOC_GDSC 1
+#define HLOS1_VOTE_LPASS_ADSP_GDSC 2
+#define HLOS1_VOTE_LPASS_CORE_GDSC 3
+#define USB30_GDSC

[PATCH v2 0/6] Add support for MSM8996 GDSCs

[Rajendra Nayak]

Changes since v1:
* For votable gdscs which are 'on' at boot, put an explicit vote
* Added a delay post disable for votable gdscs
* Added back the status check after timeout
* rearranged some patch ordering to avoid bisect issues

This series adds support for GDSCs' which are part of gcc and mmcc
in QCOM msm8996 SoC. Series applies on top of clk-next

There are many more cases of gdscs within gdscs (hierarchical power
domains) in msm8996 (msm8974 has one such instance which is supported
upstream) and hence the series adds support within gdsc driver to
handle this.

Also msm8996 has gdscs with gds hw controllers within, for ensuring
slave device idleness before gdscs are powered off, hence the series
also adds support for gdscs with gds hw controllers.

ToDo: Series does not yet add support for gpu gdscs which are part
of mmcc

Tested on apq8096 dragonboards to make sure all modelled gdscs can
be turned on/off successfully

Rajendra Nayak (6):
  clk: qcom: gdsc: Add support for hierarchical power domains
  clk: qcom: gdsc: Add support for gdscs with gds hw controller
  clk: qcom: gdsc: Add support for votable gdscs
  clk: qcom: gdsc: Add GDSCs in msm8996 GCC
  clk: qcom: gdsc: Add mmcc gdscs for msm8996 family
  clk: qcom: mmcc8974: Use gdscs .parent and remove genpd calls

 arch/arm64/boot/dts/qcom/msm8996.dtsi |   2 +
 drivers/clk/qcom/common.c |  14 ++-
 drivers/clk/qcom/gcc-msm8996.c|  92 +++
 drivers/clk/qcom/gdsc.c   |  89 +++
 drivers/clk/qcom/gdsc.h   |  34 --
 drivers/clk/qcom/mmcc-msm8974.c   |  14 +--
 drivers/clk/qcom/mmcc-msm8996.c   | 157 ++
 include/dt-bindings/clock/qcom,gcc-msm8996.h  |  11 ++
 include/dt-bindings/clock/qcom,mmcc-msm8996.h |  17 +++
 9 files changed, 382 insertions(+), 48 deletions(-)

-- 
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of Code Aurora Forum, hosted by The Linux Foundation

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[PATCH v2 6/6] clk: qcom: mmcc8974: Use gdscs .parent and remove genpd calls

[Rajendra Nayak]

With gdsc driver capable of handling hierarchical power domains,
specify oxili_gdsc as parent of oxilicx_gdsc.

Remove all direct calls to genpd from the mmcc clock driver. The
adding and removing of subdomains is now handled from within
the gdsc driver.

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/mmcc-msm8974.c | 14 ++
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index bbe28ed..6b2e4e8 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -2400,6 +2400,7 @@ static struct gdsc oxilicx_gdsc = {
.pd = {
.name = "oxilicx",
},
+   .parent = _gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
 };
 
@@ -2625,22 +2626,11 @@ static int mmcc_msm8974_probe(struct platform_device 
*pdev)
clk_pll_configure_sr_hpm_lp(, regmap, _config, true);
clk_pll_configure_sr_hpm_lp(, regmap, _config, false);
 
-   ret = qcom_cc_really_probe(pdev, _msm8974_desc, regmap);
-   if (ret)
-   return ret;
-
-   return pm_genpd_add_subdomain(_gdsc.pd, _gdsc.pd);
-}
-
-static int mmcc_msm8974_remove(struct platform_device *pdev)
-{
-   pm_genpd_remove_subdomain(_gdsc.pd, _gdsc.pd);
-   return 0;
+   return qcom_cc_really_probe(pdev, _msm8974_desc, regmap);
 }
 
 static struct platform_driver mmcc_msm8974_driver = {
.probe  = mmcc_msm8974_probe,
-   .remove = mmcc_msm8974_remove,
.driver = {
.name   = "mmcc-msm8974",
.of_match_table = mmcc_msm8974_match_table,
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

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Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v2 2/6] clk: qcom: gdsc: Add support for gdscs with gds hw controller

[Rajendra Nayak]

Some gdsc power domains can have a gds_hw_controller block inside
to help ensure all slave devices within the power domain are idle
before the gdsc is actually switched off.
This is mainly useful in power domains which host a MMU, in which
case its necessary to make sure there are no outstanding MMU operations
or pending bus transactions before the power domain is turned off.

In gdscs with gds_hw_controller block, its necessary to check the
gds_hw_ctrl status bits instead of the ones in gdscr, to determine
the state of the powerdomain.

While at it, also move away from using jiffies and use ktime APIs
instead for busy looping on status bits.

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/gdsc.c | 44 +++-
 drivers/clk/qcom/gdsc.h |  2 ++
 2 files changed, 29 insertions(+), 17 deletions(-)

diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index bfab75b..9f530b7 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -42,12 +43,12 @@
 
 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
 
-static int gdsc_is_enabled(struct gdsc *sc)
+static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
 {
u32 val;
int ret;
 
-   ret = regmap_read(sc->regmap, sc->gdscr, );
+   ret = regmap_read(sc->regmap, reg, );
if (ret)
return ret;
 
@@ -58,28 +59,35 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
 {
int ret;
u32 val = en ? 0 : SW_COLLAPSE_MASK;
-   u32 check = en ? PWR_ON_MASK : 0;
-   unsigned long timeout;
+   ktime_t start;
+   unsigned int status_reg = sc->gdscr;
 
ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
if (ret)
return ret;
 
-   timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
-   do {
-   ret = regmap_read(sc->regmap, sc->gdscr, );
-   if (ret)
-   return ret;
+   if (sc->gds_hw_ctrl) {
+   status_reg = sc->gds_hw_ctrl;
+   /*
+* The gds hw controller asserts/de-asserts the status bit soon
+* after it receives a power on/off request from a master.
+* The controller then takes around 8 xo cycles to start its
+* internal state machine and update the status bit. During
+* this time, the status bit does not reflect the true status
+* of the core.
+* Add a delay of 1 us between writing to the SW_COLLAPSE bit
+* and polling the status bit.
+*/
+   udelay(1);
+   }
 
-   if ((val & PWR_ON_MASK) == check)
+   start = ktime_get();
+   do {
+   if (gdsc_is_enabled(sc, status_reg) == en)
return 0;
-   } while (time_before(jiffies, timeout));
-
-   ret = regmap_read(sc->regmap, sc->gdscr, );
-   if (ret)
-   return ret;
+   } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
 
-   if ((val & PWR_ON_MASK) == check)
+   if (gdsc_is_enabled(sc, status_reg) == en)
return 0;
 
return -ETIMEDOUT;
@@ -165,6 +173,7 @@ static int gdsc_init(struct gdsc *sc)
 {
u32 mask, val;
int on, ret;
+   unsigned int reg;
 
/*
 * Disable HW trigger: collapse/restore occur based on registers writes.
@@ -185,7 +194,8 @@ static int gdsc_init(struct gdsc *sc)
return ret;
}
 
-   on = gdsc_is_enabled(sc);
+   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
+   on = gdsc_is_enabled(sc, reg);
if (on < 0)
return on;
 
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 4e9dfc1..66a43be 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -32,6 +32,7 @@ struct reset_controller_dev;
  * @pd: generic power domain
  * @regmap: regmap for MMIO accesses
  * @gdscr: gsdc control register
+ * @gds_hw_ctrl: gds_hw_ctrl register
  * @cxcs: offsets of branch registers to toggle mem/periph bits in
  * @cxc_count: number of @cxcs
  * @pwrsts: Possible powerdomain power states
@@ -44,6 +45,7 @@ struct gdsc {
struct generic_pm_domain*parent;
struct regmap   *regmap;
unsigned intgdscr;
+   unsigned intgds_hw_ctrl;
unsigned int*cxcs;
unsigned intcxc_count;
const u8pwrsts;
-- 
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of Code Aurora Forum, hosted by The Linux Foundation

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[PATCH v2 5/6] clk: qcom: gdsc: Add mmcc gdscs for msm8996 family

[Rajendra Nayak]

Add all gdsc data which are part of mmcc on msm8996 family

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi |   1 +
 drivers/clk/qcom/mmcc-msm8996.c   | 157 ++
 include/dt-bindings/clock/qcom,mmcc-msm8996.h |  17 +++
 3 files changed, 175 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 31e7bd9..0506fb8 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -252,6 +252,7 @@
compatible = "qcom,mmcc-msm8996";
#clock-cells = <1>;
#reset-cells = <1>;
+   #power-domain-cells = <1>;
reg = <0x8c 0x4>;
assigned-clocks = < MMPLL9_PLL>,
  < MMPLL1_PLL>,
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index 064f3ea..a0a7338 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -32,6 +32,7 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "gdsc.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 
@@ -2917,6 +2918,144 @@ static struct clk_hw *mmcc_msm8996_hws[] = {
_div.hw,
 };
 
+struct gdsc mmagic_video_gdsc = {
+   .gdscr = 0x119c,
+   .gds_hw_ctrl = 0x120c,
+   .pd = {
+   .name = "mmagic_video",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+   .flags = VOTABLE,
+};
+
+struct gdsc mmagic_mdss_gdsc = {
+   .gdscr = 0x247c,
+   .gds_hw_ctrl = 0x2480,
+   .pd = {
+   .name = "mmagic_mdss",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+   .flags = VOTABLE,
+};
+
+struct gdsc mmagic_camss_gdsc = {
+   .gdscr = 0x3c4c,
+   .gds_hw_ctrl = 0x3c50,
+   .pd = {
+   .name = "mmagic_camss",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+   .flags = VOTABLE,
+};
+
+struct gdsc venus_gdsc = {
+   .gdscr = 0x1024,
+   .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
+   .cxc_count = 3,
+   .pd = {
+   .name = "venus",
+   },
+   .parent = _video_gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc venus_core0_gdsc = {
+   .gdscr = 0x1040,
+   .cxcs = (unsigned int []){ 0x1048 },
+   .cxc_count = 1,
+   .pd = {
+   .name = "venus_core0",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc venus_core1_gdsc = {
+   .gdscr = 0x1044,
+   .cxcs = (unsigned int []){ 0x104c },
+   .cxc_count = 1,
+   .pd = {
+   .name = "venus_core1",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc camss_gdsc = {
+   .gdscr = 0x34a0,
+   .cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
+   .cxc_count = 2,
+   .pd = {
+   .name = "camss",
+   },
+   .parent = _camss_gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc vfe0_gdsc = {
+   .gdscr = 0x3664,
+   .cxcs = (unsigned int []){ 0x36a8 },
+   .cxc_count = 1,
+   .pd = {
+   .name = "vfe0",
+   },
+   .parent = _gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc vfe1_gdsc = {
+   .gdscr = 0x3674,
+   .cxcs = (unsigned int []){ 0x36ac },
+   .cxc_count = 1,
+   .pd = {
+   .name = "vfe0",
+   },
+   .parent = _gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc jpeg_gdsc = {
+   .gdscr = 0x35a4,
+   .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
+   .cxc_count = 4,
+   .pd = {
+   .name = "jpeg",
+   },
+   .parent = _gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc cpp_gdsc = {
+   .gdscr = 0x36d4,
+   .cxcs = (unsigned int []){ 0x36b0 },
+   .cxc_count = 1,
+   .pd = {
+   .name = "cpp",
+   },
+   .parent = _gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc fd_gdsc = {
+   .gdscr = 0x3b64,
+   .cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
+   .cxc_count = 2,
+   .pd = {
+   .name = "fd",
+   },
+   .parent = _gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct gdsc mdss_gdsc = {
+   .gdscr = 0x2304,
+   .cxcs = (unsigned int []){ 0x2310, 0x231c },
+   .cxc_count = 2,
+   .pd = {
+   .name = "mdss",
+   },
+   .parent = _mdss_gdsc.pd,
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
 static struct clk_regmap *mmcc_msm8996_clocks[] = {
[MMPLL0_EARLY] = _early.clkr,
[MMPLL0_PLL] = ,
@@ -3093,6 +3232,22 @@ static struct clk_regmap *mmcc_msm8996_clocks

[PATCH 5/6] clk: qcom: gdsc: Do not check for disabled status on votable gdscs

[Rajendra Nayak]

Some gdscs might be controlled via voting registers and might not
really disable when the kernel intends to disable them (due to other
votes keeping them enabled)
Mark these gdscs with a flag for we do not check/wait on a disable
status for these gdscs within the kernel disable callback.

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/gcc-msm8996.c  |  4 
 drivers/clk/qcom/gdsc.c |  4 
 drivers/clk/qcom/gdsc.h | 15 ---
 drivers/clk/qcom/mmcc-msm8996.c |  3 +++
 4 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index c5bce5f..bb8c61f 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -3067,6 +3067,7 @@ static struct gdsc aggre0_noc_gdsc = {
.name = "aggre0_noc",
},
.pwrsts = PWRSTS_OFF_ON,
+   .flags = VOTABLE,
 };
 
 static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
@@ -3075,6 +3076,7 @@ static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
.name = "hlos1_vote_aggre0_noc",
},
.pwrsts = PWRSTS_OFF_ON,
+   .flags = VOTABLE,
 };
 
 static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
@@ -3083,6 +3085,7 @@ static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
.name = "hlos1_vote_lpass_adsp",
},
.pwrsts = PWRSTS_OFF_ON,
+   .flags = VOTABLE,
 };
 
 static struct gdsc hlos1_vote_lpass_core_gdsc = {
@@ -3091,6 +3094,7 @@ static struct gdsc hlos1_vote_lpass_core_gdsc = {
.name = "hlos1_vote_lpass_core",
},
.pwrsts = PWRSTS_OFF_ON,
+   .flags = VOTABLE,
 };
 
 static struct gdsc usb30_gdsc = {
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index fb2e43c..984537f 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -65,6 +65,10 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
if (ret)
return ret;
 
+   /* If disabling votable gdscs, don't poll on status */
+   if ((sc->flags & VOTABLE) && !en)
+   return 0;
+
timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
 
if (sc->gds_hw_ctrl) {
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 66a43be..91cbb09 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -20,13 +20,6 @@
 struct regmap;
 struct reset_controller_dev;
 
-/* Powerdomain allowable state bitfields */
-#define PWRSTS_OFF BIT(0)
-#define PWRSTS_RET BIT(1)
-#define PWRSTS_ON  BIT(2)
-#define PWRSTS_OFF_ON  (PWRSTS_OFF | PWRSTS_ON)
-#define PWRSTS_RET_ON  (PWRSTS_RET | PWRSTS_ON)
-
 /**
  * struct gdsc - Globally Distributed Switch Controller
  * @pd: generic power domain
@@ -49,6 +42,14 @@ struct gdsc {
unsigned int*cxcs;
unsigned intcxc_count;
const u8pwrsts;
+/* Powerdomain allowable state bitfields */
+#define PWRSTS_OFF BIT(0)
+#define PWRSTS_RET BIT(1)
+#define PWRSTS_ON  BIT(2)
+#define PWRSTS_OFF_ON  (PWRSTS_OFF | PWRSTS_ON)
+#define PWRSTS_RET_ON  (PWRSTS_RET | PWRSTS_ON)
+   const u8flags;
+#define VOTABLEBIT(0)
struct reset_controller_dev *rcdev;
unsigned int*resets;
unsigned intreset_count;
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index 236acf5..a0a7338 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -2925,6 +2925,7 @@ struct gdsc mmagic_video_gdsc = {
.name = "mmagic_video",
},
.pwrsts = PWRSTS_OFF_ON,
+   .flags = VOTABLE,
 };
 
 struct gdsc mmagic_mdss_gdsc = {
@@ -2934,6 +2935,7 @@ struct gdsc mmagic_mdss_gdsc = {
.name = "mmagic_mdss",
},
.pwrsts = PWRSTS_OFF_ON,
+   .flags = VOTABLE,
 };
 
 struct gdsc mmagic_camss_gdsc = {
@@ -2943,6 +2945,7 @@ struct gdsc mmagic_camss_gdsc = {
.name = "mmagic_camss",
},
.pwrsts = PWRSTS_OFF_ON,
+   .flags = VOTABLE,
 };
 
 struct gdsc venus_gdsc = {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

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[PATCH 2/6] clk: qcom: gdsc: Add support for gdscs with gds hw controller

[Rajendra Nayak]

Some gdsc power domains can have a gds_hw_controller block inside
to help ensure all slave devices within the power domain are idle
before the gdsc is actually switched off.
This is mainly useful in power domains which host a MMU, in which
case its necessary to make sure there are no outstanding MMU operations
or pending bus transactions before the power domain is turned off.

In gdscs with gds_hw_controller block, its necessary to check the
gds_hw_ctrl status bits instead of the ones in gdscr, to determine
the state of the powerdomain.

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/gdsc.c | 38 ++
 drivers/clk/qcom/gdsc.h |  2 ++
 2 files changed, 24 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index a164c38..fb2e43c 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -42,12 +42,12 @@
 
 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
 
-static int gdsc_is_enabled(struct gdsc *sc)
+static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
 {
u32 val;
int ret;
 
-   ret = regmap_read(sc->regmap, sc->gdscr, );
+   ret = regmap_read(sc->regmap, reg, );
if (ret)
return ret;
 
@@ -58,30 +58,34 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
 {
int ret;
u32 val = en ? 0 : SW_COLLAPSE_MASK;
-   u32 check = en ? PWR_ON_MASK : 0;
unsigned long timeout;
+   unsigned int status_reg = sc->gdscr;
 
ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
if (ret)
return ret;
 
timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
-   do {
-   ret = regmap_read(sc->regmap, sc->gdscr, );
-   if (ret)
-   return ret;
 
-   if ((val & PWR_ON_MASK) == check)
+   if (sc->gds_hw_ctrl) {
+   status_reg = sc->gds_hw_ctrl;
+   /*
+* The gds hw controller asserts/de-asserts the status bit soon
+* after it receives a power on/off request from a master.
+* The controller then takes around 8 xo cycles to start its internal
+* state machine and update the status bit. During this time, the
+* status bit does not reflect the true status of the core.
+* Add a delay of 1 us between writing to the SW_COLLAPSE bit and
+* polling the status bit
+*/
+   udelay(1);
+   }
+
+   do {
+   if (gdsc_is_enabled(sc, status_reg) == en)
return 0;
} while (time_before(jiffies, timeout));
 
-   ret = regmap_read(sc->regmap, sc->gdscr, );
-   if (ret)
-   return ret;
-
-   if ((val & PWR_ON_MASK) == check)
-   return 0;
-
return -ETIMEDOUT;
 }
 
@@ -165,6 +169,7 @@ static int gdsc_init(struct gdsc *sc)
 {
u32 mask, val;
int on, ret;
+   unsigned int reg;
 
/*
 * Disable HW trigger: collapse/restore occur based on registers writes.
@@ -185,7 +190,8 @@ static int gdsc_init(struct gdsc *sc)
return ret;
}
 
-   on = gdsc_is_enabled(sc);
+   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
+   on = gdsc_is_enabled(sc, reg);
if (on < 0)
return on;
 
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 4e9dfc1..66a43be 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -32,6 +32,7 @@ struct reset_controller_dev;
  * @pd: generic power domain
  * @regmap: regmap for MMIO accesses
  * @gdscr: gsdc control register
+ * @gds_hw_ctrl: gds_hw_ctrl register
  * @cxcs: offsets of branch registers to toggle mem/periph bits in
  * @cxc_count: number of @cxcs
  * @pwrsts: Possible powerdomain power states
@@ -44,6 +45,7 @@ struct gdsc {
struct generic_pm_domain*parent;
struct regmap   *regmap;
unsigned intgdscr;
+   unsigned intgds_hw_ctrl;
unsigned int*cxcs;
unsigned intcxc_count;
const u8pwrsts;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at  http://www.tux.org/lkml/

[PATCH 3/6] clk: qcom: gdsc: Add GDSCs in msm8996 GCC

[Rajendra Nayak]

Add all data for the GDSCs which are part of msm8996 GCC block

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi|  1 +
 drivers/clk/qcom/gcc-msm8996.c   | 88 
 include/dt-bindings/clock/qcom,gcc-msm8996.h | 11 
 3 files changed, 100 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 2c2736d..31e7bd9 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -147,6 +147,7 @@
compatible = "qcom,gcc-msm8996";
#clock-cells = <1>;
#reset-cells = <1>;
+   #power-domain-cells = <1>;
reg = <0x30 0x9>;
};
 
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 16d7c32..c5bce5f 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -30,6 +30,7 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "gdsc.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 
@@ -3059,6 +3060,79 @@ static struct clk_hw *gcc_msm8996_hws[] = {
_ice_core_postdiv_clk_src.hw,
 };
 
+static struct gdsc aggre0_noc_gdsc = {
+   .gdscr = 0x81004,
+   .gds_hw_ctrl = 0x81028,
+   .pd = {
+   .name = "aggre0_noc",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
+   .gdscr = 0x7d024,
+   .pd = {
+   .name = "hlos1_vote_aggre0_noc",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
+   .gdscr = 0x7d034,
+   .pd = {
+   .name = "hlos1_vote_lpass_adsp",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc hlos1_vote_lpass_core_gdsc = {
+   .gdscr = 0x7d038,
+   .pd = {
+   .name = "hlos1_vote_lpass_core",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc usb30_gdsc = {
+   .gdscr = 0xf004,
+   .pd = {
+   .name = "usb30",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc pcie0_gdsc = {
+   .gdscr = 0x6b004,
+   .pd = {
+   .name = "pcie0",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc pcie1_gdsc = {
+   .gdscr = 0x6d004,
+   .pd = {
+   .name = "pcie1",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc pcie2_gdsc = {
+   .gdscr = 0x6e004,
+   .pd = {
+   .name = "pcie2",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc ufs_gdsc = {
+   .gdscr = 0x75004,
+   .pd = {
+   .name = "ufs",
+   },
+   .pwrsts = PWRSTS_OFF_ON,
+};
+
 static struct clk_regmap *gcc_msm8996_clocks[] = {
[GPLL0_EARLY] = _early.clkr,
[GPLL0] = ,
@@ -3245,6 +3319,18 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
[GCC_RX1_USB2_CLKREF_CLK] = _rx1_usb2_clkref_clk.clkr,
 };
 
+static struct gdsc *gcc_msm8996_gdscs[] = {
+   [AGGRE0_NOC_GDSC] = _noc_gdsc,
+   [HLOS1_VOTE_AGGRE0_NOC_GDSC] = _vote_aggre0_noc_gdsc,
+   [HLOS1_VOTE_LPASS_ADSP_GDSC] = _vote_lpass_adsp_gdsc,
+   [HLOS1_VOTE_LPASS_CORE_GDSC] = _vote_lpass_core_gdsc,
+   [USB30_GDSC] = _gdsc,
+   [PCIE0_GDSC] = _gdsc,
+   [PCIE1_GDSC] = _gdsc,
+   [PCIE2_GDSC] = _gdsc,
+   [UFS_GDSC] = _gdsc,
+};
+
 static const struct qcom_reset_map gcc_msm8996_resets[] = {
[GCC_SYSTEM_NOC_BCR] = { 0x4000 },
[GCC_CONFIG_NOC_BCR] = { 0x5000 },
@@ -3363,6 +3449,8 @@ static const struct qcom_cc_desc gcc_msm8996_desc = {
.num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
.resets = gcc_msm8996_resets,
.num_resets = ARRAY_SIZE(gcc_msm8996_resets),
+   .gdscs = gcc_msm8996_gdscs,
+   .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
 };
 
 static const struct of_device_id gcc_msm8996_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h 
b/include/dt-bindings/clock/qcom,gcc-msm8996.h
index 888e75c..6f814db 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8996.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -336,4 +336,15 @@
 #define GCC_MSS_Q6_BCR 99
 #define GCC_QREFS_VBG_CAL_BCR  100
 
+/* Indexes for GDSCs */
+#define AGGRE0_NOC_GDSC0
+#define HLOS1_VOTE_AGGRE0_NOC_GDSC 1
+#define HLOS1_VOTE_LPASS_ADSP_GDSC 2
+#define HLOS1_VOTE_LPASS_CORE_GDSC 3
+#define USB30_GDSC 4
+#define PCIE0_GDSC 5
+#define PCIE1_GDSC 6
+#define PCIE2_GDSC   

[PATCH 1/6] clk: qcom: gdsc: Add support for hierarchical power domains

[Rajendra Nayak]

Some qcom SoCs' can have hierarchical power domains. Let the gdsc structs
specify the parents (if any) and the driver add genpd subdomains for them.

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/common.c | 14 +-
 drivers/clk/qcom/gdsc.c   | 27 +--
 drivers/clk/qcom/gdsc.h   | 17 -
 3 files changed, 46 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index 8fa4772..cf100f9 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -98,6 +98,7 @@ int qcom_cc_really_probe(struct platform_device *pdev,
struct clk **clks;
struct qcom_reset_controller *reset;
struct qcom_cc *cc;
+   struct gdsc_desc *scd;
size_t num_clks = desc->num_clks;
struct clk_regmap **rclks = desc->clks;
 
@@ -143,15 +144,18 @@ int qcom_cc_really_probe(struct platform_device *pdev,
devm_add_action(dev, qcom_cc_reset_unregister, >rcdev);
 
if (desc->gdscs && desc->num_gdscs) {
-   ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs,
-   >rcdev, regmap);
+   scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
+   if (!scd)
+   return -ENOMEM;
+   scd->dev = dev;
+   scd->scs = desc->gdscs;
+   scd->num = desc->num_gdscs;
+   ret = gdsc_register(scd, >rcdev, regmap);
if (ret)
return ret;
+   devm_add_action(dev, qcom_cc_gdsc_unregister, scd);
}
 
-   devm_add_action(dev, qcom_cc_gdsc_unregister, dev);
-
-
return 0;
 }
 EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index da9fad8..a164c38 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -201,11 +201,14 @@ static int gdsc_init(struct gdsc *sc)
return 0;
 }
 
-int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
+int gdsc_register(struct gdsc_desc *desc,
  struct reset_controller_dev *rcdev, struct regmap *regmap)
 {
int i, ret;
struct genpd_onecell_data *data;
+   struct device *dev = desc->dev;
+   struct gdsc **scs = desc->scs;
+   size_t num = desc->num;
 
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
@@ -228,10 +231,30 @@ int gdsc_register(struct device *dev, struct gdsc **scs, 
size_t num,
data->domains[i] = [i]->pd;
}
 
+   /* Add subdomains */
+   for (i = 0; i < num; i++) {
+   if (!scs[i])
+   continue;
+   if (scs[i]->parent)
+   pm_genpd_add_subdomain(scs[i]->parent, [i]->pd);
+   }
+
return of_genpd_add_provider_onecell(dev->of_node, data);
 }
 
-void gdsc_unregister(struct device *dev)
+void gdsc_unregister(struct gdsc_desc *desc)
 {
+   int i;
+   struct device *dev = desc->dev;
+   struct gdsc **scs = desc->scs;
+   size_t num = desc->num;
+
+   /* Remove subdomains */
+   for (i = 0; i < num; i++) {
+   if (!scs[i])
+   continue;
+   if (scs[i]->parent)
+   pm_genpd_remove_subdomain(scs[i]->parent, [i]->pd);
+   }
of_genpd_del_provider(dev->of_node);
 }
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 5ded268..4e9dfc1 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -41,6 +41,7 @@ struct reset_controller_dev;
  */
 struct gdsc {
struct generic_pm_domainpd;
+   struct generic_pm_domain*parent;
struct regmap   *regmap;
unsigned intgdscr;
unsigned int*cxcs;
@@ -51,18 +52,24 @@ struct gdsc {
unsigned intreset_count;
 };
 
+struct gdsc_desc {
+   struct device *dev;
+   struct gdsc **scs;
+   size_t num;
+};
+
 #ifdef CONFIG_QCOM_GDSC
-int gdsc_register(struct device *, struct gdsc **, size_t n,
- struct reset_controller_dev *, struct regmap *);
-void gdsc_unregister(struct device *);
+int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
+ struct regmap *);
+void gdsc_unregister(struct gdsc_desc *desc);
 #else
-static inline int gdsc_register(struct device *d, struct gdsc **g, size_t n,
+static inline int gdsc_register(struct gdsc_desc *desc,
struct reset_controller_dev *rcdev,
struct regmap *r)
 {
return -ENOSYS;
 }
 
-static inline void gdsc_unregister(struct device *d) {};
+static inline void gdsc_unregister(struct gdsc_desc *desc) {};
 #endif /* CONFIG_QCOM_GDSC */
 #end

Re: [PATCH 2/4] arm64: dts: Add msm8996 SoC and MTP board support

[Rajendra Nayak]

On 11/18/2015 06:42 AM, Stephen Boyd wrote:
> Add initial device tree support for the Qualcomm MSM8996 SoC and
> MTP8996 evaluation board.
> 
> Signed-off-by: Stephen Boyd 
> ---
[]...

> +
> + spmi_bus: qcom,spmi@400f000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0x400f000 0x1000>,
> +   <0x440 0x80>,
> +   <0x4c0 0x80>,
> +   <0x580 0x20>,
> +   <0x400a000 0x002100>;
> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> + interrupt-names = "periph_irq";
> + interrupts = ;
> + qcom,ee = <0>;
> + qcom,channel = <0>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + };
> +
> + mmcc: clock-controller@8c {
> + compatible = "qcom,mmcc-msm8996";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + reg = <0x8c 0xc>;

I think the size here should be 0x4 and not 0xc

regards,
Rajendra

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Re: [PATCH 0/5] Add support for MSM8996 clock controllers

[Rajendra Nayak]

On 11/18/2015 06:37 AM, Stephen Boyd wrote:
> These patches add support for the global and multimedia clock controllers
> found on MSM8996 devices. The first patch allows us to implement a
> "power of two" divider of different widths with a table based divider.
> The second patch adds support for Alpha PLLs and the 3rd and 5th patches
> add support for the two clock controllers. The fourth patch is
> a new type of clock ops for the graphics clock that does some custom
> ping-pong between different PLLs when switching graphics frequencies.
> 
> Some work is still pending, mostly adding GDSCs and configuring the

I have the GDSC support patches done on top. Will post once I 
get some reasonable testing done.

> multimedia PLLs for FSM voting mode vs. manually enabling and
> disabling them. So a v2 is probably going to come out after
> some more testing is done.
> 
> Cc: Rajendra Nayak <rna...@codeaurora.com>
> 
> Stephen Boyd (5):
>   clk: divider: Cap table divider values to 'width' member
>   clk: qcom: Add Alpha PLL support
>   clk: qcom: Add MSM8996 Global Clock Control (GCC) driver
>   clk: qcom: Add gfx3d ping-pong PLL frequency switching
>   clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver
> 
>  .../devicetree/bindings/clock/qcom,gcc.txt |1 +
>  .../devicetree/bindings/clock/qcom,mmcc.txt|1 +
>  drivers/clk/clk-divider.c  |9 +-
>  drivers/clk/qcom/Kconfig   |   17 +
>  drivers/clk/qcom/Makefile  |3 +
>  drivers/clk/qcom/clk-alpha-pll.c   |  355 +++
>  drivers/clk/qcom/clk-alpha-pll.h   |   57 +
>  drivers/clk/qcom/clk-rcg.h |1 +
>  drivers/clk/qcom/clk-rcg2.c|   87 +
>  drivers/clk/qcom/gcc-msm8996.c | 3332 
> 
>  drivers/clk/qcom/mmcc-msm8996.c| 3209 +++
>  include/dt-bindings/clock/qcom,gcc-msm8996.h   |  333 ++
>  include/dt-bindings/clock/qcom,mmcc-msm8996.h  |  285 ++
>  13 files changed, 7686 insertions(+), 4 deletions(-)
>  create mode 100644 drivers/clk/qcom/clk-alpha-pll.c
>  create mode 100644 drivers/clk/qcom/clk-alpha-pll.h
>  create mode 100644 drivers/clk/qcom/gcc-msm8996.c
>  create mode 100644 drivers/clk/qcom/mmcc-msm8996.c
>  create mode 100644 include/dt-bindings/clock/qcom,gcc-msm8996.h
>  create mode 100644 include/dt-bindings/clock/qcom,mmcc-msm8996.h
> 

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Re: [PATCH v2 6/6] clk: qcom: mmcc8974: Use gdscs .parent and remove genpd calls

[Rajendra Nayak]

On 02/12/2016 06:03 AM, Stephen Boyd wrote:
> On 12/01, Rajendra Nayak wrote:
>> With gdsc driver capable of handling hierarchical power domains,
>> specify oxili_gdsc as parent of oxilicx_gdsc.
>>
>> Remove all direct calls to genpd from the mmcc clock driver. The
>> adding and removing of subdomains is now handled from within
>> the gdsc driver.
>>
>> Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
>> ---
> 
> Applied to clk-next + this squashed in

Thanks Stephen, for fixing these up before pulling in.
I will resubmit the dtsi parts as a separate patch.

> 
> ---8<
> diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
> index 6b2e4e808125..bcda56e81503 100644
> --- a/drivers/clk/qcom/mmcc-msm8974.c
> +++ b/drivers/clk/qcom/mmcc-msm8974.c
> @@ -2617,7 +2617,6 @@ MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
>  static int mmcc_msm8974_probe(struct platform_device *pdev)
>  {
>   struct regmap *regmap;
> - int ret;
>  
>   regmap = qcom_cc_map(pdev, _msm8974_desc);
>   if (IS_ERR(regmap))
> 

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hosted by The Linux Foundation

Re: [PATCH v2 2/2] regulator: qcom_spmi: Only use selector based regulator ops

[Rajendra Nayak]

[]...
  
>  static int spmi_regulator_select_voltage_same_range(struct spmi_regulator 
> *vreg,
> - int min_uV, int max_uV, u8 *range_sel, u8 *voltage_sel,
> - unsigned *selector)
> + int min_uV, int max_uV)
>  {
>   const struct spmi_voltage_range *range;
>   int uV = min_uV;
> - int i;
> + int i, selector;
>  
>   range = spmi_regulator_find_range(vreg);
>   if (!range)
> @@ -638,8 +665,8 @@ static int 
> spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg,
>* Force uV to be an allowed set point by applying a ceiling function to
>* the uV value.
>*/
> - *voltage_sel = DIV_ROUND_UP(uV - range->min_uV, range->step_uV);
> - uV = *voltage_sel * range->step_uV + range->min_uV;
> + uV = DIV_ROUND_UP(uV - range->min_uV, range->step_uV);
> + uV = uV * range->step_uV + range->min_uV;
>  
>   if (uV > max_uV) {
>   /*
> @@ -649,43 +676,49 @@ static int 
> spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg,
>   goto different_range;
>   }
>  
> - *selector = 0;
> + selector = 0;
>   for (i = 0; i < vreg->set_points->count; i++) {
>   if (uV >= vreg->set_points->range[i].set_point_min_uV
>   && uV <= vreg->set_points->range[i].set_point_max_uV) {
> - *selector +=
> + selector +=
>   (uV - vreg->set_points->range[i].set_point_min_uV)
>   / vreg->set_points->range[i].step_uV;
>   break;
>   }
>  
> - *selector += vreg->set_points->range[i].n_voltages;
> + selector += vreg->set_points->range[i].n_voltages;
>   }
>  
> - if (*selector >= vreg->set_points->n_voltages)
> + if (selector >= vreg->set_points->n_voltages)
>   goto different_range;
>  
>   return 0;

This should now return selector instead of 0

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[PATCH 3/5] arm: dts: apq8084: Add thermal zones, tsens and qfprom nodes

[Rajendra Nayak]

Add thermal zones, tsens and qfprom nodes

Acked-by: Eduardo Valentin <edubez...@gmail.com>
Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-apq8084.dtsi | 119 
 1 file changed, 119 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi 
b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 7c2df06..41e09c8 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -94,6 +94,104 @@
};
};
 
+   thermal-zones {
+   cpu-thermal0 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 5>;
+
+   trips {
+   cpu_alert0: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit0: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+
+   cpu-thermal1 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 6>;
+
+   trips {
+   cpu_alert1: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit1: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+
+   cpu-thermal2 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 7>;
+
+   trips {
+   cpu_alert2: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit2: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+
+   cpu-thermal3 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 8>;
+
+   trips {
+   cpu_alert3: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit3: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+   };
+
cpu-pmu {
compatible = "qcom,krait-pmu";
interrupts = <1 7 0xf04>;
@@ -150,6 +248,27 @@
reg = <0xf9011000 0x1000>;
};
 
+   qfprom: qfprom@fc4bc000 {
+   #address-cells = <1>;
+   #size-ce

[PATCH 2/5] arm: dts: apq8064: Add thermal zones, tsens and qfprom nodes

[Rajendra Nayak]

TSENS is part of GCC, hence add TSENS properties as part of GCC node.
Also add thermal zones and qfprom nodes.
Update GCC bindings doc to mention the possibility of optional TSENS
properties that can be part of GCC node.

Acked-by: Eduardo Valentin <edubez...@gmail.com>
Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 .../devicetree/bindings/clock/qcom,gcc.txt |  18 
 arch/arm/boot/dts/qcom-apq8064.dtsi| 119 +
 2 files changed, 137 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt 
b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 9a60fde..16e2f84 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -23,6 +23,13 @@ Required properties :
 Optional properties :
 - #power-domain-cells : shall contain 1
 
+Optional properties:
+- Qualcomm TSENS (thermal sensor device) on some devices can
+be part of GCC and hence the TSENS properties can also be
+part of the GCC/clock-controller node.
+For more details on the TSENS properties please refer
+Documentation/devicetree/bindings/thermal/qcom-tsens.txt
+
 Example:
clock-controller@90 {
compatible = "qcom,gcc-msm8960";
@@ -31,3 +38,14 @@ Example:
#reset-cells = <1>;
#power-domain-cells = <1>;
};
+
+Example of GCC with TSENS properties:
+   clock-controller@90 {
+   compatible = "qcom,gcc-apq8064";
+   reg = <0x0090 0x4000>;
+   nvmem-cells = <_calib>, <_backup>;
+   nvmem-cell-names = "calib", "calib_backup";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   #thermal-sensor-cells = <1>;
+   };
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi 
b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 906bb81..e54c215 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -86,6 +86,108 @@
};
};
 
+   thermal-zones {
+   cpu-thermal0 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 7>;
+   coefficients = <1199 0>;
+
+   trips {
+   cpu_alert0: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit0: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+
+   cpu-thermal1 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 8>;
+   coefficients = <1132 0>;
+
+   trips {
+   cpu_alert1: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit1: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+
+   cpu-thermal2 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 9>;
+   coefficients = <1199 0>;
+
+   trips {
+   cpu_alert2: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit2: trip@1 {
+ 

[PATCH 1/5] arm: dts: msm8974: Add thermal zones, tsens and qfprom nodes

[Rajendra Nayak]

Add thermal zones, tsens and qfprom nodes

Acked-by: Eduardo Valentin <edubez...@gmail.com>
Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-msm8974.dtsi | 119 
 1 file changed, 119 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi 
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 561d4d1..f9b0d90 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -131,6 +131,104 @@
};
};
 
+   thermal-zones {
+   cpu-thermal0 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 5>;
+
+   trips {
+   cpu_alert0: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit0: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+
+   cpu-thermal1 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 6>;
+
+   trips {
+   cpu_alert1: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit1: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+
+   cpu-thermal2 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 7>;
+
+   trips {
+   cpu_alert2: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit2: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+
+   cpu-thermal3 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 8>;
+
+   trips {
+   cpu_alert3: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit3: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+   };
+
cpu-pmu {
compatible = "qcom,krait-pmu";
interrupts = <1 7 0xf04>;
@@ -287,6 +385,27 @@
reg = <0xf9011000 0x1000>;
};
 
+   qfprom: qfprom@fc4bc000 {
+   #address-cells = <1>;
+   #size-ce

[PATCH 5/5] arm64: dts: msm8996: Add thermal zones and tsens node

[Rajendra Nayak]

Add thermal zones and tsens nodes

Acked-by: Eduardo Valentin <edubez...@gmail.com>
Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 108 ++
 1 file changed, 108 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 55ec3e8..6363891 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -97,6 +97,108 @@
};
};
 
+   thermal-zones {
+   cpu-thermal0 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 3>;
+
+   trips {
+   cpu_alert0: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   cpu_crit0: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+
+   cpu-thermal1 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 5>;
+
+   trips {
+   cpu_alert1: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   cpu_crit1: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+
+   cpu-thermal2 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 8>;
+
+   trips {
+   cpu_alert2: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   cpu_crit2: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+
+   cpu-thermal3 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 10>;
+
+   trips {
+   cpu_alert3: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   cpu_crit3: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+   };
+
timer {
compatible = "arm,armv8-timer";
interrupts = ,
@@ -181,6 +283,12 @@
status = "disabled";
};
 
+   tsens0: thermal-sensor@4a8000 {
+   compatible = "qcom,msm8996-tsens";
+

[PATCH 0/5] dts patches for qcom tsens support

[Rajendra Nayak]

Hi Andy,

Tsens driver is now pulled in and on its way to be merged in 4.8 [1]
These are the corresponding dts changes for the various platforms
supported by the driver.
None currently have support for cpufreq, so I have empty cooling-maps
added with a TODO to update once cpufreq support is available as
suggested by Eduardo.

regards,
Rajendra

[1] https://www.spinics.net/lists/arm-kernel/msg515721.html

Rajendra Nayak (5):
  arm: dts: msm8974: Add thermal zones, tsens and qfprom nodes
  arm: dts: apq8064: Add thermal zones, tsens and qfprom nodes
  arm: dts: apq8084: Add thermal zones, tsens and qfprom nodes
  arm64: dts: msm8916: Add thermal zones, tsens and qfprom nodes
  arm64: dts: msm8996: Add thermal zones and tsens node

 .../devicetree/bindings/clock/qcom,gcc.txt |  18 
 arch/arm/boot/dts/qcom-apq8064.dtsi| 119 +
 arch/arm/boot/dts/qcom-apq8084.dtsi| 119 +
 arch/arm/boot/dts/qcom-msm8974.dtsi| 119 +
 arch/arm64/boot/dts/qcom/msm8916.dtsi  |  72 +
 arch/arm64/boot/dts/qcom/msm8996.dtsi  | 108 +++
 6 files changed, 555 insertions(+)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 4/5] arm64: dts: msm8916: Add thermal zones, tsens and qfprom nodes

[Rajendra Nayak]

Add thermal zones, tsens and qfprom nodes

Acked-by: Eduardo Valentin <edubez...@gmail.com>
Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 72 +++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 11bdc24..0f850a1 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -155,6 +155,57 @@
interrupts = ;
};
 
+   thermal-zones {
+   cpu-thermal0 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 4>;
+
+   trips {
+   cpu_alert0: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit0: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+
+   cpu-thermal1 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 3>;
+
+   trips {
+   cpu_alert1: trip@0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit1: trip@1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   /* TODO: Add when cpufreq support is available 
*/
+   };
+   };
+
+   };
+
timer {
compatible = "arm,armv8-timer";
interrupts = ,
@@ -609,6 +660,27 @@
clocks = < GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
+
+   qfprom: qfprom@5c000 {
+   compatible = "qcom,qfprom";
+   reg = <0x5c000 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   tsens_caldata: caldata@d0 {
+   reg = <0xd0 0x8>;
+   };
+   tsens_calsel: calsel@ec {
+   reg = <0xec 0x4>;
+   };
+   };
+
+   tsens: thermal-sensor@4a8000 {
+   compatible = "qcom,msm8916-tsens";
+   reg = <0x4a8000 0x2000>;
+   nvmem-cells = <_caldata>, <_calsel>;
+   nvmem-cell-names = "calib", "calib_sel";
+   #thermal-sensor-cells = <1>;
+   };
};
 
smd {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 0/5] dts patches for qcom tsens support

[Rajendra Nayak]

Hey Andy,

Tsens driver patches are pulled in by Eduardo [1]
but looks like they missed the 4.8 merge window.
Nevertheless, these are dts changes for the various platforms
supported by the driver, which are acked by Eduardo.
Can you please pull these in for 4.9? (I am hoping the driver
would be merged in in 4.9 as well)

Changes from v1:
- Fixed the warings seen when compiled with W=1 as suggested by Rob

[1] https://www.spinics.net/lists/arm-kernel/msg515721.html

Rajendra Nayak (5):
  arm: dts: msm8974: Add thermal zones, tsens and qfprom nodes
  arm: dts: apq8064: Add thermal zones, tsens and qfprom nodes
  arm: dts: apq8084: Add thermal zones, tsens and qfprom nodes
  arm64: dts: msm8916: Add thermal zones, tsens and qfprom nodes
  arm64: dts: msm8996: Add thermal zones, tsens and qfprom nodes

 .../devicetree/bindings/clock/qcom,gcc.txt |  18 
 arch/arm/boot/dts/qcom-apq8064.dtsi| 103 +
 arch/arm/boot/dts/qcom-apq8084.dtsi| 103 +
 arch/arm/boot/dts/qcom-msm8974.dtsi| 103 +
 arch/arm64/boot/dts/qcom/msm8916.dtsi  |  64 +
 arch/arm64/boot/dts/qcom/msm8996.dtsi  |  92 ++
 6 files changed, 483 insertions(+)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 4/5] arm64: dts: msm8916: Add thermal zones, tsens and qfprom nodes

[Rajendra Nayak]

Add thermal zones, tsens and qfprom nodes

Acked-by: Eduardo Valentin <edubez...@gmail.com>
Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 64 +++
 1 file changed, 64 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 11bdc24..4bc047b 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -155,6 +155,49 @@
interrupts = ;
};
 
+   thermal-zones {
+   cpu-thermal0 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 4>;
+
+   trips {
+   cpu_alert0: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit0: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   cpu-thermal1 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 3>;
+
+   trips {
+   cpu_alert1: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit1: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   };
+
timer {
compatible = "arm,armv8-timer";
interrupts = ,
@@ -609,6 +652,27 @@
clocks = < GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
+
+   qfprom: qfprom@5c000 {
+   compatible = "qcom,qfprom";
+   reg = <0x5c000 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   tsens_caldata: caldata@d0 {
+   reg = <0xd0 0x8>;
+   };
+   tsens_calsel: calsel@ec {
+   reg = <0xec 0x4>;
+   };
+   };
+
+   tsens: thermal-sensor@4a8000 {
+   compatible = "qcom,msm8916-tsens";
+   reg = <0x4a8000 0x2000>;
+   nvmem-cells = <_caldata>, <_calsel>;
+   nvmem-cell-names = "calib", "calib_sel";
+   #thermal-sensor-cells = <1>;
+   };
};
 
smd {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 2/5] arm: dts: apq8064: Add thermal zones, tsens and qfprom nodes

[Rajendra Nayak]

TSENS is part of GCC, hence add TSENS properties as part of GCC node.
Also add thermal zones and qfprom nodes.
Update GCC bindings doc to mention the possibility of optional TSENS
properties that can be part of GCC node.

Acked-by: Eduardo Valentin <edubez...@gmail.com>
Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 .../devicetree/bindings/clock/qcom,gcc.txt |  18 
 arch/arm/boot/dts/qcom-apq8064.dtsi| 103 +
 2 files changed, 121 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt 
b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 9a60fde..16e2f84 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -23,6 +23,13 @@ Required properties :
 Optional properties :
 - #power-domain-cells : shall contain 1
 
+Optional properties:
+- Qualcomm TSENS (thermal sensor device) on some devices can
+be part of GCC and hence the TSENS properties can also be
+part of the GCC/clock-controller node.
+For more details on the TSENS properties please refer
+Documentation/devicetree/bindings/thermal/qcom-tsens.txt
+
 Example:
clock-controller@90 {
compatible = "qcom,gcc-msm8960";
@@ -31,3 +38,14 @@ Example:
#reset-cells = <1>;
#power-domain-cells = <1>;
};
+
+Example of GCC with TSENS properties:
+   clock-controller@90 {
+   compatible = "qcom,gcc-apq8064";
+   reg = <0x0090 0x4000>;
+   nvmem-cells = <_calib>, <_backup>;
+   nvmem-cell-names = "calib", "calib_backup";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   #thermal-sensor-cells = <1>;
+   };
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi 
b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 74a9b6c..9cd13ab 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -86,6 +86,92 @@
};
};
 
+   thermal-zones {
+   cpu-thermal0 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 7>;
+   coefficients = <1199 0>;
+
+   trips {
+   cpu_alert0: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit0: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   cpu-thermal1 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 8>;
+   coefficients = <1132 0>;
+
+   trips {
+   cpu_alert1: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit1: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   cpu-thermal2 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 9>;
+   coefficients = <1199 0>;
+
+   trips {
+   cpu_alert2: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit2: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+

[PATCH v2 5/5] arm64: dts: msm8996: Add thermal zones, tsens and qfprom nodes

[Rajendra Nayak]

Add thermal zones, tsens and qfprom nodes

Acked-by: Eduardo Valentin <edubez...@gmail.com>
Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 92 +++
 1 file changed, 92 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 55ec3e8..f52cba3 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -97,6 +97,92 @@
};
};
 
+   thermal-zones {
+   cpu-thermal0 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 3>;
+
+   trips {
+   cpu_alert0: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   cpu_crit0: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   cpu-thermal1 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 5>;
+
+   trips {
+   cpu_alert1: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   cpu_crit1: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   cpu-thermal2 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 8>;
+
+   trips {
+   cpu_alert2: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   cpu_crit2: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   cpu-thermal3 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 10>;
+
+   trips {
+   cpu_alert3: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   cpu_crit3: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+   };
+
timer {
compatible = "arm,armv8-timer";
interrupts = ,
@@ -181,6 +267,12 @@
status = "disabled";
};
 
+   tsens0: thermal-sensor@4a8000 {
+   compatible = "qcom,msm8996-tsens";
+   reg = <0x4a8000 0x2000>;
+   #thermal-sensor-cells = <1>;
+   };
+
blsp2_uart1: serial@75b {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b 0x1000>;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 3/5] arm: dts: apq8084: Add thermal zones, tsens and qfprom nodes

[Rajendra Nayak]

Add thermal zones, tsens and qfprom nodes

Acked-by: Eduardo Valentin <edubez...@gmail.com>
Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-apq8084.dtsi | 103 
 1 file changed, 103 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi 
b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 7c2df06..39eb7a4 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -94,6 +94,88 @@
};
};
 
+   thermal-zones {
+   cpu-thermal0 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 5>;
+
+   trips {
+   cpu_alert0: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit0: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   cpu-thermal1 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 6>;
+
+   trips {
+   cpu_alert1: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit1: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   cpu-thermal2 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 7>;
+
+   trips {
+   cpu_alert2: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit2: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   cpu-thermal3 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 8>;
+
+   trips {
+   cpu_alert3: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit3: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+   };
+
cpu-pmu {
compatible = "qcom,krait-pmu";
interrupts = <1 7 0xf04>;
@@ -150,6 +232,27 @@
reg = <0xf9011000 0x1000>;
};
 
+   qfprom: qfprom@fc4bc000 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "qcom,qfprom";
+   reg = <0xfc4bc000 0x1000>;
+   tsens_calib: calib@d0 {
+   reg = <0xd0 0x18>;
+   };
+   tsens_backup: backup@440 {
+   reg = <0x440 0x10>;
+   };
+   };
+
+   tsens: thermal-sensor@fc4a8000 {
+   compatible = "qcom,msm8974-tsens";
+   reg = <0xfc4a8000 0x2000>;
+ 

[PATCH v2 1/5] arm: dts: msm8974: Add thermal zones, tsens and qfprom nodes

[Rajendra Nayak]

Add thermal zones, tsens and qfprom nodes

Acked-by: Eduardo Valentin <edubez...@gmail.com>
Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-msm8974.dtsi | 103 
 1 file changed, 103 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi 
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 561d4d1..255c61a 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -131,6 +131,88 @@
};
};
 
+   thermal-zones {
+   cpu-thermal0 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 5>;
+
+   trips {
+   cpu_alert0: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit0: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   cpu-thermal1 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 6>;
+
+   trips {
+   cpu_alert1: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit1: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   cpu-thermal2 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 7>;
+
+   trips {
+   cpu_alert2: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit2: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   cpu-thermal3 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+
+   thermal-sensors = < 8>;
+
+   trips {
+   cpu_alert3: trip0 {
+   temperature = <75000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_crit3: trip1 {
+   temperature = <11>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+   };
+
cpu-pmu {
compatible = "qcom,krait-pmu";
interrupts = <1 7 0xf04>;
@@ -287,6 +369,27 @@
reg = <0xf9011000 0x1000>;
};
 
+   qfprom: qfprom@fc4bc000 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "qcom,qfprom";
+   reg = <0xfc4bc000 0x1000>;
+   tsens_calib: calib@d0 {
+   reg = <0xd0 0x18>;
+   };
+   tsens_backup: backup@440 {
+   reg = <0x440 0x10>;
+   };
+   };
+
+   tsens: thermal-sensor@fc4a8000 {
+   compatible = "qcom,msm8974-tsens";
+   reg = <0xfc4a8000 0x2000>;
+ 

[PATCH v2 01/10] clk: Fix inconsistencies in usage of data types

[Rajendra Nayak]

index is of type u8 in all places except in clk_hw_get_parent_by_index()
and return value of all round_rate functions is long except for
clk_hw_round_rate(). Make them consistent with the rest of the places

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/clk.c| 4 ++--
 include/linux/clk-provider.h | 5 ++---
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 820a939..e768071 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -261,7 +261,7 @@ static struct clk_core *clk_core_get_parent_by_index(struct 
clk_core *core,
 }
 
 struct clk_hw *
-clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index)
+clk_hw_get_parent_by_index(const struct clk_hw *hw, u8 index)
 {
struct clk_core *parent;
 
@@ -889,7 +889,7 @@ int __clk_determine_rate(struct clk_hw *hw, struct 
clk_rate_request *req)
 }
 EXPORT_SYMBOL_GPL(__clk_determine_rate);
 
-unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate)
+long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate)
 {
int ret;
struct clk_rate_request req;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index a39c0c5..230a249 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -732,8 +732,7 @@ const char *clk_hw_get_name(const struct clk_hw *hw);
 struct clk_hw *__clk_get_hw(struct clk *clk);
 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
-struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
- unsigned int index);
+struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, u8 index);
 unsigned int __clk_get_enable_count(struct clk *clk);
 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
 unsigned long __clk_get_flags(struct clk *clk);
@@ -760,7 +759,7 @@ static inline void __clk_hw_set_clk(struct clk_hw *dst, 
struct clk_hw *src)
 /*
  * FIXME clock api without lock protection
  */
-unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
+long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
 
 struct of_device_id;
 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 00/10] clk: qcom: PLL updates

[Rajendra Nayak]

Hi,

This series adds some additional support to the clk-alpha-pll and the
clk-pll drivers in preperation to add the CPU clock driver support
on msm8996

Changes in v2:
* Patch 1 to 6 are same as v1 post, added patches 7 to 10

Rajendra Nayak (8):
  clk: Fix inconsistencies in usage of data types
  clk: qcom: Add support for alpha pll hwfsm ops
  clk: qcom: Add support to initialize alpha plls
  clk: qcom: Add support for PLLs with alpha mode
  clk: qcom: Add support for PLLs with early output
  clk: qcom: Add support for PLLs supporting dynamic reprogramming
  clk: qcom: Add support to enable FSM mode for votable alpha PLLs
  clk: qcom: Add .is_enabled ops for clk-alpha-pll

Taniya Das (2):
  clk: qcom: Cleanup some macro defs
  clk: qcom: Fix .set_rate to handle alpha PLLs w/wo dynamic update

 drivers/clk/clk.c|   4 +-
 drivers/clk/qcom/clk-alpha-pll.c | 235 ++-
 drivers/clk/qcom/clk-alpha-pll.h |  17 +++
 drivers/clk/qcom/clk-pll.c   | 123 +---
 drivers/clk/qcom/clk-pll.h   |  12 +-
 drivers/clk/qcom/common.c|  29 +
 drivers/clk/qcom/common.h|   2 +
 include/linux/clk-provider.h |   5 +-
 8 files changed, 378 insertions(+), 49 deletions(-)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 08/10] clk: qcom: Cleanup some macro defs

[Rajendra Nayak]

From: Taniya Das <t...@codeaurora.org>

Move all
'# define XYZ'
to
'#define XYZ'

Signed-off-by: Taniya Das <t...@codeaurora.org>
Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index e8f3505..854487e 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -21,28 +21,28 @@
 #include "common.h"
 
 #define PLL_MODE   0x00
-# define PLL_OUTCTRL   BIT(0)
-# define PLL_BYPASSNL  BIT(1)
-# define PLL_RESET_N   BIT(2)
-# define PLL_LOCK_COUNT_SHIFT  8
-# define PLL_LOCK_COUNT_MASK   0x3f
-# define PLL_BIAS_COUNT_SHIFT  14
-# define PLL_BIAS_COUNT_MASK   0x3f
-# define PLL_VOTE_FSM_ENA  BIT(20)
-# define PLL_VOTE_FSM_RESETBIT(21)
-# define PLL_ACTIVE_FLAG   BIT(30)
-# define PLL_LOCK_DET  BIT(31)
+#define PLL_OUTCTRLBIT(0)
+#define PLL_BYPASSNL   BIT(1)
+#define PLL_RESET_NBIT(2)
+#define PLL_LOCK_COUNT_SHIFT   8
+#define PLL_LOCK_COUNT_MASK0x3f
+#define PLL_BIAS_COUNT_SHIFT   14
+#define PLL_BIAS_COUNT_MASK0x3f
+#define PLL_VOTE_FSM_ENA   BIT(20)
+#define PLL_VOTE_FSM_RESET BIT(21)
+#define PLL_ACTIVE_FLAGBIT(30)
+#define PLL_LOCK_DET   BIT(31)
 
 #define PLL_L_VAL  0x04
 #define PLL_ALPHA_VAL  0x08
 #define PLL_ALPHA_VAL_U0x0c
 
 #define PLL_USER_CTL   0x10
-# define PLL_POST_DIV_SHIFT8
-# define PLL_POST_DIV_MASK 0xf
-# define PLL_ALPHA_EN  BIT(24)
-# define PLL_VCO_SHIFT 20
-# define PLL_VCO_MASK  0x3
+#define PLL_POST_DIV_SHIFT 8
+#define PLL_POST_DIV_MASK  0xf
+#define PLL_ALPHA_EN   BIT(24)
+#define PLL_VCO_SHIFT  20
+#define PLL_VCO_MASK   0x3
 
 #define PLL_USER_CTL_U 0x14
 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 10/10] clk: qcom: Fix .set_rate to handle alpha PLLs w/wo dynamic update

[Rajendra Nayak]

From: Taniya Das <t...@codeaurora.org>

Alpha PLLs which do not support dynamic update feature
need to be explicitly disabled before a rate change. The ones which do
support dynamic update don't have to be disabled but need to follow a update
sequence (as implemented by clk_alpha_pll_dynamic_update() in the patch).
They also need the PLL_HW_LOGIC_BYPASS bit set at init.

Signed-off-by: Taniya Das <t...@codeaurora.org>
Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 48 
 drivers/clk/qcom/clk-alpha-pll.h |  1 +
 2 files changed, 49 insertions(+)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 2184dc1..68c90f3 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -113,6 +113,11 @@ static int wait_for_pll_offline(struct clk_alpha_pll *pll, 
u32 mask)
 #define PLL_OFFLINE_ACKBIT(28)
 #define PLL_ACTIVE_FLAGBIT(30)
 
+/* alpha pll with dynamic update support */
+#define PLL_UPDATE BIT(22)
+#define PLL_HW_LOGIC_BYPASSBIT(23)
+#define PLL_ACK_LATCH  BIT(29)
+
 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 const struct alpha_pll_config *config)
 {
@@ -138,6 +143,37 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, 
struct regmap *regmap,
if (pll->flags & SUPPORTS_VOTE_FSM)
qcom_pll_set_fsm_mode(regmap, pll->offset + PLL_MODE, 6, 0);
 
+   if (pll->flags & SUPPORTS_DYNAMIC_UPDATE)
+   regmap_update_bits(regmap, pll->offset + PLL_MODE,
+  PLL_HW_LOGIC_BYPASS,
+  PLL_HW_LOGIC_BYPASS);
+}
+
+static int clk_alpha_pll_dynamic_update(struct clk_alpha_pll *pll)
+{
+   u32 val;
+
+   /* Latch the input to the PLL */
+   regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_MODE,
+  PLL_UPDATE, PLL_UPDATE);
+
+   /* Wait for 2 reference cycle before checking ACK bit */
+   udelay(1);
+
+   regmap_read(pll->clkr.regmap, pll->offset + PLL_MODE, );
+   if (!(val & PLL_ACK_LATCH)) {
+   WARN(1, "PLL latch failed. Output may be unstable!\n");
+   return -EINVAL;
+   }
+
+   /* Return latch input to 0 */
+   regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_MODE,
+  PLL_UPDATE, 0);
+
+   /* Wait for PLL output to stabilize */
+   udelay(100);
+
+   return 0;
 }
 
 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
@@ -366,6 +402,7 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long 
parent_rate)
 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  unsigned long prate)
 {
+   int enabled;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
const struct pll_vco *vco;
u32 l, off = pll->offset;
@@ -378,6 +415,11 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, 
unsigned long rate,
return -EINVAL;
}
 
+   enabled = hw->init->ops->is_enabled(hw);
+
+   if (!(pll->flags & SUPPORTS_DYNAMIC_UPDATE) && enabled)
+   hw->init->ops->disable(hw);
+
a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
 
regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l);
@@ -391,6 +433,12 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, 
unsigned long rate,
regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, PLL_ALPHA_EN,
   PLL_ALPHA_EN);
 
+   if (!(pll->flags & SUPPORTS_DYNAMIC_UPDATE) && enabled)
+   hw->init->ops->enable(hw);
+
+   if (pll->flags & SUPPORTS_DYNAMIC_UPDATE)
+   clk_alpha_pll_dynamic_update(pll);
+
return 0;
 }
 
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 4bd42fd..23e32db 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -36,6 +36,7 @@ struct clk_alpha_pll {
size_t num_vco;
 
 #define SUPPORTS_VOTE_FSM  BIT(0)
+#define SUPPORTS_DYNAMIC_UPDATEBIT(1)
u8 flags;
struct clk_regmap clkr;
 };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 07/10] clk: qcom: Add support to enable FSM mode for votable alpha PLLs

[Rajendra Nayak]

The votable alpha PLLs need to have the fsm mode enabled as part
of the initialization. The sequence seems to be the same as used
by clk-pll, so move the function which does this into a common
place and reuse it for the clk-alpha-pll

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
 drivers/clk/qcom/clk-alpha-pll.c |  5 +
 drivers/clk/qcom/clk-alpha-pll.h |  2 ++
 drivers/clk/qcom/clk-pll.c   | 25 +++--
 drivers/clk/qcom/common.c| 29 +
 drivers/clk/qcom/common.h|  2 ++
 5 files changed, 41 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 8b8710f..e8f3505 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -18,6 +18,7 @@
 #include 
 
 #include "clk-alpha-pll.h"
+#include "common.h"
 
 #define PLL_MODE   0x00
 # define PLL_OUTCTRL   BIT(0)
@@ -133,6 +134,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, 
struct regmap *regmap,
mask |= config->post_div_mask;
 
regmap_update_bits(regmap, pll->offset + PLL_USER_CTL, mask, val);
+
+   if (pll->flags & SUPPORTS_VOTE_FSM)
+   qcom_pll_set_fsm_mode(regmap, pll->offset + PLL_MODE, 6, 0);
+
 }
 
 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 12a349e..4bd42fd 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -35,6 +35,8 @@ struct clk_alpha_pll {
const struct pll_vco *vco_table;
size_t num_vco;
 
+#define SUPPORTS_VOTE_FSM  BIT(0)
+   u8 flags;
struct clk_regmap clkr;
 };
 
diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
index 13d3f64..776278b 100644
--- a/drivers/clk/qcom/clk-pll.c
+++ b/drivers/clk/qcom/clk-pll.c
@@ -23,6 +23,7 @@
 #include 
 
 #include "clk-pll.h"
+#include "common.h"
 
 #define PLL_OUTCTRLBIT(0)
 #define PLL_BYPASSNL   BIT(1)
@@ -230,26 +231,6 @@ const struct clk_ops clk_pll_vote_ops = {
 EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
 
 static void
-clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap, u8 lock_count)
-{
-   u32 val;
-   u32 mask;
-
-   /* De-assert reset to FSM */
-   regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0);
-
-   /* Program bias count and lock count */
-   val = 1 << PLL_BIAS_COUNT_SHIFT | lock_count << PLL_LOCK_COUNT_SHIFT;
-   mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
-   mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
-   regmap_update_bits(regmap, pll->mode_reg, mask, val);
-
-   /* Enable PLL FSM voting */
-   regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_ENA,
-   PLL_VOTE_FSM_ENA);
-}
-
-static void
 clk_pll_set_dynamic_fsm_mode(struct clk_pll *pll, struct regmap *regmap)
 {
u32 val;
@@ -300,7 +281,7 @@ void clk_pll_configure_sr(struct clk_pll *pll, struct 
regmap *regmap,
 {
clk_pll_configure(pll, regmap, config);
if (fsm_mode)
-   clk_pll_set_fsm_mode(pll, regmap, 8);
+   qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8);
 }
 EXPORT_SYMBOL_GPL(clk_pll_configure_sr);
 
@@ -309,7 +290,7 @@ void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, 
struct regmap *regmap,
 {
clk_pll_configure(pll, regmap, config);
if (fsm_mode)
-   clk_pll_set_fsm_mode(pll, regmap, 0);
+   qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0);
 }
 EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
 
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index f7c226a..6bf5abd 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -25,6 +25,14 @@
 #include "reset.h"
 #include "gdsc.h"
 
+#define PLL_LOCK_COUNT_SHIFT   8
+#define PLL_LOCK_COUNT_MASK0x3f
+#define PLL_BIAS_COUNT_SHIFT   14
+#define PLL_BIAS_COUNT_MASK0x3f
+#define PLL_VOTE_FSM_ENA   BIT(20)
+#define PLL_DYN_FSM_ENABIT(20)
+#define PLL_VOTE_FSM_RESET BIT(21)
+
 struct qcom_cc {
struct qcom_reset_controller reset;
struct clk_onecell_data data;
@@ -74,6 +82,27 @@ qcom_cc_map(struct platform_device *pdev, const struct 
qcom_cc_desc *desc)
 }
 EXPORT_SYMBOL_GPL(qcom_cc_map);
 
+void
+qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 
lock_count)
+{
+   u32 val;
+   u32 mask;
+
+   /* De-assert reset to FSM */
+   regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);
+
+   /* Program bias count and lock count */
+   val = bias_count << PLL_BIAS_COUNT_SHIFT |
+   lock_count << PLL_LOCK_COUNT_SHIFT;
+   mask = PLL_BIAS_COUN

[PATCH v2 06/10] clk: qcom: Add support for PLLs supporting dynamic reprogramming

[Rajendra Nayak]

Some PLLs can support dynamic reprogramming, which means just a L value
change is whats needed to change the PLL frequency without having to
explicitly enable/disable or bypass/re-lock the PLL.
Add support for such PLLs' initial configuration and the ops needed to
support the dynamic reprogramming thereafter.

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/clk-pll.c | 106 +
 drivers/clk/qcom/clk-pll.h |   9 +++-
 2 files changed, 114 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
index b463432..13d3f64 100644
--- a/drivers/clk/qcom/clk-pll.c
+++ b/drivers/clk/qcom/clk-pll.c
@@ -32,6 +32,7 @@
 #define PLL_BIAS_COUNT_SHIFT   14
 #define PLL_BIAS_COUNT_MASK0x3f
 #define PLL_VOTE_FSM_ENA   BIT(20)
+#define PLL_DYN_FSM_ENABIT(20)
 #define PLL_VOTE_FSM_RESET BIT(21)
 
 static int clk_pll_enable(struct clk_hw *hw)
@@ -248,6 +249,19 @@ clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap 
*regmap, u8 lock_count)
PLL_VOTE_FSM_ENA);
 }
 
+static void
+clk_pll_set_dynamic_fsm_mode(struct clk_pll *pll, struct regmap *regmap)
+{
+   u32 val;
+   u32 mask;
+
+   mask = PLL_BIAS_COUNT_MASK | PLL_DYN_FSM_ENA;
+   val = 6 << PLL_BIAS_COUNT_SHIFT;
+   val |= PLL_DYN_FSM_ENA;
+
+   regmap_update_bits(regmap, pll->mode_reg, mask, val);
+}
+
 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
const struct pll_config *config)
 {
@@ -299,6 +313,21 @@ void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, 
struct regmap *regmap,
 }
 EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
 
+void clk_pll_configure_dynamic(struct clk_pll *pll, struct regmap *regmap,
+  const struct pll_config *config)
+{
+   u32 config_ctl_reg = pll->config_ctl_reg;
+   u32 config_ctl_hi_reg = pll->config_ctl_reg + 4;
+
+   clk_pll_configure(pll, regmap, config);
+
+   regmap_write(regmap, config_ctl_reg, config->config_ctl_val);
+   regmap_write(regmap, config_ctl_hi_reg, config->config_ctl_hi_val);
+
+   clk_pll_set_dynamic_fsm_mode(pll, regmap);
+}
+EXPORT_SYMBOL_GPL(clk_pll_configure_dynamic);
+
 static int clk_pll_sr2_enable(struct clk_hw *hw)
 {
struct clk_pll *pll = to_clk_pll(hw);
@@ -373,3 +402,80 @@ const struct clk_ops clk_pll_sr2_ops = {
.determine_rate = clk_pll_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_pll_sr2_ops);
+
+static int clk_pll_dynamic_enable(struct clk_hw *hw)
+{
+   struct clk_pll *pll = to_clk_pll(hw);
+
+   /* Wait for 50us explicitly to avoid transient locks */
+   udelay(50);
+
+   return wait_for_pll(pll);
+};
+
+static void clk_pll_dynamic_disable(struct clk_hw *hw)
+{
+   /* 8 reference clock cycle delay mandated by the HPG */
+   udelay(1);
+};
+
+static unsigned long
+clk_pll_dynamic_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+   u32 l_val;
+   int ret;
+
+   struct clk_pll *pll = to_clk_pll(hw);
+
+   ret = regmap_read(pll->clkr.regmap, pll->l_reg, _val);
+   if (ret)
+   return ret;
+
+   return l_val * parent_rate;
+};
+
+static int
+clk_pll_dynamic_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
+{
+   struct clk_pll *pll = to_clk_pll(hw);
+   const struct pll_freq_tbl *f;
+
+   f = find_freq(pll->freq_tbl, req->rate);
+   if (!f)
+   req->rate = DIV_ROUND_UP(req->rate, req->best_parent_rate)
+   * req->best_parent_rate;
+   else
+   req->rate = f->freq;
+
+   if (req->rate < pll->min_rate)
+   req->rate = pll->min_rate;
+   else if (req->rate > pll->max_rate)
+   req->rate = pll->max_rate;
+
+   return 0;
+}
+
+static int
+clk_pll_dynamic_set_rate(struct clk_hw *hw, unsigned long rate,
+unsigned long prate)
+{
+   u32 l_val;
+   struct clk_pll *pll = to_clk_pll(hw);
+
+   if ((rate < pll->min_rate) || (rate > pll->max_rate) || !prate)
+   return -EINVAL;
+
+   l_val = rate / prate;
+   regmap_write(pll->clkr.regmap, pll->l_reg, l_val);
+
+   return 0;
+}
+
+const struct clk_ops clk_pll_dynamic_ops = {
+   .enable = clk_pll_dynamic_enable,
+   .disable = clk_pll_dynamic_disable,
+   .set_rate = clk_pll_dynamic_set_rate,
+   .recalc_rate = clk_pll_dynamic_recalc_rate,
+   .determine_rate = clk_pll_dynamic_determine_rate,
+};
+EXPORT_SYMBOL_GPL(clk_pll_dynamic_ops);
diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h
index dbe22a9..627588f 100644
--- a/drivers/clk/qcom/clk-pll.h
+++ b/drivers/clk/qcom/clk-pll.h
@@ -52,9 +52,12 @@ struct clk_pll {
u32 config_reg;
u32 mode_reg;
u32 status_re

[PATCH v2 05/10] clk: qcom: Add support for PLLs with early output

[Rajendra Nayak]

Some PLLs can have an additional early output (apart from
the main and aux outputs). Add support for the PLL driver
so it can be used to initialize/configure the early output

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/clk-pll.c | 2 ++
 drivers/clk/qcom/clk-pll.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
index 08d2fa2..b463432 100644
--- a/drivers/clk/qcom/clk-pll.c
+++ b/drivers/clk/qcom/clk-pll.c
@@ -268,6 +268,7 @@ static void clk_pll_configure(struct clk_pll *pll, struct 
regmap *regmap,
val |= config->mn_ena_mask;
val |= config->main_output_mask;
val |= config->aux_output_mask;
+   val |= config->early_output_mask;
 
mask = config->vco_mask;
mask |= config->pre_div_mask;
@@ -275,6 +276,7 @@ static void clk_pll_configure(struct clk_pll *pll, struct 
regmap *regmap,
mask |= config->mn_ena_mask;
mask |= config->main_output_mask;
mask |= config->aux_output_mask;
+   mask |= config->early_output_mask;
 
regmap_update_bits(regmap, pll->config_reg, mask, val);
 }
diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h
index 083727e..dbe22a9 100644
--- a/drivers/clk/qcom/clk-pll.h
+++ b/drivers/clk/qcom/clk-pll.h
@@ -81,6 +81,7 @@ struct pll_config {
u32 mn_ena_mask;
u32 main_output_mask;
u32 aux_output_mask;
+   u32 early_output_mask;
 };
 
 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 09/10] clk: qcom: Add .is_enabled ops for clk-alpha-pll

[Rajendra Nayak]

This would be useful in subsequent patches when the .set_rate operation
would need to identify if the PLL is actually enabled

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 854487e..2184dc1 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -198,6 +198,23 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
wait_for_pll_disable(pll, PLL_ACTIVE_FLAG);
 }
 
+static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
+{
+   int ret;
+   u32 val, off;
+   struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+
+   off = pll->offset;
+   ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, );
+   if (ret)
+   return ret;
+
+   if (val & PLL_LOCK_DET)
+   return 1;
+   else
+   return 0;
+}
+
 static int clk_alpha_pll_enable(struct clk_hw *hw)
 {
int ret;
@@ -398,6 +415,7 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, 
unsigned long rate,
 const struct clk_ops clk_alpha_pll_ops = {
.enable = clk_alpha_pll_enable,
.disable = clk_alpha_pll_disable,
+   .is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = clk_alpha_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = clk_alpha_pll_set_rate,
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 03/10] clk: qcom: Add support to initialize alpha plls

[Rajendra Nayak]

Add a function to do initial configuration of the alpha plls

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 23 +++
 drivers/clk/qcom/clk-alpha-pll.h | 13 +
 2 files changed, 36 insertions(+)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index bae31f9..8b8710f 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -112,6 +112,29 @@ static int wait_for_pll_offline(struct clk_alpha_pll *pll, 
u32 mask)
 #define PLL_OFFLINE_ACKBIT(28)
 #define PLL_ACTIVE_FLAGBIT(30)
 
+void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+const struct alpha_pll_config *config)
+{
+   u32 val, mask;
+
+   regmap_write(regmap, pll->offset + PLL_CONFIG_CTL,
+config->config_ctl_val);
+
+   val = config->main_output_mask;
+   val |= config->aux_output_mask;
+   val |= config->aux2_output_mask;
+   val |= config->early_output_mask;
+   val |= config->post_div_val;
+
+   mask = config->main_output_mask;
+   mask |= config->aux_output_mask;
+   mask |= config->aux2_output_mask;
+   mask |= config->early_output_mask;
+   mask |= config->post_div_mask;
+
+   regmap_update_bits(regmap, pll->offset + PLL_USER_CTL, mask, val);
+}
+
 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
 {
int ret;
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index f78bf4c..12a349e 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -51,8 +51,21 @@ struct clk_alpha_pll_postdiv {
struct clk_regmap clkr;
 };
 
+struct alpha_pll_config {
+   u32 config_ctl_val;
+   u32 main_output_mask;
+   u32 aux_output_mask;
+   u32 aux2_output_mask;
+   u32 early_output_mask;
+   u32 post_div_val;
+   u32 post_div_mask;
+};
+
 extern const struct clk_ops clk_alpha_pll_ops;
 extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
 extern const struct clk_ops clk_alpha_pll_postdiv_ops;
 
+void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+const struct alpha_pll_config *config);
+
 #endif
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 04/10] clk: qcom: Add support for PLLs with alpha mode

[Rajendra Nayak]

Some PLLs can support an alpha mode, and a single alpha
register (instead of registers to program the M/N values),
the contents of which depend on the alpha mode selected.
(They are either treated as two's complement or M/N value)
Add support for this in the clk PLL driver.

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/clk-pll.c | 8 ++--
 drivers/clk/qcom/clk-pll.h | 2 ++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
index 5b940d6..08d2fa2 100644
--- a/drivers/clk/qcom/clk-pll.c
+++ b/drivers/clk/qcom/clk-pll.c
@@ -255,8 +255,12 @@ static void clk_pll_configure(struct clk_pll *pll, struct 
regmap *regmap,
u32 mask;
 
regmap_write(regmap, pll->l_reg, config->l);
-   regmap_write(regmap, pll->m_reg, config->m);
-   regmap_write(regmap, pll->n_reg, config->n);
+   if (pll->alpha_reg) {
+   regmap_write(regmap, pll->alpha_reg, config->alpha);
+   } else {
+   regmap_write(regmap, pll->m_reg, config->m);
+   regmap_write(regmap, pll->n_reg, config->n);
+   }
 
val = config->vco_val;
val |= config->pre_div_val;
diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h
index ffd0c63..083727e 100644
--- a/drivers/clk/qcom/clk-pll.h
+++ b/drivers/clk/qcom/clk-pll.h
@@ -48,6 +48,7 @@ struct clk_pll {
u32 l_reg;
u32 m_reg;
u32 n_reg;
+   u32 alpha_reg;
u32 config_reg;
u32 mode_reg;
u32 status_reg;
@@ -70,6 +71,7 @@ struct pll_config {
u16 l;
u32 m;
u32 n;
+   u32 alpha;
u32 vco_val;
u32 vco_mask;
u32 pre_div_val;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 02/10] clk: qcom: Add support for alpha pll hwfsm ops

[Rajendra Nayak]

Add support to enable/disable the alpha pll using hwfsm

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 109 ++-
 drivers/clk/qcom/clk-alpha-pll.h |   1 +
 2 files changed, 98 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index e6a03ea..bae31f9 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -62,9 +62,10 @@
 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
   struct clk_alpha_pll_postdiv, clkr)
 
-static int wait_for_pll(struct clk_alpha_pll *pll)
+static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
+   const char *action)
 {
-   u32 val, mask, off;
+   u32 val, off;
int count;
int ret;
const char *name = clk_hw_get_name(>clkr.hw);
@@ -74,26 +75,101 @@ static int wait_for_pll(struct clk_alpha_pll *pll)
if (ret)
return ret;
 
-   if (val & PLL_VOTE_FSM_ENA)
-   mask = PLL_ACTIVE_FLAG;
-   else
-   mask = PLL_LOCK_DET;
-
-   /* Wait for pll to enable. */
for (count = 100; count > 0; count--) {
ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, );
if (ret)
return ret;
-   if ((val & mask) == mask)
+   if (inverse && (val & mask))
+   return 0;
+   else if ((val & mask) == mask)
return 0;
 
udelay(1);
}
 
-   WARN(1, "%s didn't enable after voting for it!\n", name);
+   WARN(1, "%s failed to %s!\n", name, action);
return -ETIMEDOUT;
 }
 
+static int wait_for_pll_enable(struct clk_alpha_pll *pll, u32 mask)
+{
+   return wait_for_pll(pll, mask, 0, "enable");
+}
+
+static int wait_for_pll_disable(struct clk_alpha_pll *pll, u32 mask)
+{
+   return wait_for_pll(pll, mask, 1, "disable");
+}
+
+static int wait_for_pll_offline(struct clk_alpha_pll *pll, u32 mask)
+{
+   return wait_for_pll(pll, mask, 0, "offline");
+}
+
+/* alpha pll with hwfsm support */
+#define PLL_OFFLINE_REQBIT(7)
+#define PLL_FSM_ENABIT(20)
+#define PLL_OFFLINE_ACKBIT(28)
+#define PLL_ACTIVE_FLAGBIT(30)
+
+static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
+{
+   int ret;
+   u32 val, off;
+   struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+
+   off = pll->offset;
+   ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, );
+   if (ret)
+   return ret;
+
+   /* Enable HW FSM mode, clear OFFLINE request */
+   val |= PLL_FSM_ENA;
+   val &= ~PLL_OFFLINE_REQ;
+   ret = regmap_write(pll->clkr.regmap, off + PLL_MODE, val);
+   if (ret)
+   return ret;
+
+   /* Make sure enable request goes through before waiting for update */
+   mb();
+
+   ret = wait_for_pll_enable(pll, PLL_ACTIVE_FLAG);
+   if (ret)
+   return ret;
+
+   return 0;
+}
+
+static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
+{
+   int ret;
+   u32 val, off;
+   struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+
+   off = pll->offset;
+   ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, );
+   if (ret)
+   return;
+
+   /* Request PLL_OFFLINE and wait for ack */
+   ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
+   if (ret)
+   return;
+
+   ret = wait_for_pll_offline(pll, PLL_OFFLINE_ACK);
+   if (ret)
+   return;
+
+   /* Disable hwfsm */
+   ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+PLL_FSM_ENA, 0);
+   if (ret)
+   return;
+
+   wait_for_pll_disable(pll, PLL_ACTIVE_FLAG);
+}
+
 static int clk_alpha_pll_enable(struct clk_hw *hw)
 {
int ret;
@@ -112,7 +188,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
ret = clk_enable_regmap(hw);
if (ret)
return ret;
-   return wait_for_pll(pll);
+   return wait_for_pll_enable(pll, PLL_ACTIVE_FLAG);
}
 
/* Skip if already enabled */
@@ -136,7 +212,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
if (ret)
return ret;
 
-   ret = wait_for_pll(pll);
+   ret = wait_for_pll_enable(pll, PLL_LOCK_DET);
if (ret)
return ret;
 
@@ -300,6 +376,15 @@ const struct clk_ops clk_alpha_pll_ops = {
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
 
+const struct clk_ops clk_alpha_pll_hwfsm_ops = {