On 03/14/2013 07:13:46 PM, Kevin Hilman wrote:
The new context tracking subsystem unconditionally includes kvm_host.h
headers for the guest enter/exit macros. This causes a compile
failure when KVM is not enabled.
Fix by adding an IS_ENABLED(CONFIG_KVM) check to kvm_host so it can
be included/c
On 02/04/2013 07:02:14 AM, Joerg Roedel wrote:
On Thu, Jan 31, 2013 at 09:32:26AM +, Sethi Varun-B16395 wrote:
> We need a mechanism to determine the maximum number of subwindows
supported by PAMU. How about representing it in the iommu_domain
structure:
> struct iommu_domain {
>str
On 02/07/2013 02:07:00 AM, Zhao Chenhui wrote:
The Freescale implementation of the MPIC only allows a single CPU
destination for non-IPI interrupts. Test the flag MPIC_SINGLE_DEST_CPU
to check if the Destination registers should be set.
This prevents more than one bit is set at secondary process
On 04/02/2013 08:35:54 PM, Timur Tabi wrote:
On Tue, Apr 2, 2013 at 11:18 AM, Joerg Roedel wrote:
> > + panic("\n");
>
> A kernel panic seems like an over-reaction to an access violation.
We have no way to determining what code caused the violation, so we
can't just kill the process. I ag
On 11/05/2012 04:10:46 PM, Timur Tabi wrote:
Varun Sethi wrote:
> Added the following domain attributes required by FSL PAMU driver:
> 1. Subwindows field added to the iommu domain geometry attribute.
> 2. Added new iommu stash attribute, which allows setting of the
>LIODN specific stash id p
On 11/05/2012 05:04:13 PM, Timur Tabi wrote:
Varun Sethi wrote:
> + /* PAACE Offset 0x00 */
> + u32 wbah;/* only valid for
Primary PAACE */
> + u32 addr_bitfields; /* See P/S PAACE_AF_* */
> +
> + /* PAACE Offset 0x08 */
> + /* Interpretation of first 32 bits dependent on D
On 07/26/2012 09:02 AM, Li Yang wrote:
> On Fri, Jul 20, 2012 at 8:42 PM, Zhao Chenhui
> wrote:
>> Changes for v8:
>> * Separated the cpu hotplug patch into three patches, as follows
>> [PATCH v8 1/7] powerpc/smp: use a struct epapr_spin_table to replace macros
>> [PATCH v8 2/7] powerpc/smp: a
On Tue, 2013-10-01 at 13:38 -0500, Kim Phillips wrote:
> Hi,
>
> Santosh and I are having a problem figuring out how to enable binding
> (and re-binding) platform devices to a platform VFIO driver (see
> Antonis' WIP: [1]) in an upstream-acceptable manner.
>
> Binding platform drivers currently d
On Tue, 2013-10-01 at 14:15 -0500, Scott Wood wrote:
> On Tue, 2013-10-01 at 13:38 -0500, Kim Phillips wrote:
> > Hi,
> >
> > Santosh and I are having a problem figuring out how to enable binding
> > (and re-binding) platform devices to a platform VFIO driver (see
&
On Tue, 2013-10-01 at 16:59 -0500, Kim Phillips wrote:
> On Tue, 1 Oct 2013 14:15:38 -0500
> Scott Wood wrote:
>
> > I think the ideal interface would be if you could write the sysfs device
> > name into the vfio bind file (or some new file in the same directory),
>
On Wed, 2013-10-02 at 13:25 -0500, Yoder Stuart-B08248 wrote:
>
> > -Original Message-
> > From: Christoffer Dall [mailto:christoffer.d...@linaro.org]
> > Sent: Wednesday, October 02, 2013 10:14 AM
> > To: Alex Williamson
> > Cc: Kim Phillips; gre...@linuxfoundation.org; linux-
> > ker...@
On Wed, 2013-10-02 at 11:43 -0700, Christoffer Dall wrote:
> On Wed, Oct 02, 2013 at 01:32:38PM -0500, Scott Wood wrote:
> > On Wed, 2013-10-02 at 13:25 -0500, Yoder Stuart-B08248 wrote:
> > >
> > > > -Original Message-
> > > > From: Christoffe
On Wed, 2013-10-02 at 21:13 +0100, Christoffer Dall wrote:
> On Wed, Oct 02, 2013 at 03:04:15PM -0500, Kim Phillips wrote:
> > On Wed, 2 Oct 2013 11:43:30 -0700
> > Christoffer Dall wrote:
> >
> > > On Wed, Oct 02, 2013 at 01:32:38PM -0500, Scott Wood wrote:
> &
On Wed, 2013-10-02 at 13:37 -0700, gre...@linuxfoundation.org wrote:
> On Wed, Oct 02, 2013 at 11:43:30AM -0700, Christoffer Dall wrote:
> > > What's wrong with a non-vfio-specific flag that a driver can set, that
> > > indicates that the driver is willing to try to bind to any device on the
> > >
On Wed, 2013-10-02 at 14:16 -0700, gre...@linuxfoundation.org wrote:
> On Wed, Oct 02, 2013 at 04:08:41PM -0500, Scott Wood wrote:
> > On Wed, 2013-10-02 at 13:37 -0700, gre...@linuxfoundation.org wrote:
> > > On Wed, Oct 02, 2013 at 11:43:30AM -0700, Christoffer Dall wrote:
>
On Wed, 2013-10-02 at 16:40 -0700, gre...@linuxfoundation.org wrote:
> On Wed, Oct 02, 2013 at 04:35:15PM -0500, Scott Wood wrote:
> > On Wed, 2013-10-02 at 14:16 -0700, gre...@linuxfoundation.org wrote:
> > > On Wed, Oct 02, 2013 at 04:08:41PM -0500, Scott Wood wrote:
>
On Thu, 2013-10-03 at 11:54 -0700, gre...@linuxfoundation.org wrote:
> On Thu, Oct 03, 2013 at 01:33:27PM -0500, Scott Wood wrote:
> > What it looks like we do still want from the driver core is the ability
> > for a driver to say that it should not be bound to a device except v
On 07/04/2013 05:35:28 AM, Gupta Ruchika-R66431 wrote:
Hi,
I am trying to unbind a platform device from a driver. Even when the
remove function of the device returns an EBUSY error, the device is
unbound from the driver. Is this the right behavior ? Why does kernel
forcefully unbind the
On 07/05/2013 01:27:05 AM, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this
patch add
the device tree nodes for them.
Signed-off-by: Hongbo Zhang
---
arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 90
++
On Fri, 2013-09-13 at 07:04 +0200, leroy christophe wrote:
> Le 12/09/2013 20:44, Scott Wood a écrit :
> > On Thu, 2013-09-12 at 20:25 +0200, Christophe Leroy wrote:
> >> This is a reorganisation of the setup of the TLB at kernel startup, in
> >> order
> >>
On Thu, 2013-09-12 at 18:15 +0100, Mark Rutland wrote:
> On Tue, Sep 03, 2013 at 10:01:50AM +0100, Hongbo Zhang wrote:
> > On 09/02/2013 11:58 PM, Mark Rutland wrote:
> > > May some channels be unusable for some reason, or will all eight
> > > channels be wired on any given Elo3 DMA?
> > Sorry, not
On Wed, 2013-08-28 at 13:48 +0100, Mark Rutland wrote:
> On Wed, Aug 28, 2013 at 09:18:55AM +0100, Hongbo Zhang wrote:
> > On 08/27/2013 07:25 PM, Mark Rutland wrote:
> > > On Tue, Aug 27, 2013 at 11:42:01AM +0100, hongbo.zh...@freescale.com
> > > wrote:
> > >> From: Hongbo Zhang
> > >>
> > >> Th
On Wed, 2013-09-11 at 18:44 +0200, Christophe Leroy wrote:
> Activating CONFIG_PIN_TLB is supposed to pin the IMMR and the first three
> 8Mbytes pages. But the setting of the MD_CTR was missing so as the index is
> decremented every DTLB update, the pinning of the third 8Mbytes page was
> overwriti
On Thu, 2013-09-12 at 20:25 +0200, Christophe Leroy wrote:
> This is a reorganisation of the setup of the TLB at kernel startup, in order
> to handle the CONFIG_PIN_TLB case in accordance with chapter 8.10.3 of MPC866
> and MPC885 reference manuals.
>
> Signed-off-by: Christophe Leroy
>
> diff -u
On Tue, 2013-10-08 at 10:47 -0600, Bjorn Helgaas wrote:
> On Thu, Oct 3, 2013 at 11:19 PM, Bhushan Bharat-R65777
> wrote:
>
> >> I don't know enough about VFIO to understand why these new interfaces are
> >> needed. Is this the first VFIO IOMMU driver? I see
> >> vfio_iommu_spapr_tce.c and
> >
On Thu, 2013-09-19 at 12:59 +0530, Bharat Bhushan wrote:
> @@ -376,6 +405,7 @@ static int fsl_of_msi_probe(struct platform_device *dev)
> int len;
> u32 offset;
> static const u32 all_avail[] = { 0, NR_MSI_IRQS };
> + static int bank_index;
>
> match = of_match_device(
On Tue, 2013-10-08 at 17:25 -0600, Bjorn Helgaas wrote:
> >> - u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
> >> + dma_addr_t msiir; /* MSIIR Address in CCSR */
> >
> > Are you sure dma_addr_t is right here, versus phys_addr_t? It implies
> > that it's the output of t
On Wed, 2013-10-09 at 14:02 -0500, Yoder Stuart-B08248 wrote:
> Have been thinking about this issue some more. As Scott mentioned,
> 'wildcard' matching for a driver can be fairly done in the platform
> bus driver. We could add a new flag to the platform driver struct:
>
> diff --git a/drivers/b
On Wed, 2013-10-09 at 12:16 -0700, gre...@linuxfoundation.org wrote:
> On Wed, Oct 09, 2013 at 07:02:25PM +, Yoder Stuart-B08248 wrote:
> > Have been thinking about this issue some more. As Scott mentioned,
> > 'wildcard' matching for a driver can be fairly done in the platform
> > bus driver.
On Wed, 2013-10-09 at 14:44 -0500, Yoder Stuart-B08248 wrote:
>
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Wednesday, October 09, 2013 2:22 PM
> > To: Yoder Stuart-B08248
> > Cc: Wood Scott-B07421; Kim Phillips; Christoffer Dall; Alex Williamson;
> > linux-kernel@vger.ker
On Thu, 2013-10-10 at 02:45 -0500, Bhushan Bharat-R65777 wrote:
>
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Thursday, October 10, 2013 1:33 AM
> > To: Yoder Stuart-B08248
> > Cc: Wood Scott-B07421; Kim Phillips; Christoffer Dall; Alex Williamson;
> > linux-
> > ker...@v
o.org; santosh.shu...@linaro.org;
> > k...@vger.kernel.org; gre...@linuxfoundation.org
> > Subject: Re: RFC: (re-)binding the VFIO platform driver to a platform device
> >
> > On Wed, 9 Oct 2013 15:03:19 -0500
> > Scott Wood wrote:
> >
> > > On
On Wed, 2013-09-25 at 15:35 +0800, Hongbo Zhang wrote:
> By the way, I know maybe it is difficult, but why not introduce a
> document of maintaining rules for the dt binding docs? we have dedicated
> maintainers for this part now. Description language from one submitter
> cannot satisfy every re
On Wed, 2013-09-25 at 22:53 -0500, Bhushan Bharat-R65777 wrote:
>
> > -Original Message-
> > From: Alex Williamson [mailto:alex.william...@redhat.com]
> > Sent: Wednesday, September 25, 2013 10:10 PM
> > To: Bhushan Bharat-R65777
> > Cc: j...@8bytes.org; b...@kernel.crashing.org; ga...@ker
On Tue, 2013-09-24 at 10:18 +0200, Christophe Leroy wrote:
> Activating CONFIG_PIN_TLB is supposed to pin the IMMR and the first three
> 8Mbytes pages. But the setting of MD_CTR to a pinnable entry was missing
> before
> the pinning of the third 8Mb page. As the index is decremented module 28
> (M
On Tue, 2013-09-17 at 18:40 +0200, leroy christophe wrote:
> Le 16/09/2013 23:02, Scott Wood a écrit :
> > On Fri, 2013-09-13 at 07:04 +0200, leroy christophe wrote:
> >> Le 12/09/2013 20:44, Scott Wood a écrit :
> >>> On Thu, 2013-09-12 at 20:25 +0200, Christophe
On 10/09/2012 06:20:53 PM, Mitch Bradley wrote:
On 10/9/2012 11:16 AM, Stephen Warren wrote:
> On 10/01/2012 12:39 PM, Jon Loeliger wrote:
>>>
>>> What more do you think needs discussion re: dtc+cpp?
>>
>> How not to abuse the ever-loving shit out of it? :-)
>
> Perhaps we can just handle this th
On 10/10/2012 10:15:17 AM, Stephen Warren wrote:
On 10/09/2012 06:04 PM, Scott Wood wrote:
> On 10/09/2012 06:20:53 PM, Mitch Bradley wrote:
>> On 10/9/2012 11:16 AM, Stephen Warren wrote:
>> > On 10/01/2012 12:39 PM, Jon Loeliger wrote:
>> >>>
>> >>
On 12/03/2012 10:57:29 AM, Sethi Varun-B16395 wrote:
> -Original Message-
> From: iommu-boun...@lists.linux-foundation.org [mailto:iommu-
> boun...@lists.linux-foundation.org] On Behalf Of Joerg Roedel
> Sent: Sunday, December 02, 2012 7:33 PM
> To: Sethi Varun-B16395
> Cc: linux-kernel
On 12/03/2012 11:27:12 AM, Joerg Roedel wrote:
On Mon, Dec 03, 2012 at 04:57:29PM +, Sethi Varun-B16395 wrote:
>
>
> > -Original Message-
> > From: iommu-boun...@lists.linux-foundation.org [mailto:iommu-
> > boun...@lists.linux-foundation.org] On Behalf Of Joerg Roedel
> > Sent: Sunda
On 12/04/2012 05:53:33 AM, Sethi Varun-B16395 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Monday, December 03, 2012 10:34 PM
> To: Sethi Varun-B16395
> Cc: Joerg Roedel; linux-kernel@vger.kernel.org; iommu@lists.linux-
> foundation.org; Wood Scott-B07421; linuxppc-...@
On 10/17/2012 12:32:49 PM, Varun Sethi wrote:
Added the following domain attributes required by FSL PAMU driver:
1. Subwindows field added to the iommu domain geometry attribute.
2. Added new iommu stash attribute, which allows setting of the
LIODN specific stash id parameter through IOMMU API
On 10/22/2012 04:18:07 PM, Tabi Timur-B04825 wrote:
On Wed, Oct 17, 2012 at 12:32 PM, Varun Sethi
wrote:
> +}
> +
> +static unsigned long pamu_get_fspi_and_allocate(u32 subwin_cnt)
> +{
subwin_cnt should probably be an unsigned int.
This function needs to be documented. What value is being
On 12/10/2012 04:10:06 AM, Sethi Varun-B16395 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, December 04, 2012 11:53 PM
> To: Sethi Varun-B16395
> Cc: Wood Scott-B07421; Joerg Roedel; linux-kernel@vger.kernel.org;
> io...@lists.linux-foundation.org; linuxppc-...@
On 11/12/2012 03:02:46 PM, Geert Uytterhoeven wrote:
On Mon, Nov 12, 2012 at 9:58 PM, Geert Uytterhoeven
wrote:
> JFYI, when comparing v3.7-rc5 to v3.7-rc4[3], the summaries are:
> - build errors: +14/-4
14 regressions:
+ drivers/virt/fsl_hypervisor.c: error: 'MSR_GS' undeclared (first
use
On 11/05/2012 05:19:20 AM, Varun Sethi wrote:
Added the following domain attributes required by FSL PAMU driver:
1. Subwindows field added to the iommu domain geometry attribute.
2. Added new iommu stash attribute, which allows setting of the
LIODN specific stash id parameter through IOMMU API
On 04/22/2013 12:31:55 AM, Varun Sethi wrote:
Added the following domain attributes for the FSL PAMU driver:
1. Added new iommu stash attribute, which allows setting of the
LIODN specific stash id parameter through IOMMU API.
2. Added an attribute for enabling/disabling DMA to a particular
On 06/12/2013 10:08:29 AM, Sebastian Andrzej Siewior wrote:
On 06/12/2013 02:47 PM, Oded Gabbay wrote:
> This patch fixes a bug in the fsl_pq_mdio.c module and in relevant
device-tree
> files regarding the correct offset of the tbipa register in the
eTSEC
> controller in some of Freescale's
On 06/12/2013 03:19:30 AM, Rojhalat Ibrahim wrote:
On Tuesday 11 June 2013 12:28:59 Scott Wood wrote:
> Yes, I figured it was non-PCIe because the code change that you said
> helped was on the non-PCIe branch of the if/else. Generally it's
good
> to explicitly mention the chi
On 06/13/2013 02:21:24 AM, Rojhalat Ibrahim wrote:
On Wednesday 12 June 2013 16:50:26 Scott Wood wrote:
> On 06/12/2013 03:19:30 AM, Rojhalat Ibrahim wrote:
> > On Tuesday 11 June 2013 12:28:59 Scott Wood wrote:
> > > Yes, I figured it was non-PCIe because the code chan
setup_indirect_pci for all
device types.
fsl_indirect_read_config is now only used for booke/86xx PCIe
controllers.
Reported-by: Michael Guntsche
Cc: Scott Wood
Signed-off-by: Rojhalat Ibrahim
---
v2: Make it more consistent.
arch/powerpc/sysdev/fsl_pci.c | 20 +++-
1 file
On Thu, Feb 21, 2013 at 06:32:36AM -, LEROY Christophe wrote:
> This patch allows the use IRQ to notify the change of GPIO status on the
> MPC8xx
> CPM IO ports. This then allows to associate IRQs to GPIOs in the Device Tree.
> Ex:
> CPM1_PIO_C: gpio-controller@960 {
> #gp
On 06/17/2013 08:15:33 AM, Rojhalat Ibrahim wrote:
On Friday 14 June 2013 15:18:03 Scott Wood wrote:
> On 83xx:
> cc1: warnings being treated as errors
>
/home/scott/fsl/git/linux/upstream/arch/powerpc/sysdev/fsl_pci.c:100:23:
> error: 'fsl_indirect_pcie_ops' defined
On 05/28/2013 07:12:32 PM, Alexey Kardashevskiy wrote:
On 05/29/2013 09:35 AM, Scott Wood wrote:
> On 05/28/2013 06:30:40 PM, Alexey Kardashevskiy wrote:
>> >> >>> @@ -939,6 +940,9 @@ struct kvm_s390_ucas_mapping {
>> >> >>> #define KVM_G
On 05/29/2013 06:10:33 PM, Alexey Kardashevskiy wrote:
On 05/30/2013 06:05 AM, Scott Wood wrote:
> On 05/28/2013 07:12:32 PM, Alexey Kardashevskiy wrote:
>> On 05/29/2013 09:35 AM, Scott Wood wrote:
>> > On 05/28/2013 06:30:40 PM, Alexey Kardashevskiy wrote:
>> &g
On 05/29/2013 06:29:13 PM, Alexey Kardashevskiy wrote:
On 05/30/2013 09:14 AM, Scott Wood wrote:
> On 05/29/2013 06:10:33 PM, Alexey Kardashevskiy wrote:
>> On 05/30/2013 06:05 AM, Scott Wood wrote:
>> > But you didn't put it in the same section as
KVM_CREATE_SPAPR_TC
On 04/19/2013 05:47:38 AM, Zhao Chenhui wrote:
From: Li Yang
Signed-off-by: Li Yang
Signed-off-by: Zhao Chenhui
---
.../devicetree/bindings/powerpc/fsl/pmc.txt| 59
+++
1 files changed, 34 insertions(+), 25 deletions(-)
diff --git a/Documentation/devicetree/bind
On Thu, Feb 28, 2013 at 09:52:22AM +0100, LEROY Christophe wrote:
> This patch modifies the behaviour of the MPC8xx/8xxx watchdog. On the MPC8xx,
> at 133Mhz, the maximum timeout of the watchdog timer is 1s, which means it
> must
> be pinged twice a second. This is not in line with the Linux watch
On 06/10/2013 12:07:43 PM, Michael Guntsche wrote:
Good evening,
On Mon, Jun 10, 2013 at 1:41 PM, Rojhalat Ibrahim
wrote:
> Hi Mike,
>
> could you please try this patch:
> https://lists.ozlabs.org/pipermail/linuxppc-dev/2013-May/106624.html
> http://patchwork.ozlabs.org/patch/244515/
>
>
On 06/11/2013 02:24:28 AM, Rojhalat Ibrahim wrote:
On Monday 10 June 2013 17:52:33 Scott Wood wrote:
> On 06/10/2013 12:07:43 PM, Michael Guntsche wrote:
> > Good evening,
> >
> > This patch does not fix the problem, during boot the kernel still
> > panics. I had a cl
On 06/11/2013 12:09:42 PM, Michael Guntsche wrote:
On Tue, Jun 11, 2013 at 7:00 PM, Scott Wood
wrote:
> On 06/11/2013 02:24:28 AM, Rojhalat Ibrahim wrote:
>>
>> On Monday 10 June 2013 17:52:33 Scott Wood wrote:
>> > On 06/10/2013 12:07:43 PM, Michael Guntsche wr
On 06/30/2013 10:46:18 PM, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang
This patch adds support to 8-channel DMA engine, thus the driver
works for both
the new 8-channel and the legacy 4-channel DMA engines.
Signed-off-by: Hongbo Zhang
---
drivers/dma/fsldma.c | 48
+++
On 07/02/2013 10:47:44 PM, Hongbo Zhang wrote:
On 07/03/2013 07:13 AM, Scott Wood wrote:
Wait a second -- how are we even getting into this code on these new
DMA controllers? All 85xx-family DMA controllers use
fsldma_chan_irq directly.
Right, we are using fsldma_chan_irq, this code
On 07/03/2013 02:48:59 AM, Hongbo Zhang wrote:
On 07/03/2013 11:53 AM, Hongbo Zhang wrote:
hmm...add the devicetree-disc...@lists.ozlabs.org into list.
Note that we are discussing a better naming for this new compatible
property in the corresponding [PATCH 2/2], so I will resend a v2 of
thi
Please keep subject lines limited to 60-70 characters, and prefix with
"powerpc/83xx:".
On Mon, Mar 18, 2013 at 05:47:32PM +0400, Sergey Gerasimov wrote:
> Signed-off-by: Sergey Gerasimov
>
> ---
> arch/powerpc/boot/dts/ib8315.dts | 490 +++
> arch/powerpc/configs/83xx/ib8315_defc
On 06/27/2013 12:02:36 AM, Alexey Kardashevskiy wrote:
+/*
+ * The KVM guest can be backed with 16MB pages.
+ * In this case, we cannot do page counting from the real mode
+ * as the compound pages are used - they are linked in a list
+ * with pointers as virtual addresses which are inaccessible
On Tue, Mar 19, 2013 at 01:14:22AM -0400, Benjamin Collins wrote:
> This isn't specifically needed in order to build the kernel. It's
> stored in flash with firmware. However, keep it in the kernel for
> reference (and to have an example for fsl_dpa device tree usage).
>
> Signed-off-by: Ben Colli
On 03/21/2013 09:27:14 AM, Kevin Hilman wrote:
Gleb Natapov writes:
> On Wed, Mar 20, 2013 at 06:58:41PM -0500, Scott Wood wrote:
>> On 03/14/2013 07:13:46 PM, Kevin Hilman wrote:
>> >The new context tracking subsystem unconditionally includes
kvm_host.h
>> >heade
On 03/21/2013 02:16:00 PM, Gleb Natapov wrote:
On Thu, Mar 21, 2013 at 01:42:34PM -0500, Scott Wood wrote:
> On 03/21/2013 09:27:14 AM, Kevin Hilman wrote:
> >Gleb Natapov writes:
> >
> >> On Wed, Mar 20, 2013 at 06:58:41PM -0500, Scott Wood wrote:
> >>>
On 07/15/2013 08:35:07 AM, Kumar Gala wrote:
On Jul 5, 2013, at 1:27 AM,
wrote:
> +dma0: dma@100300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,elo3-dma";
why does this require a new compatible?
The binding has changed -- there is now a second reg entry.
On 07/15/2013 05:34:58 AM, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this
patch add
the device tree nodes for them.
Signed-off-by: Hongbo Zhang
---
.../devicetree/bindings/powerpc/fsl/dma.txt|8 +-
arch/
On 07/15/2013 03:47:06 AM, Benjamin Herrenschmidt wrote:
On Mon, 2013-07-15 at 14:04 +1000, Anton Blanchard wrote:
> Module CRCs are implemented as absolute symbols that get resolved by
> a linker script. We build an intermediate .o that contains an
> unresolved symbol for each CRC. genksysms par
On 07/16/2013 07:04:05 PM, Benjamin Herrenschmidt wrote:
On Tue, 2013-07-16 at 17:40 -0500, Scott Wood wrote:
> On 07/15/2013 03:47:06 AM, Benjamin Herrenschmidt wrote:
> > On Mon, 2013-07-15 at 14:04 +1000, Anton Blanchard wrote:
> > > Module CRCs are implemented as absolut
On 07/26/2013 05:27:15 AM, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this
patch adds
the device tree nodes for them.
Signed-off-by: Hongbo Zhang
---
.../devicetree/bindings/powerpc/fsl/dma.txt| 66
++
On 07/29/2013 05:49:02 AM, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang
This patch updates the discription of each type of DMA controller and
its
channels, it is preparation for adding another new DMA controller
binding, it
also fixes some defects of indent for text alignment at th
On 07/29/2013 05:49:03 AM, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this
patch adds
the device tree nodes for them.
Signed-off-by: Hongbo Zhang
---
.../devicetree/bindings/powerpc/fsl/dma.txt| 66
++
On Mon, May 27, 2013 at 02:29:43PM +0200, Sergey Gerasimov wrote:
> For MPC831x the bus probing function also needs the fixup to assign
> addresses to the PCI devices as it was for MPC85xx and MPC86xx.
> The fixup of the bridge vendor and device ID should be done early in
> PCI probing. Else the br
I've got it in my queue that I hope to send soon.
-Scott
On 07/31/2013 09:45:25 AM, Ian Campbell wrote:
ping?
On Fri, 2013-05-31 at 11:14 +0100, Ian Campbell wrote:
> This file is a common include for B4860 and B4420 but is not a
valid DTS itself:
> DTC arch/powerpc/boot/b4qds.dtb
On Wed, 2013-08-21 at 16:33 -0600, Stephen Warren wrote:
> On 07/29/2013 04:49 AM, hongbo.zh...@freescale.com wrote:
> > From: Hongbo Zhang
> >
> > This patch updates the discription of each type of DMA controller and its
> > channels, it is preparation for adding another new DMA controller bindi
On Wed, 2013-08-21 at 16:40 -0600, Stephen Warren wrote:
> On 07/29/2013 04:49 AM, hongbo.zh...@freescale.com wrote:
> > Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch
> > adds
> > the device tree nodes for them.
>
> > diff --git a/Documentation/devicetree/bindings/powe
On Wed, 2013-08-21 at 16:40 -0600, Stephen Warren wrote:
> On 07/29/2013 04:49 AM, hongbo.zh...@freescale.com wrote:
> > +- reg :
> > +- interrupts:
>
> s/interrupts/specifier/
Do you mean s/interrupt mapping/interrupt specifier/?
And probably s/registers
On Wed, 2013-08-21 at 17:15 -0600, Stephen Warren wrote:
> On 08/21/2013 04:57 PM, Scott Wood wrote:
> > On Wed, 2013-08-21 at 16:40 -0600, Stephen Warren wrote:
> >> On 07/29/2013 04:49 AM, hongbo.zh...@freescale.com wrote:
>
> >>> +- ranges: describe
On Wed, 2013-08-21 at 17:12 -0600, Stephen Warren wrote:
> OK, if there's some alternative run-time way of enabling chip-specific
> quirking, it's probably fine to remove the extra compatible values.
>
> Now, that does rather assume that this DMA IP block will only ever be
> used within SoCs that
On Wed, 2013-07-31 at 08:29 +0530, Deepthi Dharwar wrote:
> /*
> - * pseries_idle_probe()
> + * powerpc_idle_probe()
> * Choose state table for shared versus dedicated partition
> */
> -static int pseries_idle_probe(void)
> +static int powerpc_idle_probe(void)
> {
>
> +#ifndef PPC_POWERNV
>
On Wed, 2013-08-07 at 09:30 +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2013-08-06 at 18:08 -0500, Scott Wood wrote:
> > Here's another example. get_lppaca() will only build on book3s -- and
> > yet we get requests for e500 code to use this file.
>
> Indeed, Besides
On 07/17/2013 11:00:45 PM, Anton Blanchard wrote:
Hi Scott,
> What specifically should I do to test it?
Could you double check perf annotate works? I'm 99% sure it will but
that is what was failing on ppc64.
I'm not really sure what it's supposed to look like when "perf
annotate" works. I
On 07/22/2013 12:55:38 AM, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang
This updates the discription of each type of DMA controller and its
channels,
it is preparation for adding another new DMA controller binding, also
fixes
some defects of indent for text alignment at the same ti
On 07/23/2013 08:30:32 AM, Michael Ellerman wrote:
On Fri, Jul 19, 2013 at 05:59:30PM -0500, Scott Wood wrote:
> On 07/17/2013 11:00:45 PM, Anton Blanchard wrote:
> >
> >Hi Scott,
> >
> >> What specifically should I do to test it?
> >
> >Could you doub
On 07/24/2013 01:21:07 AM, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this
patch add
the device tree nodes for them.
Signed-off-by: Hongbo Zhang
---
.../devicetree/bindings/powerpc/fsl/dma.txt| 66
+++
On 07/24/2013 01:21:08 AM, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang
This patch adds support to 8-channel DMA engine, thus the driver
works for both
the new 8-channel and the legacy 4-channel DMA engines.
Signed-off-by: Hongbo Zhang
---
drivers/dma/Kconfig |9 +
dr
On 07/24/2013 01:21:09 AM, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang
The variable cookie is initialized in a list_for_each_entry loop,
if(unlikely)
the list is empty, this variable will be used uninitialized, so we
get a gcc
compiling warning about this. This patch fixes this def
On Thu, 2013-08-08 at 07:50 +0200, leroy christophe wrote:
> Le 26/06/2013 01:04, Scott Wood a écrit :
> > What happens if there's a race? If another CPU updates wdt_last_ping in
> > parallel, then you could see wdt_last_ping greater than the value you
> > read for
On 04/19/2013 05:47:34 AM, Zhao Chenhui wrote:
These cache operations support Freescale SoCs based on BOOK3E.
Move L1 cache operations to fsl_booke_cache.S in order to maintain
easily. And, add cache operations for backside L2 cache and platform
cache.
The backside L2 cache appears on e500mc
On 04/19/2013 05:47:35 AM, Zhao Chenhui wrote:
static int pmc_suspend_enter(suspend_state_t state)
{
- int ret;
+ int ret = 0;
+
+ switch (state) {
+#ifdef CONFIG_PPC_85xx
+ case PM_SUSPEND_MEM:
+#ifdef CONFIG_SPE
+ enable_kernel_spe();
+#endif
+
On 04/19/2013 05:47:40 AM, Zhao Chenhui wrote:
From: Chen-Hui Zhao
In the case of SMP, during the time base sync period, all time bases
of
online cores must stop, then start simultaneously.
There is a RCPM (Run Control/Power Management) module in CoreNet
based SoCs.
Define a struct ccsr_
On 04/19/2013 05:47:46 AM, Zhao Chenhui wrote:
From: Chen-Hui Zhao
The L1 Data Cache of e6500 contains no modified data, no flush
is required.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
Signed-off-by: Andy Fleming
---
arch/powerpc/kernel/fsl_booke_cache.S | 11 ++-
1 file
On 04/19/2013 05:47:45 AM, Zhao Chenhui wrote:
From: Chen-Hui Zhao
For e6500, two threads in one core share one time base. Just need
to do time base sync on first thread of one core, and skip it on
the other thread.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
Signed-off-by: Andy Flemi
On 04/24/2013 06:29:29 AM, Zhao Chenhui wrote:
On Tue, Apr 23, 2013 at 07:04:06PM -0500, Scott Wood wrote:
> On 04/19/2013 05:47:45 AM, Zhao Chenhui wrote:
> >From: Chen-Hui Zhao
> >
> >For e6500, two threads in one core share one time base. Just need
> >to do time b
On 04/24/2013 07:28:18 PM, Zhao Chenhui wrote:
On Wed, Apr 24, 2013 at 05:38:16PM -0500, Scott Wood wrote:
> On 04/24/2013 06:29:29 AM, Zhao Chenhui wrote:
> >On Tue, Apr 23, 2013 at 07:04:06PM -0500, Scott Wood wrote:
> >> On 04/19/2013 05:47:45 AM, Zhao Chenhui wrote:
> &g
On 04/28/2013 04:56:34 AM, Zhao Chenhui wrote:
On Thu, Apr 25, 2013 at 07:07:24PM -0500, Scott Wood wrote:
> On 04/24/2013 07:28:18 PM, Zhao Chenhui wrote:
> >On Wed, Apr 24, 2013 at 05:38:16PM -0500, Scott Wood wrote:
> >> We shouldn't base it on CPU_FTR_SMT. For
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