Thankyou for the comments.
On 08/05/13 17:18, Arnd Bergmann wrote:
On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
The STiH415 is the next generation of HD, AVC set-top box processors for
satellite, cable, terrestrial and IP-STB
On 08/05/13 17:20, Arnd Bergmann wrote:
On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
diff --git a/arch/arm/mach-stih41x/board-dt.c
b/arch/arm/mach-stih41x/board-dt.c
index 8005f71..1f23aca 100644
--- a/arch/arm/mach-stih41x/board-dt.c
+++ b/arch/arm/mach-stih41x/board-dt.c
@@ -63,6
Thankyou for your comments.
On 08/05/13 15:50, Arnd Bergmann wrote:
On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch introduces syscon_claim, syscon_read, syscon_write,
syscon_release APIs to help drivers to use syscon
Thankyou for the comments.
On 08/05/13 16:01, Mark Brown wrote:
On Wed, May 08, 2013 at 04:50:22PM +0200, Arnd Bergmann wrote:
In many cases a single syconf register contains bits related to multiple
devices, and therefore it need to be shared across multiple drivers at
bit level. The same IP
Thankyou for the comments.
On 08/05/13 15:34, Arnd Bergmann wrote:
On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
+*st-asc(Serial Port)
+
+Required properties:
+- compatible : Should be st,asc.
Are there any hardware revision
On 08/05/13 15:39, Jean-Christophe PLAGNIOL-VILLARD wrote:
+
Please remove all forward declarations, by reordering the functions in
the way they are called.
and drop the dummy functions
We can not remove the dummy functions, as the serial-core does not check
it before using them.
Hi Arnd,
Thankyou for extending the discussion.
On 08/05/13 20:48, Arnd Bergmann wrote:
On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
the pinctrl driver calls syconf_claim(np, st,alt-control) to get a
field and then do a read/write on the field.
Just in pinctrl driver we use around 50
On 09/05/13 10:51, Mark Brown wrote:
On Wed, May 08, 2013 at 06:42:04PM +0100, Srinivas KANDAGATLA wrote:
Fix your mailer to word wrap within paragraphs.
Sorry about that.
Ultimately the syscon_write use the regmap_update_bits, however we
really want is the flexibility in using/referring
On 09/05/13 14:26, Mark Brown wrote:
On Thu, May 09, 2013 at 12:58:01PM +0100, Srinivas KANDAGATLA wrote:
Currently, we have two bits of information which come from device trees.
1 The syscon bank/group definition itself.
2 syscon register offsets and bits information to the drivers
On 08/05/13 15:38, Arnd Bergmann wrote:
On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
From: Stuart Menefy stuart.men...@st.com
This is a simple driver for the global timer module found in the Cortex
A9-MP cores from revision r1p0 onwards. This should be able to perform
the functions
On 09/05/13 15:40, Mark Brown wrote:
So what exactly is the driver doing then? If the register maps look
nothing like each other then what's the common functionality the driver
is providing?
What I meant here is that, sysconf registers are reassigned per SOC, so
the sysconf register
On 09/05/13 15:51, Arnd Bergmann wrote:
It won't.
Looking at the code in clocksource_of_init it just goes through the
of_device_id table, which is not used in case of non-DT.
All new platforms are DT-only, and none of the old platforms use this
driver, so it does not matter.
It makes
On 09/06/13 17:00, Lars-Peter Clausen wrote:
[...]
+int regmap_field_write(struct regmap_field *field, unsigned int val)
+{
+int field_bits;
+unsigned int reg_mask;
+field_bits = field-msb - field-lsb + 1;
+reg_mask = ((BIT(field_bits) - 1) field-lsb);
+return
rates.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Greg Kroah-Hartman gre...@linuxfoundation.org
---
.../devicetree/bindings/tty/serial/st-asc.txt | 18
From: Srinivas Kandagatla srinivas.kandaga...@st.com
Here is new patch-set incorporating all the review comments.
This patch-set adds basic support for STMicroelectronics STi SOCs
which includes STiH415 and STiH416 with B2000 and B2020 board support.
STiH415 and STiH416 are dual-core ARM
Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Rob Herring robherri...@gmail.com
CC: Linus Walleij linus.wall...@linaro.org
CC: Will Deacon will.dea
the signal.
About driver:
This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
pinconf, pinmux, gpio subsystems. All the pinctrl related config
information can only come from device trees.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore
pinctrl.
This patch adds support to ST System Configuration registers, which can
be configured by the drivers.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stuart Menefy stuart.men...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Linus Walleij linus.wall...@linaro.org
CC
are based on regmaps,
like some clocks or pinctrls which can work on the regmap_fields
directly without having to worry about bit positions.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Mark Brown broo...@kernel.org
CC: Arnd Bergmann a...@arndb.de
CC: Alexander Shiyan shc_w
The STiH415 is the next generation of HD, AVC set-top box processors for
satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9
1.0 GHz, dual-core CPU.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy
This patch adds stih415 and stih416 support to multi_v7_defconfig.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
---
arch/arm/configs/multi_v7_defconfig | 32 +++-
1 files changed, 15 insertions(+), 17 deletions
This patch adds low level debug uart support to sti based SOCs.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
---
arch/arm/Kconfig.debug | 38 +++
arch/arm/include/debug/sti.S | 61
B2000 board is reference board for STIH415/416 SOCs, it has
2 x UART, 4x USB, 2 x Ethernet, 1 x SATA, 1 x PCIe, and 1GB RAM.
This patch add initial support to b2000 with STiH415/416 with UART2 as
console and a heard beat LED.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC
a/arch/arm/boot/dts/stih415-b2020.dts
b/arch/arm/boot/dts/stih415-b2020.dts
new file mode 100644
index 000..442b019
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2020.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (RD) Limited.
+ * Author: Srinivas Kandagatla srinivas.kandaga
The STiH416 is advanced HD AVC processor with 3D graphics acceleration
and 1.2-GHz ARM Cortex-A9 SMP CPU.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Linus
On 10/06/13 10:15, Mark Brown wrote:
On Sun, Jun 09, 2013 at 06:00:19PM +0200, Lars-Peter Clausen wrote:
+int regmap_field_write(struct regmap_field *field, unsigned int val)
+{
+ int field_bits;
+ unsigned int reg_mask;
+ field_bits = field-msb - field-lsb + 1;
+ reg_mask =
Thanks for testing...
On 10/06/13 11:40, Mark Rutland wrote:
On Mon, Jun 10, 2013 at 10:27:57AM +0100, Srinivas KANDAGATLA wrote:
This patch adds stih415 and stih416 support to multi_v7_defconfig.
This seems to drop a few options also:
CONFIG_ARM_ARCH_TIMER
Same as last comment 2
On 10/06/13 12:15, Michal Simek wrote:
Thankyou for your comments,
Hi,
hmm - that's a nice bug that thunderbird is not able to send this email. :-(
Let's comment it again via gmail.
diff --git a/arch/arm/boot/dts/stih415.dtsi
b/arch/arm/boot/dts/stih415.dtsi
new file mode
Thankyou for your comment and suggestion,
I will fix the POSIX compliant issue.
On 10/06/13 10:35, Russell King - ARM Linux wrote:
On Mon, Jun 10, 2013 at 10:21:00AM +0100, Srinivas KANDAGATLA wrote:
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically
On 10/06/13 14:16, Linus Walleij wrote:
On Mon, Jun 10, 2013 at 11:22 AM, Srinivas KANDAGATLA
srinivas.kandaga...@st.com wrote:
This mfd driver provides higher level inialization routines for various
IPs like Ethernet, USB, PCIE, SATA and so on. Also it provides way to
get to syscfg
Thanks for the comments.
On 10/06/13 15:02, Arnd Bergmann wrote:
On Monday 10 June 2013 14:52:38 Srinivas KANDAGATLA wrote:
On 10/06/13 14:16, Linus Walleij wrote:
On Mon, Jun 10, 2013 at 11:22 AM, Srinivas KANDAGATLA
srinivas.kandaga...@st.com wrote:
This mfd driver provides higher level
Thankyou for your comments.
On 10/06/13 14:52, Arnd Bergmann wrote:
On Monday 10 June 2013 10:27:05 Srinivas KANDAGATLA wrote:
+soc {
+pin-controller-sbc {
+#address-cells = 1;
+#size-cells = 1;
+compatible
On 11/06/13 00:19, Russell King - ARM Linux wrote:
On Mon, Jun 10, 2013 at 12:46:59PM +0100, Srinivas KANDAGATLA wrote:
+ aux_ctrl = (0x1 L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
+ (0x1 L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
+ (0x1
On 10/06/13 15:02, Arnd Bergmann wrote:
There are multiple ways of doing that, e.g. you could export a function
from syscon.c that you call to register the device node and then import
the regmap from syscon into your high-level driver again.
Hi Arnd/Linus,
Thankyou for your comments,
I did
On 11/06/13 11:48, Mark Brown wrote:
On Mon, Jun 10, 2013 at 10:21:58AM +0100, Srinivas KANDAGATLA wrote:
It is common to access regmap registers at bit level, using
regmap_update_bits or regmap_read functions, however the end user has to
take care of a mask or shifting. This becomes overhead
From: Srinivas Kandagatla srinivas.kandaga...@st.com
It is common to access regmap registers at bit level, using
regmap_update_bits or regmap_read functions, however the end user has to
take care of a mask or shifting. This becomes overhead when such use
cases are high. Having a common function
On 11/06/13 21:13, Linus Walleij wrote:
On Tue, Jun 11, 2013 at 4:05 PM, Srinivas KANDAGATLA
srinivas.kandaga...@st.com wrote:
Doing this is not adding any value to the driver, because
1. Currently the driver only support DT boot paths, in my previous RFC
patches, Arnd suggested to get rid
On 10/06/13 14:15, Mark Rutland wrote:
CONFIG_EXPERIMENTAL's gone as of 3d374d09f1: final removal of
CONFIG_EXPERIMENTAL, so that's fine to go. CONFIG_GPIO_PL061 and
CONFIG_MMC_WMT get selected elsewhere, so that's fine.
Am planning to send a patch to clean this up, so that any new platform
On 13/06/13 12:56, Russell King - ARM Linux wrote:
On Tue, Jun 11, 2013 at 07:50:31AM +0100, Srinivas KANDAGATLA wrote:
You are right, It does not make sense to use BIT() macro for field which
has more than 1 bit. I think using mix of both BIT() and the old style
will make code look bit
On 10/06/13 14:52, Arnd Bergmann wrote:
On Monday 10 June 2013 10:27:05 Srinivas KANDAGATLA wrote:
+ soc {
+ pin-controller-sbc {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = st,stih416-pinctrl, simple
On 04/06/13 22:01, Mark Brown wrote:
On Tue, May 28, 2013 at 03:58:00PM +0100, Srinivas KANDAGATLA wrote:
+#define REGMAP_FIELD_INIT(regmap, reg, lsb, msb) { \
+.regmap = regmap, \
+.reg = reg
Thankyou for reviewing the patch.
On 05/06/13 12:41, Mark Brown wrote:
On Wed, Jun 05, 2013 at 10:21:23AM +0100, Srinivas KANDAGATLA wrote:
I think I'd prefer to see a struct passed in here for the field
definition - this would make it easier to initialise from static data,
otherwise people
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP is common
across all the ST parts for settop box platforms.
ASC is embedded in ST COMMS IP block. It supports Rx Tx
Thankyou for the comments.
On 21/06/13 16:56, Thomas Gleixner wrote:
On Fri, 21 Jun 2013, Srinivas KANDAGATLA wrote:
+static void gt_clockevent_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *clk)
+{
+unsigned long ctrl;
+
+ctrl
On 24/06/13 12:57, Linus Walleij wrote:
On Fri, Jun 21, 2013 at 3:41 PM, Srinivas KANDAGATLA
srinivas.kandaga...@st.com wrote:
Hi Linus W,
If its not too late can this patch be considered for 3.11 via pinctrl tree?
There is a build dependecy with regmap_field apis pulled by Mark Brown
Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Rob Herring robherri...@gmail.com
CC: Linus Walleij linus.wall...@linaro.org
CC: Will Deacon will.dea
On 24/06/13 21:06, Stephen Boyd wrote:
On 06/24/13 08:53, Srinivas KANDAGATLA wrote:
+
+static void gt_clockevents_stop(struct clock_event_device *clk)
+{
+gt_clockevent_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
+disable_percpu_irq(clk-irq);
+}
+
+static int __cpuinit
On 24/06/13 21:01, Thomas Gleixner wrote:
On Mon, 24 Jun 2013, Srinivas KANDAGATLA wrote:
From: Stuart Menefy stuart.men...@st.com
This is a simple driver for the global timer module found in the Cortex
A9-MP cores from revision r1p0 onwards. This should be able to perform
the functions
On 24/06/13 18:54, Olof Johansson wrote:
On Fri, Jun 21, 2013 at 11:37:56AM +0100, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
Thankyou all for reviewing the v3 patches.
This patch-set adds basic support for STMicroelectronics STi SOCs
which includes
Thankyou for the comments.
On 24/06/13 23:08, Stephen Boyd wrote:
On 06/24/13 08:53, Srinivas KANDAGATLA wrote:
+#include linux/clkdev.h
Why do you need this include?
+#include asm/mach/irq.h
And this one?
Removed them.
+static u64 gt_counter_read(void)
+{
+u64 counter
Thankyou for the comments,
On 24/06/13 23:00, Stephen Boyd wrote:
On 06/24/13 14:08, Srinivas KANDAGATLA wrote:
On 24/06/13 21:06, Stephen Boyd wrote:
On 06/24/13 08:53, Srinivas KANDAGATLA wrote:
I think the problem is your clockevent has no rating. Please give it a
rating (300?) so
Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
Reviewed-by: Thomas Gleixner t...@linutronix.de
CC: Arnd Bergmann a...@arndb.de
CC: Rob Herring robherri...@gmail.com
CC: Linus Walleij
On 24/06/13 15:12, Mark Brown wrote:
On Mon, Jun 24, 2013 at 01:57:56PM +0200, Linus Walleij wrote:
This seems fairly complete, but I cannot have such a basic dependency onto
the regmap tree this late in the merge window, i.e. I'm not ready to pull
all of regmap into the pinctrl tree. I'd
On 25/06/13 00:38, Greg Kroah-Hartman wrote:
On Mon, Jun 24, 2013 at 08:21:43AM +0100, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP
On 25/06/13 11:58, Linus Walleij wrote:
On Mon, Jun 24, 2013 at 4:12 PM, Mark Brown broo...@kernel.org wrote:
On Mon, Jun 24, 2013 at 01:57:56PM +0200, Linus Walleij wrote:
This seems fairly complete, but I cannot have such a basic dependency onto
the regmap tree this late in the merge
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch-set adds basic support for STMicroelectronics STi series SOCs
which includes STiH415 and STiH416 with B2000 and B2020 board support.
STiH415 and STiH416 are dual-core ARM Cortex-A9 CPU, designed for use in
Set-top-boxes. The SOC
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds low level debug uart support to sti based SOCs.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
---
arch/arm/Kconfig.debug | 35
arch/arm/include
From: Srinivas Kandagatla srinivas.kandaga...@st.com
The STiH416 is advanced HD AVC processor with 3D graphics acceleration
and 1.2-GHz ARM Cortex-A9 SMP CPU.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch is generated after re-running savedefconfig on top of
multi_v7_defconfig which gets rid of some of the options, as they are
now slected by mach level or other Kconfigs.
The reason to generate this patch is because, it becomes
From: Srinivas Kandagatla srinivas.kandaga...@st.com
The STiH415 is the next generation of HD, AVC set-top box processors for
satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9
1.0 GHz, dual-core CPU.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen
From: Srinivas Kandagatla srinivas.kandaga...@st.com
B2020 ADI board is reference board for STIH415/416 SOCs, it has 2 x
UART, 4x USB, 1 x Ethernet, 1 x SATA, 1 x PCIe, and 2GB RAM with
standard set-top box IPs.
This patch adds initial support to B2020 with STiH415/416 with SBC_UART1
as console
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds stih415 and stih416 support to multi_v7_defconfig.
CONFIG_ARM_ERRATA_754322 is removed as it is selected by the sti
mach level kconfig.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
arch/arm/configs
From: Srinivas Kandagatla srinivas.kandaga...@st.com
B2000 board is reference board for STIH415/416 SOCs, it has
2 x UART, 4x USB, 2 x Ethernet, 1 x SATA, 1 x PCIe, and 1GB RAM.
This patch add initial support to b2000 with STiH415/416 with UART2 as
console and a heard beat LED.
Signed-off
Thanks for the comments.
On 25/06/13 14:17, Thomas Gleixner wrote:
On Tue, 25 Jun 2013, Srinivas KANDAGATLA wrote:
If its not too late can this patch be considered for 3.11 via clocksource
tree?
Sure. No worry, though I noticed a little detail when reading through it
again. See below
On 25/06/13 21:47, Olof Johansson wrote:
On Tue, Jun 25, 2013 at 1:30 PM, Olof Johansson o...@lixom.net wrote:
On Tue, Jun 25, 2013 at 12:13:42PM +0100, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch-set adds basic support for STMicroelectronics STi
Thanks for your comments,
On 25/06/13 22:14, Sören Brinkmann wrote:
+Example:
+
+ timer@2c000600 {
+ compatible = arm,cortex-a9-global-timer;
+ reg = 0x2c000600 0x20;
+ interrupts = 1 13 0xf01;
+ };
Isn't a 'clocks' entry missing here?
Yep, I will add it
Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Rob Herring robherri...@gmail.com
CC: Linus Walleij linus.wall...@linaro.org
CC: Will Deacon will.dea
On 26/06/13 14:24, Daniel Lezcano wrote:
If its not too late can this patch be considered for 3.11 via clocksource
tree?
This patch has no build dependencies.
I took it in my tree but it is too late for a 3.11, sorry.
Thanks Daniel.
Thanks
-- Daniel
--
To unsubscribe from this
Hi Mark,
We have pretty much completed reworking the patch-set we sent recently
for the STiH41x SOC support. We are waiting for your feedback on this patch.
Thanks,
srini
On 28/05/13 15:58, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
It is common
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch moves sirfsoc_of_rstc_init from early_initcall to .init_early
in machine descriptor, doing this way a multi_v7 kernel will not crash
on non-prima2 SOCs.
Without this patch the multi_v7 kernel panics if we boot it on any non
prima2
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch moves all postcore_initcalls to very first calls in
init_machine. This should achieve the same sequencing as done via
postcore_initcalls.
Without this patch a multi_v7 kernel panics if we boot it on any
non prima2 parts with below
From: Srinivas Kandagatla srinivas.kandaga...@st.com
If we try to boot a multi_v7_defconfig kernel on any ARM parts other than
prima2, you will hit kernel panics. This is because some of the code is still
using explicit early_initcall and postcore_initcalls.
Moving these calls to machine
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds Clocksource drivers menu to clocksource drivers.
The reason to add this is because, some of the clocksource Kconfig
options like *SHED_CLK ones are selectable and they appear at random
places in the device drivers menu
On 31/05/13 13:24, Barry Song wrote:
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
hi Sriniva,
i think my arm: prima2: move to generic reset controller driver
framework fixs this too:
http://www.spinics.net/lists/arm-kernel/msg246206.html
I did look at the patch, I think
On 31/05/13 19:40, John Stultz wrote:
And only just now did I notice that there are user-prompts in the
drivers/clocksource/Kconfig.
I suspect the platform support options can safely select the proper
clocksource config options without requiring the user to configure it.
For the most part
Hi Barry,
Thanks for testing,
I think this patch introduced a sequencing issue.
Just re-looking at the code, is there any reason for this to be
init_earlycall? And do a ioremap at that early stage?
Can't we move it to device_init level function sirfsoc_mach_init() at
which it will be safe to do
On 03/06/13 04:51, Barry Song wrote:
did you see this one?
[PATCH v2] arm: prima2: use of_platform_populate instead of
of_platform_bus_probe
http://www.spinics.net/lists/arm-kernel/msg243710.html
Yes, I think this is a nice cleanup for simplest case. But Prima
platforms do much more
On 03/06/13 11:07, Barry Song wrote:
i want to move sirfsoc_of_pwrc_init and sirfsoc_of_pwrc_init to
sirfsoc_pm_init as only suspend entries need them. then the result is
like:
int __init sirfsoc_pm_init(void)
{
+ sirfsoc_of_pwrc_init();
+ sirfsoc_memc_init();
From: Srinivas Kandagatla srinivas.kandaga...@st.com
When I tried booting a stih415 Dual core A9 with multi_v7_defconfig, it
failed to boot. The issues seems to be changing by enabling or disabling
VT8550 platform. Having a quick look at dt_compat list, it seems to miss
a NULL terminator, which
Hi Arnd,
Thankyou for the comments.
On 17/05/13 15:36, Arnd Bergmann wrote:
On Thursday 09 May 2013, Srinivas KANDAGATLA wrote:
On 08/05/13 20:48, Arnd Bergmann wrote:
I agree, my initial approach was having a dedicated driver specific to
ST syscon, however syscon seems to do things very much
On 23/05/13 22:44, Arnd Bergmann wrote:
Thankyou Arnd for extending this discussion.
On Monday 20 May 2013, Srinivas KANDAGATLA wrote:
On 17/05/13 15:36, Arnd Bergmann wrote:
On the other hand using device trees to describe the HW
configuration(sysconfs) made more sense and got rid of SOC
From: Srinivas Kandagatla srinivas.kandaga...@st.com
It is common to access regmap registers at bit level, using
regmap_update_bits or regmap_read functions, however the end user has to
take care of a mask or shifting. This becomes overhead when such use
cases are high. Having a common function
On 31/10/13 15:38, Mark Brown wrote:
On Thu, Oct 31, 2013 at 11:54:01AM +, srinivas.kandaga...@st.com wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch uses the new BITS_MASK macro for generating mask for multiple
bits.
Acked-by: Mark Brown broo...@linaro.org
On 28/10/13 15:02, Maxime Coquelin wrote:
6 IMHO, the compatible string should be vendor,IP-name-IP-version
rather than first SoC.
I agree.
In this case, we add support to revision 4 of SSC IP.
Its not the revision its name of the new IP which is SSC4. However this
driver is also compatible
.../devicetree/bindings/media/remote-control.txt | 31
1 files changed, 31 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/media/remote-control.txt
diff --git a/Documentation/devicetree/bindings/media/remote-control.txt
-of-tree kernel.
http://git.stlinux.com/?p=stm/linux-stm.git;a=blob;f=drivers/stm/sysconf.c
Any suggestions?
thanks,
srini
On 09/05/13 10:51, Mark Brown wrote:
On Wed, May 08, 2013 at 06:42:04PM +0100, Srinivas KANDAGATLA wrote:
Fix your mailer to word wrap within paragraphs.
Ultimately
Hi Mark,
On 12/05/13 15:59, Mark Brown wrote:
On Wed, May 08, 2013 at 11:20:09AM +0100, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
If we dump syscon regmap registers via debugfs you will notice that the
dump contains lot of values.
Sorry, can
From: Srinivas Kandagatla srinivas.kandaga...@st.com
regmap_debugfs_get_dump_start should return the offset of the register
it should start reading from, However in the current code at one point
the code does not return correct register offset.
With this patch all the returns from this function
-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
Cc: Srinivas Kandagatla srinivas.kandaga...@st.com
Cc: Stuart Menefy stuart.men...@st.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: ker...@stlinux.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux
On 04/07/13 00:04, David Miller wrote:
You are going to have to fix up the following build warnings and resubmit:
CC [M] drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.o
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c: In function
‘stmmac_mdio_reset’:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds dt support to dwmac version 3.610 and 3.710 these
versions are integrated in STiH415 and STiH416 ARM A9 SOCs.
To support these IP version, some of the device tree properties are
extended.
Signed-off-by: Srinivas Kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds phy reset callback support for stmmac driver via device
trees. It adds three new properties to gmac device tree bindings to
define the reset signal via gpio.
With this patch users can conveniently pass reset gpio number
From: Srinivas Kandagatla srinivas.kandaga...@st.com
Hi Peppe/Dave,
Thankyou for the comments on v1 patches.
This patch series adds support to new gmac versions 3.6.10 and 3.710, these
versions of IP are integrated into ST STiH415/STiH416 SOCs.
This patchset also adds phy reset capablity
From: Srinivas Kandagatla srinivas.kandaga...@st.com
In some DT use-cases platform data might be already allocated and passed
via AUXDATA. These are the cases where machine level code populates few
callbacks in the platform data.
This patch adds check and reuses platform_data if its valid
From: Srinivas Kandagatla srinivas.kandaga...@st.com
Some of the ARM_ERRATA selection is not done in the initial SOC support
patches. This patch selects 2 new ARM_ERRATA's and removes one which was
actually fixed.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
arch/arm/mach
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch fixes a bug in pinctrl setup of serial2 device, Some of the
pins in the pinctrl node of serial2 do not belong to that
pin-controller. This patch divides them in the pins into there
respective pin controller nodes.
Without this patch
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to STiH416 SOC, which has two ethernet
snps,dwmac controllers version 3.710. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch series fixes 2 configuration issues and adds ethernet support to
STiH415, STiH416 based B2000, B2020 boards.
With this patchset B2000 and B2020 can have basic ethernet support in
MII and RGMII modes.
Thanks,
srini
Srinivas
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to STiH415 SOC, which has two ethernet
snps,dwmac controllers version 3.610. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas
Thanks Arnd,
On 09/07/13 00:18, Arnd Bergmann wrote:
On Monday 08 July 2013, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch series fixes 2 configuration issues and adds ethernet support to
STiH415, STiH416 based B2000, B2020 boards.
Hi Srini
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