Hi Rob,
On 10/31/2016 12:36 AM, Rob Herring wrote:
On Thu, Oct 27, 2016 at 03:00:23PM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Add the Arria10 DevKit System Resource Chip register and state
monitoring module to the MFD.
Signed-off-by: Thor Thayer
---
Note: This needs
Hi Lee,
On 10/31/2016 03:02 AM, Lee Jones wrote:
On Thu, 27 Oct 2016, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Add the Altera Arria10 DevKit System Resource Monitor functionality
to the MFD device.
Signed-off-by: Thor Thayer
---
v2 Change from -mon to -monitor for clarity
From: Thor Thayer
Add maintainer for the Altera I2C Controller Driver.
Signed-off-by: Thor Thayer
---
v2-4 No change
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ced1383..c00af95 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -636,6
From: Thor Thayer
Add driver support for the Altera I2C Controller. The I2C
controller is soft IP for use in FPGAs.
Signed-off-by: Thor Thayer
---
v2 Remove altr, from fifo-size to agree with bindings.
Change compatible string to "altr,softip-i2c"
v3 Add version to compati
From: Thor Thayer
This patch series adds the Altera I2C Controller driver for use in FPGAs.
The device tree patch was removed in this version because this I2C is not
the default I2C master.
Thor Thayer (3):
MAINTAINERS: Add Altera I2C Controller Driver
dt-bindings: i2c: Add Altera I2C
From: Thor Thayer
Add the documentation to support the Altera synthesizable
logic I2C Controller in FPGA.
Signed-off-by: Thor Thayer
Acked-by: Rob Herring
---
v2 Change the subject to identify dt-bindings
Add synthesizable logic to description.
Change compatible string to "
ile (reg < reg_end);
+ ret = of_address_to_resource(np, 0, );
+ if (ret)
+ continue;
+
+ total_mem += resource_size();
}
edac_dbg(0, "total_mem 0x%lx\n", total_mem);
return total_mem;
Nice change! Tested
Hi Steffen,
On 06/06/2017 01:40 AM, Steffen Trumtrar wrote:
Hi!
thor.tha...@linux.intel.com writes:
From: Thor Thayer
Add the Altera I2C Controller to the CycloneV SoCFPGA device tree.
Signed-off-by: Thor Thayer
---
v2 Remove altr, from fifo-size.
Rename compatible string to "
From: Thor Thayer
Add the device tree entries needed to support the EMAC AXI
bus settings on the Arria10 SoCFPGA chip.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi
b
From: Thor Thayer
Add the device tree entries needed to support the EMAC AXI
bus settings on the Arria10 SoCFPGA chip.
Signed-off-by: Thor Thayer
---
v2 Add the AXI configuration to the other DW EMACs in the chip.
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 9 +
1 file changed, 9
From: Thor Thayer
Add the Altera Arria10 DevKit sysfs attributes to the
MFD device. Update copyright and email.
Signed-off-by: Thor Thayer
---
drivers/mfd/altera-a10sr.c | 98 --
1 file changed, 95 insertions(+), 3 deletions(-)
diff --git a/drivers
From: Thor Thayer
This series of patches adds the Altera Arria10 Development Kit System
Manager Reset Controller.
Thor Thayer (5):
dt-bindings: mfd: Add Altera Arria10 SR Reset Controller bindings
dt-bindings: Add Arria10 System Resource reset manager offsets
reset: Add Altera Arria10
From: Thor Thayer
Add Arria10 System Resource Manager Reset Controller to MFD.
Signed-off-by: Thor Thayer
---
drivers/mfd/altera-a10sr.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
index 06e1f7f..96e7d2c 100644
--- a/drivers
From: Thor Thayer
Add the Altera Arria10 System Resource Reset Controller to the MFD
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
b/arch/arm/boot/dts
From: Thor Thayer
The Arria10 System Resource reset manager handles the Arria10
peripheral PHYs. This patch adds the offsets for these PHYs.
Signed-off-by: Thor Thayer
---
MAINTAINERS| 1 +
include/dt-bindings/reset/altr,rst-mgr-a10sr.h | 31
From: Thor Thayer
This patch adds the reset controller functionality to the Arria10
System Resource Manager.
Signed-off-by: Thor Thayer
---
MAINTAINERS | 1 +
drivers/reset/Kconfig | 7 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-a10sr.c | 176
From: Thor Thayer
This patch adds documentation for the Altera A10-SR Reset
Controller DT bindings.
Signed-off-by: Thor Thayer
---
Documentation/devicetree/bindings/mfd/altera-a10sr.txt | 11 +++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd
Hi Philipp,
On 02/16/2017 04:30 AM, Philipp Zabel wrote:
Hi Thor,
thank you for the patch. A few comments below:
On Wed, 2017-02-15 at 15:50 -0600, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
This patch adds the reset controller functionality to the Arria10
System Resource Manager
On 02/16/2017 10:12 AM, Dinh Nguyen wrote:
On 02/15/2017 03:50 PM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add the Altera Arria10 System Resource Reset Controller to the MFD
Signed-off-by: Thor Thayer
Nit:
Please have the commit header as "ARM: dts: socfpga:"
From: Thor Thayer
The peripherals EDACs only exist on the Arria10 SoCFPGA. The Cyclone5
initialization has EDAC warnings when the peripherals aren't found
in the device tree. Fix by checking for Arria10 in the init functions.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c | 29
Hi Boris,
On 04/04/2017 04:59 AM, Borislav Petkov wrote:
On Mon, Apr 03, 2017 at 02:01:06PM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
The peripherals EDACs only exist on the Arria10 SoCFPGA. The Cyclone5
initialization has EDAC warnings when the peripherals aren't found
From: Thor Thayer
The peripherals EDACs only exist on the Arria10 SoCFPGA. The Cyclone5
initialization has EDAC warnings when the peripherals aren't found
in the device tree. Fix by checking for Arria10 in the init functions.
Signed-off-by: Thor Thayer
---
v2 Change valid_model() return value
From: Thor Thayer
The peripherals EDACs only exist on the Arria10 SoCFPGA. The Cyclone5
initialization has EDAC warnings when the peripherals aren't found
in the device tree. Fix by checking for Arria10 in the init functions.
Signed-off-by: Thor Thayer
---
v2 Change valid_model() return value
Hi Lee,
On 02/28/2017 08:42 AM, Philipp Zabel wrote:
On Wed, 2017-02-22 at 11:10 -0600, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add Peripheral PHY Reset Controller to the Arria10
Development Kit System Resource Chip's MFD.
Signed-off-by: Thor Thayer
---
v2 Changes to commit
On 03/13/2017 09:42 AM, Philipp Zabel wrote:
On Thu, 2017-03-09 at 10:03 -0600, Thor Thayer wrote:
Hi Lee,
On 02/28/2017 08:42 AM, Philipp Zabel wrote:
On Wed, 2017-02-22 at 11:10 -0600, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add Peripheral PHY Reset Controller to the Arria10
{ .compatible = "altr,socfpga-ocram-ecc",
- .data = (void *)_data },
- { .compatible = "altr,socfpga-a10-ocram-ecc",
- .data = (void *)_ocramecc_data },
+ { .compatible = "altr,socfpga-ocram-ecc", .data = _data },
+ { .compatible = "altr,socfpga-a10-ocram-ecc", .data =
_ocramecc_data },
#endif
{},
};
Acked-by: Thor Thayer
ac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
- panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
- }
- return IRQ_HANDLED;
-}
-
static irqreturn_t altr_edac_a10_irq_handler(int irq, void *dev_id)
{
irqreturn_t rc = IRQ_NONE;
Acked-by: Thor Thayer
Hi Boris,
On 04/15/2016 04:46 PM, Borislav Petkov wrote:
On Fri, Apr 15, 2016 at 10:27:54AM -0500, Thor Thayer wrote:
I'll update this patch to only count errors.
... and also think about what that counting is going to bring. If it is
only going to be there to show how many network errors
On 04/18/2016 03:02 PM, Borislav Petkov wrote:
On Mon, Apr 18, 2016 at 09:27:16AM -0500, Thor Thayer wrote:
We're still getting the single bit correction
By that you mean, you get that by enabling ECC on the FIFO block?
Yes, you are correct. I'd still get the single bit correction
On 04/18/2016 03:06 PM, Borislav Petkov wrote:
On Mon, Apr 18, 2016 at 10:02:27PM +0200, Borislav Petkov wrote:
the number of uncorrectable errors is useful from a system point of
view.
I forgot: so altr_edac_a10_ecc_irq() panics on uncorrectable errors. Do we want
to do that even for UEs
Hi Boris.
On 02/08/2016 05:39 AM, Borislav Petkov wrote:
On Wed, Jan 27, 2016 at 10:13:20AM -0600, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory
On 04/15/2016 04:40 AM, Mauro Carvalho Chehab wrote:
Em Thu, 14 Apr 2016 09:35:01 -0500
Rob Herring escreveu:
On Tue, Apr 12, 2016 at 05:12:55PM -0500, ttha...@opensource.altera.com wrote:
This patch set adds the memory initialization functions for Altera's
Arria10 peripherals, the first
Hi,
On 03/31/2016 01:48 PM, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Enable ECC for Arria10 On-Chip RAM on machine startup. The ECC has to
be enabled and memory initialized before data is stored in memory
otherwise the ECC will fail on reads.
Signed-off-by: Thor Thayer
---
v2
Hi Dinh,
On 03/30/2016 12:11 PM, Dinh Nguyen wrote:
On Wed, 30 Mar 2016, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Enable ECC for Arria10 On-Chip RAM on machine startup. The ECC has to be
enabled before data is stored in memory otherwise the ECC will fail
on reads.
Signed-off
Hi Boris,
On 04/05/2016 12:31 AM, Borislav Petkov wrote:
On Tue, Apr 05, 2016 at 12:25:33AM -0500, Thor Thayer wrote:
I realize that I'm not calling iounmap(ecc_block_base) and I'll fix that in
the next revision with a goto.
I'm assuming nothing else changes. Because I've applied 1-4 already
On 07/27/2016 12:10 PM, Borislav Petkov wrote:
On Thu, Jul 14, 2016 at 11:06:43AM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Add Altera Arria10 NAND FIFO memory EDAC support.
Signed-off-by: Thor Thayer
---
drivers/edac/Kconfig |7 +++
drivers/edac
altr_a10sr_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
Reviewed-by: Thor Thayer
On 08/08/2016 08:36 AM, Borislav Petkov wrote:
On Tue, Aug 02, 2016 at 10:56:20AM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Add Altera Arria10 SD-MMC FIFO memory EDAC support. The SD-MMC
is a dual port RAM implementation which is different than any
of the other
Hi Rob,
On 06/21/2016 08:33 AM, Rob Herring wrote:
On Mon, Jun 20, 2016 at 09:50:49AM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2
On 06/21/2016 10:48 AM, Rob Herring wrote:
On Tue, Jun 21, 2016 at 9:46 AM, Thor Thayer
wrote:
Hi Rob,
On 06/21/2016 08:33 AM, Rob Herring wrote:
On Mon, Jun 20, 2016 at 09:50:49AM -0500, ttha...@opensource.altera.com
wrote:
From: Thor Thayer
Add the device tree bindings needed
Hi Boris,
On 03/04/2016 04:38 AM, Borislav Petkov wrote:
On Tue, Mar 01, 2016 at 10:38:19AM -0600, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Addition of the Arria10 L2 Cache ECC handling. The major
changes affect the L2 ECC registers not being grouped
together. The Arria10 IRQ
Hi Boris,
On 03/07/2016 01:43 PM, ttha...@opensource.altera.com wrote:
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, the IRQ
status needs to be determined because the IRQs are shared.
The IRQ status register is read to determine if the IRQ
was for this ECC peripheral
Hi Dinh,
On 03/08/2016 08:50 AM, Dinh Nguyen wrote:
On 03/07/2016 01:43 PM, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 Match register value (l2-ecc
On 01/04/2016 03:07 PM, Borislav Petkov wrote:
On Mon, Jan 04, 2016 at 02:55:43PM -0600, Dinh Nguyen wrote:
Right. So for us, if we build in SDRAM ECC unconditionally, there is a
requirement with the bootloader to turn on ECC and scrub the memory.
Huh, how does a built-in piece of code
On 01/04/2016 04:01 PM, Borislav Petkov wrote:
On Mon, Jan 04, 2016 at 03:33:23PM -0600, Thor Thayer wrote:
The decision about ECC or non-ECC SDRAM is made before building the Linux
image and must be matched to the appropriate bootloader (ECC or non-ECC).
If ECC is desired for SDRAM
On 01/05/2016 04:58 AM, Borislav Petkov wrote:
On Mon, Jan 04, 2016 at 05:42:40PM -0600, Thor Thayer wrote:
and then the defines are also used to conditionally include the L2 or OCRAM
ECC functions because everything is in one file.
So?
You don't have to do those funny games
Hi Vladimir,
On 01/22/2016 12:02 AM, Vladimir Zapolskiy wrote:
Hi Thor,
On 21.01.2016 19:34, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory
On 01/22/2016 12:08 PM, Borislav Petkov wrote:
On Fri, Jan 22, 2016 at 06:56:57PM +0200, Vladimir Zapolskiy wrote:
it sounds like the author of the original change is Dinh, but if you agreed
about authorship transfer, then "From: Thor Thayer" statement should be
correct, but in any
On 01/22/2016 08:35 PM, Rob Herring wrote:
On Thu, Jan 21, 2016 at 11:34:26AM -0600, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch
On Wed, 2014-04-23 at 16:54 +0200, Borislav Petkov wrote:
> On Tue, Apr 15, 2014 at 06:30:10PM -0500, ttha...@altera.com wrote:
> > From: Thor Thayer
> >
> > Added EDAC support for reporting ECC errors of CycloneV
> > and ArriaV SDRAM controller.
> > - The SD
On Tue, 2014-04-08 at 12:08 +0200, Borislav Petkov wrote:
> On Mon, Apr 07, 2014 at 04:54:09PM -0500, ttha...@altera.com wrote:
> > From: Thor Thayer
> >
> > Added EDAC support for reporting ECC errors of CycloneV
> > and ArriaV SDRAM controller.
> > - The SD
On Tue, 2014-04-08 at 14:45 +0200, Steffen Trumtrar wrote:
> On Tue, Apr 08, 2014 at 11:45:25AM +0100, Mark Rutland wrote:
> > On Mon, Apr 07, 2014 at 10:54:09PM +0100, ttha...@altera.com wrote:
> > > From: Thor Thayer
> > >
> > > Added EDAC support
On Tue, 2014-04-08 at 15:38 +0200, Steffen Trumtrar wrote:
> Hi!
>
> On Mon, Apr 07, 2014 at 04:54:07PM -0500, ttha...@altera.com wrote:
> > From: Thor Thayer
> >
> > Addition of the Altera SDRAM controller bindings and device
> > tree changes to t
On Tue, 2014-04-08 at 18:22 +0200, Borislav Petkov wrote:
> On Tue, Apr 08, 2014 at 05:10:54PM +0100, Mark Rutland wrote:
> > Typically the bindings would go with the driver via the appropriate
> > subsystem maintainer. That way we don't get bindings without drivers
> > or vice-versa if there's a
On Tue, 2014-04-08 at 13:52 -0500, Rob Herring wrote:
> On Tue, Apr 8, 2014 at 11:02 AM, delicious quinoa
> wrote:
> > On Tue, Apr 8, 2014 at 9:33 AM, Steffen Trumtrar
> > wrote:
> >> On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote:
> >>> On
On Tue, 2014-04-08 at 13:52 -0500, Rob Herring wrote:
> On Tue, Apr 8, 2014 at 11:02 AM, delicious quinoa
> wrote:
> > On Tue, Apr 8, 2014 at 9:33 AM, Steffen Trumtrar
> > wrote:
> >> On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote:
> >>> On
On Tue, 2014-04-08 at 13:52 -0500, Rob Herring wrote:
> On Tue, Apr 8, 2014 at 11:02 AM, delicious quinoa
> wrote:
> > On Tue, Apr 8, 2014 at 9:33 AM, Steffen Trumtrar
> > wrote:
> >> On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote:
> >>> On
On Tue, 2014-04-01 at 07:33 +0200, Steffen Trumtrar wrote:
On Mon, Mar 31, 2014 at 05:07:07PM -0500, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
snip
Can't we get rid of all these global pointers instead of adding to them?
Yes. I will remove this file from
On Tue, 2014-04-01 at 07:28 +0200, Steffen Trumtrar wrote:
Hi!
On Mon, Mar 31, 2014 at 05:07:06PM -0500, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.
snip
diff
On Wed, 2014-04-02 at 00:19 +0200, Steffen Trumtrar wrote:
Hi!
On Tue, Apr 01, 2014 at 03:11:41PM -0500, Thor Thayer - Sendmail wrote:
On Tue, 2014-04-01 at 07:28 +0200, Steffen Trumtrar wrote:
Hi!
On Mon, Mar 31, 2014 at 05:07:06PM -0500, ttha...@altera.com wrote:
From: Thor
On Tue, 2014-04-01 at 07:33 +0200, Steffen Trumtrar wrote:
> On Mon, Mar 31, 2014 at 05:07:07PM -0500, ttha...@altera.com wrote:
> > From: Thor Thayer
> >
> >
>
> Can't we get rid of all these global pointers instead of adding to them?
Yes. I will remove this
On Tue, 2014-04-01 at 07:28 +0200, Steffen Trumtrar wrote:
> Hi!
>
> On Mon, Mar 31, 2014 at 05:07:06PM -0500, ttha...@altera.com wrote:
> > From: Thor Thayer
> >
> > Addition of the Altera SDRAM controller bindings and device
> > tree changes to the Altera S
On Wed, 2014-04-02 at 00:19 +0200, Steffen Trumtrar wrote:
> Hi!
>
> On Tue, Apr 01, 2014 at 03:11:41PM -0500, Thor Thayer - Sendmail wrote:
> > On Tue, 2014-04-01 at 07:28 +0200, Steffen Trumtrar wrote:
> > > Hi!
> > >
> > > On Mon, Mar 31, 2014 at
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