On Fri, 2013-08-09 at 00:12 +0200, Rafael J. Wysocki wrote:
On Thursday, August 08, 2013 11:15:20 AM Toshi Kani wrote:
On Fri, 2013-08-02 at 18:04 -0600, Toshi Kani wrote:
On Sat, 2013-08-03 at 01:43 +0200, Rafael J. Wysocki wrote:
On Friday, August 02, 2013 03:46:15 PM Toshi Kani wrote
On Fri, 2013-08-09 at 01:14 +0200, Rafael J. Wysocki wrote:
On Thursday, August 08, 2013 04:50:42 PM Toshi Kani wrote:
On Fri, 2013-08-09 at 00:12 +0200, Rafael J. Wysocki wrote:
On Thursday, August 08, 2013 11:15:20 AM Toshi Kani wrote:
On Fri, 2013-08-02 at 18:04 -0600, Toshi Kani
On Fri, 2013-08-09 at 13:52 +0800, Tang Chen wrote:
On 08/09/2013 12:47 AM, Toshi Kani wrote:
add_memory() and remove_memory() can only handle a memory range aligned
with section. There are problems when an unaligned range is added and
then deleted as follows:
- add_memory
On Fri, 2013-08-09 at 15:28 +0800, Tang Chen wrote:
On 08/07/2013 12:56 AM, Toshi Kani wrote:
On Tue, 2013-08-06 at 19:11 +0900, Yasuaki Ishimatsu wrote:
try_offline_node() checks that all cpus related with removed node have been
removed by using cpu_present_bits. If all cpus related
On Sat, 2013-08-10 at 01:29 +0200, Rafael J. Wysocki wrote:
On Friday, August 09, 2013 04:16:56 PM Toshi Kani wrote:
On Fri, 2013-08-09 at 15:28 +0800, Tang Chen wrote:
On 08/07/2013 12:56 AM, Toshi Kani wrote:
On Tue, 2013-08-06 at 19:11 +0900, Yasuaki Ishimatsu wrote
,
add_memory() fails with -EINVAL when a given range is unaligned, and
does not add such memory range. This prevents remove_memory() to be
called with an unaligned range as well. Note that remove_memory() has
to use BUG_ON() since this function cannot fail.
Signed-off-by: Toshi Kani toshi.k...@hp.com
On Mon, 2013-08-12 at 07:37 +0800, Wanpeng Li wrote:
On Sat, Aug 10, 2013 at 01:17:32PM -0600, Toshi Kani wrote:
add_memory() and remove_memory() can only handle a memory range aligned
with section. There are problems when an unaligned range is added and
then deleted as follows
-by: Toshi Kani toshi.k...@hp.com
---
drivers/acpi/acpi_processor.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/acpi/acpi_processor.c b/drivers/acpi/acpi_processor.c
index 5a74a9c..f29e06e 100644
--- a/drivers/acpi/acpi_processor.c
+++ b/drivers/acpi
updates the cpu maps without
holding the the writer lock. This patchset fixes this problem.
---
The patchset is based on linux-next of the pm tree.
---
Toshi Kani (2):
CPU hotplug: Export cpu_hotplug_begin() interface
ACPI: Acquire writer lock to update cpu maps
---
drivers/acpi
.
cpu_present_mask is updated by the ACPI processor handler. Therefore,
this patch changes the interfaces to global, and exports them in cpu.h.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
include/linux/cpu.h |4
kernel/cpu.c|9 +++--
2 files changed, 7 insertions(+), 6
() and remove_memory() that
lock_device_hotplug() is required.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
mm/memory_hotplug.c | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
index ca1dd3a..0b4b0f7 100644
On Sun, 2013-08-11 at 22:42 +0200, Rafael J. Wysocki wrote:
On Friday, August 09, 2013 08:11:19 PM Toshi Kani wrote:
On Sat, 2013-08-10 at 01:29 +0200, Rafael J. Wysocki wrote:
On Friday, August 09, 2013 04:16:56 PM Toshi Kani wrote:
On Fri, 2013-08-09 at 15:28 +0800, Tang Chen wrote
On Sun, 2013-08-11 at 23:13 +0200, Rafael J. Wysocki wrote:
On Thursday, August 08, 2013 04:50:42 PM Toshi Kani wrote:
On Fri, 2013-08-09 at 00:12 +0200, Rafael J. Wysocki wrote:
On Thursday, August 08, 2013 11:15:20 AM Toshi Kani wrote:
On Fri, 2013-08-02 at 18:04 -0600, Toshi Kani
-by: Rafael J. Wysocki rafael.j.wyso...@intel.com
Acked-by: Toshi Kani toshi.k...@hp.com
---
Hi Greg,
Can you please kindly queue up this one for 3.12?
I've added the Toshi's ACK as he said it looked good to him. :-)
That's fine by me.
-Toshi
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On Tue, 2013-08-13 at 02:43 +0200, Rafael J. Wysocki wrote:
On Monday, August 12, 2013 09:45:52 AM Toshi Kani wrote:
CPU system maps are protected with reader/writer locks. The reader
lock, put_online_cpus(), assures that the maps are not updated while
holding the lock. The writer lock
On Tue, 2013-08-13 at 02:45 +0200, Rafael J. Wysocki wrote:
On Monday, August 12, 2013 02:40:43 PM Toshi Kani wrote:
On Sun, 2013-08-11 at 23:13 +0200, Rafael J. Wysocki wrote:
On Thursday, August 08, 2013 04:50:42 PM Toshi Kani wrote:
On Fri, 2013-08-09 at 00:12 +0200, Rafael J. Wysocki
Mammedov imamm...@redhat.com
Hi Igor,
Sorry for long delay... Can you please combine patch 1/5 and 2/5? When
a CPU is marked as present, its APIC ID must be valid. So, it does not
make sense to separate patch 1/5 and 2/5. With that change:
Acked-by: Toshi Kani toshi.k...@hp.com
Thanks
On Mon, 2014-04-14 at 17:11 +0200, Igor Mammedov wrote:
acpi_processor_add() assumes that present at boot CPUs
are always onlined, it is not so if a CPU failed to become
onlined. As result acpi_processor_add() will mark such CPU
device as onlined in sysfs and following attempts to
) to wakeup CPU#%u\n, err, cpu);
return -EIO;
}
Looks good.
Acked-by: Toshi Kani toshi.k...@hp.com
I will review patch 5/5 later (probably tomorrow).
Thanks,
-Toshi
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On Mon, 2014-04-14 at 17:11 +0200, Igor Mammedov wrote:
Hang is observed on virtual machines during CPU hotplug,
especially in big guests with many CPUs. (It reproducible
more often if host is over-committed).
It happens because master CPU gives up waiting on
secondary CPU and allows it to
On Fri, 2014-05-02 at 10:21 +0200, Igor Mammedov wrote:
On Thu, 01 May 2014 17:11:56 -0600
Toshi Kani toshi.k...@hp.com wrote:
:
When 10s passed, the master could set a new flag, ex.
cpu_callout_error_mask, which wait_for_master_cpu() checks and call
play_dead() when it is set
On Fri, 2014-05-02 at 13:32 +0200, Igor Mammedov wrote:
On Wed, 30 Apr 2014 15:25:51 -0600
Toshi Kani toshi.k...@hp.com wrote:
On Mon, 2014-04-14 at 17:11 +0200, Igor Mammedov wrote:
acpi_processor_add() assumes that present at boot CPUs
are always onlined, it is not so if a CPU failed
.
Acked-by: Toshi Kani toshi.k...@hp.com
-Toshi
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Please read the FAQ at http://www.tux.org/lkml/
changed, 51 insertions(+), 79 deletions(-)
For the changes under arch/x86/kernel (I'm not familiar with Xen):
Acked-by: Toshi Kani toshi.k...@hp.com
Thanks,
-Toshi
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On Tue, 2014-06-24 at 09:31 +0900, Yasuaki Ishimatsu wrote:
(2014/06/21 3:30), Toshi Kani wrote:
On Wed, 2014-06-18 at 15:38 +0900, Yasuaki Ishimatsu wrote:
:
@@ -186,7 +186,12 @@ void sync_global_pgds(unsigned long start, unsigned
long end)
const pgd_t *pgd_ref
synchronize PGD to PGD entries
of all processes MM since synchronized range of memory [start, end]
is wrong.
Unfortunately the start argument is modified in remove_pagetable().
So this patch fixes the issue.
Signed-off-by: Yasuaki Ishimatsu isimatu.yasu...@jp.fujitsu.com
Acked-by: Toshi
On Wed, 2014-06-18 at 15:38 +0900, Yasuaki Ishimatsu wrote:
:
@@ -186,7 +186,12 @@ void sync_global_pgds(unsigned long start, unsigned long
end)
const pgd_t *pgd_ref = pgd_offset_k(address);
struct page *page;
- if (pgd_none(*pgd_ref))
+
On Wed, 2014-07-16 at 15:28 -0600, Toshi Kani wrote:
On Tue, 2014-07-15 at 20:40 -0400, Konrad Rzeszutek Wilk wrote:
On July 15, 2014 5:23:24 PM EDT, Toshi Kani toshi.k...@hp.com wrote:
On Tue, 2014-07-15 at 13:09 -0700, H. Peter Anvin wrote:
On 07/15/2014 12:34 PM, Toshi Kani wrote
On Mon, 2014-07-21 at 09:47 -0700, H. Peter Anvin wrote:
On 07/21/2014 09:31 AM, Toshi Kani wrote:
Do you have any comments / suggestions for this approach?
Approach to what, specifically?
Keep in mind the PAT bit is different for large pages. This needs to be
dealt with.
You
On Mon, 2014-07-21 at 09:47 -0700, H. Peter Anvin wrote:
On 07/21/2014 09:31 AM, Toshi Kani wrote:
Do you have any comments / suggestions for this approach?
Approach to what, specifically?
Keep in mind the PAT bit is different for large pages. This needs to be
dealt with.
You
On Mon, 2014-07-21 at 10:32 -0700, H. Peter Anvin wrote:
On 07/21/2014 10:16 AM, Toshi Kani wrote:
:
I would also like a systematic way to deal with the fact
that Xen (sigh) is stuck with a separate mapping system.
I guess Linux could adopt the Xen mappings if that makes it easier
On Mon, 2014-07-21 at 14:33 -0400, Konrad Rzeszutek Wilk wrote:
On Mon, Jul 21, 2014 at 10:32:34AM -0700, H. Peter Anvin wrote:
On 07/21/2014 10:16 AM, Toshi Kani wrote:
:
I would also like a systematic way to deal with the fact
that Xen (sigh) is stuck with a separate mapping system
the term used
sounds some state of CPU, which is not the case here. How about
cpu_number_mask? This is more specific and avoids such confusion.
Otherwise, the change looks good.
Reviewed-by: Toshi Kani toshi.k...@hp.com
Thanks,
-Toshi
+
+/*
* Get the LAPIC version
*/
^^
ps. I had
the term used
sounds representing some state of CPU, which is not the case here.
How about cpu_number_mask? This would be more specific, and avoid such
confusion.
Otherwise, the change looks good to me.
Reviewed-by: Toshi Kani toshi.k...@hp.com
Thanks,
-Toshi
+
+/*
* Get the LAPIC version
applies on top of the Linus's tree, 3.16.0-rc5.
---
Toshi Kani (11):
1/11: x86, mm, pat: Redefine _PAGE_CACHE_UC as UC_MINUS
2/11: x86, mm, pat: Define _PAGE_CACHE_WT for PA3/7 of PAT
3/11: x86, mm, pat: Change reserve_memtype() to handle WT type
4/11: x86, mm, asm-gen: Add ioremap_wt
This patch cleans up the PWT PCD bit manipulation in fbdev,
and uses _PAGE_CACHE_type macros, instead. This keeps the
fbdev code independent from the PAT slot assignment.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/fb.h |3 ++-
drivers/video/fbdev
This patch introduces ioremap_wt() for creating WT maps on x86.
It follows the same model as ioremap_wc() for multi-architecture
support. ARCH_HAS_IOREMAP_WT is defined in x86's io.h to indicate
that ioremap_wt() is implemented on x86.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86
This patch cleans up the PWT PCD bit manipulation for the kernel
memory types in Xen, and uses _PAGE_CACHE_type macros, instead.
This keeps the Xen code independent from the PAT slot assignment.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/xen/enlighten.c |2 +-
arch/x86/xen
This patch cleans up the PCD bit manipulation in EFI virtual mapping,
and uses _PAGE_CACHE_type macros, instead. This keeps the efi code
independent from the PAT slot assignment.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/platform/efi/efi_64.c |4 ++--
1 file changed, 2
value.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/pgtable.h |2 +-
arch/x86/include/asm/pgtable_types.h |4
arch/x86/mm/pat.c|4 ++--
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/pgtable.h b
This patch defines _PAGE_CACHE_WT and its relevant macros, which
now use the PA3/7 slot in the PAT MSR. pat_init() is also changed
to set the WT memory type to the PA3/7 slot in the PAT MSR.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/pgtable_types.h |5 +
arch
is changed to
set the PCD PWT bits in order to avoid any change. They do not
support PAT and MTRRs.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/pgtable_types.h | 10 +-
arch/x86/mm/ioremap.c| 14 +-
arch/x86/mm/pat.c
() uses the page flags
limited to three memory types, WB, WC and UC.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/cacheflush.h |2 ++
arch/x86/mm/pat.c | 12 +---
arch/x86/mm/pat_internal.h|1 +
3 files changed, 12 insertions(+), 3
This patch introduces set_memory_wt() and set_memory_array_wt()
for setting a given range of the memory attribute to WT.
Note that reserve_memtype() only supports tracking of WT for
non-RAM ranges at this point.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/cacheflush.h
This patch introduces pgprot_writethrough() for setting the WT type
for a given pgprot_t.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/pgtable_types.h |3 +++
arch/x86/mm/pat.c|9 +
include/asm-generic/pgtable.h|4
3
change_page_attr_set_clr() directly for all memory types, and keep
them independent from the PAT slot assignment.
It also introduces pgprot_set_cache() for setting a specified page
cache value to a pgprot_t value.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/mm/pageattr.c | 36
On Tue, 2014-07-15 at 13:09 -0700, H. Peter Anvin wrote:
On 07/15/2014 12:34 PM, Toshi Kani wrote:
This RFC patchset is aimed to seek comments/suggestions for the design
and changes to support of Write-Through (WT) mapping. The study below
shows that using WT mapping may be useful for non
On Tue, 2014-07-15 at 12:56 -0700, Andy Lutomirski wrote:
On Tue, Jul 15, 2014 at 12:34 PM, Toshi Kani toshi.k...@hp.com wrote:
This patch changes reserve_memtype() to handle the new WT type.
When (!pat_enabled new_type), it continues to set either WB
or UC- to *new_type. When pat_enabled
.
I will send userspace patches as well.
Limitation is I only write support for x86_64, test on below machines:
Lenovo thinkpad t420
Dell inspiron 14 - 3421
HP Z420 workstation
Qemu + OVMF
Tested on an HP 60-way UEFI platform (proto). For the series:
Tested-by: Toshi Kani toshi.k...@hp.com
On Sat, 2013-12-21 at 17:35 +, Matt Fleming wrote:
On Fri, 20 Dec, at 06:02:10PM, Dave Young wrote:
Here is the V7 patchset for supporting kexec kernel efi runtime.
Per pervious discussion I pass the 1st kernel efi runtime mapping
via setup_data to 2nd kernel. Besides of the runtime
On Mon, 2013-12-23 at 07:36 +, Matt Fleming wrote:
On Sun, 22 Dec, at 02:27:01PM, Toshi Kani wrote:
The kexec branch is missing the following change, which is required for
fast reboot with multi-cpus.
commit 279f1df915c3a6ed3075d98a849705bf53851f99
Author: Vivek Goyal vgo
On Wed, 2014-02-05 at 22:49 +0100, Rafael J. Wysocki wrote:
On Wednesday, February 05, 2014 08:52:49 AM Toshi Kani wrote:
On Wed, 2014-02-05 at 11:05 +, Rafael J. Wysocki wrote:
On Tuesday, February 04, 2014 05:48:28 PM Toshi Kani wrote:
When an eject request is sent to an ejected
...@jp.fujitsu.com
Signed-off-by: Wanpeng Li wanpeng...@linux.intel.com
The change looks good to me.
Reviewed-by: Toshi Kani toshi.k...@hp.com
Thanks,
-Toshi
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On Tue, 2014-07-15 at 16:36 -0700, Andy Lutomirski wrote:
On Tue, Jul 15, 2014 at 4:10 PM, Toshi Kani toshi.k...@hp.com wrote:
On Tue, 2014-07-15 at 12:56 -0700, Andy Lutomirski wrote:
On Tue, Jul 15, 2014 at 12:34 PM, Toshi Kani toshi.k...@hp.com wrote:
This patch changes reserve_memtype
On Tue, 2014-07-15 at 17:28 -0700, Andy Lutomirski wrote:
On Tue, Jul 15, 2014 at 4:53 PM, Toshi Kani toshi.k...@hp.com wrote:
:
In this patch, I left using reserve_ram_pages_type() since I do not see
much reason to use WT for RAM, either.
I hereby predict that someone, some day
On Tue, 2014-07-15 at 20:40 -0400, Konrad Rzeszutek Wilk wrote:
On July 15, 2014 5:23:24 PM EDT, Toshi Kani toshi.k...@hp.com wrote:
On Tue, 2014-07-15 at 13:09 -0700, H. Peter Anvin wrote:
On 07/15/2014 12:34 PM, Toshi Kani wrote:
:
I have given this piece of feedback at least three
On Fri, 2014-08-22 at 15:16 -0700, Andrew Morton wrote:
On Mon, 18 Aug 2014 11:25:36 +0800 Zhang Zhen zhenzhang.zh...@huawei.com
wrote:
On 2014/8/16 5:37, Toshi Kani wrote:
On Wed, 2014-08-13 at 12:10 +0800, Zhang Zhen wrote:
Currently memory-hotplug has two limits:
1
On Tue, 2014-08-26 at 08:16 +0200, Juergen Gross wrote:
At the moment there are a lot of places that handle setting or getting
the page cache mode by treating the pgprot bits equal to the cache mode.
This is only true because there are a lot of assumptions about the setup
of the PAT MSR.
it is possible to use the same kernel with different PAT
configurations, e.g. supporting Xen.
Signed-off-by: Juergen Gross jgr...@suse.com
Reviewed-by: Toshi Kani toshi.k...@hp.com
Thanks,
-Toshi
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On Tue, 2014-08-26 at 11:48 -0700, Andy Lutomirski wrote:
On 08/25/2014 11:16 PM, Juergen Gross wrote:
The x86 architecture offers via the PAT (Page Attribute Table) a way to
specify different caching modes in page table entries. The PAT MSR contains
8 entries each specifying one of 6
On Tue, 2014-08-19 at 15:25 +0200, jgr...@suse.com wrote:
From: Juergen Gross jgr...@suse.com
At the moment there are a lot of places that handle setting or getting
the page cache mode by treating the pgprot bits equal to the cache mode.
This is only true because there are a lot of
On Tue, 2014-08-19 at 15:25 +0200, jgr...@suse.com wrote:
From: Juergen Gross jgr...@suse.com
At the moment there are a lot of places that handle setting or getting
the page cache mode by treating the pgprot bits equal to the cache mode.
This is only true because there are a lot of
On Fri, 2014-08-22 at 10:24 +0100, Jan Beulich wrote:
On 21.08.14 at 11:30, jgr...@suse.com wrote:
On 08/20/2014 09:26 PM, Toshi Kani wrote:
On Tue, 2014-08-19 at 15:25 +0200, jgr...@suse.com wrote:
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -27,6 +27,35 @@
#include
On Wed, 2014-08-13 at 12:10 +0800, Zhang Zhen wrote:
Currently memory-hotplug has two limits:
1. If the memory block is in ZONE_NORMAL, you can change it to
ZONE_MOVABLE, but this memory block must be adjacent to ZONE_MOVABLE.
2. If the memory block is in ZONE_MOVABLE, you can change it to
regarding cache mode
Changes in V3:
- corrected two minor nits (UC_MINUS, again) detected by Toshi Kani
Changes in V2:
- simplified handling of PAT MSR write under Xen as suggested by David
Vrabel
- removed resetting of pat_enabled under Xen
- two small corrections requested by Toshi
zhenzhang.zh...@huawei.com
CC: Wang Nan wangn...@huawei.com
CC: Tang Chen tangc...@cn.fujitsu.com
CC: Toshi Kani toshi.k...@hp.com
CC: Dave Hansen dave.han...@intel.com
CC: David Rientjes rient...@google.com
---
mm/memory_hotplug.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
allocator
in try_offline_node().
Signed-off-by: Yasuaki Ishimatsu isimatu.yasu...@jp.fujitsu.com
Thanks for the update. It looks good.
Reviewed-by: Toshi Kani toshi.k...@hp.com
-Toshi
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of the PAT management.
https://lkml.org/lkml/2014/8/26/61
All new/modified interfaces have been tested.
---
Toshi Kani (5):
1/5 x86, mm, pat: Set WT to PA4 slot of PAT MSR
2/5 x86, mm, pat: Change reserve_memtype() to handle WT
3/5 x86, mm, asm-gen: Add ioremap_wt() for WT
4/5 x86, mm: Add
, model 0x5
Pentium 3, E27 family 0x6, model 0x7
Pentium M, Y26 family 0x6, model 0x9
Pentium 4, N46 family 0xf, model 0x0
For these affected processors, _PAGE_CACHE_MODE_WT is redirected to UC-
per the default setup in __cachemode2pte_tbl[].
Signed-off-by: Toshi Kani toshi.k...@hp.com
This patch adds ioremap_wt() for creating WT mapping on x86.
It follows the same model as ioremap_wc() for multi-architecture
support. ARCH_HAS_IOREMAP_WT is defined in the x86 version of
io.h to indicate that ioremap_wt() is implemented on x86.
Signed-off-by: Toshi Kani toshi.k...@hp.com
reserve_ram_pages_type() uses the page flags limited to three memory
types, WB, WC and UC.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/cacheflush.h |4
arch/x86/mm/pat.c | 16 +---
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git
This patch adds pgprot_writethrough() for setting WT to a given
pgprot_t.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/pgtable_types.h |3 +++
arch/x86/mm/pat.c| 10 ++
include/asm-generic/pgtable.h|4
3 files changed, 17
This patch adds set_memory_wt(), set_memory_array_wt(), and
set_pages_array_wt() for setting range(s) of memory to WT.
Note that reserve_memtype() only supports WT for non-RAM ranges
at this point.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/cacheflush.h |6
On Thu, 2014-09-04 at 11:57 -0700, Andy Lutomirski wrote:
On Thu, Sep 4, 2014 at 11:35 AM, Toshi Kani toshi.k...@hp.com wrote:
This patch adds set_memory_wt(), set_memory_array_wt(), and
set_pages_array_wt() for setting range(s) of memory to WT.
Possibly dumb question: I thought
On Thu, 2014-09-04 at 12:14 -0700, Andy Lutomirski wrote:
On Thu, Sep 4, 2014 at 11:57 AM, Toshi Kani toshi.k...@hp.com wrote:
On Thu, 2014-09-04 at 11:57 -0700, Andy Lutomirski wrote:
On Thu, Sep 4, 2014 at 11:35 AM, Toshi Kani toshi.k...@hp.com wrote:
This patch adds set_memory_wt
On Thu, 2014-09-04 at 17:11 -0300, Henrique de Moraes Holschuh wrote:
On Thu, 04 Sep 2014, Toshi Kani wrote:
This patch sets WT to the PA4 slot in the PAT MSR when the processor
is not affected by the PAT errata. The upper 4 slots of the PAT MSR
are continued to be unused on the following
On Thu, 2014-09-04 at 14:31 -0600, Toshi Kani wrote:
On Thu, 2014-09-04 at 17:11 -0300, Henrique de Moraes Holschuh wrote:
On Thu, 04 Sep 2014, Toshi Kani wrote:
This patch sets WT to the PA4 slot in the PAT MSR when the processor
is not affected by the PAT errata. The upper 4 slots
On Thu, 2014-09-04 at 16:34 -0700, Andy Lutomirski wrote:
On Thu, Sep 4, 2014 at 4:19 PM, Henrique de Moraes Holschuh
h...@hmh.eng.br wrote:
On Thu, 04 Sep 2014, H. Peter Anvin wrote:
On 09/04/2014 01:11 PM, Henrique de Moraes Holschuh wrote:
I am worried of uncharted territory, here.
On Fri, 2014-09-05 at 12:23 +0200, Ingo Molnar wrote:
* Toshi Kani toshi.k...@hp.com wrote:
On Thu, 2014-09-04 at 14:31 -0600, Toshi Kani wrote:
On Thu, 2014-09-04 at 17:11 -0300, Henrique de Moraes Holschuh wrote:
On Thu, 04 Sep 2014, Toshi Kani wrote:
This patch sets WT
On Thu, 2014-09-04 at 17:51 -0700, Andy Lutomirski wrote:
On Thu, Sep 4, 2014 at 5:29 PM, Toshi Kani toshi.k...@hp.com wrote:
On Thu, 2014-09-04 at 16:34 -0700, Andy Lutomirski wrote:
On Thu, Sep 4, 2014 at 4:19 PM, Henrique de Moraes Holschuh
h...@hmh.eng.br wrote:
On Thu, 04 Sep 2014
On Fri, 2014-09-05 at 08:07 -0700, H. Peter Anvin wrote:
On 09/05/2014 07:00 AM, Toshi Kani wrote:
That's a fine idea, but as Ingo also suggested, I am going to disable
this feature on all Pentium 4 models. That should give us a safety
margin. Using slot 4 has a benefit that it keeps
On Fri, 2014-09-05 at 08:41 -0700, H. Peter Anvin wrote:
On 09/05/2014 08:22 AM, Toshi Kani wrote:
On Fri, 2014-09-05 at 08:07 -0700, H. Peter Anvin wrote:
On 09/05/2014 07:00 AM, Toshi Kani wrote:
That's a fine idea, but as Ingo also suggested, I am going to disable
this feature on all
On Sun, 2014-09-07 at 09:49 -0700, Andy Lutomirski wrote:
On Sun, Sep 7, 2014 at 1:49 AM, Yigal Korman yi...@plexistor.com wrote:
I think that what confused Andy (or at least me) is the documentation in
Documentation/x86/pat.txt
If it's possible, can you please update pat.txt as part of
On Mon, 2014-09-08 at 10:23 -0700, Andy Lutomirski wrote:
On Sep 8, 2014 8:18 AM, Toshi Kani toshi.k...@hp.com wrote:
On Sun, 2014-09-07 at 09:49 -0700, Andy Lutomirski wrote:
On Sun, Sep 7, 2014 at 1:49 AM, Yigal Korman yi...@plexistor.com wrote:
I think that what confused Andy
On Tue, 2014-08-26 at 08:16 +0200, Juergen Gross wrote:
Update the translation tables from cache mode to pgprot values according to
the PAT settings. This enables changing the cache attributes of a PAT index in
just one place without having to change at the users side.
With this change it is
On Fri, 2014-09-12 at 15:33 -0400, Konrad Rzeszutek Wilk wrote:
- /* Set PWT to Write-Combining. All other bits stay the same */
- /*
-* PTE encoding used in Linux:
-* PAT
-* |PCD
-* ||PWT
-* |||
-* 000 WB _PAGE_CACHE_WB
On Mon, 2014-09-15 at 06:25 +0200, Mike Galbraith wrote:
On Thu, 2014-09-11 at 16:21 +0900, Yasuaki Ishimatsu wrote:
There is no response for two months since posting v4.
What can I do for pushing the patch to upstream?
Looks to me like we have two patches floating about for more or less
,
Andy Lutomirski)
- Updated documentation to cover WT interfaces and usages.
(Andy Lutomirski, Yigal Korman)
---
Toshi Kani (7):
1/7 x86, mm, pat: Set WT to PA7 slot of PAT MSR
2/7 x86, mm, pat: Change reserve_memtype() to handle WT
3/7 x86, mm, asm-gen: Add ioremap_wt() for WT
4/7 x86
reserve_ram_pages_type() uses the page flags limited to three memory
types, WB, WC and UC.
Signed-off-by: Toshi Kani toshi.k...@hp.com
Reviewed-by: Konrad Rzeszutek Wilk konrad.w...@oracle.com
---
arch/x86/include/asm/cacheflush.h |4
arch/x86/mm/pat.c | 16 +---
2 files
This patch adds pgprot_writethrough() for setting WT to a given
pgprot_t.
Signed-off-by: Toshi Kani toshi.k...@hp.com
Reviewed-by: Konrad Rzeszutek Wilk konrad.w...@oracle.com
---
arch/x86/include/asm/pgtable_types.h |3 +++
arch/x86/mm/pat.c| 10 ++
include/asm
This patch adds set_memory_wt(), set_memory_array_wt() and
set_pages_array_wt() for setting specified range(s) of the
regular memory to WT.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
Documentation/x86/pat.txt |9 --
arch/x86/include/asm/cacheflush.h |6 +++-
arch/x86/mm
() is changed to call set_page_memtype() with _PGMT_WB,
and set_page_memtype() handles any undefined type as a bug.
This patch then defines _PGMT_WT to the released slot. This enables
set_page_memtype() to track the WT type.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm
in case the system has PAT but nopat boot
option is specified.
As a result of this change, cache aliasing is checked for all cases
including !pat_enabled.
Signed-off-by: Toshi Kani toshi.k...@hp.com
Reviewed-by: Juergen Gross jgr...@suse.com
---
arch/x86/mm/init.c |6 ++-
arch/x86/mm
ioremap_wt().
Signed-off-by: Toshi Kani toshi.k...@hp.com
Reviewed-by: Konrad Rzeszutek Wilk konrad.w...@oracle.com
---
Documentation/x86/pat.txt |4 +++-
arch/x86/include/asm/io.h |2 ++
arch/x86/mm/ioremap.c | 24
include/asm-generic/io.h|4
in __cachemode2pte_tbl[].
Signed-off-by: Toshi Kani toshi.k...@hp.com
Reviewed-by: Juergen Gross jgr...@suse.com
---
arch/x86/mm/pat.c | 64 +
1 file changed, 49 insertions(+), 15 deletions(-)
diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index
of 4k and large pages.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
I have two minor comments (which I should have caught before)... Other
wise, the changes look good to me.
Reviewed-by: Toshi Kani toshi.k...@hp.com
/*
diff --git
, Henrique de Moraes Holschuh,
Andy Lutomirski)
- Updated documentation to cover WT interfaces and usages.
(Andy Lutomirski, Yigal Korman)
---
Toshi Kani (6):
1/6 x86, mm, pat: Set WT to PA4 slot of PAT MSR
2/6 x86, mm, pat: Change reserve_memtype() to handle WT
3/6 x86, mm, asm-gen: Add
NV-DIMM
range with ioremap_cache() and then modifies a specific range
to WT with set_memory_wt().
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/cacheflush.h |6 +++
arch/x86/mm/pageattr.c| 73 ++---
2 files changed, 72
in __cachemode2pte_tbl[].
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/mm/pat.c | 43 ---
1 file changed, 28 insertions(+), 15 deletions(-)
diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index ff31851..598d7c7 100644
--- a/arch/x86/mm/pat.c
+++ b
reserve_ram_pages_type() uses the page flags limited to three memory
types, WB, WC and UC.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/cacheflush.h |4
arch/x86/mm/pat.c | 16 +---
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git
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