On 31/03/21 05:24PM, Chunfeng Yun wrote:
> On Tue, 2021-03-30 at 23:03 +0530, Pratyush Yadav wrote:
> > Some platforms like TI's J721E can have the CSI2RX paired with an
> > external DPHY. Add support to enable and configure the DPHY using the
> > generic PHY framework.
> &
On 02/04/21 01:23PM, Laurent Pinchart wrote:
> Hi Pratyush,
>
> Thank you for the patch.
>
> On Tue, Mar 30, 2021 at 11:03:46PM +0530, Pratyush Yadav wrote:
> > Convert Cadence DPHY binding to YAML.
> >
> > Signed-off-by: Pratyush Yadav
> > ---
> &g
On 02/04/21 01:31PM, Laurent Pinchart wrote:
> Hi Pratyush,
>
> Thank you for the patch.
>
> On Tue, Mar 30, 2021 at 11:03:47PM +0530, Pratyush Yadav wrote:
> > The clocks are not used by the DPHY when used in Rx mode so make them
> > optional.
>
> Is
On 02/04/21 01:35PM, Laurent Pinchart wrote:
> Hi Pratyush,
>
> Thank you for the patch.
>
> On Tue, Mar 30, 2021 at 11:03:48PM +0530, Pratyush Yadav wrote:
> > This property is needed on TI platforms to enable the PD of the DPHY
> > before it can be used.
> >
On 02/04/21 01:38PM, Laurent Pinchart wrote:
> Hi Pratyush,
>
> Thank you for the patch.
>
> On Tue, Mar 30, 2021 at 11:03:35PM +0530, Pratyush Yadav wrote:
> > Allow callers to set the PHY mode. The main mode should always be
> > PHY_MODE_MIPI_DPHY
On 02/04/21 01:53PM, Laurent Pinchart wrote:
> On Fri, Apr 02, 2021 at 01:01:22PM +0300, Laurent Pinchart wrote:
> > On Thu, Apr 01, 2021 at 10:52:01AM -0500, Rob Herring wrote:
> > > On Tue, Mar 30, 2021 at 11:03:44PM +0530, Pratyush Yadav wrote:
> > > > TI's
On 02/04/21 01:01PM, Laurent Pinchart wrote:
> On Thu, Apr 01, 2021 at 10:52:01AM -0500, Rob Herring wrote:
> > On Tue, Mar 30, 2021 at 11:03:44PM +0530, Pratyush Yadav wrote:
> > > TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate
> > > capture over
On 01/04/21 10:52AM, Rob Herring wrote:
> On Tue, Mar 30, 2021 at 11:03:44PM +0530, Pratyush Yadav wrote:
> > TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate
> > capture over a CSI-2 bus. The TI CSI2RX platform driver glues all the
> > parts together
On 02/04/21 01:55PM, Laurent Pinchart wrote:
> Hi Pratyush,
>
> Thank you for the patch.
>
> On Tue, Mar 30, 2021 at 11:03:41PM +0530, Pratyush Yadav wrote:
> > The subdevice power needs to be turned on before the stream is started.
> > Otherwise it might not be in
On 06/04/21 10:25PM, Pratyush Yadav wrote:
> On 06/04/21 06:33PM, Péter Ujfalusi wrote:
> >
> >
> > On 4/6/21 6:09 PM, Pratyush Yadav wrote:
> > > On 04/04/21 04:24PM, Péter Ujfalusi wrote:
> > >> Hi Pratyush,
> > >>
> > >> On 3
On 06/04/21 06:33PM, Péter Ujfalusi wrote:
>
>
> On 4/6/21 6:09 PM, Pratyush Yadav wrote:
> > On 04/04/21 04:24PM, Péter Ujfalusi wrote:
> >> Hi Pratyush,
> >>
> >> On 3/30/21 8:33 PM, Pratyush Yadav wrote:
> >>> The CSI2RX subsystem uses PSI
On 02/04/21 01:47PM, Laurent Pinchart wrote:
> Hi Pratyush,
>
> Thank you for the patch.
Thank you for the review :-)
>
> On Tue, Mar 30, 2021 at 11:03:42PM +0530, Pratyush Yadav wrote:
> > When this bridge driver is being user by another platform driver, it
> >
On 04/04/21 04:24PM, Péter Ujfalusi wrote:
> Hi Pratyush,
>
> On 3/30/21 8:33 PM, Pratyush Yadav wrote:
> > The CSI2RX subsystem uses PSI-L DMA to transfer frames to memory. It can
> > have up to 32 threads but the current driver only supports using one. So
> > add a
On 31/03/21 09:06AM, Tomi Valkeinen wrote:
> Hi,
>
> On 30/03/2021 20:33, Pratyush Yadav wrote:
> > TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate
> > capture over a CSI-2 bus.
> >
> > The Cadence CSI2RX IP acts as a bridge between the TI
On 01/04/21 03:13PM, Mark Brown wrote:
> On Thu, Apr 01, 2021 at 01:09:32AM +0530, Pratyush Yadav wrote:
>
> > I did take a look by running git log on
> > Documentation/devicetree/bindings/spi/ and there is no single style
> > being used. Using "dt-bindings: sp
sh names, depending on
> the SFDP differentiator.
>
> Fixes: 04b8edad262e ("mtd: spi-nor: macronix: Add support for mx25l51245g")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Tudor Ambarus
Acked-by: Pratyush Yadav
> ---
> drivers/mtd/spi-nor/macronix.c | 3 ---
On 01/04/21 01:57PM, Vignesh Raghavendra wrote:
>
>
> On 3/29/21 11:52 PM, Pratyush Yadav wrote:
> >>> + cdns,fifo-depth:
> >>> +description:
> >>> + Size of the data FIFO in words.
> >>> +$ref: "/schem
On 31/03/21 08:11PM, Mark Brown wrote:
> On Fri, Mar 26, 2021 at 06:30:34PM +0530, Pratyush Yadav wrote:
> > From: Ramuthevar Vadivel Murugan
> >
> >
> > There is no way as of now to have a parent or bus defining properties
> > for child nodes. For now, a
On 31/03/21 06:36PM, Vinod Koul wrote:
> On 31-03-21, 17:10, Pratyush Yadav wrote:
> > On 31/03/21 03:03PM, Vinod Koul wrote:
> > > On 30-03-21, 23:03, Pratyush Yadav wrote:
> > > > Hi,
> > > >
> > > > This series adds support for
On 31/03/21 03:03PM, Vinod Koul wrote:
> On 30-03-21, 23:03, Pratyush Yadav wrote:
> > Hi,
> >
> > This series adds support for CSI2 capture on J721E. It includes some
> > fixes to the Cadence CSI2RX driver, adds Rx support to Cadence DPHY
> > driver, and finally
This property is needed on TI platforms to enable the PD of the DPHY
before it can be used.
Signed-off-by: Pratyush Yadav
---
Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
b
The clocks are not used by the DPHY when used in Rx mode so make them
optional.
Signed-off-by: Pratyush Yadav
---
Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
b/Documentation
Convert Cadence DPHY binding to YAML.
Signed-off-by: Pratyush Yadav
---
.../devicetree/bindings/phy/cdns,dphy.txt | 20
.../devicetree/bindings/phy/cdns,dphy.yaml| 51 +++
2 files changed, 51 insertions(+), 20 deletions(-)
delete mode 100644 Documentation
lly return the data to a buffer
supplied by the application.
Signed-off-by: Pratyush Yadav
---
MAINTAINERS | 7 +
drivers/media/platform/Kconfig| 11 +
drivers/media/platform/ti-vpe/Makefile| 1 +
drivers/media/platform/ti-vpe/ti-csi2
TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate
capture over a CSI-2 bus. The TI CSI2RX platform driver glues all the
parts together.
Signed-off-by: Pratyush Yadav
---
.../devicetree/bindings/media/ti,csi2rx.yaml | 70 +++
1 file changed, 70 insertions
The CSI2RX subsystem uses PSI-L DMA to transfer frames to memory. It can
have up to 32 threads but the current driver only supports using one. So
add an entry for that one thread.
Signed-off-by: Pratyush Yadav
---
drivers/dma/ti/k3-psil-j721e.c | 10 ++
1 file changed, 10 insertions
platform
driver. More can be added later as needed.
Signed-off-by: Pratyush Yadav
---
drivers/media/platform/cadence/cdns-csi2rx.c | 77
1 file changed, 77 insertions(+)
diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c
b/drivers/media/platform/cadence/cdns
The subdevice power needs to be turned on before the stream is started.
Otherwise it might not be in the proper state to stream the data. Turn
it off when stopping the stream.
Signed-off-by: Pratyush Yadav
---
drivers/media/platform/cadence/cdns-csi2rx.c | 8
1 file changed, 8
that demands all streams to use the 0th virtual
channel. Prefer this case over the former because it is less arbitrary
and also makes it very clear what the limitations of the current driver
is instead of giving a false impression that multiple virtual channels
are supported.
Signed-off-by: Pratyush
The stream stop procedure says that the STOP bit should be set when the
stream is to be stopped, and then the ready bit in stream status
register polled to make sure the STOP operation is finished.
Signed-off-by: Pratyush Yadav
---
drivers/media/platform/cadence/cdns-csi2rx.c | 18
to their
default values.
Signed-off-by: Pratyush Yadav
---
drivers/media/platform/cadence/cdns-csi2rx.c | 147 +--
1 file changed, 137 insertions(+), 10 deletions(-)
diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c
b/drivers/media/platform/cadence/cdns-csi2rx.c
index
This resets the stream state machines and FIFOs, giving them a clean
slate. On J721E if the streams are not reset before starting the
capture, the captured frame gets wrapped around vertically on every run
after the first.
Signed-off-by: Pratyush Yadav
---
drivers/media/platform/cadence/cdns
the submode to PHY_MIPI_DPHY_SUBMODE_RX in the set_mode()
callback.
Signed-off-by: Pratyush Yadav
---
drivers/phy/cadence/cdns-dphy.c | 237
1 file changed, 237 insertions(+)
diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c
index
and Tx for MIPI D-PHY with submodes
Pratyush Yadav (15):
phy: cdns-dphy: Prepare for Rx support
phy: cdns-dphy: Allow setting mode
phy: cdns-dphy: Add Rx support
media: cadence: csi2rx: Add external DPHY support
media: cadence: csi2rx: Soft reset the streams before starting capture
media
Allow callers to set the PHY mode. The main mode should always be
PHY_MODE_MIPI_DPHY but the submode can either be
PHY_MIPI_DPHY_SUBMODE_RX or PHY_MIPI_DPHY_SUBMODE_TX. Update the ops
based on the requested submode.
Signed-off-by: Pratyush Yadav
---
drivers/phy/cadence/cdns-dphy.c | 30
in the Rx hooks.
The clocks "psm" and "pll_ref" are not used by the Rx path so make them
optional in the probe and then check if they exist in the power_on()
hook.
Signed-off-by: Pratyush Yadav
---
drivers/phy/cadence/cdns-dphy.c | 140
with PHY_MODE_MIPI_DPHY.
The default (zero value) is kept to Tx so only the rkisp1 driver, which
uses D-PHY in Rx mode, needs to be adapted.
Signed-off-by: Paul Kocialkowski
Signed-off-by: Pratyush Yadav
---
include/linux/phy/phy-mipi-dphy.h | 13 +
1 file changed, 13 insertions(+)
diff --git
.compatible = "intel,lgm-qspi",
> .data = _lgm_qspi,
> },
> + {
> + .compatible = "pensando,cdns-qspi",
> + .data = _cdns_qspi,
> + },
> { /* end of table */ }
> };
>
> --
> 2.17.1
>
Rest of the patch looks good to me.
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
thevar Vadivel Murugan
> + - Brad Larson
> +
> +properties:
> + compatible:
> +contains:
> + enum:
> +- cdns,qspi-nor # Generic default
> +- ti,k2g-qspi # TI 66AK2G SoC
> +- ti,am654-ospi # TI AM654 SoC
> +- intel,lgm-qspi # Intel LGM SoC
> +- pensando,cdns-qspi # Pensando Elba SoC
Wouldn't this allow any combination of all 5 strings? So for example
this would allow "ti,am654-ospi", "pensando,cdns-qspi" which is
obviously not correct.
I sent a patch recently [0] that does this correctly and it has gotten
Rob's blessing. So I suggest you build your patch on top of that.
[...]
[0]
https://patchwork.kernel.org/project/spi-devel-general/patch/20210326130034.15231-5-p.ya...@ti.com/
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 27/03/21 12:36PM, Rob Herring wrote:
> On Fri, Mar 26, 2021 at 06:30:34PM +0530, Pratyush Yadav wrote:
> > From: Ramuthevar Vadivel Murugan
> >
> >
> > There is no way as of now to have a parent or bus defining properties
> > for child nodes. For now, a
Signed-off-by: Pratyush Yadav
[p.ya...@ti.com: Fix how compatible is defined, make reset optional, fix
minor typos, remove subnode properties in example, update commit
message.]
---
.../bindings/spi/cadence-quadspi.txt | 68 -
.../bindings/spi/cdns,qspi-nor.yaml | 143
The TI specific compatible should be followed by the generic
"cdns,qspi-nor" compatible.
Signed-off-by: Pratyush Yadav
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
b/arch/arm6
-devel-general/patch/20201116031003.19062-6-vadivel.muruganx.ramuthe...@linux.intel.com/
Pratyush Yadav (3):
arm64: dts: ti: k3-j721e-mcu: Fix ospi compatible
arm64: dts: ti: k3-j7200-mcu: Fix ospi compatible
arm64: dts: ti: k3-am64-main: Fix ospi compatible
Ramuthevar Vadivel Murugan (1):
dt
The TI specific compatible should be followed by the generic
"cdns,qspi-nor" compatible.
Signed-off-by: Pratyush Yadav
---
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dt
The TI specific compatible should be followed by the generic
"cdns,qspi-nor" compatible.
Signed-off-by: Pratyush Yadav
---
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wake
On 24/03/21 12:07AM, Michael Walle wrote:
> Hi Pratyush,
>
> Am 2021-03-11 20:12, schrieb Pratyush Yadav:
> > Some controllers like the Cadence OSPI controller need to perform a
> > calibration sequence to operate at high clock speeds. This calibration
> > should happ
On 24/03/21 12:17AM, Michael Walle wrote:
> Am 2021-03-11 20:12, schrieb Pratyush Yadav:
> > Currently the spi_mem_op to read from the flash is used in two places:
> > spi_nor_create_read_dirmap() and spi_nor_spimem_read_data(). In a later
> > commit this number will incre
sers.
Acked-by: Pratyush Yadav
>
> Signed-off-by: Michael Walle
> ---
> drivers/mtd/spi-nor/Makefile | 2 +-
> drivers/mtd/spi-nor/core.c | 5 +++
> drivers/mtd/spi-nor/core.h | 3 ++
> drivers/mtd/spi-nor/sysfs.c | 86
> 4 files c
ed-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 22/03/21 11:31PM, Michael Walle wrote:
> Am 2021-03-22 19:42, schrieb Pratyush Yadav:
> > On 22/03/21 04:32PM, Michael Walle wrote:
> > > Am 2021-03-22 15:21, schrieb Pratyush Yadav:
> > > > On 18/03/21 10:24AM, Michael Walle wrote:
> > > > > +
&g
On 22/03/21 04:32PM, Michael Walle wrote:
> Am 2021-03-22 15:21, schrieb Pratyush Yadav:
> > On 18/03/21 10:24AM, Michael Walle wrote:
[...]
> > > @@ -1311,6 +1317,49 @@ int spi_nor_parse_sfdp(struct spi_nor *nor,
> > > }
> > > }
> > >
t; + if (attr == _attr_sfdp && nor->sfdp)
> + return 0444;
> +
> + return 0;
> +}
> +
> +static struct attribute_group spi_nor_sysfs_attr_group = {
> + .name = NULL,
> + .is_bin_visible = spi_nor_sysfs_is_bin_visible,
> + .attrs = spi_nor_sysfs_entries,
> + .bin_attrs = spi_nor_sysfs_bin_entries,
> +};
> +
> +int spi_nor_sysfs_create(struct spi_nor *nor)
> +{
> + return sysfs_create_group(>dev->kobj, _nor_sysfs_attr_group);
> +}
> +
> +void spi_nor_sysfs_remove(struct spi_nor *nor)
> +{
> + sysfs_remove_group(>dev->kobj, _nor_sysfs_attr_group);
> +}
> --
> 2.20.1
>
Rest of it looks good to me.
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
ad operations
> * @write_proto: the SPI protocol for write operations
> * @reg_proto: the SPI protocol for read_reg/write_reg/erase
> operations
> + * @sfdp:the SFDP data of the flash
> * @controller_ops: SPI NOR controller driver specific operations.
> * @params: [FLASH-SPECIFIC] SPI NOR flash parameters and settings.
> * The structure includes legacy flash parameters and
> @@ -404,6 +406,7 @@ struct spi_nor {
> boolsst_write_second;
> u32 flags;
> enum spi_nor_cmd_extcmd_ext_type;
> + struct sfdp *sfdp;
>
> const struct spi_nor_controller_ops *controller_ops;
>
> --
> 2.20.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 16/03/21 12:00AM, Pratyush Yadav wrote:
> +Cc mtd list
>
> Hi,
>
> On 15/03/21 05:45PM, Kuldeep Singh wrote:
> > Convert the Freescale DSPI binding to DT schema format using json-schema.
> >
> > Signed-off-by: Kuldeep Singh
> > ---
> > Hi
ide in swp.c.
>
> Signed-off-by: Tudor Ambarus
Acked-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 22/03/21 09:51AM, Tudor Ambarus wrote:
> - bool return value for spi_nor_check_lock_status_sr(), gets rid of
> the return 1,
> - introduce temporary variables for better readability.
>
> Suggested-by: Joe Perches
> Signed-off-by: Tudor Ambarus
Reviewed-by: Pratyush Y
re. Maybe also add a comment at the top of
the file mentioning the full name "Software Write Protection logic" or
something similar for clarification.
>
> >>>
> >>
>
> cut
>
> >
> > I am not a fan of renaming Kconfig options as it breaks make
> > olddefconfig flow which many developers rely on.
> >
>
> I'm fine keeping them as they are for now. If someone else screams we will
> reconsider.
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 16/03/21 06:45PM, Michael Walle wrote:
> Am 2021-03-15 19:30, schrieb Pratyush Yadav:
>
> ..
> > > +patternProperties:
> > > + "@[0-9a-f]+":
>
> Shouldn't this be "^.*@[0-9a-f]+$"?
The pattern has to match _anywhere_ in the string so bo
On 16/03/21 12:15PM, Michael Walle wrote:
> Am 2021-03-16 12:04, schrieb Pratyush Yadav:
> > On 12/03/21 08:05PM, Michael Walle wrote:
> > > If spi_nor_read_sfdp() is used after probe, we have to set read_proto
> > > and the read dirmap.
> > >
On 16/03/21 12:01PM, Michael Walle wrote:
> Hi Pratyush,
>
> Am 2021-03-16 11:42, schrieb Pratyush Yadav:
> > On 12/03/21 08:05PM, Michael Walle wrote:
> > > Save the sftp_size in the spi_nor struct so we can use it to dump the
> > > SFDP table
d_raw(nor, addr, len, buf);
>
> nor->read_opcode = read_opcode;
> + nor->read_proto = read_proto;
> + nor->dirmap.rdesc = rdesc;
> nor->addr_width = addr_width;
> nor->read_dummy = read_dummy;
>
> --
> 2.20.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
nor.h
> index a0d572855444..a58118b8b002 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -404,6 +404,7 @@ struct spi_nor {
> boolsst_write_second;
> u32 flags;
> enum spi_nor_cmd_extcmd_ext_type;
> + size_t sfdp_size;
Documentation for this variable missing.
>
> const struct spi_nor_controller_ops *controller_ops;
>
> --
> 2.20.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
clock-names = "dspi";
> - spi-num-chipselects = <5>;
> - bus-num = <0>;
> - pinctrl-names = "default";
> - pinctrl-0 = <_dspi0_1>;
> - big-endian;
> -
> - sflash: at26df081a@0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "atmel,at26df081a";
> - spi-max-frequency = <1600>;
> - spi-cpol;
> - spi-cpha;
> - reg = <0>;
> - linux,modalias = "m25p80";
> - modal = "at26df081a";
> - fsl,spi-cs-sck-delay = <100>;
> - fsl,spi-sck-cs-delay = <50>;
> - };
> -};
> -
> -
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d92f85ca831d..e2c5b7367db9 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -7060,7 +7060,7 @@ FREESCALE DSPI DRIVER
> M: Vladimir Oltean
> L: linux-...@vger.kernel.org
> S: Maintained
> -F: Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
> +F: Documentation/devicetree/bindings/spi/fsl,spi-fsl-dspi.yaml
> F: drivers/spi/spi-fsl-dspi.c
> F: include/linux/spi/spi-fsl-dspi.h
>
> --
> 2.17.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
ot otherwise discovered or specified.
>
> Signed-off-by: Tudor Ambarus
Reviewed-by: Pratyush Yadav
> ---
> drivers/mtd/spi-nor/core.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> ind
to
mean "Register locking ops". That is, ops to lock/unlock flash
registers. If you do want to keep using "register", IMO
spi_nor_locking_ops_register() would be better.
>
> Thanks,
> ta
>
> >
> > I don't have a strong opinion on that so far. I just noticed because
> > I put the check into spi_nor_otp_init() for my OTP series. They should
> > be the same though.
> >
> >> + spi_nor_register_locking_ops(nor);
> >
> > -michael
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 12/03/21 11:23AM, tudor.amba...@microchip.com wrote:
> On 3/12/21 12:10 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > On 12/03/21 09:09AM, tudor.amba...@microchip.com wro
On 12/03/21 02:32PM, Michael Walle wrote:
> Am 2021-03-11 20:12, schrieb Pratyush Yadav:
> > The main problem here is telling the controller where to find the
> > pattern and how to read it. This RFC uses nvmem cells which point to a
> > fixed partition containing the
On 12/03/21 11:20AM, Michael Walle wrote:
> Am 2021-03-12 11:10, schrieb Pratyush Yadav:
> > There is usually a delay from when the flash drives the data line (IOW,
> > puts a data bit on it) and when the signal reaches the controller. This
> > delay can vary by the
On 12/03/21 09:13AM, tudor.amba...@microchip.com wrote:
> On 3/11/21 9:12 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > Check if a read is eligible for PHY and if it is, enable PHY a
On 12/03/21 09:09AM, tudor.amba...@microchip.com wrote:
> On 3/11/21 9:12 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > Hi,
> >
> > This series adds support for O
can only be used with DAC mode
reads, and only in chunks of 16 bytes. For all other operations, PHY
mode should be turned off.
[0] https://www.ti.com/lit/pdf/spract2/
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-cadence-quadspi.c | 617 ++
1 file changed, 617
partition table that contains the calibration partition, along with the
rest of the partitions for the platform. Also add a nvmem cell that
points to the calibration partition.
Signed-off-by: Pratyush Yadav
---
Based on patch
https://patchwork.kernel.org/project/linux-arm-kernel/patch
-by: Pratyush Yadav
---
drivers/spi/spi-cadence-quadspi.c | 203 ++
1 file changed, 182 insertions(+), 21 deletions(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c
b/drivers/spi/spi-cadence-quadspi.c
index e2d6ea833423..e64d8e125263 100644
--- a/drivers/spi/spi-cadence
a hook that can be used to tell the controller
when the flash is ready for calibration. Whether calibration is needed
depends on the controller.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 12
include/linux/spi/spi-mem.h | 8
2 files changed, 20
Once the flash is initialized tell the controller it can run
calibration procedures if needed. This can be useful when calibration is
needed to run at higher clock speeds.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi-nor/core.c | 12 ++--
1 file changed, 10 insertions(+), 2
-1-ansuels...@gmail.com/
[2]
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210305153926.3479-2-p.ya...@ti.com/
Pratyush Yadav (6):
spi: spi-mem: Tell controller when device is ready for calibration
mtd: spi-nor: core: consolidate read op creation
mtd: spi-nor: core: run
can then fill in the details like address, data length, data
buffer location.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi-nor/core.c | 62 --
1 file changed, 32 insertions(+), 30 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor
On 11/03/21 07:22AM, Nishanth Menon wrote:
> On 21:43-20210305, Vignesh Raghavendra wrote:
> >
> >
> > On 3/5/21 9:09 PM, Pratyush Yadav wrote:
> > > TI J7200 has the Cadence OSPI controller for interfacing with OSPI
> > > flashes. Add its node to allow usi
On 09/03/21 06:35PM, Vignesh Raghavendra wrote:
> Both AM64 EVM and SK have a 512Mb S28HS512T Octal SPI NOR flash.
> Add DT node for the same.
>
> Signed-off-by: Vignesh Raghavendra
Reviewed-by: Pratyush Yadav
> ---
>
> Bootlog:
>
> SK: https://pastebin.ubuntu.com
On 09/03/21 06:35PM, Vignesh Raghavendra wrote:
> AM64 SoC has a single Octal SPI (OSPI) instance under Flash SubSystem
> (FSS). Add DT entry for the same.
>
> Signed-off-by: Vignesh Raghavendra
Reviewed-by: Pratyush Yadav
> ---
> arch/arm64/boot/dts/ti/k3-a
On 08/03/21 11:23AM, Tudor Ambarus wrote:
> It's already been the case for some time that Michael and Pratyush
> are reviewing SPI NOR patches. Update MAINTAINERS to reflect reality.
>
> Signed-off-by: Tudor Ambarus
Acked-by: Pratyush Yadav
> ---
> Michael, Pratyush, plea
page_offset = addr & (nor->page_size - 1);
> } else {
> uint64_t aux = addr;
Reviewed-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 06/03/21 11:50AM, Tudor Ambarus wrote:
> else is not generally useful after a break or return.
>
> Signed-off-by: Tudor Ambarus
Reviewed-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
p for
> 'commit 69a8eed58cc0 ("mtd: spi-nor: Don't copy self-pointing struct around")'
>
> Signed-off-by: Tudor Ambarus
Reviewed-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
pcode = 0x%02x, erase_cmd->count = %d\n",
erase_cmd->count is an unsigned value (u32) so it should be %u instead
of %d.
Other than this,
Reviewed-by: Pratyush Yadav
> + cmd->size, cmd->opcode, cmd->count);
> +
> ret = s
TI J7200 has the Cadence OSPI controller for interfacing with OSPI
flashes. Add its node to allow using SPI flashes.
Signed-off-by: Pratyush Yadav
---
Notes:
Changes in v2:
- Do not force a pulldown on the DQS line because it already has a
pulldown resistor.
.../boot/dts/ti/k3
.
Signed-off-by: Pratyush Yadav
---
Notes:
No changes in v2.
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index
.
Signed-off-by: Pratyush Yadav
---
Notes:
No changes in v2.
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 57720e6a04c5
Hi,
Now that the OSPI controller driver and the SPI NOR core have support
for 8D-8D-8D mode, the device tree can be updated to allow Octal DTR
transactions.
Pratyush Yadav (3):
arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI
arm64: dts: ti: am654-base-board: Enable 8D-8D-8D
On 03/03/21 10:14PM, Junio C Hamano wrote:
> Eric Sunshine writes:
>
> > On Wed, Mar 3, 2021 at 7:23 PM Junio C Hamano wrote:
> >> Pratyush Yadav (1):
> >> git-gui: remove lines starting with the comment character
> >
> > Is there some way th
On 02/03/21 01:10PM, Vignesh Raghavendra wrote:
>
>
> On 3/2/21 1:28 AM, Pratyush Yadav wrote:
> > +
> > + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
> > + pinctrl-single,pins = <
> > + J721E_WKUP_IOPAD(0x,
.
Signed-off-by: Pratyush Yadav
---
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index fe3043943906..9e87fb313a54 100644
.
Signed-off-by: Pratyush Yadav
---
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 57720e6a04c5..2fee2906183d 100644
--- a/arch/arm64
TI J7200 has the Cadence OSPI controller for interfacing with OSPI
flashes. Add its node to allow using SPI flashes.
Signed-off-by: Pratyush Yadav
---
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++
2 files
Hi,
Now that the OSPI controller driver and the SPI NOR core have support
for 8D-8D-8D mode, the device tree can be updated to allow Octal DTR
transactions.
Pratyush Yadav (3):
arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI
arm64: dts: ti: am654-base-board: Enable 8D-8D-8D
callable instruction
> with modified stack frame
>
> Change the unreachable() into an error return that can be
> handled if it ever happens, rather than silently crashing
> the kernel.
>
> Fixes: 65498c6ae241 ("spi: rockchip: support 4bit words")
> Signed-off-by:
On 26/02/21 10:49AM, Arnd Bergmann wrote:
> On Fri, Feb 26, 2021 at 9:16 AM 'Pratyush Yadav' via Clang Built Linux
> wrote:
> >
> > Hi,
> >
> > On 25/02/21 01:55PM, Arnd Bergmann wrote:
> > > From: Arnd Bergmann
> > >
> > > Building
nel - try using WARN_ON & recovery code rather
than BUG() or BUG_ON()
Which makes sense to me. This is not something bad enough to justify
crashing the kernel.
> }
>
> if (use_dma) {
> --
> 2.29.2
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
ooks good
at first look. Small nitpick: move this line just after the above for
loop that initializes this array.
>
> return 0;
> }
> --
> 2.25.1
>
>
> __
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
ret = spi_nor_wait_till_ready(nor);
> if (ret)
> goto erase_err;
> +
> + addr += mtd->erasesize;
> + len -= mtd->erasesize;
Do these changes have any practical benefit? IMO they are worth doin
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