Re: [PATCH] x86/cpu/zhaoxin: Fix wrong lowercase naming and indent
On 19/01/2021 01:25, Isaac Chen wrote:
> This is printed during kernel boot, match it with other supported x86 cpus.
> [0.00] KERNEL supported cpus:
> [0.00] Intel GenuineIntel
> [0.00] AMD AuthenticAMD
> [0.00] Hygon HygonGenuine
> [0.00] Centaur CentaurHauls
> [0.00] zhaoxin Shanghai
>
> Signed-off-by: Isaac Chen
> ---
> arch/x86/kernel/cpu/zhaoxin.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
> index 05fa4ef63490..f155bbd2aa97 100644
> --- a/arch/x86/kernel/cpu/zhaoxin.c
> +++ b/arch/x86/kernel/cpu/zhaoxin.c
> @@ -120,8 +120,8 @@ zhaoxin_size_cache(struct cpuinfo_x86 *c, unsigned int
> size)
> #endif
>
> static const struct cpu_dev zhaoxin_cpu_dev = {
> - .c_vendor = "zhaoxin",
> - .c_ident= { " Shanghai " },
> + .c_vendor = "Zhaoxin",
Thanks for this patch.
> + .c_ident= { "Shanghai" },
The Vendor Identification String from CPUID leaf 0x of Zhaoxin
CPUs is not "Shanghai", ".c_ident = { "Shanghai" }," will cause the
matching of Zhaoxin CPUs fail.
Please do not modify ".c_ident = { " Shanghai " },".
Sincerely,
Tonyw
Re: [PATCH v1 1/3] x86/cpufeatures: Add low performance CRC32C instruction CPU feature
On 11/01/2021 19:03, Borislav Petkov wrote: > On Mon, Jan 11, 2021 at 06:51:59PM +0800, Tony W Wang-oc wrote: >> This issue will be enhanced by hardware and patch submit will be pending. > > I have no clue what that has to do with your current patch... you might > need to explain more verbosely. > After internal research, decided to fix the low performance crc32c instruction issue on these Zhaoxin CPUs by microcode. So, do not need this patch anymore. Sincerely Tonyw
Re: [PATCH v1 2/3] x86/cpu: Set low performance CRC32C flag on some Zhaoxin CPUs
On 07/01/2021 23:52, Dave Hansen wrote: > On 1/6/21 10:19 PM, Tony W Wang-oc wrote: >> +/* >> + * These CPUs declare support SSE4.2 instruction sets but >> + * having low performance CRC32C instruction implementation. >> + */ >> +if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b)) >> +set_cpu_cap(c, X86_FEATURE_CRC32C); >> } > > On the Intel side, we've tried to move away from open-coded model > numbers. Say another CPU is released that has a microarchitecture close > to 0x3b, but has a model of 0x3c. It's a *LOT* easier to grep for > INTEL_FAM6_NEHALEM (or whatever) than 0x3c. See: > > arch/x86/include/asm/intel-family.h > > for examples. > . > Got it, thanks for your suggestion. Sincerely Tonyw
Re: [PATCH v1 1/3] x86/cpufeatures: Add low performance CRC32C instruction CPU feature
On 07/01/2021 14:37, Borislav Petkov wrote: > On Thu, Jan 07, 2021 at 02:19:06PM +0800, Tony W Wang-oc wrote: >> SSE4.2 on Zhaoxin CPUs are compatible with Intel. The presence of >> CRC32C instruction is enumerated by CPUID.01H:ECX.SSE4_2[bit 20] = 1. >> Some Zhaoxin CPUs declare support SSE4.2 instruction sets but their >> CRC32C instruction are working with low performance. >> >> Add a synthetic CPU flag to indicates that the CRC32C instruction is >> not working as intended. This low performance CRC32C instruction flag >> is depend on X86_FEATURE_XMM4_2. >> >> Signed-off-by: Tony W Wang-oc >> --- >> arch/x86/include/asm/cpufeatures.h | 1 + >> arch/x86/kernel/cpu/cpuid-deps.c | 1 + >> 2 files changed, 2 insertions(+) >> >> diff --git a/arch/x86/include/asm/cpufeatures.h >> b/arch/x86/include/asm/cpufeatures.h >> index 84b8878..9e8151b 100644 >> --- a/arch/x86/include/asm/cpufeatures.h >> +++ b/arch/x86/include/asm/cpufeatures.h >> @@ -292,6 +292,7 @@ >> #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in >> kernel entry SWAPGS path */ >> #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split >> lock */ >> #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory >> Bandwidth Allocation */ >> +#define X86_FEATURE_CRC32C (11*32+ 8) /* "" Low performance CRC32C >> instruction */ > > Didn't hpa say to create a BUG flag for it - X86_BUG...? Low performance > insn sounds like a bug and not a feature to me. > > And call it X86_BUG_CRC32C_SLOW or ..._UNUSABLE to denote what it means. > This issue will be enhanced by hardware and patch submit will be pending. Sincerely Tonyw
Re: [PATCH] crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs
On 03/01/2021 05:12, Herbert Xu wrote: > On Tue, Dec 15, 2020 at 06:28:11PM +0800, Tony W Wang-oc wrote: >> The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2. >> On platforms with Zhaoxin CPUs supporting this X86 feature, when >> crc32c-intel and crc32c-generic are both registered, system will >> use crc32c-intel because its .cra_priority is greater than >> crc32c-generic. >> >> When doing lmbench3 Create and Delete file test on partitions with >> ext4 enabling metadata checksum, found using crc32c-generic driver >> could get about 20% performance gain than using the driver crc32c-intel >> on some Zhaoxin CPUs. >> >> This case expect to use crc32c-generic driver for these Zhaoxin CPUs >> to get performance gain, so remove these Zhaoxin CPUs support from >> crc32c-intel. >> >> Signed-off-by: Tony W Wang-oc >> --- >> arch/x86/crypto/crc32c-intel_glue.c | 21 +++-- >> 1 file changed, 19 insertions(+), 2 deletions(-) > > This does not seem to address the latest comment from hpa. > Yes, please ignore this patch. Have send new patch set per Hpa's suggestion. Sincerely Tonyw > Thanks, >
Re: [PATCH] crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs
On 22/12/2020 12:54, h...@zytor.com wrote: > On December 21, 2020 7:01:39 PM PST, tonywwang...@zhaoxin.com wrote: >> On December 22, 2020 3:27:33 AM GMT+08:00, h...@zytor.com wrote: >>> On December 20, 2020 6:46:25 PM PST, tonywwang...@zhaoxin.com wrote: >>>> On December 16, 2020 1:56:45 AM GMT+08:00, Eric Biggers >>>> wrote: >>>>> On Tue, Dec 15, 2020 at 10:15:29AM +0800, Tony W Wang-oc wrote: >>>>>> >>>>>> On 15/12/2020 04:41, Eric Biggers wrote: >>>>>>> On Mon, Dec 14, 2020 at 10:28:19AM +0800, Tony W Wang-oc wrote: >>>>>>>> On 12/12/2020 01:43, Eric Biggers wrote: >>>>>>>>> On Fri, Dec 11, 2020 at 07:29:04PM +0800, Tony W Wang-oc >> wrote: >>>>>>>>>> The driver crc32c-intel match CPUs supporting >>>>> X86_FEATURE_XMM4_2. >>>>>>>>>> On platforms with Zhaoxin CPUs supporting this X86 feature, >>>> When >>>>>>>>>> crc32c-intel and crc32c-generic are both registered, system >>>> will >>>>>>>>>> use crc32c-intel because its .cra_priority is greater than >>>>>>>>>> crc32c-generic. This case expect to use crc32c-generic driver >>>>> for >>>>>>>>>> some Zhaoxin CPUs to get performance gain, So remove these >>>>> Zhaoxin >>>>>>>>>> CPUs support from crc32c-intel. >>>>>>>>>> >>>>>>>>>> Signed-off-by: Tony W Wang-oc >>>>>>>>> >>>>>>>>> Does this mean that the performance of the crc32c instruction >>> on >>>>> those CPUs is >>>>>>>>> actually slower than a regular C implementation? That's very >>>>> weird. >>>>>>>>> >>>>>>>> >>>>>>>> From the lmbench3 Create and Delete file test on those chips, I >>>>> think yes. >>>>>>>> >>>>>>> >>>>>>> Did you try measuring the performance of the hashing itself, and >>>>> not some >>>>>>> higher-level filesystem operations? >>>>>>> >>>>>> >>>>>> Yes. Was testing on these Zhaoxin CPUs, the result is that with >> the >>>>> same >>>>>> input value the generic C implementation takes fewer time than the >>>>>> crc32c instruction implementation. >>>>>> >>>>> >>>>> And that is really "working as intended"? >>>> >>>> These CPU's crc32c instruction is not working as intended. >>>> >>>> Why do these CPUs even >>>>> declare that >>>>> they support the crc32c instruction, when it is so slow? >>>>> >>>> >>>> The presence of crc32c and some other instructions supports are >>>> enumerated by CPUID.01:ECX[SSE4.2] = 1, other instructions are ok >>>> except the crc32c instruction. >>>> >>>>> Are there any other instruction sets (AES-NI, PCLMUL, SSE, SSE2, >> AVX, >>>>> etc.) that >>>>> these CPUs similarly declare support for but they are uselessly >> slow? >>>> >>>> No. >>>> >>>> Sincerely >>>> Tonyw >>>> >>>>> >>>>> - Eric >>> >>> Then the right thing to do is to disable the CPUID bit in the >>> vendor-specific startup code. >> >> This way makes these CPUs do not support all instruction sets >> enumerated >> by CPUID.01:ECX[SSE4.2]. >> While only crc32c instruction is slow, just expect the crc32c-intel >> driver do not >> match these CPUs. >> >> Sincerely >> Tonyw > > Then create a BUG flag for it, or factor out CRC32C into a synthetic flag. We > *do not* bury this information in drivers; it becomes a recipe for the same > problems over and over. > Thanks for your suggestion. Have send new patch set. Sincerely Tonyw
[PATCH v1 0/3] crypto: x86/crc32c-intel - Exclude some Zhaoxin CPUs
The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2. On platforms with Zhaoxin CPUs supporting this X86 feature, when crc32c-intel and crc32c-generic are both registered, system will use crc32c-intel because its .cra_priority is greater than crc32c-generic. When doing lmbench3 Create and Delete file test on partitions with ext4 enabling metadata checksum, found using crc32c-generic driver could get about 20% performance gain than using the driver crc32c-intel on some Zhaoxin CPUs. Lower-level testing result is that with the same input value the generic C implementation takes fewer time than the crc32c instruction implementation on these CPUs. This case expect to use crc32c-generic driver for these CPUs to get performance gain. The presence of crc32c is enumerated by CPUID.01:ECX[SSE4.2] = 1, and these CPUs other SSE4.2 instructions is ok. Add a synthetic flag to indicates low performance CRC32C instruction implementation, set this flag in Zhaoxin CPUs specific init phase, and exclude CPUs which setting this flag from the driver crc32c-intel. https://lkml.org/lkml/2020/12/21/789 Tony W Wang-oc (3): x86/cpufeatures: Add low performance CRC32C instruction CPU feature x86/cpu: Set low performance CRC32C flag on some Zhaoxin CPUs crypto: x86/crc32c-intel Exclude low performance CRC32C instruction CPUs arch/x86/crypto/crc32c-intel_glue.c | 5 + arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/centaur.c | 7 +++ arch/x86/kernel/cpu/cpuid-deps.c| 1 + arch/x86/kernel/cpu/zhaoxin.c | 6 ++ 5 files changed, 20 insertions(+) -- 2.7.4
[PATCH v1 3/3] crypto: x86/crc32c-intel Exclude low performance CRC32C instruction CPUs
Low performance CRC32C instruction CPUs expect to use the driver
crc32c-generic. So remove these CPUs support from crc32c-intel.
Signed-off-by: Tony W Wang-oc
---
arch/x86/crypto/crc32c-intel_glue.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/x86/crypto/crc32c-intel_glue.c
b/arch/x86/crypto/crc32c-intel_glue.c
index feccb52..1b6d289 100644
--- a/arch/x86/crypto/crc32c-intel_glue.c
+++ b/arch/x86/crypto/crc32c-intel_glue.c
@@ -224,6 +224,11 @@ static int __init crc32c_intel_mod_init(void)
{
if (!x86_match_cpu(crc32c_cpu_id))
return -ENODEV;
+
+ /* Don't merit use low performance CRC32C instruction */
+ if (boot_cpu_has(X86_FEATURE_CRC32C))
+ return -ENODEV;
+
#ifdef CONFIG_X86_64
if (boot_cpu_has(X86_FEATURE_PCLMULQDQ)) {
alg.update = crc32c_pcl_intel_update;
--
2.7.4
[PATCH v1 2/3] x86/cpu: Set low performance CRC32C flag on some Zhaoxin CPUs
Some Zhaoxin CPUs declare support SSE4.2 instruction sets but having a CRC32C instruction implementation that not working as intended. Set low performance CRC32C flag on these CPUs for later use. Signed-off-by: Tony W Wang-oc --- arch/x86/kernel/cpu/centaur.c | 7 +++ arch/x86/kernel/cpu/zhaoxin.c | 6 ++ 2 files changed, 13 insertions(+) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 345f7d9..13e6fbe 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -109,6 +109,13 @@ static void early_init_centaur(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); } + + /* +* These CPUs declare support SSE4.2 instruction sets but +* having low performance CRC32C instruction implementation. +*/ + if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b)) + set_cpu_cap(c, X86_FEATURE_CRC32C); } static void init_centaur(struct cpuinfo_x86 *c) diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c index 05fa4ef..837ec65 100644 --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -79,6 +79,12 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c) c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); } + /* +* These CPUs declare support SSE4.2 instruction sets but +* having low performance CRC32C instruction implementation. +*/ + if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b)) + set_cpu_cap(c, X86_FEATURE_CRC32C); } static void init_zhaoxin(struct cpuinfo_x86 *c) -- 2.7.4
[PATCH v1 1/3] x86/cpufeatures: Add low performance CRC32C instruction CPU feature
SSE4.2 on Zhaoxin CPUs are compatible with Intel. The presence of
CRC32C instruction is enumerated by CPUID.01H:ECX.SSE4_2[bit 20] = 1.
Some Zhaoxin CPUs declare support SSE4.2 instruction sets but their
CRC32C instruction are working with low performance.
Add a synthetic CPU flag to indicates that the CRC32C instruction is
not working as intended. This low performance CRC32C instruction flag
is depend on X86_FEATURE_XMM4_2.
Signed-off-by: Tony W Wang-oc
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/cpuid-deps.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h
b/arch/x86/include/asm/cpufeatures.h
index 84b8878..9e8151b 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -292,6 +292,7 @@
#define X86_FEATURE_FENCE_SWAPGS_KERNEL(11*32+ 5) /* "" LFENCE in
kernel entry SWAPGS path */
#define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */
#define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory
Bandwidth Allocation */
+#define X86_FEATURE_CRC32C (11*32+ 8) /* "" Low performance CRC32C
instruction */
/* Intel-defined CPU features, CPUID level 0x0007:1 (EAX), word 12 */
#define X86_FEATURE_AVX512_BF16(12*32+ 5) /* AVX512 BFLOAT16
instructions */
diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
index 42af31b6..7d7fca7 100644
--- a/arch/x86/kernel/cpu/cpuid-deps.c
+++ b/arch/x86/kernel/cpu/cpuid-deps.c
@@ -72,6 +72,7 @@ static const struct cpuid_dep cpuid_deps[] = {
{ X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW },
{ X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES},
{ X86_FEATURE_PER_THREAD_MBA, X86_FEATURE_MBA },
+ { X86_FEATURE_CRC32C, X86_FEATURE_XMM4_2},
{}
};
--
2.7.4
[PATCH] crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs
The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.
On platforms with Zhaoxin CPUs supporting this X86 feature, when
crc32c-intel and crc32c-generic are both registered, system will
use crc32c-intel because its .cra_priority is greater than
crc32c-generic.
When doing lmbench3 Create and Delete file test on partitions with
ext4 enabling metadata checksum, found using crc32c-generic driver
could get about 20% performance gain than using the driver crc32c-intel
on some Zhaoxin CPUs.
This case expect to use crc32c-generic driver for these Zhaoxin CPUs
to get performance gain, so remove these Zhaoxin CPUs support from
crc32c-intel.
Signed-off-by: Tony W Wang-oc
---
arch/x86/crypto/crc32c-intel_glue.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/x86/crypto/crc32c-intel_glue.c
b/arch/x86/crypto/crc32c-intel_glue.c
index feccb52..5171091 100644
--- a/arch/x86/crypto/crc32c-intel_glue.c
+++ b/arch/x86/crypto/crc32c-intel_glue.c
@@ -215,14 +215,31 @@ static struct shash_alg alg = {
};
static const struct x86_cpu_id crc32c_cpu_id[] = {
- X86_MATCH_FEATURE(X86_FEATURE_XMM4_2, NULL),
+ /*
+* Negative entries; exclude these chips from using this driver.
+* They match the positive rule below, but their CRC32 instruction
+* implementation is so slow, it doesn't merit use.
+*/
+ X86_MATCH_VENDOR_FAM_FEATURE(ZHAOXIN, 0x6, X86_FEATURE_XMM4_2, false),
+ X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x1b,
X86_FEATURE_XMM4_2, false),
+ X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x3b,
X86_FEATURE_XMM4_2, false),
+ X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 0x6, X86_FEATURE_XMM4_2, false),
+ X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x1b,
X86_FEATURE_XMM4_2, false),
+ X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x3b,
X86_FEATURE_XMM4_2, false),
+ /*
+* Positive entry; SSE-4.2 instructions include special purpose CRC32
+* instructions.
+*/
+ X86_MATCH_FEATURE(X86_FEATURE_XMM4_2, true),
{}
};
MODULE_DEVICE_TABLE(x86cpu, crc32c_cpu_id);
static int __init crc32c_intel_mod_init(void)
{
- if (!x86_match_cpu(crc32c_cpu_id))
+ const struct x86_cpu_id *m = x86_match_cpu(crc32c_cpu_id);
+
+ if (!m || !m->driver_data)
return -ENODEV;
#ifdef CONFIG_X86_64
if (boot_cpu_has(X86_FEATURE_PCLMULQDQ)) {
--
2.7.4
Re: [PATCH] crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs
On 15/12/2020 16:58, Peter Zijlstra wrote:
> On Mon, Dec 14, 2020 at 11:59:52AM +0800, Tony W Wang-oc wrote:
>
> Didn't I mention something about a comment?
>
Really sorry for this.
>> static const struct x86_cpu_id crc32c_cpu_id[] = {
>> +X86_MATCH_VENDOR_FAM_FEATURE(ZHAOXIN, 0x6, X86_FEATURE_XMM4_2, 1),
>> +X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x1b,
>> X86_FEATURE_XMM4_2, 1),
>> +X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x3b,
>> X86_FEATURE_XMM4_2, 1),
>> +X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 0x6, X86_FEATURE_XMM4_2, 1),
>> +X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x1b,
>> X86_FEATURE_XMM4_2, 1),
>> +X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x3b,
>> X86_FEATURE_XMM4_2, 1),
>> X86_MATCH_FEATURE(X86_FEATURE_XMM4_2, NULL),
>> {}
>
> Also, the above is weird in that is has the negative entries marked
> positive, and 1/NULL are inconsistent.
>
> Something like so then?
> That's better!
> ---
>
> diff --git a/arch/x86/crypto/crc32c-intel_glue.c
> b/arch/x86/crypto/crc32c-intel_glue.c
> index feccb5254c7e..f6e6669a5102 100644
> --- a/arch/x86/crypto/crc32c-intel_glue.c
> +++ b/arch/x86/crypto/crc32c-intel_glue.c
> @@ -215,14 +215,31 @@ static struct shash_alg alg = {
> };
>
> static const struct x86_cpu_id crc32c_cpu_id[] = {
> - X86_MATCH_FEATURE(X86_FEATURE_XMM4_2, NULL),
> + /*
> + * Negative entries; exclude these chips from using this driver.
> + * They match the positive rule below, but their CRC32 instruction
> + * implementation is so slow, it doesn't merrit use.
Will fix the typo merrit -> merit and resend the patch.
Sincerely
Tony
> + */
> + X86_MATCH_VENDOR_FAM_FEATURE(ZHAOXIN, 0x6, X86_FEATURE_XMM4_2, false),
> + X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x1b,
> X86_FEATURE_XMM4_2, false),
> + X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x3b,
> X86_FEATURE_XMM4_2, false),
> + X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 0x6, X86_FEATURE_XMM4_2, false),
> + X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x1b,
> X86_FEATURE_XMM4_2, false),
> + X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x3b,
> X86_FEATURE_XMM4_2, false),
> + /*
> + * Positive entry; SSE-4.2 instructions include special purpose CRC32
> + * instructions.
> + */
> + X86_MATCH_FEATURE(X86_FEATURE_XMM4_2, true),
> {}
> };
> MODULE_DEVICE_TABLE(x86cpu, crc32c_cpu_id);
>
> static int __init crc32c_intel_mod_init(void)
> {
> - if (!x86_match_cpu(crc32c_cpu_id))
> + const struct x86_cpu_id *m = x86_match_cpu(crc32c_cpu_id);
> +
> + if (!m || !m->driver_data)
> return -ENODEV;
> #ifdef CONFIG_X86_64
> if (boot_cpu_has(X86_FEATURE_PCLMULQDQ)) {
> .
>
Re: [PATCH] crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs
On 15/12/2020 04:41, Eric Biggers wrote: > On Mon, Dec 14, 2020 at 10:28:19AM +0800, Tony W Wang-oc wrote: >> On 12/12/2020 01:43, Eric Biggers wrote: >>> On Fri, Dec 11, 2020 at 07:29:04PM +0800, Tony W Wang-oc wrote: >>>> The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2. >>>> On platforms with Zhaoxin CPUs supporting this X86 feature, When >>>> crc32c-intel and crc32c-generic are both registered, system will >>>> use crc32c-intel because its .cra_priority is greater than >>>> crc32c-generic. This case expect to use crc32c-generic driver for >>>> some Zhaoxin CPUs to get performance gain, So remove these Zhaoxin >>>> CPUs support from crc32c-intel. >>>> >>>> Signed-off-by: Tony W Wang-oc >>> >>> Does this mean that the performance of the crc32c instruction on those CPUs >>> is >>> actually slower than a regular C implementation? That's very weird. >>> >> >> From the lmbench3 Create and Delete file test on those chips, I think yes. >> > > Did you try measuring the performance of the hashing itself, and not some > higher-level filesystem operations? > Yes. Was testing on these Zhaoxin CPUs, the result is that with the same input value the generic C implementation takes fewer time than the crc32c instruction implementation. Sincerely Tony
[PATCH] crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs
The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.
On platforms with Zhaoxin CPUs supporting this X86 feature, when
crc32c-intel and crc32c-generic are both registered, system will
use crc32c-intel because its .cra_priority is greater than
crc32c-generic.
When doing lmbench3 Create and Delete file test on partitions with
ext4 enabling metadata checksum, found using crc32c-generic driver
could get about 20% performance gain than using the driver crc32c-intel
on some Zhaoxin CPUs.
This case expect to use crc32c-generic driver for these Zhaoxin CPUs
to get performance gain, so remove these Zhaoxin CPUs support from
crc32c-intel.
Signed-off-by: Tony W Wang-oc
---
arch/x86/crypto/crc32c-intel_glue.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/x86/crypto/crc32c-intel_glue.c
b/arch/x86/crypto/crc32c-intel_glue.c
index feccb52..2cbbdde 100644
--- a/arch/x86/crypto/crc32c-intel_glue.c
+++ b/arch/x86/crypto/crc32c-intel_glue.c
@@ -215,6 +215,12 @@ static struct shash_alg alg = {
};
static const struct x86_cpu_id crc32c_cpu_id[] = {
+ X86_MATCH_VENDOR_FAM_FEATURE(ZHAOXIN, 0x6, X86_FEATURE_XMM4_2, 1),
+ X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x1b,
X86_FEATURE_XMM4_2, 1),
+ X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x3b,
X86_FEATURE_XMM4_2, 1),
+ X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 0x6, X86_FEATURE_XMM4_2, 1),
+ X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x1b,
X86_FEATURE_XMM4_2, 1),
+ X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x3b,
X86_FEATURE_XMM4_2, 1),
X86_MATCH_FEATURE(X86_FEATURE_XMM4_2, NULL),
{}
};
@@ -222,7 +228,9 @@ MODULE_DEVICE_TABLE(x86cpu, crc32c_cpu_id);
static int __init crc32c_intel_mod_init(void)
{
- if (!x86_match_cpu(crc32c_cpu_id))
+ const struct x86_cpu_id *m = x86_match_cpu(crc32c_cpu_id);
+
+ if (!m || m->driver_data)
return -ENODEV;
#ifdef CONFIG_X86_64
if (boot_cpu_has(X86_FEATURE_PCLMULQDQ)) {
--
2.7.4
Re: [PATCH] crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs
On 12/12/2020 18:54, Ard Biesheuvel wrote: > On Sat, 12 Dec 2020 at 10:36, Ard Biesheuvel wrote: >> >> On Fri, 11 Dec 2020 at 20:07, Eric Biggers wrote: >>> >>> On Fri, Dec 11, 2020 at 07:29:04PM +0800, Tony W Wang-oc wrote: >>>> The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2. >>>> On platforms with Zhaoxin CPUs supporting this X86 feature, When >>>> crc32c-intel and crc32c-generic are both registered, system will >>>> use crc32c-intel because its .cra_priority is greater than >>>> crc32c-generic. This case expect to use crc32c-generic driver for >>>> some Zhaoxin CPUs to get performance gain, So remove these Zhaoxin >>>> CPUs support from crc32c-intel. >>>> >>>> Signed-off-by: Tony W Wang-oc >>> >>> Does this mean that the performance of the crc32c instruction on those CPUs >>> is >>> actually slower than a regular C implementation? That's very weird. >>> >> >> This driver does not use CRC instructions, but carryless >> multiplication and aggregation. So I suppose the pclmulqdq instruction >> triggers some pathological performance limitation here. >> > > Just noticed it uses both crc instructions and pclmulqdq instructions. > Sorry for the noise. > >> That means the crct10dif driver probably needs the same treatment. > > Tony, can you confirm that the problem is in the CRC instructions and > not in the PCLMULQDQ code path that supersedes it when available? CRC instructions. sincerely Tony
Re: [PATCH] crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs
On 12/12/2020 01:43, Eric Biggers wrote: > On Fri, Dec 11, 2020 at 07:29:04PM +0800, Tony W Wang-oc wrote: >> The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2. >> On platforms with Zhaoxin CPUs supporting this X86 feature, When >> crc32c-intel and crc32c-generic are both registered, system will >> use crc32c-intel because its .cra_priority is greater than >> crc32c-generic. This case expect to use crc32c-generic driver for >> some Zhaoxin CPUs to get performance gain, So remove these Zhaoxin >> CPUs support from crc32c-intel. >> >> Signed-off-by: Tony W Wang-oc > > Does this mean that the performance of the crc32c instruction on those CPUs is > actually slower than a regular C implementation? That's very weird. > >From the lmbench3 Create and Delete file test on those chips, I think yes. sincerely Tony
Re: [PATCH] crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs
On 11/12/2020 21:00, Peter Zijlstra wrote:
> On Fri, Dec 11, 2020 at 07:29:04PM +0800, Tony W Wang-oc wrote:
>> The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.
>> On platforms with Zhaoxin CPUs supporting this X86 feature, When
>> crc32c-intel and crc32c-generic are both registered, system will
>> use crc32c-intel because its .cra_priority is greater than
>> crc32c-generic. This case expect to use crc32c-generic driver for
>> some Zhaoxin CPUs to get performance gain, So remove these Zhaoxin
>> CPUs support from crc32c-intel.
>>
>> Signed-off-by: Tony W Wang-oc
>> ---
>> arch/x86/crypto/crc32c-intel_glue.c | 8
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/x86/crypto/crc32c-intel_glue.c
>> b/arch/x86/crypto/crc32c-intel_glue.c
>> index feccb52..6dafdae 100644
>> --- a/arch/x86/crypto/crc32c-intel_glue.c
>> +++ b/arch/x86/crypto/crc32c-intel_glue.c
>> @@ -222,8 +222,16 @@ MODULE_DEVICE_TABLE(x86cpu, crc32c_cpu_id);
>>
>> static int __init crc32c_intel_mod_init(void)
>> {
>> +struct cpuinfo_x86 *c = _cpu_data;
>> +
>> if (!x86_match_cpu(crc32c_cpu_id))
>> return -ENODEV;
>> +
>> +if (c->x86_vendor == X86_VENDOR_ZHAOXIN || c->x86_vendor ==
>> X86_VENDOR_CENTAUR) {
>> +if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b))
>> +return -ENODEV;
>> +}
>
> Egads, why can't you use that x86_match_cpu() above, and also this
> really wants a comment on why you're excluding these chips.
When doing lmbench3 Create and Delete file test on partitions with ext4
enabling metadata checksum, found using crc32c-generic driver could get
about 20% performance gain than using the driver crc32c-intel on these
chips.
Also, since
> (IIRC) ZHAOXIN is basically AND, shouldn't they also be listed?
>
> That is; write it like:
>
> m = x86_match_cpu(crc32_cpu_id);
> if (!m || !m->data)
> return -ENODEV;
>
> That way you can have positive and negative matches in the array
> (obviously the existing FEATURE test would need data=1 and be last).
> .
>
Lot thanks for you suggestion, will list these chips in crc32c_cpu_id
and use x86_match_cpu:
static const struct x86_cpu_id crc32c_cpu_id[] = {
+ X86_MATCH_VENDOR_FAM_FEATURE(ZHAOXIN, 0x6, X86_FEATURE_XMM4_2, 1),
+ X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x1b,
X86_FEATURE_XMM4_2, 1),
+ X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x3b,
X86_FEATURE_XMM4_2, 1),
+ X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 0x6, X86_FEATURE_XMM4_2, 1),
+ X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x1b,
X86_FEATURE_XMM4_2, 1),
+ X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x3b,
X86_FEATURE_XMM4_2, 1),
X86_MATCH_FEATURE(X86_FEATURE_XMM4_2, NULL),
{}
};
@@ -228,8 +234,10 @@ MODULE_DEVICE_TABLE(x86cpu, crc32c_cpu_id);
static int __init crc32c_intel_mod_init(void)
{
- if (!x86_match_cpu(crc32c_cpu_id))
+ const struct x86_cpu_id *m = x86_match_cpu(crc32c_cpu_id);
+ if (!m || m->driver_data)
return -ENODEV;
sincerely
TonyWWangoc
[PATCH] crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs
The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.
On platforms with Zhaoxin CPUs supporting this X86 feature, When
crc32c-intel and crc32c-generic are both registered, system will
use crc32c-intel because its .cra_priority is greater than
crc32c-generic. This case expect to use crc32c-generic driver for
some Zhaoxin CPUs to get performance gain, So remove these Zhaoxin
CPUs support from crc32c-intel.
Signed-off-by: Tony W Wang-oc
---
arch/x86/crypto/crc32c-intel_glue.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/x86/crypto/crc32c-intel_glue.c
b/arch/x86/crypto/crc32c-intel_glue.c
index feccb52..6dafdae 100644
--- a/arch/x86/crypto/crc32c-intel_glue.c
+++ b/arch/x86/crypto/crc32c-intel_glue.c
@@ -222,8 +222,16 @@ MODULE_DEVICE_TABLE(x86cpu, crc32c_cpu_id);
static int __init crc32c_intel_mod_init(void)
{
+ struct cpuinfo_x86 *c = _cpu_data;
+
if (!x86_match_cpu(crc32c_cpu_id))
return -ENODEV;
+
+ if (c->x86_vendor == X86_VENDOR_ZHAOXIN || c->x86_vendor ==
X86_VENDOR_CENTAUR) {
+ if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b))
+ return -ENODEV;
+ }
+
#ifdef CONFIG_X86_64
if (boot_cpu_has(X86_FEATURE_PCLMULQDQ)) {
alg.update = crc32c_pcl_intel_update;
--
2.7.4
[tip: x86/cpu] x86/cpu/centaur: Add Centaur family >=7 CPUs initialization support
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: 33b4711df4c1b3aec7c267c60fc24abccfadd40c
Gitweb:
https://git.kernel.org/tip/33b4711df4c1b3aec7c267c60fc24abccfadd40c
Author:Tony W Wang-oc
AuthorDate:Tue, 08 Sep 2020 18:57:46 +08:00
Committer: Borislav Petkov
CommitterDate: Fri, 11 Sep 2020 10:53:19 +02:00
x86/cpu/centaur: Add Centaur family >=7 CPUs initialization support
Add Centaur family >=7 CPUs specific initialization support.
Signed-off-by: Tony W Wang-oc
Signed-off-by: Borislav Petkov
Link:
https://lkml.kernel.org/r/1599562666-31351-3-git-send-email-tonywwang...@zhaoxin.com
---
arch/x86/kernel/cpu/centaur.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 5f81158..345f7d9 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -65,6 +65,9 @@ static void init_c3(struct cpuinfo_x86 *c)
c->x86_cache_alignment = c->x86_clflush_size * 2;
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
}
+
+ if (c->x86 >= 7)
+ set_cpu_cap(c, X86_FEATURE_REP_GOOD);
}
enum {
@@ -95,7 +98,8 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
if (c->x86 == 5)
set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
#endif
- if (c->x86 == 6 && c->x86_model >= 0xf)
+ if ((c->x86 == 6 && c->x86_model >= 0xf) ||
+ (c->x86 >= 7))
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
#ifdef CONFIG_X86_64
@@ -204,7 +208,7 @@ static void init_centaur(struct cpuinfo_x86 *c)
sprintf(c->x86_model_id, "WinChip %s", name);
}
#endif
- if (c->x86 == 6)
+ if (c->x86 == 6 || c->x86 >= 7)
init_c3(c);
#ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
[tip: x86/cpu] x86/cpu/centaur: Replace two-condition switch-case with an if statement
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: 8687bdc04128b2bd16faaae11db10128ad0da7b8
Gitweb:
https://git.kernel.org/tip/8687bdc04128b2bd16faaae11db10128ad0da7b8
Author:Tony W Wang-oc
AuthorDate:Tue, 08 Sep 2020 18:57:45 +08:00
Committer: Borislav Petkov
CommitterDate: Fri, 11 Sep 2020 10:50:01 +02:00
x86/cpu/centaur: Replace two-condition switch-case with an if statement
Use a normal if statements instead of a two-condition switch-case.
[ bp: Massage commit message. ]
Signed-off-by: Tony W Wang-oc
Signed-off-by: Borislav Petkov
Link:
https://lkml.kernel.org/r/1599562666-31351-2-git-send-email-tonywwang...@zhaoxin.com
---
arch/x86/kernel/cpu/centaur.c | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index c5cf336..5f81158 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -90,18 +90,14 @@ enum {
static void early_init_centaur(struct cpuinfo_x86 *c)
{
- switch (c->x86) {
#ifdef CONFIG_X86_32
- case 5:
- /* Emulate MTRRs using Centaur's MCR. */
+ /* Emulate MTRRs using Centaur's MCR. */
+ if (c->x86 == 5)
set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
- break;
#endif
- case 6:
- if (c->x86_model >= 0xf)
- set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
- break;
- }
+ if (c->x86 == 6 && c->x86_model >= 0xf)
+ set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+
#ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_SYSENTER32);
#endif
@@ -145,9 +141,8 @@ static void init_centaur(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
}
- switch (c->x86) {
#ifdef CONFIG_X86_32
- case 5:
+ if (c->x86 == 5) {
switch (c->x86_model) {
case 4:
name = "C6";
@@ -207,12 +202,10 @@ static void init_centaur(struct cpuinfo_x86 *c)
c->x86_cache_size = (cc>>24)+(dd>>24);
}
sprintf(c->x86_model_id, "WinChip %s", name);
- break;
+ }
#endif
- case 6:
+ if (c->x86 == 6)
init_c3(c);
- break;
- }
#ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
#endif
[PATCH v1 1/2] x86/cpu: replace two-condition switch-case with if statement
Use if-case instead two-condition switch-case.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/centaur.c | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index c5cf336..5f811586 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -90,18 +90,14 @@ enum {
static void early_init_centaur(struct cpuinfo_x86 *c)
{
- switch (c->x86) {
#ifdef CONFIG_X86_32
- case 5:
- /* Emulate MTRRs using Centaur's MCR. */
+ /* Emulate MTRRs using Centaur's MCR. */
+ if (c->x86 == 5)
set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
- break;
#endif
- case 6:
- if (c->x86_model >= 0xf)
- set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
- break;
- }
+ if (c->x86 == 6 && c->x86_model >= 0xf)
+ set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+
#ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_SYSENTER32);
#endif
@@ -145,9 +141,8 @@ static void init_centaur(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
}
- switch (c->x86) {
#ifdef CONFIG_X86_32
- case 5:
+ if (c->x86 == 5) {
switch (c->x86_model) {
case 4:
name = "C6";
@@ -207,12 +202,10 @@ static void init_centaur(struct cpuinfo_x86 *c)
c->x86_cache_size = (cc>>24)+(dd>>24);
}
sprintf(c->x86_model_id, "WinChip %s", name);
- break;
+ }
#endif
- case 6:
+ if (c->x86 == 6)
init_c3(c);
- break;
- }
#ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
#endif
--
2.7.4
[PATCH v1 2/2] x86/cpu: add Centaur Family >=7 CPUs initialization support
add Centaur Family >=7 CPUs specific initialization support in centaur.c
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/centaur.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 5f811586..345f7d9 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -65,6 +65,9 @@ static void init_c3(struct cpuinfo_x86 *c)
c->x86_cache_alignment = c->x86_clflush_size * 2;
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
}
+
+ if (c->x86 >= 7)
+ set_cpu_cap(c, X86_FEATURE_REP_GOOD);
}
enum {
@@ -95,7 +98,8 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
if (c->x86 == 5)
set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
#endif
- if (c->x86 == 6 && c->x86_model >= 0xf)
+ if ((c->x86 == 6 && c->x86_model >= 0xf) ||
+ (c->x86 >= 7))
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
#ifdef CONFIG_X86_64
@@ -204,7 +208,7 @@ static void init_centaur(struct cpuinfo_x86 *c)
sprintf(c->x86_model_id, "WinChip %s", name);
}
#endif
- if (c->x86 == 6)
+ if (c->x86 == 6 || c->x86 >= 7)
init_c3(c);
#ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
--
2.7.4
[PATCH v1 0/2] add Centaur Family >= 7 CPUs support
New Centaur CPUs have Family >= 7. So, add specific initialization for these CPUs in centaur.c In order to handle Family >= 7, also use if instead two-condition switch-case in centaur.c Tony W Wang-oc (2): x86/cpu: replace two-condition switch-case with if statement x86/cpu: add Centaur Family >=7 CPUs initialization support arch/x86/kernel/cpu/centaur.c | 27 --- 1 file changed, 12 insertions(+), 15 deletions(-) -- 2.7.4
Re: [PATCH] x86/cpufeatures: Add new Zhaoxin CPU features
On 07/07/2020 00:02, Luck, Tony wrote: > On Mon, Jun 29, 2020 at 07:21:29PM +0800, Tony W Wang-oc wrote: >> Add new Zhaoxin CPU features for enumeration in /proc/cpuinfo: >> SM2, SM2_EN, SM3, SM4, SM3_EN, SM4_EN, PARALLAX, PARALLAX_EN, >> TM3, TM3_EN, RNG2, RNG2_EN, PHE2, PHE2_EN, RSA, RSA_EN. >> >> CPUID.(EAX=0xc001,ECX=0):EDX[bit 0] SM2 >> CPUID.(EAX=0xc001,ECX=0):EDX[bit 1] SM2_EN >> CPUID.(EAX=0xc001,ECX=0):EDX[bit 4] SM3 SM4 >> CPUID.(EAX=0xc001,ECX=0):EDX[bit 5] SM3_EN SM4_EN >> CPUID.(EAX=0xc001,ECX=0):EDX[bit 16] PARALLAX >> CPUID.(EAX=0xc001,ECX=0):EDX[bit 17] PARALLAX_EN >> CPUID.(EAX=0xc001,ECX=0):EDX[bit 20] TM3 >> CPUID.(EAX=0xc001,ECX=0):EDX[bit 21] TM3_EN >> CPUID.(EAX=0xc001,ECX=0):EDX[bit 22] RNG2 >> CPUID.(EAX=0xc001,ECX=0):EDX[bit 23] RNG2_EN >> CPUID.(EAX=0xc001,ECX=0):EDX[bit 25] PHE2 >> CPUID.(EAX=0xc001,ECX=0):EDX[bit 26] PHE2_EN >> CPUID.(EAX=0xc001,ECX=0):EDX[bit 27] RSA >> CPUID.(EAX=0xc001,ECX=0):EDX[bit 28] RSA_EN >> >> SM2, SM3, SM4 are Chinese Cipher Security algorithm. >> PARALLAX is a feature that automatically adjusts processors's voltage >> as a function of temperature. >> TM3 is Zhaoxin CPU Thermal Monitor v3. >> RNG2 is Zhaoxin Random Number Generation v2. >> PHE2 is Zhaoxin Padlock Hash Engine v2. >> RSA is Zhaoxin hardware support for RSA algorithm. > > Boris is on vacation, so I'll ask the question that he would ask > if he were here ... "Are there some follow-up patches that use all > of these feature bits?" No for up to now. Sincerely TonyWWang-oc > > Just adding bits to /proc/cpuinfo is of limited use. > > -Tony > . >
[PATCH] x86/cpufeatures: Add new Zhaoxin CPU features
Add new Zhaoxin CPU features for enumeration in /proc/cpuinfo: SM2, SM2_EN, SM3, SM4, SM3_EN, SM4_EN, PARALLAX, PARALLAX_EN, TM3, TM3_EN, RNG2, RNG2_EN, PHE2, PHE2_EN, RSA, RSA_EN. CPUID.(EAX=0xc001,ECX=0):EDX[bit 0] SM2 CPUID.(EAX=0xc001,ECX=0):EDX[bit 1] SM2_EN CPUID.(EAX=0xc001,ECX=0):EDX[bit 4] SM3 SM4 CPUID.(EAX=0xc001,ECX=0):EDX[bit 5] SM3_EN SM4_EN CPUID.(EAX=0xc001,ECX=0):EDX[bit 16] PARALLAX CPUID.(EAX=0xc001,ECX=0):EDX[bit 17] PARALLAX_EN CPUID.(EAX=0xc001,ECX=0):EDX[bit 20] TM3 CPUID.(EAX=0xc001,ECX=0):EDX[bit 21] TM3_EN CPUID.(EAX=0xc001,ECX=0):EDX[bit 22] RNG2 CPUID.(EAX=0xc001,ECX=0):EDX[bit 23] RNG2_EN CPUID.(EAX=0xc001,ECX=0):EDX[bit 25] PHE2 CPUID.(EAX=0xc001,ECX=0):EDX[bit 26] PHE2_EN CPUID.(EAX=0xc001,ECX=0):EDX[bit 27] RSA CPUID.(EAX=0xc001,ECX=0):EDX[bit 28] RSA_EN SM2, SM3, SM4 are Chinese Cipher Security algorithm. PARALLAX is a feature that automatically adjusts processors's voltage as a function of temperature. TM3 is Zhaoxin CPU Thermal Monitor v3. RNG2 is Zhaoxin Random Number Generation v2. PHE2 is Zhaoxin Padlock Hash Engine v2. RSA is Zhaoxin hardware support for RSA algorithm. Signed-off-by: Tony W Wang-oc --- arch/x86/include/asm/cpufeatures.h | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index c693ebf..a6c2d2b 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -145,9 +145,13 @@ #define X86_FEATURE_RDRAND ( 4*32+30) /* RDRAND instruction */ #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ -/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC001, word 5 */ +/* VIA/Cyrix/Centaur/Zhaoxin-defined CPU features, CPUID level 0xC001, word 5 */ +#define X86_FEATURE_SM2( 5*32+ 0) /* Chinese cipher security hardware support of SM2 */ +#define X86_FEATURE_SM2_EN ( 5*32+ 1) /* SM2 enabled */ #define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ #define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ +#define X86_FEATURE_CCS( 5*32+ 4) /* "sm3 sm4" Chinese Cipher Security hardware support*/ +#define X86_FEATURE_CCS_EN ( 5*32+ 5) /* "sm3_en sm4_en" sm3 sm4 enabled */ #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ #define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ @@ -156,6 +160,16 @@ #define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ #define X86_FEATURE_PMM( 5*32+12) /* PadLock Montgomery Multiplier */ #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ +#define X86_FEATURE_PARALLAX ( 5*32+16) /* Parallax auto adjust processor voltage */ +#define X86_FEATURE_PARALLAX_EN( 5*32+17) /* Parallax auto adjust processor voltage enabled */ +#define X86_FEATURE_TM3( 5*32+20) /* Thermal Monitor v3 support */ +#define X86_FEATURE_TM3_EN ( 5*32+21) /* TM3 enabled */ +#define X86_FEATURE_RNG2 ( 5*32+22) /* RNG v2 present */ +#define X86_FEATURE_RNG2_EN( 5*32+23) /* RNG v2 enabled */ +#define X86_FEATURE_PHE2 ( 5*32+25) /* PHE v2 present */ +#define X86_FEATURE_PHE2_EN( 5*32+26) /* PHE v2 enabled */ +#define X86_FEATURE_RSA( 5*32+27) /* RSA hardware support */ +#define X86_FEATURE_RSA_EN ( 5*32+28) /* RSA enabled */ /* More extended AMD flags: CPUID level 0x8001, ECX, word 6 */ #define X86_FEATURE_LAHF_LM( 6*32+ 0) /* LAHF/SAHF in long mode */ -- 2.7.4
Re: [PATCH 10/16] x86/cpu: Detect VMX features on Intel, Centaur and Zhaoxin CPUs
On Sat, Oct 5, 2019, Sean Christopherson wrote:
>Add an entry in struct cpuinfo_x86 to track VMX capabilities and fill
>the capabilities during IA32_FEATURE_CONTROL MSR initialization.
>
>Make the VMX capabilities dependent on X86_INTEL_FEATURE_CONTROL and
>X86_FEATURE_NAMES so as to avoid unnecessary overhead on CPUs that
>can't
>possibly support VMX, or when /proc/cpuinfo is not available.
>
>Signed-off-by: Sean Christopherson
>---
> arch/x86/Kconfig.cpu | 4 ++
> arch/x86/include/asm/processor.h | 3 ++
> arch/x86/include/asm/vmxfeatures.h| 5 +++
> arch/x86/kernel/cpu/common.c | 3 ++
> arch/x86/kernel/cpu/feature_control.c | 59
>+++
> 5 files changed, 74 insertions(+)
>
>diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
>index e78f39adae7b..e7571bd0f515 100644
>--- a/arch/x86/Kconfig.cpu
>+++ b/arch/x86/Kconfig.cpu
>@@ -391,6 +391,10 @@ config X86_FEATURE_CONTROL_MSR
> def_bool y
> depends on CPU_SUP_INTEL || CPU_SUP_CENTAUR ||
>CPU_SUP_ZHAOXIN
>
>+config X86_VMX_FEATURE_NAMES
>+ def_bool y
>+ depends on X86_FEATURE_CONTROL_MSR &&
>X86_FEATURE_NAMES
>+
> menuconfig PROCESSOR_SELECT
> bool "Supported processor vendors" if EXPERT
> ---help---
>diff --git a/arch/x86/include/asm/processor.h
>b/arch/x86/include/asm/processor.h
>index 4c3f41d7be5f..3b5dc9b1e7c4 100644
>--- a/arch/x86/include/asm/processor.h
>+++ b/arch/x86/include/asm/processor.h
>@@ -84,6 +84,9 @@ struct cpuinfo_x86 {
> #ifdef CONFIG_X86_64
> /* Number of 4K pages in DTLB/ITLB combined(in pages): */
> int x86_tlbsize;
>+#endif
>+#ifdef CONFIG_X86_VMX_FEATURE_NAMES
>+ __u32 vmx_capability[NVMXINTS];
> #endif
> __u8x86_virt_bits;
> __u8x86_phys_bits;
>diff --git a/arch/x86/include/asm/vmxfeatures.h
>b/arch/x86/include/asm/vmxfeatures.h
>index ab82e3643d0c..d33ea1c165fd 100644
>--- a/arch/x86/include/asm/vmxfeatures.h
>+++ b/arch/x86/include/asm/vmxfeatures.h
>@@ -2,6 +2,11 @@
> #ifndef _ASM_X86_VMXFEATURES_H
> #define _ASM_X86_VMXFEATURES_H
>
>+/*
>+ * Defines VMX CPU feature bits
>+ */
>+#define NVMXINTS 3 /* N 32-bit words worth of info */
>+
> /*
> * Note: If the comment begins with a quoted string, that string is used
> * in /proc/cpuinfo instead of the macro name. If the string is "",
>diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
>index 9ae7d1bcd4f4..33537556dac6 100644
>--- a/arch/x86/kernel/cpu/common.c
>+++ b/arch/x86/kernel/cpu/common.c
>@@ -1421,6 +1421,9 @@ static void identify_cpu(struct cpuinfo_x86 *c)
> #endif
> c->x86_cache_alignment = c->x86_clflush_size;
> memset(>x86_capability, 0, sizeof(c->x86_capability));
>+#ifdef CONFIG_X86_VMX_FEATURE_NAMES
>+ memset(>vmx_capability, 0, sizeof(c->vmx_capability));
>+#endif
>
> generic_identify(c);
>
>diff --git a/arch/x86/kernel/cpu/feature_control.c
>b/arch/x86/kernel/cpu/feature_control.c
>index 74c76159a046..43eb65e8cd18 100644
>--- a/arch/x86/kernel/cpu/feature_control.c
>+++ b/arch/x86/kernel/cpu/feature_control.c
>@@ -4,6 +4,61 @@
> #include
> #include
> #include
>+#include
>+
>+#ifdef CONFIG_X86_VMX_FEATURE_NAMES
>+enum vmx_feature_leafs {
>+ MISC_FEATURES = 0,
>+ PRIMARY_PROC_CONTROLS,
>+ SECONDARY_PROC_CONTROLS,
>+ NR_VMX_FEATURE_WORDS,
>+};
>+
>+#define EPT_BIT(x) BIT(VMX_FEATURE_##x & 0x1f)
>+
>+static void init_vmx_capabilities(struct cpuinfo_x86 *c)
>+{
>+ u32 supported, funcs, ept, vpid, ign;
>+
>+ BUILD_BUG_ON(NVMXINTS != NR_VMX_FEATURE_WORDS);
>+
>+ /*
>+ * The high bits contain the allowed-1 settings, i.e. features that can
>+ * be turned on. The low bits contain the allowed-0 settings, i.e.
>+ * features that can be turned off. Ignore the allowed-0 settings,
>+ * if a feature can be turned on then it's supported.
>+ */
>+ rdmsr(MSR_IA32_VMX_PINBASED_CTLS, ign, supported);
>+ rdmsr_safe(MSR_IA32_VMX_VMFUNC, , );
>+
>+ /*
>+ * Except for EPT+VPID, which enumerates support for both in a single
>+ * MSR, low for EPT, high for VPID.
>+ */
>+ rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, , );
>+
>+ /* Pin, EPT, VPID and VM-Func are merged into a single word. */
>+ WARN_ON_ONCE(supported >> 16);
>+ WARN_ON_ONCE(funcs >> 4);
>+ c->vmx_capability[MISC_FEATURES] = (supported & 0x) |
>+ ((vpid & 0x1) << 24) |
>+ ((funcs & 0xf) << 28);
>+
>+ /* EPT bits are scattered and must be manually handled. */
>+ if (ept & VMX_EPT_EXECUTE_ONLY_BIT)
>+ c->vmx_capability[MISC_FEATURES] |=
>EPT_BIT(EPT_EXECUTE_ONLY);
>+ if (ept & VMX_EPT_1GB_PAGE_BIT)
Typo? Should be: if (ept & VMX_EPT_AD_BIT)
TonyWWang-oc
>+ c->vmx_capability[MISC_FEATURES] |= EPT_BIT(EPT_AD);
>+
[tip: ras/core] x86/mce: Add Zhaoxin MCE support
The following commit has been merged into the ras/core branch of tip:
Commit-ID: 6e898d2bf67a82df0aa0c955adc9278faba9a635
Gitweb:
https://git.kernel.org/tip/6e898d2bf67a82df0aa0c955adc9278faba9a635
Author:Tony W Wang-oc
AuthorDate:Wed, 18 Sep 2019 14:19:30 +08:00
Committer: Borislav Petkov
CommitterDate: Tue, 01 Oct 2019 12:32:27 +02:00
x86/mce: Add Zhaoxin MCE support
All newer Zhaoxin CPUs are compatible with Intel's Machine-Check
Architecture, so add support for them.
[ bp: Reflow comment in vendor_disable_error_reporting() and massage
commit message. ]
Signed-off-by: Tony W Wang-oc
Signed-off-by: Borislav Petkov
Cc: cooper...@zhaoxin.com
Cc: davidw...@zhaoxin.com
Cc: herryy...@zhaoxin.com
Cc: "H. Peter Anvin"
Cc: Ingo Molnar
Cc: linux-edac
Cc: qiyuanw...@zhaoxin.com
Cc: Thomas Gleixner
Cc: Tony Luck
Cc: x86-ml
Link:
https://lkml.kernel.org/r/1568787573-1297-2-git-send-email-tonywwang...@zhaoxin.com
---
arch/x86/kernel/cpu/mce/core.c | 44 +++--
1 file changed, 31 insertions(+), 13 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 743370e..a780fe0 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -488,8 +488,9 @@ int mce_usable_address(struct mce *m)
if (!(m->status & MCI_STATUS_ADDRV))
return 0;
- /* Checks after this one are Intel-specific: */
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ /* Checks after this one are Intel/Zhaoxin-specific: */
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 1;
if (!(m->status & MCI_STATUS_MISCV))
@@ -507,10 +508,13 @@ EXPORT_SYMBOL_GPL(mce_usable_address);
bool mce_is_memory_error(struct mce *m)
{
- if (m->cpuvendor == X86_VENDOR_AMD ||
- m->cpuvendor == X86_VENDOR_HYGON) {
+ switch (m->cpuvendor) {
+ case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
return amd_mce_is_memory_error(m);
- } else if (m->cpuvendor == X86_VENDOR_INTEL) {
+
+ case X86_VENDOR_INTEL:
+ case X86_VENDOR_ZHAOXIN:
/*
* Intel SDM Volume 3B - 15.9.2 Compound Error Codes
*
@@ -527,9 +531,10 @@ bool mce_is_memory_error(struct mce *m)
return (m->status & 0xef80) == BIT(7) ||
(m->status & 0xef00) == BIT(8) ||
(m->status & 0xeffc) == 0xc;
- }
- return false;
+ default:
+ return false;
+ }
}
EXPORT_SYMBOL_GPL(mce_is_memory_error);
@@ -1697,6 +1702,18 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c)
if (c->x86 == 6 && c->x86_model == 45)
quirk_no_way_out = quirk_sandybridge_ifu;
}
+
+ if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
+ /*
+* All newer Zhaoxin CPUs support MCE broadcasting. Enable
+* synchronization with a one second timeout.
+*/
+ if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model ==
0x1f)) {
+ if (cfg->monarch_timeout < 0)
+ cfg->monarch_timeout = USEC_PER_SEC;
+ }
+ }
+
if (cfg->monarch_timeout < 0)
cfg->monarch_timeout = 0;
if (cfg->bootlog != 0)
@@ -2014,15 +2031,16 @@ static void mce_disable_error_reporting(void)
static void vendor_disable_error_reporting(void)
{
/*
-* Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs
-* are socket-wide.
-* Disabling them for just a single offlined CPU is bad, since it will
-* inhibit reporting for all shared resources on the socket like the
-* last level cache (LLC), the integrated memory controller (iMC), etc.
+* Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
+* MSRs are socket-wide. Disabling them for just a single offlined CPU
+* is bad, since it will inhibit reporting for all shared resources on
+* the socket like the last level cache (LLC), the integrated memory
+* controller (iMC), etc.
*/
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
- boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+ boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
return;
mce_disable_error_reporting();
[tip: ras/core] x86/mce: Add Zhaoxin CMCI support
The following commit has been merged into the ras/core branch of tip:
Commit-ID: 5a3d56a034be9e8e87a6cb9ed3f2928184db1417
Gitweb:
https://git.kernel.org/tip/5a3d56a034be9e8e87a6cb9ed3f2928184db1417
Author:Tony W Wang-oc
AuthorDate:Wed, 18 Sep 2019 14:19:32 +08:00
Committer: Borislav Petkov
CommitterDate: Tue, 01 Oct 2019 12:33:09 +02:00
x86/mce: Add Zhaoxin CMCI support
All newer Zhaoxin CPUs support CMCI and are compatible with Intel's
Machine-Check Architecture. Add that support for Zhaoxin CPUs.
[ bp: Massage comments and export intel_init_cmci(). ]
Signed-off-by: Tony W Wang-oc
Signed-off-by: Borislav Petkov
Cc: cooper...@zhaoxin.com
Cc: davidw...@zhaoxin.com
Cc: herryy...@zhaoxin.com
Cc: "H. Peter Anvin"
Cc: Ingo Molnar
Cc: linux-edac
Cc: qiyuanw...@zhaoxin.com
Cc: Thomas Gleixner
Cc: Tony Luck
Cc: x86-ml
Link:
https://lkml.kernel.org/r/1568787573-1297-4-git-send-email-tonywwang...@zhaoxin.com
---
arch/x86/kernel/cpu/mce/core.c | 27 +++
arch/x86/kernel/cpu/mce/intel.c| 6 --
arch/x86/kernel/cpu/mce/internal.h | 2 ++
3 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index a780fe0..1e6b8a4 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1777,6 +1777,29 @@ static void mce_centaur_feature_init(struct cpuinfo_x86
*c)
}
}
+static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
+{
+ struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
+
+ /*
+* These CPUs have MCA bank 8 which reports only one error type called
+* SVAD (System View Address Decoder). The reporting of that error is
+* controlled by IA32_MC8.CTL.0.
+*
+* If enabled, prefetching on these CPUs will cause SVAD MCE when
+* virtual machines start and result in a system panic. Always disable
+* bank 8 SVAD error by default.
+*/
+ if ((c->x86 == 7 && c->x86_model == 0x1b) ||
+ (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
+ if (this_cpu_read(mce_num_banks) > 8)
+ mce_banks[8].ctl = 0;
+ }
+
+ intel_init_cmci();
+ mce_adjust_timer = cmci_intel_adjust_timer;
+}
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1798,6 +1821,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c)
mce_centaur_feature_init(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_init(c);
+ break;
+
default:
break;
}
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 88cd959..fb6e990 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -85,8 +85,10 @@ static int cmci_supported(int *banks)
* initialization is vendor keyed and this
* makes sure none of the backdoors are entered otherwise.
*/
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 0;
+
if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)
return 0;
rdmsrl(MSR_IA32_MCG_CAP, cap);
@@ -423,7 +425,7 @@ void cmci_disable_bank(int bank)
raw_spin_unlock_irqrestore(_discover_lock, flags);
}
-static void intel_init_cmci(void)
+void intel_init_cmci(void)
{
int banks;
diff --git a/arch/x86/kernel/cpu/mce/internal.h
b/arch/x86/kernel/cpu/mce/internal.h
index 43031db..a7ee230 100644
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -45,11 +45,13 @@ unsigned long cmci_intel_adjust_timer(unsigned long
interval);
bool mce_intel_cmci_poll(void);
void mce_intel_hcpu_update(unsigned long cpu);
void cmci_disable_bank(int bank);
+void intel_init_cmci(void);
#else
# define cmci_intel_adjust_timer mce_adjust_timer_default
static inline bool mce_intel_cmci_poll(void) { return false; }
static inline void mce_intel_hcpu_update(unsigned long cpu) { }
static inline void cmci_disable_bank(int bank) { }
+static inline void intel_init_cmci(void) { }
#endif
void mce_timer_kick(unsigned long interval);
[tip: ras/core] x86/mce: Add Zhaoxin LMCE support
The following commit has been merged into the ras/core branch of tip:
Commit-ID: 70f0c230031dfef3c9b3e37b2a8c18d3f7186fb2
Gitweb:
https://git.kernel.org/tip/70f0c230031dfef3c9b3e37b2a8c18d3f7186fb2
Author:Tony W Wang-oc
AuthorDate:Wed, 18 Sep 2019 14:19:33 +08:00
Committer: Borislav Petkov
CommitterDate: Tue, 01 Oct 2019 12:33:33 +02:00
x86/mce: Add Zhaoxin LMCE support
Newer Zhaoxin CPUs support LMCE compatible with Intel. Add support for
that.
[ bp: Export functions and massage. ]
Signed-off-by: Tony W Wang-oc
Signed-off-by: Borislav Petkov
Cc: cooper...@zhaoxin.com
Cc: davidw...@zhaoxin.com
Cc: herryy...@zhaoxin.com
Cc: "H. Peter Anvin"
Cc: Ingo Molnar
Cc: linux-edac
Cc: qiyuanw...@zhaoxin.com
Cc: Thomas Gleixner
Cc: Tony Luck
Cc: x86-ml
Link:
https://lkml.kernel.org/r/1568787573-1297-5-git-send-email-tonywwang...@zhaoxin.com
---
arch/x86/kernel/cpu/mce/core.c | 22 --
arch/x86/kernel/cpu/mce/intel.c| 4 ++--
arch/x86/kernel/cpu/mce/internal.h | 4
3 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 1e6b8a4..5f42f25 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1132,6 +1132,12 @@ static bool __mc_check_crashing_cpu(int cpu)
u64 mcgstatus;
mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
+
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
+ if (mcgstatus & MCG_STATUS_LMCES)
+ return false;
+ }
+
if (mcgstatus & MCG_STATUS_RIPV) {
mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
return true;
@@ -1282,9 +1288,10 @@ void do_machine_check(struct pt_regs *regs, long
error_code)
/*
* Check if this MCE is signaled to only this logical processor,
-* on Intel only.
+* on Intel, Zhaoxin only.
*/
- if (m.cpuvendor == X86_VENDOR_INTEL)
+ if (m.cpuvendor == X86_VENDOR_INTEL ||
+ m.cpuvendor == X86_VENDOR_ZHAOXIN)
lmce = m.mcgstatus & MCG_STATUS_LMCES;
/*
@@ -1797,9 +1804,15 @@ static void mce_zhaoxin_feature_init(struct cpuinfo_x86
*c)
}
intel_init_cmci();
+ intel_init_lmce();
mce_adjust_timer = cmci_intel_adjust_timer;
}
+static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
+{
+ intel_clear_lmce();
+}
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1836,6 +1849,11 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86
*c)
case X86_VENDOR_INTEL:
mce_intel_feature_clear(c);
break;
+
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_clear(c);
+ break;
+
default:
break;
}
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index fb6e990..68a1d25 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -444,7 +444,7 @@ void intel_init_cmci(void)
cmci_recheck();
}
-static void intel_init_lmce(void)
+void intel_init_lmce(void)
{
u64 val;
@@ -457,7 +457,7 @@ static void intel_init_lmce(void)
wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);
}
-static void intel_clear_lmce(void)
+void intel_clear_lmce(void)
{
u64 val;
diff --git a/arch/x86/kernel/cpu/mce/internal.h
b/arch/x86/kernel/cpu/mce/internal.h
index a7ee230..842b273 100644
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -46,12 +46,16 @@ bool mce_intel_cmci_poll(void);
void mce_intel_hcpu_update(unsigned long cpu);
void cmci_disable_bank(int bank);
void intel_init_cmci(void);
+void intel_init_lmce(void);
+void intel_clear_lmce(void);
#else
# define cmci_intel_adjust_timer mce_adjust_timer_default
static inline bool mce_intel_cmci_poll(void) { return false; }
static inline void mce_intel_hcpu_update(unsigned long cpu) { }
static inline void cmci_disable_bank(int bank) { }
static inline void intel_init_cmci(void) { }
+static inline void intel_init_lmce(void) { }
+static inline void intel_clear_lmce(void) { }
#endif
void mce_timer_kick(unsigned long interval);
[PATCH v4 3/4] x86/mce: Add Zhaoxin CMCI support
All Zhaoxin newer CPUs support CMCI that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin CMCI in
mce/core.c and mce/intel.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 25 +
arch/x86/kernel/cpu/mce/intel.c | 5 -
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 7bcd8c1..65c5a1f 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1777,6 +1777,27 @@ static void mce_centaur_feature_init(struct cpuinfo_x86
*c)
}
}
+static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
+{
+ struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
+
+ /*
+* These CPUs have MCA bank 8, that only has one error called SVAD
+* (System View Address Decoder) which be controlled by IA32_MC8.CTL.0
+* If enabled, the prefetch on these CPUs will cause SVAD machine
+* check exception when virtual machine startup and cause system
+* panic. Always disable bank 8 SVAD error by default.
+*/
+ if ((c->x86 == 7 && c->x86_model == 0x1b) ||
+ (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
+ if (this_cpu_read(mce_num_banks) > 8)
+ mce_banks[8].ctl = 0;
+ }
+
+ intel_init_cmci();
+ mce_adjust_timer = cmci_intel_adjust_timer;
+}
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1798,6 +1819,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c)
mce_centaur_feature_init(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_init(c);
+ break;
+
default:
break;
}
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 70799a5..87c473f 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -84,9 +84,12 @@ static int cmci_supported(int *banks)
* Vendor check is not strictly needed, but the initial
* initialization is vendor keyed and this
* makes sure none of the backdoors are entered otherwise.
+* Checks the vendor are Intel/Zhaoxin-specific:
*/
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 0;
+
if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)
return 0;
rdmsrl(MSR_IA32_MCG_CAP, cap);
--
2.7.4
[PATCH v4 0/4] x86/mce: Add supports for Zhaoxin MCA
Zhaoxin newer CPUs support MCE, CMCI and LMCE that compatible with Intel's "Machine-Check Architecture". To enable the supports of Linux kernel to Zhaoxin's MCA, add specific patches for Zhaoxin's MCE, CMCI and LMCE. patches about Zhaoxin's CMCI, LMCE use 3 functions in mce/intel.c, so make these functions non-static. Some Zhaoxin's CPUs have MCA bank 8, that only has one error called SVAD (System View Address Decoder) which be controlled by IA32_MC8.CTL.0. If enabled, the prefetch on these CPUs will cause SVAD machine check exception when virtual machine startup and cause system panic. Add a quirk for these Zhaoxin CPUs MCA bank 8. v3->v4: - remove redundant if-case test (patch 4/4) v2->v3: - Make ifelse-case to switch-case (patch 1/4) - Simplify Zhaoxin CPU FMS checking (patch 1/4, 3/4) - Revert 1 unused function intel_ppin_init() (patch 2/4) - Rework mce_zhaoxin_feature_init() as static (patch 3/4) - Rework comment about Zhaoxin MCA SVAD and CMCI (patch 3/4) - Rework mce_zhaoxin_feature_clear() as static (patch 4/4) - Add comment and change coding style (patch 4/4) v1->v2: - Fix redefinition of "mce_zhaoxin_feature_init" (patch 3/4) - Fix redefinition of "mce_zhaoxin_feature_clear" (patch 4/4) Tony W Wang-oc (4): x86/mce: Add Zhaoxin MCE support x86/mce: Make 3 functions non-static x86/mce: Add Zhaoxin CMCI support x86/mce: Add Zhaoxin LMCE support arch/x86/kernel/cpu/mce/core.c | 83 -- arch/x86/kernel/cpu/mce/intel.c| 11 +++-- arch/x86/kernel/cpu/mce/internal.h | 6 +++ 3 files changed, 84 insertions(+), 16 deletions(-) -- 2.7.4
[PATCH v4 1/4] x86/mce: Add Zhaoxin MCE support
All Zhaoxin newer CPUs support MCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin MCE in
mce/core.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 38 --
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 743370e..7bcd8c1 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -488,8 +488,9 @@ int mce_usable_address(struct mce *m)
if (!(m->status & MCI_STATUS_ADDRV))
return 0;
- /* Checks after this one are Intel-specific: */
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ /* Checks after this one are Intel/Zhaoxin-specific: */
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 1;
if (!(m->status & MCI_STATUS_MISCV))
@@ -507,10 +508,13 @@ EXPORT_SYMBOL_GPL(mce_usable_address);
bool mce_is_memory_error(struct mce *m)
{
- if (m->cpuvendor == X86_VENDOR_AMD ||
- m->cpuvendor == X86_VENDOR_HYGON) {
+ switch (m->cpuvendor) {
+ case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
return amd_mce_is_memory_error(m);
- } else if (m->cpuvendor == X86_VENDOR_INTEL) {
+
+ case X86_VENDOR_INTEL:
+ case X86_VENDOR_ZHAOXIN:
/*
* Intel SDM Volume 3B - 15.9.2 Compound Error Codes
*
@@ -527,9 +531,10 @@ bool mce_is_memory_error(struct mce *m)
return (m->status & 0xef80) == BIT(7) ||
(m->status & 0xef00) == BIT(8) ||
(m->status & 0xeffc) == 0xc;
- }
- return false;
+ default:
+ return false;
+ }
}
EXPORT_SYMBOL_GPL(mce_is_memory_error);
@@ -1697,6 +1702,18 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c)
if (c->x86 == 6 && c->x86_model == 45)
quirk_no_way_out = quirk_sandybridge_ifu;
}
+
+ if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
+ /*
+* All newer Zhaoxin CPUs support MCE broadcasting. Enable
+* synchronization with a one second timeout.
+*/
+ if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model ==
0x1f)) {
+ if (cfg->monarch_timeout < 0)
+ cfg->monarch_timeout = USEC_PER_SEC;
+ }
+ }
+
if (cfg->monarch_timeout < 0)
cfg->monarch_timeout = 0;
if (cfg->bootlog != 0)
@@ -2014,15 +2031,16 @@ static void mce_disable_error_reporting(void)
static void vendor_disable_error_reporting(void)
{
/*
-* Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs
-* are socket-wide.
+* Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
+* MSRs are socket-wide.
* Disabling them for just a single offlined CPU is bad, since it will
* inhibit reporting for all shared resources on the socket like the
* last level cache (LLC), the integrated memory controller (iMC), etc.
*/
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
- boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+ boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
return;
mce_disable_error_reporting();
--
2.7.4
[PATCH v4 2/4] x86/mce: Make 3 functions non-static
These functions are declared static and cannot be used in others
.c source file. this commit removes the static attribute and adds
the declaration to the header for these functions.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/intel.c| 6 +++---
arch/x86/kernel/cpu/mce/internal.h | 6 ++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 88cd959..70799a5 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -423,7 +423,7 @@ void cmci_disable_bank(int bank)
raw_spin_unlock_irqrestore(_discover_lock, flags);
}
-static void intel_init_cmci(void)
+void intel_init_cmci(void)
{
int banks;
@@ -442,7 +442,7 @@ static void intel_init_cmci(void)
cmci_recheck();
}
-static void intel_init_lmce(void)
+void intel_init_lmce(void)
{
u64 val;
@@ -455,7 +455,7 @@ static void intel_init_lmce(void)
wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);
}
-static void intel_clear_lmce(void)
+void intel_clear_lmce(void)
{
u64 val;
diff --git a/arch/x86/kernel/cpu/mce/internal.h
b/arch/x86/kernel/cpu/mce/internal.h
index 43031db..842b273 100644
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -45,11 +45,17 @@ unsigned long cmci_intel_adjust_timer(unsigned long
interval);
bool mce_intel_cmci_poll(void);
void mce_intel_hcpu_update(unsigned long cpu);
void cmci_disable_bank(int bank);
+void intel_init_cmci(void);
+void intel_init_lmce(void);
+void intel_clear_lmce(void);
#else
# define cmci_intel_adjust_timer mce_adjust_timer_default
static inline bool mce_intel_cmci_poll(void) { return false; }
static inline void mce_intel_hcpu_update(unsigned long cpu) { }
static inline void cmci_disable_bank(int bank) { }
+static inline void intel_init_cmci(void) { }
+static inline void intel_init_lmce(void) { }
+static inline void intel_clear_lmce(void) { }
#endif
void mce_timer_kick(unsigned long interval);
--
2.7.4
[PATCH v4 4/4] x86/mce: Add Zhaoxin LMCE support
Zhaoxin newer CPUs support LMCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin LMCE
in mce/core.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 65c5a1f..88a9622 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1132,6 +1132,12 @@ static bool __mc_check_crashing_cpu(int cpu)
u64 mcgstatus;
mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
+
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
+ if (mcgstatus & MCG_STATUS_LMCES)
+ return false;
+ }
+
if (mcgstatus & MCG_STATUS_RIPV) {
mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
return true;
@@ -1282,9 +1288,10 @@ void do_machine_check(struct pt_regs *regs, long
error_code)
/*
* Check if this MCE is signaled to only this logical processor,
-* on Intel only.
+* on Intel, Zhaoxin only.
*/
- if (m.cpuvendor == X86_VENDOR_INTEL)
+ if (m.cpuvendor == X86_VENDOR_INTEL ||
+ m.cpuvendor == X86_VENDOR_ZHAOXIN)
lmce = m.mcgstatus & MCG_STATUS_LMCES;
/*
@@ -1795,9 +1802,15 @@ static void mce_zhaoxin_feature_init(struct cpuinfo_x86
*c)
}
intel_init_cmci();
+ intel_init_lmce();
mce_adjust_timer = cmci_intel_adjust_timer;
}
+static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
+{
+ intel_clear_lmce();
+}
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1834,6 +1847,9 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86
*c)
case X86_VENDOR_INTEL:
mce_intel_feature_clear(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_clear(c);
+ break;
default:
break;
}
--
2.7.4
Re: [PATCH v3 4/4] x86/mce: Add Zhaoxin LMCE support
On Mon, Sep 16, 2019, Luck, Tony wrote:
>On Mon, Sep 16, 2019 at 11:37:18AM +0000, Tony W Wang-oc wrote:
>> Zhaoxin newer CPUs support LMCE that compatible with Intel's
>> "Machine-Check Architecture", so add support for Zhaoxin LMCE
>> in mce/core.c.
>>
>> Signed-off-by: Tony W Wang-oc
>> ---
>> arch/x86/kernel/cpu/mce/core.c | 35
>+--
>> 1 file changed, 33 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
>> index 65c5a1f..acdd76b 100644
>> --- a/arch/x86/kernel/cpu/mce/core.c
>> +++ b/arch/x86/kernel/cpu/mce/core.c
>> @@ -1132,6 +1132,27 @@ static bool __mc_check_crashing_cpu(int cpu)
>> u64 mcgstatus;
>>
>> mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
>> +
>> +if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
>> +if (mcgstatus & MCG_STATUS_LMCES)
>> +return false;
>> +
>> +if (!(mcgstatus & MCG_STATUS_LMCES)) {
>
>Don't really need this test ... you already did "return false" if
>the LMCES bit was set ... so this test is redundant (and you can avoid
>indenting the next dozen lines.
Got it, Thank you.
But have a question about below codes:
if (mcgstatus & MCG_STATUS_RIPV) {
mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
return true;
}
These seems require all #MC exception errors set MCG_STATUS_RIPV = 1
in order to skip synchronize which "return true;" actually does for this.
As Intel SDM show, "Recoverable-not-continuable SRAR Type" errors may
set MCG_STATUS_RIPV = 0, PCC = 0. When these #MC errors broadcast
to offline CPU, may cause kernel panic with synchronize timeout (offline
CPU can't skip synchronize in this case).
Could "return true;" outside the if-case?
if (mcgstatus & MCG_STATUS_RIPV) {
mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
}
return true;
Sincerely
TonyWWang-oc
[PATCH v3 4/4] x86/mce: Add Zhaoxin LMCE support
Zhaoxin newer CPUs support LMCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin LMCE
in mce/core.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 35 +--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 65c5a1f..acdd76b 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1132,6 +1132,27 @@ static bool __mc_check_crashing_cpu(int cpu)
u64 mcgstatus;
mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
+
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
+ if (mcgstatus & MCG_STATUS_LMCES)
+ return false;
+
+ if (!(mcgstatus & MCG_STATUS_LMCES)) {
+ /*
+* Clear the MCG_STATUS_RIPV valid status
+* bit so that a second MCE won't cause a
+* shutdown.
+*/
+ if (mcgstatus & MCG_STATUS_RIPV)
+ mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
+ /*
+* On this CPU, skip synchronize regardless
+* of MCG_STATUS_RIPV status.
+*/
+ return true;
+ }
+ }
+
if (mcgstatus & MCG_STATUS_RIPV) {
mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
return true;
@@ -1282,9 +1303,10 @@ void do_machine_check(struct pt_regs *regs, long
error_code)
/*
* Check if this MCE is signaled to only this logical processor,
-* on Intel only.
+* on Intel, Zhaoxin only.
*/
- if (m.cpuvendor == X86_VENDOR_INTEL)
+ if (m.cpuvendor == X86_VENDOR_INTEL ||
+ m.cpuvendor == X86_VENDOR_ZHAOXIN)
lmce = m.mcgstatus & MCG_STATUS_LMCES;
/*
@@ -1795,9 +1817,15 @@ static void mce_zhaoxin_feature_init(struct cpuinfo_x86
*c)
}
intel_init_cmci();
+ intel_init_lmce();
mce_adjust_timer = cmci_intel_adjust_timer;
}
+static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
+{
+ intel_clear_lmce();
+}
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1834,6 +1862,9 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86
*c)
case X86_VENDOR_INTEL:
mce_intel_feature_clear(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_clear(c);
+ break;
default:
break;
}
--
2.7.4
[PATCH v3 3/4] x86/mce: Add Zhaoxin CMCI support
All Zhaoxin newer CPUs support CMCI that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin CMCI in
mce/core.c and mce/intel.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 25 +
arch/x86/kernel/cpu/mce/intel.c | 5 -
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 7bcd8c1..65c5a1f 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1777,6 +1777,27 @@ static void mce_centaur_feature_init(struct cpuinfo_x86
*c)
}
}
+static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
+{
+ struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
+
+ /*
+* These CPUs have MCA bank 8, that only has one error called SVAD
+* (System View Address Decoder) which be controlled by IA32_MC8.CTL.0
+* If enabled, the prefetch on these CPUs will cause SVAD machine
+* check exception when virtual machine startup and cause system
+* panic. Always disable bank 8 SVAD error by default.
+*/
+ if ((c->x86 == 7 && c->x86_model == 0x1b) ||
+ (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
+ if (this_cpu_read(mce_num_banks) > 8)
+ mce_banks[8].ctl = 0;
+ }
+
+ intel_init_cmci();
+ mce_adjust_timer = cmci_intel_adjust_timer;
+}
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1798,6 +1819,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c)
mce_centaur_feature_init(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_init(c);
+ break;
+
default:
break;
}
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 70799a5..87c473f 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -84,9 +84,12 @@ static int cmci_supported(int *banks)
* Vendor check is not strictly needed, but the initial
* initialization is vendor keyed and this
* makes sure none of the backdoors are entered otherwise.
+* Checks the vendor are Intel/Zhaoxin-specific:
*/
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 0;
+
if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)
return 0;
rdmsrl(MSR_IA32_MCG_CAP, cap);
--
2.7.4
[PATCH v3 1/4] x86/mce: Add Zhaoxin MCE support
All Zhaoxin newer CPUs support MCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin MCE in
mce/core.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 38 --
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 743370e..7bcd8c1 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -488,8 +488,9 @@ int mce_usable_address(struct mce *m)
if (!(m->status & MCI_STATUS_ADDRV))
return 0;
- /* Checks after this one are Intel-specific: */
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ /* Checks after this one are Intel/Zhaoxin-specific: */
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 1;
if (!(m->status & MCI_STATUS_MISCV))
@@ -507,10 +508,13 @@ EXPORT_SYMBOL_GPL(mce_usable_address);
bool mce_is_memory_error(struct mce *m)
{
- if (m->cpuvendor == X86_VENDOR_AMD ||
- m->cpuvendor == X86_VENDOR_HYGON) {
+ switch (m->cpuvendor) {
+ case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
return amd_mce_is_memory_error(m);
- } else if (m->cpuvendor == X86_VENDOR_INTEL) {
+
+ case X86_VENDOR_INTEL:
+ case X86_VENDOR_ZHAOXIN:
/*
* Intel SDM Volume 3B - 15.9.2 Compound Error Codes
*
@@ -527,9 +531,10 @@ bool mce_is_memory_error(struct mce *m)
return (m->status & 0xef80) == BIT(7) ||
(m->status & 0xef00) == BIT(8) ||
(m->status & 0xeffc) == 0xc;
- }
- return false;
+ default:
+ return false;
+ }
}
EXPORT_SYMBOL_GPL(mce_is_memory_error);
@@ -1697,6 +1702,18 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c)
if (c->x86 == 6 && c->x86_model == 45)
quirk_no_way_out = quirk_sandybridge_ifu;
}
+
+ if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
+ /*
+* All newer Zhaoxin CPUs support MCE broadcasting. Enable
+* synchronization with a one second timeout.
+*/
+ if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model ==
0x1f)) {
+ if (cfg->monarch_timeout < 0)
+ cfg->monarch_timeout = USEC_PER_SEC;
+ }
+ }
+
if (cfg->monarch_timeout < 0)
cfg->monarch_timeout = 0;
if (cfg->bootlog != 0)
@@ -2014,15 +2031,16 @@ static void mce_disable_error_reporting(void)
static void vendor_disable_error_reporting(void)
{
/*
-* Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs
-* are socket-wide.
+* Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
+* MSRs are socket-wide.
* Disabling them for just a single offlined CPU is bad, since it will
* inhibit reporting for all shared resources on the socket like the
* last level cache (LLC), the integrated memory controller (iMC), etc.
*/
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
- boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+ boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
return;
mce_disable_error_reporting();
--
2.7.4
[PATCH v3 2/4] x86/mce: Make 3 functions non-static
These functions are declared static and cannot be used in others
.c source file. this commit removes the static attribute and adds
the declaration to the header for these functions.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/intel.c| 6 +++---
arch/x86/kernel/cpu/mce/internal.h | 6 ++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 88cd959..70799a5 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -423,7 +423,7 @@ void cmci_disable_bank(int bank)
raw_spin_unlock_irqrestore(_discover_lock, flags);
}
-static void intel_init_cmci(void)
+void intel_init_cmci(void)
{
int banks;
@@ -442,7 +442,7 @@ static void intel_init_cmci(void)
cmci_recheck();
}
-static void intel_init_lmce(void)
+void intel_init_lmce(void)
{
u64 val;
@@ -455,7 +455,7 @@ static void intel_init_lmce(void)
wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);
}
-static void intel_clear_lmce(void)
+void intel_clear_lmce(void)
{
u64 val;
diff --git a/arch/x86/kernel/cpu/mce/internal.h
b/arch/x86/kernel/cpu/mce/internal.h
index 43031db..842b273 100644
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -45,11 +45,17 @@ unsigned long cmci_intel_adjust_timer(unsigned long
interval);
bool mce_intel_cmci_poll(void);
void mce_intel_hcpu_update(unsigned long cpu);
void cmci_disable_bank(int bank);
+void intel_init_cmci(void);
+void intel_init_lmce(void);
+void intel_clear_lmce(void);
#else
# define cmci_intel_adjust_timer mce_adjust_timer_default
static inline bool mce_intel_cmci_poll(void) { return false; }
static inline void mce_intel_hcpu_update(unsigned long cpu) { }
static inline void cmci_disable_bank(int bank) { }
+static inline void intel_init_cmci(void) { }
+static inline void intel_init_lmce(void) { }
+static inline void intel_clear_lmce(void) { }
#endif
void mce_timer_kick(unsigned long interval);
--
2.7.4
[PATCH v3 0/4] x86/mce: Add supports for Zhaoxin MCA
Zhaoxin newer CPUs support MCE, CMCI and LMCE that compatible with Intel's "Machine-Check Architecture". To enable the supports of Linux kernel to Zhaoxin's MCA, add specific patches for Zhaoxin's MCE, CMCI and LMCE. patches about Zhaoxin's CMCI, LMCE use 3 functions in mce/intel.c, so make these functions non-static. Some Zhaoxin's CPUs have MCA bank 8, that only has one error called SVAD (System View Address Decoder) which be controlled by IA32_MC8.CTL.0. If enabled, the prefetch on these CPUs will cause SVAD machine check exception when virtual machine startup and cause system panic. Add a quirk for these Zhaoxin CPUs MCA bank 8. v2->v3: - Make ifelse-case to switch-case (patch 1/4) - Simplify Zhaoxin CPU FMS checking (patch 1/4, 3/4) - Revert 1 unused function intel_ppin_init() (patch 2/4) - Rework mce_zhaoxin_feature_init() as static (patch 3/4) - Rework comment about Zhaoxin MCA SVAD and CMCI (patch 3/4) - Rework mce_zhaoxin_feature_clear() as static (patch 4/4) - Add comment and change coding style (patch 4/4) v1->v2: - Fix redefinition of "mce_zhaoxin_feature_init" (patch 3/4) - Fix redefinition of "mce_zhaoxin_feature_clear" (patch 4/4) TonyWWang-oc(4): x86/mce: Add Zhaoxin MCE support x86/mce: Make 3 functions non-static x86/mce: Add Zhaoxin CMCI support x86/mce: Add Zhaoxin LMCE support arch/x86/kernel/cpu/mce/core.c | 98 +- arch/x86/kernel/cpu/mce/intel.c| 11 +++-- arch/x86/kernel/cpu/mce/internal.h | 6 +++ 3 files changed, 99 insertions(+), 16 deletions(-) -- 2.7.4
Re: [PATCH v3 2/4] x86/mce: Make 3 functions non-static
On Mon, Sep 16, 2019, Thomas Gleixner wrote: >On Mon, 16 Sep 2019, Tony W Wang-oc wrote: > >> On Mon, Sep 16, 2019, Thomas Gleixner wrote: >> >On Wed, 11 Sep 2019, Tony W Wang-oc wrote: >> > >> >> These functions are declared static and cannot be used in others >> >> .c source file. this commit removes the static attribute and adds >> >> the declaration to the header for these functions. >> > >> >I'm not Cc'ed on any patches which use those functions. Please Cc the >> >relevant maintainers on all patches of such a patch series so contect can >> >be seen. >> > >> >> Patches 3/4, 4/4 in this patchsets are using these functions. Specifically, >> "[PATCH v3 3/4] x86/mce: Add Zhaoxin CMCI support " in this patchsets is >> using intel_init_cmci(), "[PATCH v3 4/4] x86/mce: Add Zhaoxin LMCE support" >> is using intel_init_lmce() and intel_clear_lmce(). >> >> I had sent all patches in this patchsets to your mailbox. Could you help to >> check again? Thank you. > >Found them by now, but please make sure that you provide cover letter >[PATCH vX 0/N ] and thread the patches proper so they reference the cover >letter. git send-email does that for you. Ok, thank you, will send this patchsets with cover letter. Sincerely TonyWWang-oc
Re: [PATCH v3 2/4] x86/mce: Make 3 functions non-static
On Mon, Sep 16, 2019, Thomas Gleixner wrote: >On Wed, 11 Sep 2019, Tony W Wang-oc wrote: > >> These functions are declared static and cannot be used in others >> .c source file. this commit removes the static attribute and adds >> the declaration to the header for these functions. > >I'm not Cc'ed on any patches which use those functions. Please Cc the >relevant maintainers on all patches of such a patch series so contect can >be seen. > Patches 3/4, 4/4 in this patchsets are using these functions. Specifically, "[PATCH v3 3/4] x86/mce: Add Zhaoxin CMCI support " in this patchsets is using intel_init_cmci(), "[PATCH v3 4/4] x86/mce: Add Zhaoxin LMCE support" is using intel_init_lmce() and intel_clear_lmce(). I had sent all patches in this patchsets to your mailbox. Could you help to check again? Thank you. >Also adding some hint to the change log which new code will use that would >be appreciated. Got it, will add in next version. Sincerely TonyWWang-oc
[PATCH v3 4/4] x86/mce: Add Zhaoxin LMCE support
Zhaoxin newer CPUs support LMCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin LMCE
in mce/core.c.
Signed-off-by: Tony W Wang-oc
---
v2->v3:
- Rework mce_zhaoxin_feature_clear() as static
- Add comment and change coding style
v1->v2:
- Fix redefinition of "mce_zhaoxin_feature_clear"
arch/x86/kernel/cpu/mce/core.c | 35 +--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 65c5a1f..acdd76b 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1132,6 +1132,27 @@ static bool __mc_check_crashing_cpu(int cpu)
u64 mcgstatus;
mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
+
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
+ if (mcgstatus & MCG_STATUS_LMCES)
+ return false;
+
+ if (!(mcgstatus & MCG_STATUS_LMCES)) {
+ /*
+* Clear the MCG_STATUS_RIPV valid status
+* bit so that a second MCE won't cause a
+* shutdown.
+*/
+ if (mcgstatus & MCG_STATUS_RIPV)
+ mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
+ /*
+* On this CPU, skip synchronize regardless
+* of MCG_STATUS_RIPV status.
+*/
+ return true;
+ }
+ }
+
if (mcgstatus & MCG_STATUS_RIPV) {
mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
return true;
@@ -1282,9 +1303,10 @@ void do_machine_check(struct pt_regs *regs, long
error_code)
/*
* Check if this MCE is signaled to only this logical processor,
-* on Intel only.
+* on Intel, Zhaoxin only.
*/
- if (m.cpuvendor == X86_VENDOR_INTEL)
+ if (m.cpuvendor == X86_VENDOR_INTEL ||
+ m.cpuvendor == X86_VENDOR_ZHAOXIN)
lmce = m.mcgstatus & MCG_STATUS_LMCES;
/*
@@ -1795,9 +1817,15 @@ static void mce_zhaoxin_feature_init(struct cpuinfo_x86
*c)
}
intel_init_cmci();
+ intel_init_lmce();
mce_adjust_timer = cmci_intel_adjust_timer;
}
+static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
+{
+ intel_clear_lmce();
+}
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1834,6 +1862,9 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86
*c)
case X86_VENDOR_INTEL:
mce_intel_feature_clear(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_clear(c);
+ break;
default:
break;
}
--
2.7.4
[PATCH v3 3/4] x86/mce: Add Zhaoxin CMCI support
All Zhaoxin newer CPUs support CMCI that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin CMCI in
mce/core.c and mce/intel.c.
Signed-off-by: Tony W Wang-oc
---
v2->v3:
- Rework mce_zhaoxin_feature_init() as static
- Rework comment about Zhaoxin MCA SVAD and CMCI
- Simplify Zhaoxin CPU FMS checking
v1->v2:
- Fix redefinition of "mce_zhaoxin_feature_init"
arch/x86/kernel/cpu/mce/core.c | 25 +
arch/x86/kernel/cpu/mce/intel.c | 5 -
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 7bcd8c1..65c5a1f 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1777,6 +1777,27 @@ static void mce_centaur_feature_init(struct cpuinfo_x86
*c)
}
}
+static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
+{
+ struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
+
+ /*
+* These CPUs have MCA bank 8, that only has one error called SVAD
+* (System View Address Decoder) which be controlled by IA32_MC8.CTL.0
+* If enabled, the prefetch on these CPUs will cause SVAD machine
+* check exception when virtual machine startup and cause system
+* panic. Always disable bank 8 SVAD error by default.
+*/
+ if ((c->x86 == 7 && c->x86_model == 0x1b) ||
+ (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
+ if (this_cpu_read(mce_num_banks) > 8)
+ mce_banks[8].ctl = 0;
+ }
+
+ intel_init_cmci();
+ mce_adjust_timer = cmci_intel_adjust_timer;
+}
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1798,6 +1819,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c)
mce_centaur_feature_init(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_init(c);
+ break;
+
default:
break;
}
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 70799a5..87c473f 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -84,9 +84,12 @@ static int cmci_supported(int *banks)
* Vendor check is not strictly needed, but the initial
* initialization is vendor keyed and this
* makes sure none of the backdoors are entered otherwise.
+* Checks the vendor are Intel/Zhaoxin-specific:
*/
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 0;
+
if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)
return 0;
rdmsrl(MSR_IA32_MCG_CAP, cap);
--
2.7.4
[PATCH v3 2/4] x86/mce: Make 3 functions non-static
These functions are declared static and cannot be used in others
.c source file. this commit removes the static attribute and adds
the declaration to the header for these functions.
Signed-off-by: Tony W Wang-oc
---
v2->v3:
- Revert 1 unused function
arch/x86/kernel/cpu/mce/intel.c| 6 +++---
arch/x86/kernel/cpu/mce/internal.h | 6 ++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 88cd959..70799a5 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -423,7 +423,7 @@ void cmci_disable_bank(int bank)
raw_spin_unlock_irqrestore(_discover_lock, flags);
}
-static void intel_init_cmci(void)
+void intel_init_cmci(void)
{
int banks;
@@ -442,7 +442,7 @@ static void intel_init_cmci(void)
cmci_recheck();
}
-static void intel_init_lmce(void)
+void intel_init_lmce(void)
{
u64 val;
@@ -455,7 +455,7 @@ static void intel_init_lmce(void)
wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);
}
-static void intel_clear_lmce(void)
+void intel_clear_lmce(void)
{
u64 val;
diff --git a/arch/x86/kernel/cpu/mce/internal.h
b/arch/x86/kernel/cpu/mce/internal.h
index 43031db..842b273 100644
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -45,11 +45,17 @@ unsigned long cmci_intel_adjust_timer(unsigned long
interval);
bool mce_intel_cmci_poll(void);
void mce_intel_hcpu_update(unsigned long cpu);
void cmci_disable_bank(int bank);
+void intel_init_cmci(void);
+void intel_init_lmce(void);
+void intel_clear_lmce(void);
#else
# define cmci_intel_adjust_timer mce_adjust_timer_default
static inline bool mce_intel_cmci_poll(void) { return false; }
static inline void mce_intel_hcpu_update(unsigned long cpu) { }
static inline void cmci_disable_bank(int bank) { }
+static inline void intel_init_cmci(void) { }
+static inline void intel_init_lmce(void) { }
+static inline void intel_clear_lmce(void) { }
#endif
void mce_timer_kick(unsigned long interval);
--
2.7.4
[PATCH v3 1/4] x86/mce: Add Zhaoxin MCE support
All Zhaoxin newer CPUs support MCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin MCE in
mce/core.c.
Signed-off-by: Tony W Wang-oc
---
v2->v3:
- Make ifelse-case to switch-case
- Simplify Zhaoxin CPU FMS checking
arch/x86/kernel/cpu/mce/core.c | 38 --
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 743370e..7bcd8c1 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -488,8 +488,9 @@ int mce_usable_address(struct mce *m)
if (!(m->status & MCI_STATUS_ADDRV))
return 0;
- /* Checks after this one are Intel-specific: */
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ /* Checks after this one are Intel/Zhaoxin-specific: */
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 1;
if (!(m->status & MCI_STATUS_MISCV))
@@ -507,10 +508,13 @@ EXPORT_SYMBOL_GPL(mce_usable_address);
bool mce_is_memory_error(struct mce *m)
{
- if (m->cpuvendor == X86_VENDOR_AMD ||
- m->cpuvendor == X86_VENDOR_HYGON) {
+ switch (m->cpuvendor) {
+ case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
return amd_mce_is_memory_error(m);
- } else if (m->cpuvendor == X86_VENDOR_INTEL) {
+
+ case X86_VENDOR_INTEL:
+ case X86_VENDOR_ZHAOXIN:
/*
* Intel SDM Volume 3B - 15.9.2 Compound Error Codes
*
@@ -527,9 +531,10 @@ bool mce_is_memory_error(struct mce *m)
return (m->status & 0xef80) == BIT(7) ||
(m->status & 0xef00) == BIT(8) ||
(m->status & 0xeffc) == 0xc;
- }
- return false;
+ default:
+ return false;
+ }
}
EXPORT_SYMBOL_GPL(mce_is_memory_error);
@@ -1697,6 +1702,18 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c)
if (c->x86 == 6 && c->x86_model == 45)
quirk_no_way_out = quirk_sandybridge_ifu;
}
+
+ if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
+ /*
+* All newer Zhaoxin CPUs support MCE broadcasting. Enable
+* synchronization with a one second timeout.
+*/
+ if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model ==
0x1f)) {
+ if (cfg->monarch_timeout < 0)
+ cfg->monarch_timeout = USEC_PER_SEC;
+ }
+ }
+
if (cfg->monarch_timeout < 0)
cfg->monarch_timeout = 0;
if (cfg->bootlog != 0)
@@ -2014,15 +2031,16 @@ static void mce_disable_error_reporting(void)
static void vendor_disable_error_reporting(void)
{
/*
-* Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs
-* are socket-wide.
+* Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
+* MSRs are socket-wide.
* Disabling them for just a single offlined CPU is bad, since it will
* inhibit reporting for all shared resources on the socket like the
* last level cache (LLC), the integrated memory controller (iMC), etc.
*/
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
- boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+ boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
return;
mce_disable_error_reporting();
--
2.7.4
答复: [PATCH v2 3/4] x86/mce: Add Zhaoxin CMCI support
On Tue, Sep 10, 2019, Borislav Petkov wrote:
>On Tue, Sep 10, 2019 at 08:19:44AM +0000, Tony W Wang-oc wrote:
>> @@ -1777,6 +1777,29 @@ static void mce_centaur_feature_init(struct
>cpuinfo_x86 *c)
>> }
>> }
>>
>> +#ifdef CONFIG_CPU_SUP_ZHAOXIN
>
>What's that ifdeffery for since you have it in the header already?
Sorry for that.
Since this function actually be called only in mce/core.c, will remove the
declare in the header file and make this function static.
>
>> +void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
>> +{
>> +struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
>> +
>> +/*
>> + * These CPUs bank8 SVAD error may be triggered unexpected when
>
>"These CPUs bank8 SVAD"??
These Zhaoxin CPUs have MCA bank 8, that only have one error called SVAD(
System View Address Decoder) which be controlled by IA32_MC8_CTL.0
>
>> + * bringup virtual machine. it is not hardware bug. Always disable
>> + * bank8 SVAD error by default.
>> + */
>
>That comment is incomprehensible. Please rewrite.
Ok, will rewrite comment in v3.
>
>> +if ((c->x86 == 6 && c->x86_model == 0x19 &&
>> +(c->x86_stepping > 3 && c->x86_stepping < 8)) ||
>> +(c->x86 == 6 && c->x86_model == 0x1f) ||
>> +(c->x86 == 7 && c->x86_model == 0x1b)) {
>
>As before: potential to simplify the test here?
Ok, will simplify as before.
>
>> +if (this_cpu_read(mce_num_banks) > 8)
>> +mce_banks[8].ctl = 0;
>> +}
>> +
>> +intel_init_cmci();
>> +mce_adjust_timer = cmci_intel_adjust_timer;
>> +}
>> +#endif
>> +
>> static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
>> {
>> switch (c->x86_vendor) {
>> @@ -1798,6 +1821,10 @@ static void __mcheck_cpu_init_vendor(struct
>cpuinfo_x86 *c)
>> mce_centaur_feature_init(c);
>> break;
>>
>> +case X86_VENDOR_ZHAOXIN:
>> +mce_zhaoxin_feature_init(c);
>> +break;
>> +
>> default:
>> break;
>> }
>> diff --git a/arch/x86/kernel/cpu/mce/intel.c
>> b/arch/x86/kernel/cpu/mce/intel.c
>> index eee4b12..b49cba7 100644
>> --- a/arch/x86/kernel/cpu/mce/intel.c
>> +++ b/arch/x86/kernel/cpu/mce/intel.c
>> @@ -85,7 +85,8 @@ static int cmci_supported(int *banks)
>> * initialization is vendor keyed and this
>> * makes sure none of the backdoors are entered otherwise.
>> */
>
>That comment above needs fixing too.
Ok.
>
>> -if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
>> +if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
>> +boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
>> return 0;
>
>< newline here.
Ok.
Sincerely
TonyWWang-oc
答复: [PATCH v2 4/4] x86/mce: Add Zhaoxin LMCE support
On Tue, Sep 10, 2019, Borislav Petkov wrote:
>On Tue, Sep 10, 2019 at 08:20:07AM +0000, Tony W Wang-oc wrote:
>> Zhaoxin newer CPUs support LMCE that compatible with Intel's
>> "Machine-Check Architecture", so add support for Zhaoxin LMCE
>> in mce/core.c.
>>
>> Signed-off-by: Tony W Wang-oc
>> ---
>> v1->v2:
>> - Fix redefinition of "mce_zhaoxin_feature_clear"
>>
>> arch/x86/include/asm/mce.h | 2 ++
>> arch/x86/kernel/cpu/mce/core.c | 25 +++--
>> 2 files changed, 25 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
>> index 0986a11..01840ec 100644
>> --- a/arch/x86/include/asm/mce.h
>> +++ b/arch/x86/include/asm/mce.h
>> @@ -352,8 +352,10 @@ static inline void mce_hygon_feature_init(struct
>cpuinfo_x86 *c){ return mce_am
>>
>> #ifdef CONFIG_CPU_SUP_ZHAOXIN
>> void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c);
>> +void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c);
>> #else
>> static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { }
>> +static inline void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) { }
>> #endif
>>
>> #endif /* _ASM_X86_MCE_H */
>> diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
>> index 8a36833..595d3af7ac 100644
>> --- a/arch/x86/kernel/cpu/mce/core.c
>> +++ b/arch/x86/kernel/cpu/mce/core.c
>> @@ -1129,6 +1129,17 @@ static bool __mc_check_crashing_cpu(int cpu)
>> u64 mcgstatus;
>>
>> mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
>> +
>> +if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
>> +if (mcgstatus & MCG_STATUS_LMCES) {
>> +return false;
>> +} else {
>> +if (mcgstatus & MCG_STATUS_RIPV)
>> +mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
>> +return true;
>> +}
>> +}
>
>Simplify:
>
>if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
>if (mcgstatus & MCG_STATUS_LMCES)
>return false;
> }
>
> <--- Now here, on your CPUs which don't set MCG_STATUS_LMCES,
>it will fallback to clearing the status register. I.e., what you do in the else
>clause.
>
On Zhaoxin CPUs don't set MCG_STATUS_LMCES, to avoid rendezvous timeout if
this CPU is offline or crashing_cpu was set, we want return true regardless of
MCG_STATUS_RIPV's setting.
Without my else clause, original codes return true only when MCG_STATUS_RIPV
be setted.
For better readability, will add comment and change coding style in v3.
Sincerely
TonyWWang-oc
答复: [PATCH v2 1/4] x86/mce: Add Zhaoxin MCE support
On Tue, Sep 10, 2019, Borislav Petkov wrote:
>On Tue, Sep 10, 2019 at 08:19:08AM +0000, Tony W Wang-oc wrote:
>> All Zhaoxin newer CPUs support MCE that compatible with Intel's
>> "Machine-Check Architecture", so add support for Zhaoxin MCE in
>> mce/core.c.
>>
>> Signed-off-by: Tony W Wang-oc
>> ---
>> arch/x86/kernel/cpu/mce/core.c | 30 --
>> 1 file changed, 24 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
>> index 743370e..3f878f6 100644
>> --- a/arch/x86/kernel/cpu/mce/core.c
>> +++ b/arch/x86/kernel/cpu/mce/core.c
>> @@ -488,8 +488,9 @@ int mce_usable_address(struct mce *m)
>> if (!(m->status & MCI_STATUS_ADDRV))
>> return 0;
>>
>> -/* Checks after this one are Intel-specific: */
>> -if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
>> +/* Checks after this one are Intel/Zhaoxin-specific: */
>> +if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
>> +boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
>> return 1;
>>
>> if (!(m->status & MCI_STATUS_MISCV))
>> @@ -510,7 +511,8 @@ bool mce_is_memory_error(struct mce *m)
>> if (m->cpuvendor == X86_VENDOR_AMD ||
>> m->cpuvendor == X86_VENDOR_HYGON) {
>> return amd_mce_is_memory_error(m);
>> -} else if (m->cpuvendor == X86_VENDOR_INTEL) {
>> +} else if (m->cpuvendor == X86_VENDOR_INTEL ||
>> + m->cpuvendor == X86_VENDOR_ZHAOXIN) {
>> /*
>> * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
>> *
>
>Make that a switch-case for better readability pls.
Ok.
>
>> @@ -1697,6 +1699,21 @@ static int __mcheck_cpu_apply_quirks(struct
>cpuinfo_x86 *c)
>> if (c->x86 == 6 && c->x86_model == 45)
>> quirk_no_way_out = quirk_sandybridge_ifu;
>> }
>> +
>> +if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
>> +/*
>> + * All newer Zhaoxin CPUs support MCE broadcasting. Enable
>> + * synchronization with a one second timeout.
>> + */
>> +if ((c->x86 == 6 && c->x86_model == 0x19 &&
>> +(c->x86_stepping > 3 && c->x86_stepping < 8)) ||
>> +(c->x86 == 6 && c->x86_model == 0x1f) ||
>> + c->x86 > 6) {
>
>Can this be simplified into maybe something like this:
>
> if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f))
>
>this is, of course, assuming that Zhaoxin doesn't do family < 6 and that
>the other steppings for model 0x19 don't matter because they don't exist
>or so...
>
Yes, Zhaoxin doesn't do family<6, and the other steppings for model 0x19
doesn't have MCA. So will simplified like this:
if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f))
Sincerely
TonyWWang-oc
答复: [PATCH v2 2/4] x86/mce: Make 4 functions non-static
On Tue, Sep 10, 2019, Borislav Petkov wrote:
>On Tue, Sep 10, 2019 at 08:19:20AM +0000, Tony W Wang-oc wrote:
>> These functions are declared static and cannot be used in others
>> .c source file. this commit removes the static attribute and adds
>> the declaration to the header for these functions.
>>
>> Signed-off-by: Tony W Wang-oc
>> ---
>> arch/x86/kernel/cpu/mce/intel.c| 8
>> arch/x86/kernel/cpu/mce/internal.h | 8
>> 2 files changed, 12 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/x86/kernel/cpu/mce/intel.c
>> b/arch/x86/kernel/cpu/mce/intel.c
>> index 88cd959..eee4b12 100644
>> --- a/arch/x86/kernel/cpu/mce/intel.c
>> +++ b/arch/x86/kernel/cpu/mce/intel.c
>> @@ -423,7 +423,7 @@ void cmci_disable_bank(int bank)
>> raw_spin_unlock_irqrestore(_discover_lock, flags);
>> }
>>
>> -static void intel_init_cmci(void)
>> +void intel_init_cmci(void)
>> {
>> int banks;
>>
>> @@ -442,7 +442,7 @@ static void intel_init_cmci(void)
>> cmci_recheck();
>> }
>>
>> -static void intel_init_lmce(void)
>> +void intel_init_lmce(void)
>> {
>> u64 val;
>>
>> @@ -455,7 +455,7 @@ static void intel_init_lmce(void)
>> wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);
>> }
>>
>> -static void intel_clear_lmce(void)
>> +void intel_clear_lmce(void)
>> {
>> u64 val;
>>
>> @@ -467,7 +467,7 @@ static void intel_clear_lmce(void)
>> wrmsrl(MSR_IA32_MCG_EXT_CTL, val);
>> }
>>
>> -static void intel_ppin_init(struct cpuinfo_x86 *c)
>> +void intel_ppin_init(struct cpuinfo_x86 *c)
>
>That one doesn't need to get exported.
>
>This can easily be missed because you're exporting them in one patch and
>using them in another. Do the exports in the same patch where you use
>them for the first time.
Got it, will fix this in v3.
Sincerely
TonyWWang-oc
[PATCH v2 3/4] x86/mce: Add Zhaoxin CMCI support
All Zhaoxin newer CPUs support CMCI that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin CMCI in
mce/core.c and mce/intel.c.
Signed-off-by: Tony W Wang-oc
---
v1->v2:
- Fix redefinition of "mce_zhaoxin_feature_init"
arch/x86/include/asm/mce.h | 6 ++
arch/x86/kernel/cpu/mce/core.c | 27 +++
arch/x86/kernel/cpu/mce/intel.c | 3 ++-
3 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index dc2d4b2..0986a11 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -350,4 +350,10 @@ umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc,
u64 *sys_addr) { return
static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) {
return mce_amd_feature_init(c); }
+#ifdef CONFIG_CPU_SUP_ZHAOXIN
+void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c);
+#else
+static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { }
+#endif
+
#endif /* _ASM_X86_MCE_H */
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 3f878f6..8a36833 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1777,6 +1777,29 @@ static void mce_centaur_feature_init(struct cpuinfo_x86
*c)
}
}
+#ifdef CONFIG_CPU_SUP_ZHAOXIN
+void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
+{
+ struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
+
+ /*
+* These CPUs bank8 SVAD error may be triggered unexpected when
+* bringup virtual machine. it is not hardware bug. Always disable
+* bank8 SVAD error by default.
+*/
+ if ((c->x86 == 6 && c->x86_model == 0x19 &&
+ (c->x86_stepping > 3 && c->x86_stepping < 8)) ||
+ (c->x86 == 6 && c->x86_model == 0x1f) ||
+ (c->x86 == 7 && c->x86_model == 0x1b)) {
+ if (this_cpu_read(mce_num_banks) > 8)
+ mce_banks[8].ctl = 0;
+ }
+
+ intel_init_cmci();
+ mce_adjust_timer = cmci_intel_adjust_timer;
+}
+#endif
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1798,6 +1821,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c)
mce_centaur_feature_init(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_init(c);
+ break;
+
default:
break;
}
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index eee4b12..b49cba7 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -85,7 +85,8 @@ static int cmci_supported(int *banks)
* initialization is vendor keyed and this
* makes sure none of the backdoors are entered otherwise.
*/
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 0;
if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)
return 0;
--
2.7.4
[PATCH v2 2/4] x86/mce: Make 4 functions non-static
These functions are declared static and cannot be used in others
.c source file. this commit removes the static attribute and adds
the declaration to the header for these functions.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/intel.c| 8
arch/x86/kernel/cpu/mce/internal.h | 8
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 88cd959..eee4b12 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -423,7 +423,7 @@ void cmci_disable_bank(int bank)
raw_spin_unlock_irqrestore(_discover_lock, flags);
}
-static void intel_init_cmci(void)
+void intel_init_cmci(void)
{
int banks;
@@ -442,7 +442,7 @@ static void intel_init_cmci(void)
cmci_recheck();
}
-static void intel_init_lmce(void)
+void intel_init_lmce(void)
{
u64 val;
@@ -455,7 +455,7 @@ static void intel_init_lmce(void)
wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);
}
-static void intel_clear_lmce(void)
+void intel_clear_lmce(void)
{
u64 val;
@@ -467,7 +467,7 @@ static void intel_clear_lmce(void)
wrmsrl(MSR_IA32_MCG_EXT_CTL, val);
}
-static void intel_ppin_init(struct cpuinfo_x86 *c)
+void intel_ppin_init(struct cpuinfo_x86 *c)
{
unsigned long long val;
diff --git a/arch/x86/kernel/cpu/mce/internal.h
b/arch/x86/kernel/cpu/mce/internal.h
index 43031db..55d1f0a 100644
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -45,11 +45,19 @@ unsigned long cmci_intel_adjust_timer(unsigned long
interval);
bool mce_intel_cmci_poll(void);
void mce_intel_hcpu_update(unsigned long cpu);
void cmci_disable_bank(int bank);
+void intel_init_cmci(void);
+void intel_init_lmce(void);
+void intel_clear_lmce(void);
+void intel_ppin_init(struct cpuinfo_x86 *c);
#else
# define cmci_intel_adjust_timer mce_adjust_timer_default
static inline bool mce_intel_cmci_poll(void) { return false; }
static inline void mce_intel_hcpu_update(unsigned long cpu) { }
static inline void cmci_disable_bank(int bank) { }
+static inline void intel_init_cmci(void) { }
+static inline void intel_init_lmce(void) { }
+static inline void intel_clear_lmce(void) { }
+static inline void intel_ppin_init(struct cpuinfo_x86 *c) { }
#endif
void mce_timer_kick(unsigned long interval);
--
2.7.4
[PATCH v2 4/4] x86/mce: Add Zhaoxin LMCE support
Zhaoxin newer CPUs support LMCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin LMCE
in mce/core.c.
Signed-off-by: Tony W Wang-oc
---
v1->v2:
- Fix redefinition of "mce_zhaoxin_feature_clear"
arch/x86/include/asm/mce.h | 2 ++
arch/x86/kernel/cpu/mce/core.c | 25 +++--
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 0986a11..01840ec 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -352,8 +352,10 @@ static inline void mce_hygon_feature_init(struct
cpuinfo_x86 *c) { return mce_am
#ifdef CONFIG_CPU_SUP_ZHAOXIN
void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c);
+void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c);
#else
static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { }
+static inline void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) { }
#endif
#endif /* _ASM_X86_MCE_H */
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 8a36833..595d3af7ac 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1129,6 +1129,17 @@ static bool __mc_check_crashing_cpu(int cpu)
u64 mcgstatus;
mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
+
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
+ if (mcgstatus & MCG_STATUS_LMCES) {
+ return false;
+ } else {
+ if (mcgstatus & MCG_STATUS_RIPV)
+ mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
+ return true;
+ }
+ }
+
if (mcgstatus & MCG_STATUS_RIPV) {
mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
return true;
@@ -1279,9 +1290,10 @@ void do_machine_check(struct pt_regs *regs, long
error_code)
/*
* Check if this MCE is signaled to only this logical processor,
-* on Intel only.
+* on Intel, Zhaoxin only.
*/
- if (m.cpuvendor == X86_VENDOR_INTEL)
+ if (m.cpuvendor == X86_VENDOR_INTEL ||
+ m.cpuvendor == X86_VENDOR_ZHAOXIN)
lmce = m.mcgstatus & MCG_STATUS_LMCES;
/*
@@ -1796,8 +1808,14 @@ void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
}
intel_init_cmci();
+ intel_init_lmce();
mce_adjust_timer = cmci_intel_adjust_timer;
}
+
+void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
+{
+ intel_clear_lmce();
+}
#endif
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
@@ -1836,6 +1854,9 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86
*c)
case X86_VENDOR_INTEL:
mce_intel_feature_clear(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_clear(c);
+ break;
default:
break;
}
--
2.7.4
[PATCH v2 1/4] x86/mce: Add Zhaoxin MCE support
All Zhaoxin newer CPUs support MCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin MCE in
mce/core.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 30 --
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 743370e..3f878f6 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -488,8 +488,9 @@ int mce_usable_address(struct mce *m)
if (!(m->status & MCI_STATUS_ADDRV))
return 0;
- /* Checks after this one are Intel-specific: */
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ /* Checks after this one are Intel/Zhaoxin-specific: */
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 1;
if (!(m->status & MCI_STATUS_MISCV))
@@ -510,7 +511,8 @@ bool mce_is_memory_error(struct mce *m)
if (m->cpuvendor == X86_VENDOR_AMD ||
m->cpuvendor == X86_VENDOR_HYGON) {
return amd_mce_is_memory_error(m);
- } else if (m->cpuvendor == X86_VENDOR_INTEL) {
+ } else if (m->cpuvendor == X86_VENDOR_INTEL ||
+ m->cpuvendor == X86_VENDOR_ZHAOXIN) {
/*
* Intel SDM Volume 3B - 15.9.2 Compound Error Codes
*
@@ -1697,6 +1699,21 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c)
if (c->x86 == 6 && c->x86_model == 45)
quirk_no_way_out = quirk_sandybridge_ifu;
}
+
+ if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
+ /*
+* All newer Zhaoxin CPUs support MCE broadcasting. Enable
+* synchronization with a one second timeout.
+*/
+ if ((c->x86 == 6 && c->x86_model == 0x19 &&
+ (c->x86_stepping > 3 && c->x86_stepping < 8)) ||
+ (c->x86 == 6 && c->x86_model == 0x1f) ||
+c->x86 > 6) {
+ if (cfg->monarch_timeout < 0)
+ cfg->monarch_timeout = USEC_PER_SEC;
+ }
+ }
+
if (cfg->monarch_timeout < 0)
cfg->monarch_timeout = 0;
if (cfg->bootlog != 0)
@@ -2014,15 +2031,16 @@ static void mce_disable_error_reporting(void)
static void vendor_disable_error_reporting(void)
{
/*
-* Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs
-* are socket-wide.
+* Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
+* MSRs are socket-wide.
* Disabling them for just a single offlined CPU is bad, since it will
* inhibit reporting for all shared resources on the socket like the
* last level cache (LLC), the integrated memory controller (iMC), etc.
*/
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
- boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+ boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
return;
mce_disable_error_reporting();
--
2.7.4
答复: [PATCH v1 3/4] x86/mce: Add Zhaoxin CMCI support
On Mon, 9 Sep 2019, kbuild test robot wrote:
>Hi Tony,
>
>I love your patch! Yet something to improve:
Glad to hear, thanks.
>
>[auto build test ERROR on linus/master]
>[cannot apply to v5.3-rc8 next-20190904]
>[if your patch is applied to the wrong git tree, please drop us a note to help
>improve the system]
>
>url:
>https://github.com/0day-ci/linux/commits/Tony-W-Wang-oc/x86-mce-Add-Zhao
>xin-MCE-support/20190909-190435
>config: i386-randconfig-b002-201936 (attached as .config)
>compiler: gcc-7 (Debian 7.4.0-11) 7.4.0
>reproduce:
># save the attached .config to linux build tree
>make ARCH=i386
>
>If you fix the issue, kindly add following tag
>Reported-by: kbuild test robot
>
>All errors (new ones prefixed by >>):
>
>>> arch/x86/kernel/cpu/mce/core.c:1780:6: error: redefinition of
>'mce_zhaoxin_feature_init'
>void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
> ^~~~
> In file included from arch/x86/kernel/cpu/mce/core.c:50:0:
> arch/x86/include/asm/mce.h:356:20: note: previous definition of
>'mce_zhaoxin_feature_init' was here
>static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { }
> ^~~~
>
>vim +/mce_zhaoxin_feature_init +1780 arch/x86/kernel/cpu/mce/core.c
>
> 1779
>> 1780 void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
> 1781 {
> 1782 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
> 1783
> 1784 /*
> 1785 * These CPUs bank8 SVAD error may be triggered unexpected
>when
> 1786 * bringup virtual machine. it is not hardware bug. Always
> disable
> 1787 * bank8 SVAD error by default.
> 1788 */
> 1789 if ((c->x86 == 6 && c->x86_model == 0x19 &&
> 1790 (c->x86_stepping > 3 && c->x86_stepping < 8)) ||
> 1791 (c->x86 == 6 && c->x86_model == 0x1f) ||
> 1792 (c->x86 == 7 && c->x86_model == 0x1b)) {
> 1793 if (this_cpu_read(mce_num_banks) > 8)
> 1794 mce_banks[8].ctl = 0;
> 1795 }
> 1796
> 1797 intel_init_cmci();
> 1798 mce_adjust_timer = cmci_intel_adjust_timer;
> 1799 }
> 1800
>
Will fix this issue in V2.
>---
>0-DAY kernel test infrastructureOpen Source Technology
>Center
>https://lists.01.org/pipermail/kbuild-all Intel Corporation
[PATCH v1 4/4] x86/mce: Add Zhaoxin LMCE support
Zhaoxin newer CPUs support LMCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin LMCE
in mce/core.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/include/asm/mce.h | 2 ++
arch/x86/kernel/cpu/mce/core.c | 25 +++--
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 0986a11..01840ec 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -352,8 +352,10 @@ static inline void mce_hygon_feature_init(struct
cpuinfo_x86 *c) { return mce_am
#ifdef CONFIG_CPU_SUP_ZHAOXIN
void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c);
+void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c);
#else
static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { }
+static inline void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) { }
#endif
#endif /* _ASM_X86_MCE_H */
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index a3b07ca..857570f 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1129,6 +1129,17 @@ static bool __mc_check_crashing_cpu(int cpu)
u64 mcgstatus;
mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
+
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
+ if (mcgstatus & MCG_STATUS_LMCES) {
+ return false;
+ } else {
+ if (mcgstatus & MCG_STATUS_RIPV)
+ mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
+ return true;
+ }
+ }
+
if (mcgstatus & MCG_STATUS_RIPV) {
mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
return true;
@@ -1279,9 +1290,10 @@ void do_machine_check(struct pt_regs *regs, long
error_code)
/*
* Check if this MCE is signaled to only this logical processor,
-* on Intel only.
+* on Intel, Zhaoxin only.
*/
- if (m.cpuvendor == X86_VENDOR_INTEL)
+ if (m.cpuvendor == X86_VENDOR_INTEL ||
+ m.cpuvendor == X86_VENDOR_ZHAOXIN)
lmce = m.mcgstatus & MCG_STATUS_LMCES;
/*
@@ -1795,9 +1807,15 @@ void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
}
intel_init_cmci();
+ intel_init_lmce();
mce_adjust_timer = cmci_intel_adjust_timer;
}
+void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
+{
+ intel_clear_lmce();
+}
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1834,6 +1852,9 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86
*c)
case X86_VENDOR_INTEL:
mce_intel_feature_clear(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_clear(c);
+ break;
default:
break;
}
--
2.7.4
[PATCH v1 2/4] x86/mce: Make 4 functions non-static
These functions are declared static and cannot be used in others
.c source file. this commit removes the static attribute and adds
the declaration to the header for these functions.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/intel.c| 8
arch/x86/kernel/cpu/mce/internal.h | 8
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 88cd959..eee4b12 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -423,7 +423,7 @@ void cmci_disable_bank(int bank)
raw_spin_unlock_irqrestore(_discover_lock, flags);
}
-static void intel_init_cmci(void)
+void intel_init_cmci(void)
{
int banks;
@@ -442,7 +442,7 @@ static void intel_init_cmci(void)
cmci_recheck();
}
-static void intel_init_lmce(void)
+void intel_init_lmce(void)
{
u64 val;
@@ -455,7 +455,7 @@ static void intel_init_lmce(void)
wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);
}
-static void intel_clear_lmce(void)
+void intel_clear_lmce(void)
{
u64 val;
@@ -467,7 +467,7 @@ static void intel_clear_lmce(void)
wrmsrl(MSR_IA32_MCG_EXT_CTL, val);
}
-static void intel_ppin_init(struct cpuinfo_x86 *c)
+void intel_ppin_init(struct cpuinfo_x86 *c)
{
unsigned long long val;
diff --git a/arch/x86/kernel/cpu/mce/internal.h
b/arch/x86/kernel/cpu/mce/internal.h
index 43031db..55d1f0a 100644
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -45,11 +45,19 @@ unsigned long cmci_intel_adjust_timer(unsigned long
interval);
bool mce_intel_cmci_poll(void);
void mce_intel_hcpu_update(unsigned long cpu);
void cmci_disable_bank(int bank);
+void intel_init_cmci(void);
+void intel_init_lmce(void);
+void intel_clear_lmce(void);
+void intel_ppin_init(struct cpuinfo_x86 *c);
#else
# define cmci_intel_adjust_timer mce_adjust_timer_default
static inline bool mce_intel_cmci_poll(void) { return false; }
static inline void mce_intel_hcpu_update(unsigned long cpu) { }
static inline void cmci_disable_bank(int bank) { }
+static inline void intel_init_cmci(void) { }
+static inline void intel_init_lmce(void) { }
+static inline void intel_clear_lmce(void) { }
+static inline void intel_ppin_init(struct cpuinfo_x86 *c) { }
#endif
void mce_timer_kick(unsigned long interval);
--
2.7.4
[PATCH v1 1/4] x86/mce: Add Zhaoxin MCE support
All Zhaoxin newer CPUs support MCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin MCE in
mce/core.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/cpu/mce/core.c | 30 --
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 743370e..3f878f6 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -488,8 +488,9 @@ int mce_usable_address(struct mce *m)
if (!(m->status & MCI_STATUS_ADDRV))
return 0;
- /* Checks after this one are Intel-specific: */
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ /* Checks after this one are Intel/Zhaoxin-specific: */
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 1;
if (!(m->status & MCI_STATUS_MISCV))
@@ -510,7 +511,8 @@ bool mce_is_memory_error(struct mce *m)
if (m->cpuvendor == X86_VENDOR_AMD ||
m->cpuvendor == X86_VENDOR_HYGON) {
return amd_mce_is_memory_error(m);
- } else if (m->cpuvendor == X86_VENDOR_INTEL) {
+ } else if (m->cpuvendor == X86_VENDOR_INTEL ||
+ m->cpuvendor == X86_VENDOR_ZHAOXIN) {
/*
* Intel SDM Volume 3B - 15.9.2 Compound Error Codes
*
@@ -1697,6 +1699,21 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c)
if (c->x86 == 6 && c->x86_model == 45)
quirk_no_way_out = quirk_sandybridge_ifu;
}
+
+ if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
+ /*
+* All newer Zhaoxin CPUs support MCE broadcasting. Enable
+* synchronization with a one second timeout.
+*/
+ if ((c->x86 == 6 && c->x86_model == 0x19 &&
+ (c->x86_stepping > 3 && c->x86_stepping < 8)) ||
+ (c->x86 == 6 && c->x86_model == 0x1f) ||
+c->x86 > 6) {
+ if (cfg->monarch_timeout < 0)
+ cfg->monarch_timeout = USEC_PER_SEC;
+ }
+ }
+
if (cfg->monarch_timeout < 0)
cfg->monarch_timeout = 0;
if (cfg->bootlog != 0)
@@ -2014,15 +2031,16 @@ static void mce_disable_error_reporting(void)
static void vendor_disable_error_reporting(void)
{
/*
-* Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs
-* are socket-wide.
+* Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
+* MSRs are socket-wide.
* Disabling them for just a single offlined CPU is bad, since it will
* inhibit reporting for all shared resources on the socket like the
* last level cache (LLC), the integrated memory controller (iMC), etc.
*/
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
- boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+ boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
return;
mce_disable_error_reporting();
--
2.7.4
[PATCH v1 3/4] x86/mce: Add Zhaoxin CMCI support
All Zhaoxin newer CPUs support CMCI that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin CMCI in
mce/core.c and mce/intel.c.
Signed-off-by: Tony W Wang-oc
---
arch/x86/include/asm/mce.h | 6 ++
arch/x86/kernel/cpu/mce/core.c | 25 +
arch/x86/kernel/cpu/mce/intel.c | 3 ++-
3 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index dc2d4b2..0986a11 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -350,4 +350,10 @@ umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc,
u64 *sys_addr) { return
static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) {
return mce_amd_feature_init(c); }
+#ifdef CONFIG_CPU_SUP_ZHAOXIN
+void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c);
+#else
+static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { }
+#endif
+
#endif /* _ASM_X86_MCE_H */
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 3f878f6..a3b07ca 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1777,6 +1777,27 @@ static void mce_centaur_feature_init(struct cpuinfo_x86
*c)
}
}
+void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
+{
+ struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
+
+ /*
+* These CPUs bank8 SVAD error may be triggered unexpected when
+* bringup virtual machine. it is not hardware bug. Always disable
+* bank8 SVAD error by default.
+*/
+ if ((c->x86 == 6 && c->x86_model == 0x19 &&
+ (c->x86_stepping > 3 && c->x86_stepping < 8)) ||
+ (c->x86 == 6 && c->x86_model == 0x1f) ||
+ (c->x86 == 7 && c->x86_model == 0x1b)) {
+ if (this_cpu_read(mce_num_banks) > 8)
+ mce_banks[8].ctl = 0;
+ }
+
+ intel_init_cmci();
+ mce_adjust_timer = cmci_intel_adjust_timer;
+}
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1798,6 +1819,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c)
mce_centaur_feature_init(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_init(c);
+ break;
+
default:
break;
}
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index eee4b12..b49cba7 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -85,7 +85,8 @@ static int cmci_supported(int *banks)
* initialization is vendor keyed and this
* makes sure none of the backdoors are entered otherwise.
*/
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 0;
if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)
return 0;
--
2.7.4
[PATCH] ALSA: hda: Add support of Zhaoxin controller
Add the new PCI ID 0x1d17 0x3288 Zhaoxin controller support
Signed-off-by: Tony W Wang-oc
---
sound/pci/hda/hda_intel.c | 4
1 file changed, 4 insertions(+)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 324a4b2..d08da0e 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -266,6 +266,7 @@ enum {
AZX_DRIVER_CTX,
AZX_DRIVER_CTHDA,
AZX_DRIVER_CMEDIA,
+ AZX_DRIVER_ZHAOXIN,
AZX_DRIVER_GENERIC,
AZX_NUM_DRIVERS, /* keep this as last entry */
};
@@ -379,6 +380,7 @@ static char *driver_short_names[] = {
[AZX_DRIVER_CTX] = "HDA Creative",
[AZX_DRIVER_CTHDA] = "HDA Creative",
[AZX_DRIVER_CMEDIA] = "HDA C-Media",
+ [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
[AZX_DRIVER_GENERIC] = "HD-Audio Generic",
};
@@ -2589,6 +2591,8 @@ static const struct pci_device_id azx_ids[] = {
.class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
.class_mask = 0xff,
.driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
+ /* Zhaoxin */
+ { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, azx_ids);
--
2.7.4
答复: 答复: [tip:x86/cpu] x86/cpu: Create Zhaoxin processors architecture support file
On Tue, 25 Jun 2019, Thomas Gleixner wrote:
> Tony,
>
> On Tue, 25 Jun 2019, Tony W Wang-oc wrote:
> > On Sun, Jun 23, 2019, Joe Perches wrote:
> > > > x86/cpu: Create Zhaoxin processors architecture support file
> > > >
> > > []
> > > > diff --git a/arch/x86/kernel/cpu/zhaoxin.c
> b/arch/x86/kernel/cpu/zhaoxin.c
> > > []
> > > > +static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
> > > > +{
> > > > + u32 lo, hi;
> > > > +
> > > > + /* Test for Extended Feature Flags presence */
> > > > + if (cpuid_eax(0xC000) >= 0xC001) {
> > > > + u32 tmp = cpuid_edx(0xC001);
> > > > +
> > > > + /* Enable ACE unit, if present and disabled */
> > > > + if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT)
> > > > {
> > >
> > > trivia:
> > >
> > > Perhaps this is more intelligible for humans to read
> > > and it deduplicates the comment as:
> > >
> > > if ((tmp & ACE_PRESENT) && !(tmp & ACE_ENABLED))
> > >
> > > The compiler produces the same object code.
> > >
> >
> > Thanks for the trivia, I will change this in the next version patch set.
>
> as you might have noticed from the tip bot commit notification mail, your
> patch set has been merged into the tip tree and is queued for the 5.3 merge
> window. So a new patch set is pointless. If at all then you can send a
> delta patch.
>
> Though I have to say, that I prefer the existing check:
>
> > > > + if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT)
> > > > {
>
> It's pretty clear, but that's really a matter of personal preference. So
> from my side there is nothing to do at all.
Got it, I will not change this code.
Thanks
TonyWWang-oc
答复: [tip:x86/cpu] x86/cpu: Create Zhaoxin processors architecture support file
On Sun, Jun 23, 2019, Joe Perches wrote:
> > x86/cpu: Create Zhaoxin processors architecture support file
> >
> []
> > diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
> []
> > +static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
> > +{
> > + u32 lo, hi;
> > +
> > + /* Test for Extended Feature Flags presence */
> > + if (cpuid_eax(0xC000) >= 0xC001) {
> > + u32 tmp = cpuid_edx(0xC001);
> > +
> > + /* Enable ACE unit, if present and disabled */
> > + if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
>
> trivia:
>
> Perhaps this is more intelligible for humans to read
> and it deduplicates the comment as:
>
> if ((tmp & ACE_PRESENT) && !(tmp & ACE_ENABLED))
>
> The compiler produces the same object code.
>
Thanks for the trivia, I will change this in the next version patch set.
Thanks
TonyWWang-oc
[tip:x86/cpu] x86/acpi/cstate: Add Zhaoxin processors support for cache flush policy in C3
Commit-ID: f8c0e061cb83bd528ff0843e717bcebc846d4838
Gitweb: https://git.kernel.org/tip/f8c0e061cb83bd528ff0843e717bcebc846d4838
Author: Tony W Wang-oc
AuthorDate: Tue, 18 Jun 2019 08:37:29 +
Committer: Thomas Gleixner
CommitDate: Sat, 22 Jun 2019 11:45:58 +0200
x86/acpi/cstate: Add Zhaoxin processors support for cache flush policy in C3
Same as Intel, Zhaoxin MP CPUs support C3 share cache and on all
recent Zhaoxin platforms ARB_DISABLE is a nop. So set related
flags correctly in the same way as Intel does.
Signed-off-by: Tony W Wang-oc
Signed-off-by: Thomas Gleixner
Cc: "h...@zytor.com"
Cc: "gre...@linuxfoundation.org"
Cc: "r...@rjwysocki.net"
Cc: "l...@kernel.org"
Cc: David Wang
Cc: "Cooper Yan(BJ-RD)"
Cc: "Qiyuan Wang(BJ-RD)"
Cc: "Herry Yang(BJ-RD)"
Link: https://lkml.kernel.org/r/a370503660994669991a7f7cda7c5...@zhaoxin.com
---
arch/x86/kernel/acpi/cstate.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index a5e5484988fd..caf2edccbad2 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -64,6 +64,21 @@ void acpi_processor_power_init_bm_check(struct
acpi_processor_flags *flags,
c->x86_stepping >= 0x0e))
flags->bm_check = 1;
}
+
+ if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
+ /*
+* All Zhaoxin CPUs that support C3 share cache.
+* And caches should not be flushed by software while
+* entering C3 type state.
+*/
+ flags->bm_check = 1;
+ /*
+* On all recent Zhaoxin platforms, ARB_DISABLE is a nop.
+* So, set bm_control to zero to indicate that ARB_DISABLE
+* is not required while entering C3 type state.
+*/
+ flags->bm_control = 0;
+ }
}
EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
[tip:x86/cpu] ACPI, x86: Add Zhaoxin processors support for NONSTOP TSC
Commit-ID: 773b2f30a3fc026f3ed121a8b945b0ae19b64ec5 Gitweb: https://git.kernel.org/tip/773b2f30a3fc026f3ed121a8b945b0ae19b64ec5 Author: Tony W Wang-oc AuthorDate: Tue, 18 Jun 2019 08:37:14 + Committer: Thomas Gleixner CommitDate: Sat, 22 Jun 2019 11:45:57 +0200 ACPI, x86: Add Zhaoxin processors support for NONSTOP TSC Zhaoxin CPUs have NONSTOP TSC feature, so enable the ACPI driver support for it. Signed-off-by: Tony W Wang-oc Signed-off-by: Thomas Gleixner Cc: "h...@zytor.com" Cc: "gre...@linuxfoundation.org" Cc: "r...@rjwysocki.net" Cc: "l...@kernel.org" Cc: David Wang Cc: "Cooper Yan(BJ-RD)" Cc: "Qiyuan Wang(BJ-RD)" Cc: "Herry Yang(BJ-RD)" Link: https://lkml.kernel.org/r/d1cfd937dabc44518d42038b55522...@zhaoxin.com --- drivers/acpi/acpi_pad.c | 1 + drivers/acpi/processor_idle.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c index 6b3f1217a237..e7dc0133f817 100644 --- a/drivers/acpi/acpi_pad.c +++ b/drivers/acpi/acpi_pad.c @@ -64,6 +64,7 @@ static void power_saving_mwait_init(void) case X86_VENDOR_HYGON: case X86_VENDOR_AMD: case X86_VENDOR_INTEL: + case X86_VENDOR_ZHAOXIN: /* * AMD Fam10h TSC will tick in all * C/P/S0/S1 states when this bit is set. diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index e387a258d649..ed56c6d20b08 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -196,6 +196,7 @@ static void tsc_check_state(int state) case X86_VENDOR_AMD: case X86_VENDOR_INTEL: case X86_VENDOR_CENTAUR: + case X86_VENDOR_ZHAOXIN: /* * AMD Fam10h TSC will tick in all * C/P/S0/S1 states when this bit is set.
[tip:x86/cpu] x86/cpu: Create Zhaoxin processors architecture support file
Commit-ID: 761fdd5e3327db6c646a09bab5ad48cd42680cd2
Gitweb: https://git.kernel.org/tip/761fdd5e3327db6c646a09bab5ad48cd42680cd2
Author: Tony W Wang-oc
AuthorDate: Tue, 18 Jun 2019 08:37:05 +
Committer: Thomas Gleixner
CommitDate: Sat, 22 Jun 2019 11:45:57 +0200
x86/cpu: Create Zhaoxin processors architecture support file
Add x86 architecture support for new Zhaoxin processors.
Carve out initialization code needed by Zhaoxin processors into
a separate compilation unit.
To identify Zhaoxin CPU, add a new vendor type X86_VENDOR_ZHAOXIN
for system recognition.
Signed-off-by: Tony W Wang-oc
Signed-off-by: Thomas Gleixner
Cc: "h...@zytor.com"
Cc: "gre...@linuxfoundation.org"
Cc: "r...@rjwysocki.net"
Cc: "l...@kernel.org"
Cc: David Wang
Cc: "Cooper Yan(BJ-RD)"
Cc: "Qiyuan Wang(BJ-RD)"
Cc: "Herry Yang(BJ-RD)"
Link: https://lkml.kernel.org/r/01042674b2f741b2aed1f797359bd...@zhaoxin.com
---
MAINTAINERS | 6 ++
arch/x86/Kconfig.cpu | 13 +++
arch/x86/include/asm/processor.h | 3 +-
arch/x86/kernel/cpu/Makefile | 1 +
arch/x86/kernel/cpu/zhaoxin.c| 167 +++
5 files changed, 189 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 57f496cff999..dfdefc6cb3a2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17477,6 +17477,12 @@ Q:
https://patchwork.linuxtv.org/project/linux-media/list/
S: Maintained
F: drivers/media/dvb-frontends/zd1301_demod*
+ZHAOXIN PROCESSOR SUPPORT
+M: Tony W Wang-oc
+L: linux-kernel@vger.kernel.org
+S: Maintained
+F: arch/x86/kernel/cpu/zhaoxin.c
+
ZPOOL COMPRESSED PAGE STORAGE API
M: Dan Streetman
L: linux...@kvack.org
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 6adce15268bd..8e29c991ba3e 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -480,3 +480,16 @@ config CPU_SUP_UMC_32
CPU might render the kernel unbootable.
If unsure, say N.
+
+config CPU_SUP_ZHAOXIN
+ default y
+ bool "Support Zhaoxin processors" if PROCESSOR_SELECT
+ help
+ This enables detection, tunings and quirks for Zhaoxin processors
+
+ You need this enabled if you want your kernel to run on a
+ Zhaoxin CPU. Disabling this option on other types of CPUs
+ makes the kernel a tiny bit smaller. Disabling it on a Zhaoxin
+ CPU might render the kernel unbootable.
+
+ If unsure, say N.
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index c34a35c78618..e57d2ca2ed87 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -144,7 +144,8 @@ enum cpuid_regs_idx {
#define X86_VENDOR_TRANSMETA 7
#define X86_VENDOR_NSC 8
#define X86_VENDOR_HYGON 9
-#define X86_VENDOR_NUM 10
+#define X86_VENDOR_ZHAOXIN 10
+#define X86_VENDOR_NUM 11
#define X86_VENDOR_UNKNOWN 0xff
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 5102bf7c8192..a7d9a4cb3ab6 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_CPU_SUP_CYRIX_32)+= cyrix.o
obj-$(CONFIG_CPU_SUP_CENTAUR) += centaur.o
obj-$(CONFIG_CPU_SUP_TRANSMETA_32) += transmeta.o
obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o
+obj-$(CONFIG_CPU_SUP_ZHAOXIN) += zhaoxin.o
obj-$(CONFIG_X86_MCE) += mce/
obj-$(CONFIG_MTRR) += mtrr/
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
new file mode 100644
index ..8e6f2f4b4afe
--- /dev/null
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0
+#include
+#include
+
+#include
+
+#include "cpu.h"
+
+#define MSR_ZHAOXIN_FCR57 0x1257
+
+#define ACE_PRESENT(1 << 6)
+#define ACE_ENABLED(1 << 7)
+#define ACE_FCR(1 << 7)/* MSR_ZHAOXIN_FCR */
+
+#define RNG_PRESENT(1 << 2)
+#define RNG_ENABLED(1 << 3)
+#define RNG_ENABLE (1 << 8)/* MSR_ZHAOXIN_RNG */
+
+#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x0020
+#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x0040
+#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x8000
+#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x0001
+#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x0002
+#define X86_VMX_FEATURE_PROC_CTLS2_VPID0x0020
+
+static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
+{
+ u32 lo, hi;
+
+ /* Test for Extended Feature Flags presence */
+ if (cpuid_eax(0xC000) >= 0xC001) {
+ u32 tmp = cpuid_edx(0xC001);
+
+ /* Enable ACE unit, if present and disabled */
+ if ((tmp & (ACE_PRESENT |
[PATCH v2 1/3] x86/cpu: Create Zhaoxin processors architecture support file
Add x86 architecture support for new Zhaoxin processors.
Carve out initialization code needed by Zhaoxin processors into
a separate compilation unit.
To identify Zhaoxin CPU, add a new vendor type X86_VENDOR_ZHAOXIN
for system recognition.
Signed-off-by: Tony W Wang-oc
---
MAINTAINERS | 6 ++
arch/x86/Kconfig.cpu | 13
arch/x86/include/asm/processor.h | 3 +-
arch/x86/kernel/cpu/Makefile | 1 +
arch/x86/kernel/cpu/zhaoxin.c| 164 +++
5 files changed, 186 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/kernel/cpu/zhaoxin.c
diff --git a/MAINTAINERS b/MAINTAINERS
index ff7c2b7e..0f10f68 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17562,6 +17562,12 @@ Q:
https://patchwork.linuxtv.org/project/linux-media/list/
S: Maintained
F: drivers/media/dvb-frontends/zd1301_demod*
+ZHAOXIN PROCESSOR SUPPORT
+M: Tony W Wang-oc
+L: linux-kernel@vger.kernel.org
+S: Maintained
+F: arch/x86/kernel/cpu/zhaoxin.c
+
ZPOOL COMPRESSED PAGE STORAGE API
M: Dan Streetman
L: linux...@kvack.org
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 6adce15..8e29c99 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -480,3 +480,16 @@ config CPU_SUP_UMC_32
CPU might render the kernel unbootable.
If unsure, say N.
+
+config CPU_SUP_ZHAOXIN
+ default y
+ bool "Support Zhaoxin processors" if PROCESSOR_SELECT
+ help
+ This enables detection, tunings and quirks for Zhaoxin processors
+
+ You need this enabled if you want your kernel to run on a
+ Zhaoxin CPU. Disabling this option on other types of CPUs
+ makes the kernel a tiny bit smaller. Disabling it on a Zhaoxin
+ CPU might render the kernel unbootable.
+
+ If unsure, say N.
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 6aba36b..3eab6ec 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -146,7 +146,8 @@ enum cpuid_regs_idx {
#define X86_VENDOR_TRANSMETA 7
#define X86_VENDOR_NSC 8
#define X86_VENDOR_HYGON 9
-#define X86_VENDOR_NUM 10
+#define X86_VENDOR_ZHAOXIN 10
+#define X86_VENDOR_NUM 11
#define X86_VENDOR_UNKNOWN 0xff
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 3ffe1b0..fab4378 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_CPU_SUP_CYRIX_32)+= cyrix.o
obj-$(CONFIG_CPU_SUP_CENTAUR) += centaur.o
obj-$(CONFIG_CPU_SUP_TRANSMETA_32) += transmeta.o
obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o
+obj-$(CONFIG_CPU_SUP_ZHAOXIN) += zhaoxin.o
obj-$(CONFIG_X86_MCE) += mce/
obj-$(CONFIG_MTRR) += mtrr/
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
new file mode 100644
index 000..d9d7de3
--- /dev/null
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+#include
+#include
+
+#include
+
+#include "cpu.h"
+
+#define MSR_ZHAOXIN_FCR57 0x1257
+
+#define ACE_PRESENT(1 << 6)
+#define ACE_ENABLED(1 << 7)
+#define ACE_FCR(1 << 7)/* MSR_ZHAOXIN_FCR */
+
+#define RNG_PRESENT(1 << 2)
+#define RNG_ENABLED(1 << 3)
+#define RNG_ENABLE (1 << 8)/* MSR_ZHAOXIN_RNG */
+
+#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x0020
+#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x0040
+#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x8000
+#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x0001
+#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x0002
+#define X86_VMX_FEATURE_PROC_CTLS2_VPID0x0020
+
+static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
+{
+ u32 lo, hi;
+
+ /* Test for Extended Feature Flags presence */
+ if (cpuid_eax(0xC000) >= 0xC001) {
+ u32 tmp = cpuid_edx(0xC001);
+
+ /* enable ACE unit, if present and disabled */
+ if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
+ rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ lo |= ACE_FCR; /* enable ACE unit */
+ wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ pr_info("CPU: Enabled ACE h/w crypto\n");
+ }
+
+ /* enable RNG unit, if present and disabled */
+ if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
+ rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ lo |= RNG_ENABLE; /* enable RNG unit */
+ wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ pr_info("CPU: Enabled h/w RNG\n");
+
[PATCH v2 2/3] ACPI, x86: add Zhaoxin processors support for NONSTOP TSC
Zhaoxin CPUs have NONSTOP TSC feature, so enable the ACPI driver support for it. Signed-off-by: Tony W Wang-oc --- drivers/acpi/acpi_pad.c | 1 + drivers/acpi/processor_idle.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c index 6b3f121..e7dc013 100644 --- a/drivers/acpi/acpi_pad.c +++ b/drivers/acpi/acpi_pad.c @@ -64,6 +64,7 @@ static void power_saving_mwait_init(void) case X86_VENDOR_HYGON: case X86_VENDOR_AMD: case X86_VENDOR_INTEL: + case X86_VENDOR_ZHAOXIN: /* * AMD Fam10h TSC will tick in all * C/P/S0/S1 states when this bit is set. diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index e387a25..ed56c6d 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -196,6 +196,7 @@ static void tsc_check_state(int state) case X86_VENDOR_AMD: case X86_VENDOR_INTEL: case X86_VENDOR_CENTAUR: + case X86_VENDOR_ZHAOXIN: /* * AMD Fam10h TSC will tick in all * C/P/S0/S1 states when this bit is set. -- 2.7.4
[PATCH v2 3/3] x86/acpi/cstate: add Zhaoxin processors support for cache flush policy in C3
Same as Intel, Zhaoxin MP CPUs support C3 share cache and on all
recent Zhaoxin platforms ARB_DISABLE is a nop. So set related
flags correctly in the same way as Intel does.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/acpi/cstate.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index a5e5484..caf2edc 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -64,6 +64,21 @@ void acpi_processor_power_init_bm_check(struct
acpi_processor_flags *flags,
c->x86_stepping >= 0x0e))
flags->bm_check = 1;
}
+
+ if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
+ /*
+* All Zhaoxin CPUs that support C3 share cache.
+* And caches should not be flushed by software while
+* entering C3 type state.
+*/
+ flags->bm_check = 1;
+ /*
+* On all recent Zhaoxin platforms, ARB_DISABLE is a nop.
+* So, set bm_control to zero to indicate that ARB_DISABLE
+* is not required while entering C3 type state.
+*/
+ flags->bm_control = 0;
+ }
}
EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
--
2.7.4
[PATCH v2 0/3] Add support for Zhaoxin Processors
As a new x86 CPU Vendor, Shanghai Zhaoxin Semiconductor Co., Ltd.
("Zhaoxin") provide high performance general-purpose x86 processors.
CPU Vendor ID "Shanghai" belongs to Zhaoxin.
To enable the supports of Linux kernel to Zhaoxin's CPUs, add a new vendor
type (X86_VENDOR_ZHAOXIN, with value of 10) in
arch/x86/include/asm/processor.h.
To enable the support of Linux kernel's specific configuration to
Zhaoxin's CPUs, add a new file arch/x86/kernel/cpu/zhaoxin.c.
This patch series have been applied and tested successfully on Zhaoxin's
Soc silicon. Also tested on other processors, it works fine and makes no
harm to the existing codes.
v1->v2:
- Rebased on 5.2.0-rc5 and tested against it.
- remove GPL "boilerplate" text in the patch.
- adjust signed-off-by: line match From: line.
- run patch series through checkpatch.pl.
v1:
- Rebased on 5.2.0-rc1 and tested against it.
- Split the patch set to small series of patches.
- Rework patch descriptions.
TonyWWang (3):
x86/cpu: Create Zhaoxin processors architecture support file
ACPI, x86: add Zhaoxin processors support for NONSTOP TSC
x86/acpi/cstate: add Zhaoxin processors support for cache flush policy
in C3
MAINTAINERS | 6 ++
arch/x86/Kconfig.cpu | 13
arch/x86/include/asm/processor.h | 3 +-
arch/x86/kernel/acpi/cstate.c| 15
arch/x86/kernel/cpu/Makefile | 1 +
arch/x86/kernel/cpu/zhaoxin.c| 164 +++
drivers/acpi/acpi_pad.c | 1 +
drivers/acpi/processor_idle.c| 1 +
8 files changed, 203 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/kernel/cpu/zhaoxin.c
--
2.7.4
[PATCH v2 3/3] x86/acpi/cstate: add Zhaoxin processors support for cache flush policy in C3
Same as Intel, Zhaoxin MP CPUs support C3 share cache and on all
recent Zhaoxin platforms ARB_DISABLE is a nop. So set related
flags correctly in the same way as Intel does.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/acpi/cstate.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index a5e5484..caf2edc 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -64,6 +64,21 @@ void acpi_processor_power_init_bm_check(struct
acpi_processor_flags *flags,
c->x86_stepping >= 0x0e))
flags->bm_check = 1;
}
+
+ if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
+ /*
+* All Zhaoxin CPUs that support C3 share cache.
+* And caches should not be flushed by software while
+* entering C3 type state.
+*/
+ flags->bm_check = 1;
+ /*
+* On all recent Zhaoxin platforms, ARB_DISABLE is a nop.
+* So, set bm_control to zero to indicate that ARB_DISABLE
+* is not required while entering C3 type state.
+*/
+ flags->bm_control = 0;
+ }
}
EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
--
2.7.4
[PATCH v2 2/3] ACPI, x86: add Zhaoxin processors support for NONSTOP TSC
Zhaoxin CPUs have NONSTOP TSC feature, so enable the ACPI driver support for it. Signed-off-by: Tony W Wang-oc --- drivers/acpi/acpi_pad.c | 1 + drivers/acpi/processor_idle.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c index a47676a..c06306e 100644 --- a/drivers/acpi/acpi_pad.c +++ b/drivers/acpi/acpi_pad.c @@ -73,6 +73,7 @@ static void power_saving_mwait_init(void) case X86_VENDOR_HYGON: case X86_VENDOR_AMD: case X86_VENDOR_INTEL: + case X86_VENDOR_ZHAOXIN: /* * AMD Fam10h TSC will tick in all * C/P/S0/S1 states when this bit is set. diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 98d4ec5..fa95ce9 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -209,6 +209,7 @@ static void tsc_check_state(int state) case X86_VENDOR_AMD: case X86_VENDOR_INTEL: case X86_VENDOR_CENTAUR: + case X86_VENDOR_ZHAOXIN: /* * AMD Fam10h TSC will tick in all * C/P/S0/S1 states when this bit is set. -- 2.7.4
答复: 答复: Re: [tip:x86/urgent] x86/mce: Ensure offline CPUs don' t participate in rendezvous process
On Fri, May 31, 2019, Raj, Ashok wrote: > On Thu, May 30, 2019 at 09:13:39AM +0000, Tony W Wang-oc wrote: > > On Thu, May 30, 2019, Tony W Wang-oc wrote: > > > Hi Ashok, > > > I have two questions about this patch, could you help to check: > > > > > > 1, for broadcast #MC exceptions, this patch seems require #MC exception > > > errors > > > set MCG_STATUS_RIPV = 1. > > > But for Intel CPU, some #MC exception errors set MCG_STATUS_RIPV = 0 > > > (like "Recoverable-not-continuable SRAR Type" Errors), for these errors > > > the patch doesn't seem to work, is that okay? > > > > > > 2, for LMCE exceptions, this patch seems require #MC exception errors > > > set MCG_STATUS_RIPV = 0 to make sure LMCE be handled normally even > > > on offline CPU. > > > For LMCE errors set MCG_STAUS_RIPV = 1, the patch prevents offline CPU > > > handle these LMCE errors, is that okay? > > > > > > > More specifically, this patch seems require #MC exceptions meet the > condition > > "MCG_STATUS_RIPV ^ MCG_STATUS_LMCES == 1"; But on a Xeon X5650 > machine (SMP), > > The offline CPU will never get a LMCE=1, since those only happen on the CPU > that's doing active work. Offline CPUs just sitting in idle. > > The specific error here is a PCC=1, so irrespective of what happens > We do capture the errors in the per-cpu log, and kernel would panic. > > What specifically this patch tries to achieve is to leave an error > sitting with MCG-STATUS.MCIP=1 and another recoverable error would shut > the > system dowm. Yes, agree with you for this point. But for question 1, When some #MC exception errors broadcast to offline CPU, like "Recoverable-not-continuable SRAR Type" Errors, set MCG_STATUS_RIPV = 0, PCC = 0, is there also the problem : " Kernel panic - not syncing: Timeout: Not all CPUs entered broadcast exception handler"? Thanks > > I don't see anything wrong with what this patch does.. > > > "Data CACHE Level-2 Generic Error" does not meet this condition. > > > > I got below message from: > https://www.centos.org/forums/viewtopic.php?p=292742 > > > > Hardware event. This is not a software error. > > MCE 0 > > CPU 4 BANK 6 TSC b7065eeaa18b0 > > TIME 1545643603 Mon Dec 24 10:26:43 2018 > > MCG status:MCIP > > MCi status: > > Uncorrected error > > Error enabled > > Processor context corrupt > > MCA: Data CACHE Level-2 Generic Error > > STATUS b2008106 MCGSTATUS 4 > > MCGCAP 1c09 APICID 4 SOCKETID 0 > > CPUID Vendor Intel Family 6 Model 44 > > > > > Thanks > > > Tony W Wang-oc
答复: Re: [tip:x86/urgent] x86/mce: Ensure offline CPUs don' t participate in rendezvous process
On Thu, May 30, 2019, Tony W Wang-oc wrote: > Hi Ashok, > I have two questions about this patch, could you help to check: > > 1, for broadcast #MC exceptions, this patch seems require #MC exception > errors > set MCG_STATUS_RIPV = 1. > But for Intel CPU, some #MC exception errors set MCG_STATUS_RIPV = 0 > (like "Recoverable-not-continuable SRAR Type" Errors), for these errors > the patch doesn't seem to work, is that okay? > > 2, for LMCE exceptions, this patch seems require #MC exception errors > set MCG_STATUS_RIPV = 0 to make sure LMCE be handled normally even > on offline CPU. > For LMCE errors set MCG_STAUS_RIPV = 1, the patch prevents offline CPU > handle these LMCE errors, is that okay? > More specifically, this patch seems require #MC exceptions meet the condition "MCG_STATUS_RIPV ^ MCG_STATUS_LMCES == 1"; But on a Xeon X5650 machine (SMP), "Data CACHE Level-2 Generic Error" does not meet this condition. I got below message from: https://www.centos.org/forums/viewtopic.php?p=292742 Hardware event. This is not a software error. MCE 0 CPU 4 BANK 6 TSC b7065eeaa18b0 TIME 1545643603 Mon Dec 24 10:26:43 2018 MCG status:MCIP MCi status: Uncorrected error Error enabled Processor context corrupt MCA: Data CACHE Level-2 Generic Error STATUS b2008106 MCGSTATUS 4 MCGCAP 1c09 APICID 4 SOCKETID 0 CPUID Vendor Intel Family 6 Model 44 > Thanks > Tony W Wang-oc
Re: [tip:x86/urgent] x86/mce: Ensure offline CPUs don' t participate in rendezvous process
Hi Ashok, I have two questions about this patch, could you help to check: 1, for broadcast #MC exceptions, this patch seems require #MC exception errors set MCG_STATUS_RIPV = 1. But for Intel CPU, some #MC exception errors set MCG_STATUS_RIPV = 0 (like "Recoverable-not-continuable SRAR Type" Errors), for these errors the patch doesn't seem to work, is that okay? 2, for LMCE exceptions, this patch seems require #MC exception errors set MCG_STATUS_RIPV = 0 to make sure LMCE be handled normally even on offline CPU. For LMCE errors set MCG_STAUS_RIPV = 1, the patch prevents offline CPU handle these LMCE errors, is that okay? Thanks Tony W Wang-oc
Re: [tip:x86/urgent] x86/mce: Ensure offline CPUs don' t participate in rendezvous process
Hi, This patch requires all #MC exception errors set MCG_STATUS_RIPV = 1? Because on offline CPUs, for #MC exception errors set MCG_STATUS_RIPV = 0 (like "Recoverable-not-continuable SRAR Type" Errors), this patch doesn't seem to work. if this patch's "return; " in a wrong place? Thanks Tony W Wang-oc
[PATCH v2 1/3] x86/cpu: Create Zhaoxin processors architecture support file
Add x86 architecture support for new Zhaoxin processors.
Carve out initialization code needed by Zhaoxin processors into
a separate compilation unit.
To identify Zhaoxin CPU, add a new vendor type X86_VENDOR_ZHAOXIN
for system recognition.
Signed-off-by: Tony W Wang-oc
---
MAINTAINERS | 6 ++
arch/x86/Kconfig.cpu | 13
arch/x86/include/asm/processor.h | 3 +-
arch/x86/kernel/cpu/Makefile | 1 +
arch/x86/kernel/cpu/zhaoxin.c| 164 +++
5 files changed, 186 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/kernel/cpu/zhaoxin.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 429c6c6..0f2995a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17458,6 +17458,12 @@ Q:
https://patchwork.linuxtv.org/project/linux-media/list/
S: Maintained
F: drivers/media/dvb-frontends/zd1301_demod*
+ZHAOXIN PROCESSOR SUPPORT
+M: Tony W Wang-oc
+L: linux-kernel@vger.kernel.org
+S: Maintained
+F: arch/x86/kernel/cpu/zhaoxin.c
+
ZPOOL COMPRESSED PAGE STORAGE API
M: Dan Streetman
L: linux...@kvack.org
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 6adce15..8e29c99 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -480,3 +480,16 @@ config CPU_SUP_UMC_32
CPU might render the kernel unbootable.
If unsure, say N.
+
+config CPU_SUP_ZHAOXIN
+ default y
+ bool "Support Zhaoxin processors" if PROCESSOR_SELECT
+ help
+ This enables detection, tunings and quirks for Zhaoxin processors
+
+ You need this enabled if you want your kernel to run on a
+ Zhaoxin CPU. Disabling this option on other types of CPUs
+ makes the kernel a tiny bit smaller. Disabling it on a Zhaoxin
+ CPU might render the kernel unbootable.
+
+ If unsure, say N.
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index c34a35c..e57d2ca 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -144,7 +144,8 @@ enum cpuid_regs_idx {
#define X86_VENDOR_TRANSMETA 7
#define X86_VENDOR_NSC 8
#define X86_VENDOR_HYGON 9
-#define X86_VENDOR_NUM 10
+#define X86_VENDOR_ZHAOXIN 10
+#define X86_VENDOR_NUM 11
#define X86_VENDOR_UNKNOWN 0xff
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 1796d2b..601fcff 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_CPU_SUP_CYRIX_32)+= cyrix.o
obj-$(CONFIG_CPU_SUP_CENTAUR) += centaur.o
obj-$(CONFIG_CPU_SUP_TRANSMETA_32) += transmeta.o
obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o
+obj-$(CONFIG_CPU_SUP_ZHAOXIN) += zhaoxin.o
obj-$(CONFIG_X86_MCE) += mce/
obj-$(CONFIG_MTRR) += mtrr/
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
new file mode 100644
index 000..d9d7de3
--- /dev/null
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+#include
+#include
+
+#include
+
+#include "cpu.h"
+
+#define MSR_ZHAOXIN_FCR57 0x1257
+
+#define ACE_PRESENT(1 << 6)
+#define ACE_ENABLED(1 << 7)
+#define ACE_FCR(1 << 7)/* MSR_ZHAOXIN_FCR */
+
+#define RNG_PRESENT(1 << 2)
+#define RNG_ENABLED(1 << 3)
+#define RNG_ENABLE (1 << 8)/* MSR_ZHAOXIN_RNG */
+
+#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x0020
+#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x0040
+#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x8000
+#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x0001
+#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x0002
+#define X86_VMX_FEATURE_PROC_CTLS2_VPID0x0020
+
+static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
+{
+ u32 lo, hi;
+
+ /* Test for Extended Feature Flags presence */
+ if (cpuid_eax(0xC000) >= 0xC001) {
+ u32 tmp = cpuid_edx(0xC001);
+
+ /* enable ACE unit, if present and disabled */
+ if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
+ rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ lo |= ACE_FCR; /* enable ACE unit */
+ wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ pr_info("CPU: Enabled ACE h/w crypto\n");
+ }
+
+ /* enable RNG unit, if present and disabled */
+ if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
+ rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ lo |= RNG_ENABLE; /* enable RNG unit */
+ wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ pr_info("CPU: Enabled h/w RNG\n");
+
[PATCH v2 0/3] Add support for Zhaoxin Processors
As a new x86 CPU Vendor, Shanghai Zhaoxin Semiconductor Co., Ltd.
("Zhaoxin") provide high performance general-purpose x86 processors.
CPU Vendor ID "Shanghai" belongs to Zhaoxin.
To enable the supports of Linux kernel to Zhaoxin's CPUs, add a new vendor
type (X86_VENDOR_ZHAOXIN, with value of 10) in
arch/x86/include/asm/processor.h.
To enable the support of Linux kernel's specific configuration to
Zhaoxin's CPUs, add a new file arch/x86/kernel/cpu/zhaoxin.c.
This patch series have been applied and tested successfully on Zhaoxin's
Soc silicon. Also tested on other processors, it works fine and makes no
harm to the existing codes.
v1->v2:
- Rebased on 5.2.0-rc2 and tested against it.
- remove GPL "boilerplate" text in the patch.
- adjust signed-off-by: line match From: line.
- run patch series through checkpatch.pl.
v1:
- Rebased on 5.2.0-rc1 and tested against it.
- Split the patch set to small series of patches.
- Rework patch descriptions.
TonyWWang (3):
x86/cpu: Create Zhaoxin processors architecture support file
ACPI, x86: add Zhaoxin processors support for NONSTOP TSC
x86/acpi/cstate: add Zhaoxin processors support for cache flush policy
in C3
MAINTAINERS | 6 ++
arch/x86/Kconfig.cpu | 13
arch/x86/include/asm/processor.h | 3 +-
arch/x86/kernel/acpi/cstate.c| 15
arch/x86/kernel/cpu/Makefile | 1 +
arch/x86/kernel/cpu/zhaoxin.c| 164 +++
drivers/acpi/acpi_pad.c | 1 +
drivers/acpi/processor_idle.c| 1 +
8 files changed, 203 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/kernel/cpu/zhaoxin.c
--
2.7.4
