Re: [PATCHv3 3/3] edac: altera: Add EDAC support for Altera SDRAM

On Thu, May 8, 2014 at 7:05 AM, Borislav Petkov b...@alien8.de wrote: On Mon, May 05, 2014 at 05:52:17PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Missing commit message. Whoops. I don't know what happened there. I'll fix it. --- v2: Use the SDRAM controller

Re: [PATCHv3 3/3] edac: altera: Add EDAC support for Altera SDRAM

On Thu, May 8, 2014 at 5:44 PM, Dinh Nguyen dinh.li...@gmail.com wrote: On 5/5/14 5:52 PM, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com --- v2: Use the SDRAM controller registers to calculate memory size instead of the Device Tree. Update To Cc list. Add maintainer

Re: [PATCHv3 3/3] edac: altera: Add EDAC support for Altera SDRAM

On Fri, May 9, 2014 at 8:52 AM, Borislav Petkov b...@alien8.de wrote: On Thu, May 08, 2014 at 03:37:19PM -0500, Thor Thayer wrote: Yes. Their reasoning is that they want to retain the rights and warranty language with the file (just in case the COPYING file changes). Ok, thanks for checking

Re: [PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

On Tue, May 20, 2014 at 9:44 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: Hi! On Tue, May 20, 2014 at 09:31:06AM -0500, Alan Tull wrote: On Mon, May 19, 2014 at 2:37 PM, Thor Thayer tthayer.li...@gmail.com wrote: diff --git a/Documentation/devicetree/bindings/arm/altera

Re: [PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

On Fri, May 16, 2014 at 2:53 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: Hi! On Thu, May 15, 2014 at 11:04:49AM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM controller bindings and device tree changes to the Altera SoC project

Re: [PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

On Mon, May 19, 2014 at 2:12 PM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: Hi Thor! On Mon, May 19, 2014 at 01:36:30PM -0500, Thor Thayer wrote: On Fri, May 16, 2014 at 2:53 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: Hi! On Thu, May 15, 2014 at 11:04:49AM -0500, ttha

Re: [PATCHv5 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM Controller

On Mon, May 26, 2014 at 4:57 AM, Borislav Petkov b...@alien8.de wrote: On Thu, May 15, 2014 at 11:04:51AM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com v2: Use the SDRAM controller registers to calculate memory size instead of the Device Tree. Update To Cc list

Re: [PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

On Tue, May 27, 2014 at 2:11 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: On Wed, May 21, 2014 at 10:38:34AM -0500, Thor Thayer wrote: On Tue, May 20, 2014 at 9:44 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: Hi! On Tue, May 20, 2014 at 09:31:06AM -0500, Alan Tull wrote

Re: [PATCHv3 3/3] edac: altera: Add EDAC support for Altera SDRAM

On Fri, May 9, 2014 at 3:52 PM, Borislav Petkov b...@alien8.de wrote: On Fri, May 09, 2014 at 03:31:53PM -0500, Thor Thayer wrote: Yes, good point. Our hardware can't recover from Double Bit Errors so I'll go back to the panic() in that path. I like the flexibility of the command line

Re: [PATCHv4 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM Controller

On Mon, May 12, 2014 at 7:12 PM, Borislav Petkov b...@alien8.de wrote: On Mon, May 12, 2014 at 06:36:57PM -0500, ttha...@altera.com wrote: + ptemp[0] = 0x5A5A5A5A; + ptemp[1] = 0xA5A5A5A5; + /* Clear the error injection bits */ + regmap_write(drvdata-mc_vbase, CTLCFG,

Re: [PATCHv3 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

Hi Sören On Mon, May 5, 2014 at 6:16 PM, Sören Brinkmann soren.brinkm...@xilinx.com wrote: Hi Thor, On Mon, 2014-05-05 at 05:52PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM controller bindings and device tree changes

Re: [PATCHv3 3/3] edac: altera: Add EDAC support for Altera SDRAM

On Tue, May 6, 2014 at 10:42 AM, Dinh Nguyen dingu...@altera.com wrote: On Mon, 2014-05-05 at 17:52 -0500, Thor Thayer wrote: From: Thor Thayer ttha...@altera.com --- v2: Use the SDRAM controller registers to calculate memory size instead of the Device Tree. Update To Cc list. Add

Re: [PATCH 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

On Tue, 2014-04-08 at 12:08 +0200, Borislav Petkov wrote: On Mon, Apr 07, 2014 at 04:54:09PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Added EDAC support for reporting ECC errors of CycloneV and ArriaV SDRAM controller. - The SDRAM Controller registers

Re: [PATCH 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

On Tue, 2014-04-08 at 14:45 +0200, Steffen Trumtrar wrote: On Tue, Apr 08, 2014 at 11:45:25AM +0100, Mark Rutland wrote: On Mon, Apr 07, 2014 at 10:54:09PM +0100, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Added EDAC support for reporting ECC errors of CycloneV

Re: [PATCH 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

On Tue, 2014-04-08 at 15:38 +0200, Steffen Trumtrar wrote: Hi! On Mon, Apr 07, 2014 at 04:54:07PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM controller bindings and device tree changes to the Altera SoC project. [snip

Re: [PATCH 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

On Tue, 2014-04-08 at 18:22 +0200, Borislav Petkov wrote: On Tue, Apr 08, 2014 at 05:10:54PM +0100, Mark Rutland wrote: Typically the bindings would go with the driver via the appropriate subsystem maintainer. That way we don't get bindings without drivers or vice-versa if there's a problem

Re: [PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

On Wed, 2014-04-23 at 16:54 +0200, Borislav Petkov wrote: On Tue, Apr 15, 2014 at 06:30:10PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Added EDAC support for reporting ECC errors of CycloneV and ArriaV SDRAM controller. - The SDRAM Controller registers

Re: [PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

On Mon, 2014-04-21 at 12:27 +0200, Pavel Machek wrote: Hi! From: Thor Thayer ttha...@altera.com Added EDAC support for reporting ECC errors of CycloneV and ArriaV SDRAM controller. - The SDRAM Controller registers are used by the FPGA bridge so these are accessed through

Re: [PATCH 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

On Tue, 2014-04-08 at 13:52 -0500, Rob Herring wrote: On Tue, Apr 8, 2014 at 11:02 AM, delicious quinoa delicious.qui...@gmail.com wrote: On Tue, Apr 8, 2014 at 9:33 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote: On Tue

Re: [PATCH 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

On Tue, 2014-04-08 at 13:52 -0500, Rob Herring wrote: On Tue, Apr 8, 2014 at 11:02 AM, delicious quinoa delicious.qui...@gmail.com wrote: On Tue, Apr 8, 2014 at 9:33 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote: On Tue

Re: [PATCH 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

On Tue, 2014-04-08 at 13:52 -0500, Rob Herring wrote: On Tue, Apr 8, 2014 at 11:02 AM, delicious quinoa delicious.qui...@gmail.com wrote: On Tue, Apr 8, 2014 at 9:33 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote: On Tue

Re: [PATCHv7 2/3] devicetree: Addition of the Altera SDRAM EDAC.

On Thu, Jun 26, 2014 at 4:45 AM, Mark Rutland mark.rutl...@arm.com wrote: On Wed, Jun 25, 2014 at 10:15:26PM +0100, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC project. Signed-off-by: Thor

Re: [PATCHv7 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM Controller.

Hi Dinh, On Wed, Jun 25, 2014 at 4:12 PM, Dinh Nguyen dinh.li...@gmail.com wrote: Hi Thor, On 06/25/2014 04:15 PM, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com This patch adds support for the CycloneV and ArriaV SDRAM controllers. Correction and reporting of SBEs, Panic

Re: [PATCHv6 1/3] devicetree: Addition of the Altera SDRAM controller

On Sat, Jun 21, 2014 at 4:04 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: Hi! On Fri, Jun 20, 2014 at 06:22:01PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM Controller bindings and device tree changes. v2: Changes to SoC SDRAM

Re: [PATCHv6 2/3] devicetree: Addition of the Altera SDRAM EDAC

On Sat, Jun 21, 2014 at 4:06 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: On Fri, Jun 20, 2014 at 06:22:02PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM EDAC bindings and device tree changes v2: Changes to SoC EDAC source code

Re: [PATCHv7 2/3] devicetree: Addition of the Altera SDRAM EDAC.

Hi Mark On Thu, Jun 26, 2014 at 4:45 AM, Mark Rutland mark.rutl...@arm.com wrote: On Wed, Jun 25, 2014 at 10:15:26PM +0100, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC project. Signed-off

Re: [PATCHv10 2/2] arm: dts: Add Altera SDRAM EDAC bindings devicetree entries.

On 08/14/2014 01:49 PM, Pavel Machek wrote: On Mon 2014-08-11 10:18:13, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC project. Signed-off-by: Thor Thayer ttha

Re: [PATCHv10 1/2] edac: altera: Add Altera SDRAM EDAC support.

On 08/14/2014 01:49 PM, Pavel Machek wrote: On Mon 2014-08-11 10:18:12, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com This patch adds support for the CycloneV and ArriaV SDRAM controllers. Correction and reporting of SBEs, Panic on DBEs. Signed-off

Re: [PATCHv9 1/3] mfd: altera: Add Altera SDRAM Controller

On 07/31/2014 03:26 AM, Lee Jones wrote: On Wed, 30 Jul 2014, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com Add a simple MFD for the Altera SDRAM Controller. Signed-off-by: Alan Tull at...@opensource.altera.com Signed-off-by: Thor Thayer ttha

Re: [PATCHv9 1/3] mfd: altera: Add Altera SDRAM Controller

On 08/01/2014 03:13 AM, Lee Jones wrote: On Thu, 31 Jul 2014, Thor Thayer wrote: On 07/31/2014 03:26 AM, Lee Jones wrote: On Wed, 30 Jul 2014, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com Add a simple MFD for the Altera SDRAM Controller. Signed-off

Re: [PATCHv9 1/3] mfd: altera: Add Altera SDRAM Controller

On 08/02/2014 12:08 PM, Steffen Trumtrar wrote: Hi! On Fri, Aug 01, 2014 at 05:27:57PM -0500, Thor Thayer wrote: On 08/01/2014 03:13 AM, Lee Jones wrote: On Thu, 31 Jul 2014, Thor Thayer wrote: On 07/31/2014 03:26 AM, Lee Jones wrote: On Wed, 30 Jul 2014, ttha...@opensource.altera.com

Re: [PATCHv10 2/2] arm: dts: Add Altera SDRAM EDAC bindings devicetree entries.

On 08/15/2014 11:07 AM, atull wrote: On Fri, 15 Aug 2014, Steffen Trumtrar wrote: Hi! Hello Thanks for the feedback... ttha...@opensource.altera.com writes: From: Thor Thayer ttha...@opensource.altera.com Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC

Re: [PATCHv9 3/3] arm: dts: Add Altera SDRAM controller bindings

On 08/17/2014 07:50 PM, Rob Herring wrote: On 07/30/2014 01:22 PM, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com Add the Altera SDRAM controller bindings and device tree changes to the Altera SoC project. Signed-off-by: Thor Thayer ttha

Re: [PATCHv2 0/4] Add Altera peripheral memories to EDAC framework

Hi Borislav, On 10/17/2014 03:33 PM, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com This patch adds the L2 cache and OCRAM peripherals to the EDAC framework using the EDAC device framework. The ECC is enabled early in the boot process in the platform

Re: [PATCHv2 0/4] Add Altera peripheral memories to EDAC framework

On 10/27/2014 03:43 PM, Borislav Petkov wrote: On Mon, Oct 27, 2014 at 01:50:24PM -0500, Thor Thayer wrote: Do you have any comments about this driver? Just a question: why do you have three .c files for something which does only error injection and nothing else AFAICT? Why isn't this part

Re: [PATCHv2 0/4] Add Altera peripheral memories to EDAC framework

On 10/27/2014 04:59 PM, Borislav Petkov wrote: On Mon, Oct 27, 2014 at 04:35:00PM -0500, Thor Thayer wrote: Should I move the EDAC Device probe and error handling from altera_edac_mgr.c to altera_edac.c? Can I mix the MC and Device models in the same file? Right, for basic practical reasons

[RESEND PATCHv5 5/5] arm: dts: Add Altera L2 Cache and OCRAM EDAC

Hi all, On 11/11/2014 06:14 PM, ttha...@opensource.altera.com wrote: From: Thor Thayerttha...@opensource.altera.com Adding the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to declare and setup On-chip RAM

Re: [PATCH] spi: spidev: Don't mangle max_speed_hz in underlying spi device

Hi Mark, On 11/08/2014 04:29 AM, Mark Brown wrote: Currently spidev allows callers to set the default speed by overriding the max_speed_hz in the underlying device. This achieves the immediate goal but is not what devices expect and can easily lead to userspace trying to set unsupported speeds

Re: [PATCHv4 1/5] arm: socfpga: Enable L2 Cache ECC on startup.

Hi Dinh, On 11/07/2014 02:13 PM, Dinh Nguyen wrote: Hi Thor, On 11/07/2014 10:54 AM, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com This patch enables the ECC for L2 cache on machine startup. The ECC has to be enabled before data is is stored in memory

Re: [PATCHv4 2/5] arm: socfpga: Enable OCRAM ECC on startup.

Hi Dinh, On 11/07/2014 02:32 PM, Dinh Nguyen wrote: Hi Thor, On 11/07/2014 10:54 AM, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com This patch enables the ECC for On-Chip RAM on machine startup. The ECC has to be enabled before data is is stored

Re: [RESEND PATCHv5 5/5] arm: dts: Add Altera L2 Cache and OCRAM EDAC

On 12/02/2014 09:01 AM, Mark Rutland wrote: Hi Thor, On Mon, Dec 01, 2014 at 08:47:41PM +, Thor Thayer wrote: Hi Boris, On 11/18/2014 02:56 PM, Thor Thayer wrote: Hi all, On 11/11/2014 06:14 PM, ttha...@opensource.altera.com wrote: From: Thor Thayerttha...@opensource.altera.com

Re: [PATCHv5 2/5] arm: socfpga: Enable OCRAM ECC on startup.

On 12/02/2014 09:11 AM, Mark Rutland wrote: On Wed, Nov 12, 2014 at 12:14:20AM +, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com This patch enables the ECC for On-Chip RAM on machine startup. The ECC has to be enabled before data is is stored

Re: [PATCHv5 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

+}; + +#endif /* #ifdef CONFIG_EDAC_ALTERA_L2C */ + MODULE_LICENSE(GPL v2); MODULE_AUTHOR(Thor Thayer); -MODULE_DESCRIPTION(EDAC Driver for Altera SDRAM Controller); +MODULE_DESCRIPTION(EDAC Driver for Altera Memories); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux

Re: [PATCHv5 5/5] arm: dts: Add Altera L2 Cache and OCRAM EDAC

On 12/02/2014 08:57 AM, Mark Rutland wrote: On Wed, Nov 12, 2014 at 12:14:23AM +, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com Adding the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies

Re: [PATCHv3 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

Hi Boris! On 11/04/2014 09:12 AM, Borislav Petkov wrote: On Thu, Oct 30, 2014 at 10:32:10AM -0500, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM

Re: [RESEND PATCHv5 5/5] arm: dts: Add Altera L2 Cache and OCRAM EDAC

Hi Boris, On 11/18/2014 02:56 PM, Thor Thayer wrote: Hi all, On 11/11/2014 06:14 PM, ttha...@opensource.altera.com wrote: From: Thor Thayerttha...@opensource.altera.com Adding the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies

Re: [PATCHv6 2/5] arm: socfpga: Enable OCRAM ECC on startup.

Hi Mark, On 02/06/2015 12:45 PM, Mark Rutland wrote: On Fri, Jan 09, 2015 at 02:53:53AM +, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com This patch enables the ECC for On-Chip RAM on machine startup. The ECC has to be enabled before data

Re: [PATCHv6 5/5] arm: dts: Add Altera L2 Cache and OCRAM EDAC entries

Hi Mark On 02/06/2015 01:24 PM, Mark Rutland wrote: On Fri, Jan 09, 2015 at 02:53:56AM +, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com Adding the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch

Re: [PATCHv6 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

On 02/06/2015 01:17 PM, Mark Rutland wrote: On Fri, Jan 09, 2015 at 02:53:55AM +, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller

[RESEND PATCHv6 5/5] arm: dts: Add Altera L2 Cache and OCRAM EDAC entries

Hi Device Tree Maintainers, On 01/08/2015 08:53 PM, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com Adding the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to declare

Re: [PATCHv6 0/5] Add Altera peripheral memories to EDAC framework

Hi Device Tree Maintainers, On 01/08/2015 08:53 PM, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com This patch adds the L2 cache and OCRAM peripherals to the EDAC framework using the EDAC device framework. The ECC is enabled early in the boot process

Re: [PATCH 3/4] edac, altera: Addition of Arria10 EDAC

On 05/14/2015 03:20 PM, Dinh Nguyen wrote: On 05/13/2015 04:49 PM, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com The Arria10 SDRAM and ECC system differs significantly from the Cyclone5 and Arria5 SoCs. This patch adds support for the Arria10 SoC. 1

Re: [PATCH 4/4] dts, altera: Arria10 SDRAM EDAC DTS additions.

Hi Arnd, On 05/15/2015 05:55 AM, Arnd Bergmann wrote: On Wednesday 13 May 2015 16:49:47 ttha...@opensource.altera.com wrote: + sdr: sdr@ffc25000 { + compatible = syscon; + reg = 0xffcfb100 0x80; + }; + A syscon node

Re: [PATCHv2 2/4] edac, altera: Refactor EDAC for Altera CycloneV SoC.

On 06/04/2015 10:26 AM, Dinh Nguyen wrote: On 06/04/2015 09:28 AM, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com The Arria10 SOC uses a completely different SDRAM controller from the earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits

Re: [PATCH] EDAC, altera: wrap edac pm with a CONFIG_PM

Hi Boris, On 06/05/2015 10:15 AM, Borislav Petkov wrote: On Fri, Jun 05, 2015 at 08:49:15AM -0500, dingu...@opensource.altera.com wrote: From: Alan Tull at...@opensource.altera.com Suspend-to-RAM and EDAC support are mutually exclusive on SOCFPGA. If the EDAC is enabled, it will prevent the

Re: [PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

On 01/04/2016 03:07 PM, Borislav Petkov wrote: On Mon, Jan 04, 2016 at 02:55:43PM -0600, Dinh Nguyen wrote: Right. So for us, if we build in SDRAM ECC unconditionally, there is a requirement with the bootloader to turn on ECC and scrub the memory. Huh, how does a built-in piece of code

Re: [PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

On 01/04/2016 04:01 PM, Borislav Petkov wrote: On Mon, Jan 04, 2016 at 03:33:23PM -0600, Thor Thayer wrote: The decision about ECC or non-ECC SDRAM is made before building the Linux image and must be matched to the appropriate bootloader (ECC or non-ECC). If ECC is desired for SDRAM

Re: [PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

On 01/05/2016 04:58 AM, Borislav Petkov wrote: On Mon, Jan 04, 2016 at 05:42:40PM -0600, Thor Thayer wrote: and then the defines are also used to conditionally include the L2 or OCRAM ECC functions because everything is in one file. So? You don't have to do those funny games

Re: [PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding

Hi Rob, On 06/21/2016 08:33 AM, Rob Herring wrote: On Mon, Jun 20, 2016 at 09:50:49AM -0500, ttha...@opensource.altera.com wrote: From: Thor Thayer <ttha...@opensource.altera.com> Add the device tree bindings needed to support the Altera Ethernet FIFO buffers on the Arria10 chip. Sign

Re: [PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding

On 06/21/2016 10:48 AM, Rob Herring wrote: On Tue, Jun 21, 2016 at 9:46 AM, Thor Thayer <ttha...@opensource.altera.com> wrote: Hi Rob, On 06/21/2016 08:33 AM, Rob Herring wrote: On Mon, Jun 20, 2016 at 09:50:49AM -0500, ttha...@opensource.altera.com wrote: From: Thor Thayer

Re: [PATCHv9 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

Hi Boris. On 02/08/2016 05:39 AM, Borislav Petkov wrote: On Wed, Jan 27, 2016 at 10:13:20AM -0600, ttha...@opensource.altera.com wrote: From: Thor Thayer <ttha...@opensource.altera.com> Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The

Re: [PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

Hi Vladimir, On 01/22/2016 12:02 AM, Vladimir Zapolskiy wrote: Hi Thor, On 21.01.2016 19:34, ttha...@opensource.altera.com wrote: From: Thor Thayer <ttha...@opensource.altera.com> Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The

Re: [PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

On 01/22/2016 12:08 PM, Borislav Petkov wrote: On Fri, Jan 22, 2016 at 06:56:57PM +0200, Vladimir Zapolskiy wrote: it sounds like the author of the original change is Dinh, but if you agreed about authorship transfer, then "From: Thor Thayer" statement should be correct, but in any

Re: [PATCHv8 2/4] ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries

On 01/22/2016 08:35 PM, Rob Herring wrote: On Thu, Jan 21, 2016 at 11:34:26AM -0600, ttha...@opensource.altera.com wrote: From: Thor Thayer <ttha...@opensource.altera.com> Adding the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This

Re: [PATCHv2 6/7] ARM: socfpga: Enable Arria10 OCRAM ECC on startup

Hi Boris, On 04/05/2016 12:31 AM, Borislav Petkov wrote: On Tue, Apr 05, 2016 at 12:25:33AM -0500, Thor Thayer wrote: I realize that I'm not calling iounmap(ecc_block_base) and I'll fix that in the next revision with a goto. I'm assuming nothing else changes. Because I've applied 1-4 already

Re: [PATCHv2 11/11] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry

Hi Dinh, On 03/08/2016 08:50 AM, Dinh Nguyen wrote: On 03/07/2016 01:43 PM, ttha...@opensource.altera.com wrote: From: Thor Thayer <ttha...@opensource.altera.com> Add the device tree entries needed to support the Altera L2 cache EDAC on the Arria10 chip. Signed-off-by: Thor Thayer

Re: [PATCHv2 07/11] EDAC, altera: Add status offset & masks

Hi Boris, On 03/07/2016 01:43 PM, ttha...@opensource.altera.com wrote: From: Thor Thayer <ttha...@opensource.altera.com> In preparation for the Arria10 peripheral ECCs, the IRQ status needs to be determined because the IRQs are shared. The IRQ status register is read to determine if t

Re: [PATCH 3/5] EDAC, altera: Addition of Arria10 L2 Cache ECC

Hi Boris, On 03/04/2016 04:38 AM, Borislav Petkov wrote: On Tue, Mar 01, 2016 at 10:38:19AM -0600, ttha...@opensource.altera.com wrote: From: Thor Thayer <ttha...@opensource.altera.com> Addition of the Arria10 L2 Cache ECC handling. The major changes affect the L2 ECC registers not

Re: [PATCHv2 6/7] ARM: socfpga: Enable Arria10 OCRAM ECC on startup

Hi, On 03/31/2016 01:48 PM, ttha...@opensource.altera.com wrote: From: Thor Thayer <ttha...@opensource.altera.com> Enable ECC for Arria10 On-Chip RAM on machine startup. The ECC has to be enabled and memory initialized before data is stored in memory otherwise the ECC will fail on

Re: [PATCH 6/7] ARM: socfpga: Enable Arria10 OCRAM ECC on startup

Hi Dinh, On 03/30/2016 12:11 PM, Dinh Nguyen wrote: On Wed, 30 Mar 2016, ttha...@opensource.altera.com wrote: From: Thor Thayer <ttha...@opensource.altera.com> Enable ECC for Arria10 On-Chip RAM on machine startup. The ECC has to be enabled before data is stored in memory otherwise t

Re: [PATCH] Add EDAC peripheral init functions & Ethernet EDAC.

On 04/15/2016 04:40 AM, Mauro Carvalho Chehab wrote: Em Thu, 14 Apr 2016 09:35:01 -0500 Rob Herring escreveu: On Tue, Apr 12, 2016 at 05:12:55PM -0500, ttha...@opensource.altera.com wrote: This patch set adds the memory initialization functions for Altera's Arria10

Re: [PATCH] Add EDAC peripheral init functions & Ethernet EDAC.

On 04/18/2016 03:02 PM, Borislav Petkov wrote: On Mon, Apr 18, 2016 at 09:27:16AM -0500, Thor Thayer wrote: We're still getting the single bit correction By that you mean, you get that by enabling ECC on the FIFO block? Yes, you are correct. I'd still get the single bit correction

Re: [PATCH] Add EDAC peripheral init functions & Ethernet EDAC.

On 04/18/2016 03:06 PM, Borislav Petkov wrote: On Mon, Apr 18, 2016 at 10:02:27PM +0200, Borislav Petkov wrote: the number of uncorrectable errors is useful from a system point of view. I forgot: so altr_edac_a10_ecc_irq() panics on uncorrectable errors. Do we want to do that even for UEs

Re: [PATCH 1/2] EDAC, altera: remove useless casts

CRAM - { .compatible = "altr,socfpga-ocram-ecc", - .data = (void *)_data }, - { .compatible = "altr,socfpga-a10-ocram-ecc", - .data = (void *)_ocramecc_data }, + { .compatible = "altr,socfpga-ocram-ecc", .data = _data }, + { .compatible

Re: [PATCH 2/2] EDAC, altera: avoid unused function warnings

OFST); - edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); - panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); - } - return IRQ_HANDLED; -} - static irqreturn_t altr_edac_a10_irq_handler(int irq, void *dev_id) { irqreturn_t rc = IRQ_NONE; Acked-by: Thor Thayer <ttha...@opensource.altera.com>

Re: [PATCH] Add EDAC peripheral init functions & Ethernet EDAC.

Hi Boris, On 04/15/2016 04:46 PM, Borislav Petkov wrote: On Fri, Apr 15, 2016 at 10:27:54AM -0500, Thor Thayer wrote: I'll update this patch to only count errors. ... and also think about what that counting is going to bring. If it is only going to be there to show how many network errors

Re: [PATCH 05/10] EDAC, altera: Add Arria10 NAND EDAC support

On 07/27/2016 12:10 PM, Borislav Petkov wrote: On Thu, Jul 14, 2016 at 11:06:43AM -0500, ttha...@opensource.altera.com wrote: From: Thor Thayer <ttha...@opensource.altera.com> Add Altera Arria10 NAND FIFO memory EDAC support. Signed-off-by: Thor Thayer <ttha...@opensource.a

Re: [PATCH 2/3] EDAC, altera: Add Arria10 SD-MMC EDAC support

On 08/08/2016 08:36 AM, Borislav Petkov wrote: On Tue, Aug 02, 2016 at 10:56:20AM -0500, ttha...@opensource.altera.com wrote: From: Thor Thayer <ttha...@opensource.altera.com> Add Altera Arria10 SD-MMC FIFO memory EDAC support. The SD-MMC is a dual port RAM implementation which is dif

[PATCHv2] ARM: dts: Add EMAC AXI settings for Arria10

From: Thor Thayer <thor.tha...@linux.intel.com> Add the device tree entries needed to support the EMAC AXI bus settings on the Arria10 SoCFPGA chip. Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> --- v2 Add the AXI configuration to the other DW EMACs in the chip. --- arch/

[PATCH] ARM: dts: Add EMAC AXI settings for Arria10

From: Thor Thayer <thor.tha...@linux.intel.com> Add the device tree entries needed to support the EMAC AXI bus settings on the Arria10 SoCFPGA chip. Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> --- arch/arm/boot/dts/socfpga_arria10.dtsi | 7 +++ 1 file changed,

[PATCHv2 4/5] mfd: altr_a10sr: Add Arria10 DevKit Reset Controller

From: Thor Thayer <thor.tha...@linux.intel.com> Add Peripheral PHY Reset Controller to the Arria10 Development Kit System Resource Chip's MFD. Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> --- v2 Changes to commit header & body for clarification. --- drivers/mfd/al

[PATCHv2 1/5] dt-bindings: mfd: Add Altera Arria10 SR Reset Controller bindings

From: Thor Thayer <thor.tha...@linux.intel.com> This patch adds documentation for the Altera A10-SR Reset Controller DT bindings. Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> --- v2 No change --- Documentation/devicetree/bindings/mfd/altera-a10sr.txt | 11 +++

[PATCHv2 0/5] Add Arria10 System Manager Reset Controller

From: Thor Thayer <thor.tha...@linux.intel.com> This series of patches adds the Altera Arria10 Development Kit System Resource Chip's Reset Controller. Thor Thayer (5): dt-bindings: mfd: Add Altera Arria10 SR Reset Controller bindings dt-bindings: reset: a10sr: Add Arria10 SR

[PATCHv2 2/5] dt-bindings: reset: a10sr: Add Arria10 SR Reset Controller offsets

From: Thor Thayer <thor.tha...@linux.intel.com> The Arria10 System Resource Chip reset controller handles the Arria10 peripheral PHYs. This patch adds the offsets for these PHYs. Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> --- v2 Add NUM_RESETs to altr,rst-mgr-a10sr.h

[PATCHv2 5/5] ARM: dts: socfpga: Add Devkit A10-SR Reset Controller

From: Thor Thayer <thor.tha...@linux.intel.com> Add the Altera Arria10 System Resource Reset Controller to the MFD Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> Acked-by: Dinh Nguyen <dingu...@kernel.org> --- v2 change commit header to ARM: dts: socfpga. ---

[PATCHv2 3/5] reset: Add Altera Arria10 SR Reset Controller

From: Thor Thayer <thor.tha...@linux.intel.com> This patch adds the reset controller functionality for Peripheral PHYs to the Arria10 System Resource Chip. Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> --- V2 Rename and move new Kconfig to correct alphabetical order

[PATCH] mfd: altr-a10sr: Add Arria10 SR sysfs attributes

From: Thor Thayer <thor.tha...@linux.intel.com> Add the Altera Arria10 DevKit sysfs attributes to the MFD device. Update copyright and email. Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> --- drivers/mfd/altera-a10sr.c | 98 ++

Re: [PATCH 3/5] reset: Add Altera Arria10 System Resource Reset Controller

Hi Philipp, On 02/16/2017 04:30 AM, Philipp Zabel wrote: Hi Thor, thank you for the patch. A few comments below: On Wed, 2017-02-15 at 15:50 -0600, thor.tha...@linux.intel.com wrote: From: Thor Thayer <thor.tha...@linux.intel.com> This patch adds the reset controller functio

Re: [PATCH 5/5] ARM: socfpga: dts: Add Devkit A10-SR Reset Controller

On 02/16/2017 10:12 AM, Dinh Nguyen wrote: On 02/15/2017 03:50 PM, thor.tha...@linux.intel.com wrote: From: Thor Thayer <thor.tha...@linux.intel.com> Add the Altera Arria10 System Resource Reset Controller to the MFD Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com>

[PATCH 4/5] mfd: altr_a10sr: Add Arria10 DevKit Resource Controller

From: Thor Thayer <thor.tha...@linux.intel.com> Add Arria10 System Resource Manager Reset Controller to MFD. Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> --- drivers/mfd/altera-a10sr.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/mfd/altera-a10sr.c b

[PATCH 0/5] Add Arria10 System Manager Reset Controller

From: Thor Thayer <thor.tha...@linux.intel.com> This series of patches adds the Altera Arria10 Development Kit System Manager Reset Controller. Thor Thayer (5): dt-bindings: mfd: Add Altera Arria10 SR Reset Controller bindings dt-bindings: Add Arria10 System Resource reset manager o

[PATCH 5/5] ARM: socfpga: dts: Add Devkit A10-SR Reset Controller

From: Thor Thayer <thor.tha...@linux.intel.com> Add the Altera Arria10 System Resource Reset Controller to the MFD Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> --- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/

[PATCH 2/5] dt-bindings: Add Arria10 System Resource reset manager offsets

From: Thor Thayer <thor.tha...@linux.intel.com> The Arria10 System Resource reset manager handles the Arria10 peripheral PHYs. This patch adds the offsets for these PHYs. Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> --- MAINTAINERS|

[PATCH 3/5] reset: Add Altera Arria10 System Resource Reset Controller

From: Thor Thayer <thor.tha...@linux.intel.com> This patch adds the reset controller functionality to the Arria10 System Resource Manager. Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> --- MAINTAINERS | 1 + drivers/reset/Kconfig | 7 ++ d

[PATCH 1/5] dt-bindings: mfd: Add Altera Arria10 SR Reset Controller bindings

From: Thor Thayer <thor.tha...@linux.intel.com> This patch adds documentation for the Altera A10-SR Reset Controller DT bindings. Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> --- Documentation/devicetree/bindings/mfd/altera-a10sr.txt | 11 +++ 1 file changed, 1

Re: [PATCH] mfd: altera-a10sr: Make altr_a10sr_regmap_config static const

const struct regmap_config altr_a10sr_regmap_config = { .reg_bits = 8, .val_bits = 8, Reviewed-by: Thor Thayer <ttha...@opensource.altera.com>

Re: [PATCH] spi: dw: Enable Slave Select with GPIO Chip Select.

On 10/06/2016 04:37 AM, Mark Brown wrote: On Wed, Oct 05, 2016 at 04:38:58PM -0500, ttha...@opensource.altera.com wrote: This patch adds the Slave Select locally so that the transfer will start and complete. The GPIO CS is taken care of earlier in the SPI framework (spi_set_cs). This seems

Re: [PATCHv2 1/2] Documentation: dt: spi: Add GPIO Slave Select Parameter

On 10/07/2016 02:33 PM, Geert Uytterhoeven wrote: On Fri, Oct 7, 2016 at 4:56 PM, <ttha...@opensource.altera.com> wrote: From: Thor Thayer <ttha...@opensource.altera.com> Some SPI masters require the slave to be selected before a transaction can occur - even in the case of GPIO

Re: [PATCH 2/4] serial: 8250: of: Load TX FIFO Load Size from DT

Hi Rob, On 09/16/2016 02:20 PM, Rob Herring wrote: On Thu, Sep 08, 2016 at 11:12:19AM -0500, ttha...@opensource.altera.com wrote: From: Thor Thayer <ttha...@opensource.altera.com> Initialize the tx_loadsz parameter if it is defined in the device tree. Signed-off-by: Thor Thayer

Re: [PATCH 1/4] Documentation: dt: serial: Add TX FIFO load size

Hi Rob, On 09/16/2016 02:19 PM, Rob Herring wrote: On Thu, Sep 08, 2016 at 11:12:18AM -0500, ttha...@opensource.altera.com wrote: From: Thor Thayer <ttha...@opensource.altera.com> Add the device tree bindings needed to support the TX FIFO load size. Signed-off-by: Thor Thayer

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