This patch series provides an update of a previous posting:
http://www.spinics.net/lists/arm-kernel/msg169075.html
Main changes:
- Changed the new API to Level of Unification Inner Shareable (LoUIS)
- Fixed a pointer bug in __cpu_suspend_save code update
- Added patches to update __cpu_disable
ARM v7 architecture introduces the concept of cache levels and registers to
probe and manage cache levels accordingly.
This patch adds v7 support for cache LoUIS (Level of Unification Inner
Shareable) operations and defines a function that allows to clean and
invalidate data caches up to LoUIS.
P
ARM v7 architecture introduced the concept of cache levels and related
coherency requirements. New processors like A7 and A15 embed an
L2 unified cache controller that becomes part of the cache level
hierarchy. Some operations in the kernel like cpu_suspend and __cpu_disable
does not require a flus
When a CPU is hotplugged out caches that reside in its power domain
lose their contents and so must be cleaned to the next memory level.
Currently, __cpu_disable calls flush_cache_all() that for new generation
processor like A15/A7 ends up cleaning and invalidating all cache levels
up to Level of
In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
all cache levels up to Level of Coherency (LoC) that includes
the L2 unified cache.
From: Santosh Shilimkar
The ARMv7 processor setup function __v7_setup() cleans and invalidates the
CPU cache before enabling MMU to start the CPU with a clean CPU local cache.
But on ARMv7 architectures like Cortex-[A15/A8], this code will end
up flushing the L2 caches(up to level of Coherency)
On Thu, Sep 13, 2012 at 3:30 PM, Shilimkar, Santosh
wrote:
> On Thu, Sep 13, 2012 at 2:57 PM, Benoit Cousson wrote:
>> On 09/13/2012 11:00 AM, Shilimkar, Santosh wrote:
>>> On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson wrote:
Hi Santosh,
On 09/11/2012 11:29 AM, Shilimkar, Santos
On Thu, Sep 13, 2012 at 2:57 PM, Benoit Cousson wrote:
> On 09/13/2012 11:00 AM, Shilimkar, Santosh wrote:
>> On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson wrote:
>>> Hi Santosh,
>>>
>>> On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
Benoit,
On Mon, Sep 10, 2012 at 7:09 PM, Sh
On 09/13/2012 11:00 AM, Shilimkar, Santosh wrote:
> On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson wrote:
>> Hi Santosh,
>>
>> On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
>>> Benoit,
>>>
>>> On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
>>> wrote:
On Mon, Sep 10, 2012 at 6:44 PM
On 09/13/2012 11:11 AM, Mark Brown wrote:
> On Wed, Sep 12, 2012 at 02:46:56PM +0300, Peter Ujfalusi wrote:
>> Hello,
>>
>> This series will switch the OMAP audio to use dmaengine.
>> The final patch which does the switch was based on Russell King's earlier
>> patch.
>
> I'm fine with this from t
On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson wrote:
> Hi Santosh,
>
> On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
>> Benoit,
>>
>> On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
>> wrote:
>>> On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson wrote:
>>
>> [...]
>>
>> Silly qu
Hi Santosh,
On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
> Benoit,
>
> On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
> wrote:
>> On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson wrote:
>>>
>
> [...]
>
> Silly question: Don't we have one arch-timer per CPU?
>
It is per C
Hi Kevin,
> Since this series is already merged, I suggest that the problem patch be
> reverted, at least for v3.7 and until the problem is better understood
> and tested.
I thought I'll give you guys some more days to fix the problem before
reverting.
>
> With that patch reverted, all my PM te
On 09/13/2012 09:24 AM, AnilKumar, Chimata wrote:
> Marc,
>
> On Wed, Sep 12, 2012 at 18:32:53, Marc Kleine-Budde wrote:
>> On 09/12/2012 02:48 PM, AnilKumar, Chimata wrote:
>>> Hi Marc,
>>>
>>> On Tue, Sep 04, 2012 at 12:57:18, Marc Kleine-Budde wrote:
On 09/04/2012 08:14 AM, AnilKumar, Chim
Marc,
On Thu, Sep 13, 2012 at 13:18:07, Marc Kleine-Budde wrote:
> On 09/13/2012 09:28 AM, AnilKumar Ch wrote:
> > Move pm_runtime_enable/disable calls to c_can.c driver. Current
> > implementation is such that platform driver is doing pm_runtime
> > enable/disable and core driver is doing put_syn
On Wed, Sep 12, 2012 at 02:46:56PM +0300, Peter Ujfalusi wrote:
> Hello,
>
> This series will switch the OMAP audio to use dmaengine.
> The final patch which does the switch was based on Russell King's earlier
> patch.
I'm fine with this from the ASoC side but it sounds like you're going to
resp
On 09/13/2012 09:28 AM, AnilKumar Ch wrote:
> Move pm_runtime_enable/disable calls to c_can.c driver. Current
> implementation is such that platform driver is doing pm_runtime
> enable/disable and core driver is doing put_sync/get_sync.
>
> PM runtime calls should be invoked if there is a valid de
On Wed, 2012-09-12 at 16:11 -0700, Kevin Hilman wrote:
> Paul Walmsley writes:
>
> [...]
>
> >
> > It kind of looks to me like there are two or three separate sets within
> > the series. My feeling is that Kevin should take the first two, then I
> > should take the rest other than 6 and 7. T
On 09/13/2012 09:52 AM, Linus Walleij wrote:
> On Wed, Sep 12, 2012 at 10:27 PM, Tony Lindgren wrote:
>> * Peter Ujfalusi [120911 01:54]:
>>> With pinctrl-single,bits it is possible to update just part of the register
>>> within the pinctrl-single,function-mask area.
>>> This is useful when one r
On Thu, Sep 13, 2012 at 1:47 AM, Kevin Hilman
wrote:
> Use of smp_processor_id() here will require the same care as pointed out
> by Roger Quadros in [PATCH] perf: Use raw_smp_processor_id insted of
> smp_processor_id.
BTW it looks like get_cpu and put_cpu is the way to go, as pointed out
by Russe
Move pm_runtime_enable/disable calls to c_can.c driver. Current
implementation is such that platform driver is doing pm_runtime
enable/disable and core driver is doing put_sync/get_sync.
PM runtime calls should be invoked if there is a valid device
pointer from platform driver so moving enable/dis
On Thu, Sep 13, 2012 at 2:11 AM, Kevin Hilman
wrote:
> Jean Pihet writes:
>
>> The newly added code for functional power states re-defines the
>> API to query and control the power domains settings.
>>
>> The API is now split in the following parts in powerdomain.h:
>> - the public or external AP
HI Kevin,
On Thu, Sep 13, 2012 at 1:47 AM, Kevin Hilman
wrote:
> Jean Pihet writes:
>
>> Trace the power domain transitions using the functional power states,
>> which include the power and logic states.
>
> Just to be clear, this means that a trace will only contain functional
> power state cha
Marc,
On Wed, Sep 12, 2012 at 18:32:53, Marc Kleine-Budde wrote:
> On 09/12/2012 02:48 PM, AnilKumar, Chimata wrote:
> > Hi Marc,
> >
> > On Tue, Sep 04, 2012 at 12:57:18, Marc Kleine-Budde wrote:
> >> On 09/04/2012 08:14 AM, AnilKumar, Chimata wrote:
> >>> Marc,
> >>>
> >>> Thanks for the commen
>From a00cbfadc0053a3c21812593997a1b7338234a9f Mon Sep 17 00:00:00 2001
From: Ramesh Gupta G
Date: Wed, 12 Sep 2012 19:05:29 +0530
Subject: [PATCH v6 2/2] OMAP:IOMMU:flush L1 and L2 caches
OMAP IOMMU need to make sure that data in the L1 and L2 caches
is visible to the MMU hardware whenever the p
>From e88037801393f86ade3c79bcc900d3c84d989655 Mon Sep 17 00:00:00 2001
From: Ramesh Gupta G
Date: Wed, 12 Sep 2012 13:07:26 +0530
Subject: [PATCH v6 1/2] ARM: new cache maintenance api for iommu
Non-coherent IOMMU drivers need to make sure
that the data held in the caches is available
for the sl
On Tue, Sep 11, 2012 at 11:13:26, S, Venkatraman wrote:
> On Tue, Sep 4, 2012 at 6:38 PM, Hebbar, Gururaja
> wrote:
> > From: Vaibhav Bedia
> >
> > In some cases mmc_suspend_host() is not able to claim the
> > host and proceed with the suspend process. The core returns
> > -EBUSY to the host con
>From a00cbfadc0053a3c21812593997a1b7338234a9f Mon Sep 17 00:00:00 2001
From: Ramesh Gupta G
Date: Thu, 13 Sep 2012 11:43:20 +0530
Subject: [PATCH v6 0/2] ARM: New cache API for iommu
This patch series is the next version to
- add a new cache maintenance api to support non-coherent iommu drivers
On Thu, Sep 13, 2012 at 2:34 AM, Kevin Hilman
wrote:
> Jean Pihet writes:
>
>> Here is a re-spin after some comments and suggestions after review
>> and discussions.
>>
>> Implement the functional states for the power domains:
>> - unify the API to use the functional states. The new API
>> cons
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