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Op 22 jun 2008, om 14:51 heeft Woodruff, Richard het volgende
geschreven:
PowerTOP version 1.10 (C) 2007 Intel Corporation
CnAvg residency P-states (frequencies)
C0 (cpu running)( 0.0%)
C00.0
> PowerTOP version 1.10 (C) 2007 Intel Corporation
>
> CnAvg residency P-states (frequencies)
> C0 (cpu running)( 0.0%)
> C00.0ms ( 0.0%)
> C1 188.9ms (0.7%)*
> C2 2036.1ms (8.0%)*
> C3 23285.1ms (91.3%)*
>
>
Paul Walmsley wrote:
On OMAP3430ES2, DSS has both an initiator standby CM_IDLEST bit, and a
target idle CM_IDLEST bit. This is a departure from previous silicon,
which only had an initiator standby bit.
This means we need to test the target idle bit after enabling
dss1_alwon_fclk. Previous clo
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Op 21 jun 2008, om 19:05 heeft Paul Walmsley het volgende geschreven:
On OMAP3430ES2, DSS has both an initiator standby CM_IDLEST bit, and a
target idle CM_IDLEST bit. This is a departure from previous silicon,
which only had an initiator standby
On OMAP3430ES2, DSS has both an initiator standby CM_IDLEST bit, and a
target idle CM_IDLEST bit. This is a departure from previous silicon,
which only had an initiator standby bit.
This means we need to test the target idle bit after enabling
dss1_alwon_fclk. Previous clock code has done the w
