On Thu, Apr 19, 2012 at 6:41 PM, Tomi Valkeinen tomi.valkei...@ti.com wrote:
On Mon, 2012-04-02 at 20:43 +0530, Chandrabhanu Mahapatra wrote:
DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling
calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC.
Hi,
What happened with this pull request? It doesn't seem to be in 3.4 at
least.
-Tero
On Mon, 2012-03-12 at 04:15 -0600, Paul Walmsley wrote:
Hi Tony
The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:
Linux 3.3-rc7 (2012-03-10 13:49:52 -0800)
are available
Hi,
On Fri, 2012-03-23 at 13:48 +0100, Jan Weitzel wrote:
Add displays to panel-generic-dpi.c
Prime View PD050VL1 (640 x 480)
Prime View PD104SLF (800 x 600)
Prime View PM070WL4 (800 x 480)
Signed-off-by: Jan Weitzel j.weit...@phytec.de
---
On Thu, 2012-03-29 at 02:45 +0300, Grazvydas Ignotas wrote:
VENC type (composite/svideo) doesn't have to be fixed by board wiring,
it is possible to provide both connectors, which is what pandora does.
Having to recompile the kernel for users who have TV connector types
that's don't match
On Thu, 19 Apr 2012 20:00:12 +0530
Raja, Govindraj govindraj.r...@ti.com wrote:
On Thu, Apr 19, 2012 at 12:38 AM, Alan Cox a...@lxorguk.ukuu.org.uk wrote:
The point is that wakeups should be enabled whenever driver is in use,
and disabled when the driver is not in use.
Which is the
Changes compared to previous version:
- rebased on top of 3.4
- added back TEMP patch for preventing DSP wakeup as Paul's powerdomain
fixes are not yet in (patch #2)
- added open switch retention support (OSWR), can be enabled by
echo 1 /debug/pm_debug/enable_oswr_mode
- fixed support for
From: Rajendra Nayak rna...@ti.com
Remove the FIXME's in the suspend sequence since
we now intend to support system level RET support.
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
---
From: Rajendra Nayak rna...@ti.com
With no driver handling DSP, if brought out of reset, it stays
active and does not assert standby. This leads to IVAHD powerdomain not
transitioning and hence preventing chip retention.
This patch is no longer needed once Paul's powerdomain fixes are merged:
From: Santosh Shilimkar santosh.shilim...@ti.com
GIC distributor control register has changed between CortexA9 r1pX and
r2pX. The Control Register secure banked version is now composed of 2
bits:
bit 0 == Secure Enable
bit 1 == Non-Secure Enable
The Non-Secure banked register has not
This will make it easier to handle next logic states for power domains
during suspend. With this patch, the parameter is also programmed to
retention for every powerdomain, thus all powerdomains enter CSWR
state after this patch.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
From: Rajendra Nayak rna...@ti.com
On OMAP4 most modules/hwmods support module level context status. On
OMAP3 and earlier, we relyed on the power domain level context status.
Identify all such modules using a 'HWMOD_CONTEXT_REG' flag, all such
hwmods already have a valid 'context_offs' populated
PM debug now contains a file that can be used to control OSWR support
enable / disable on OMAP4. Also removed the off_mode_enable file for
the same platform as it is unsupported.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/pm-debug.c | 20
From: Axel Haslam axelhas...@gmail.com
On OMAP4, there is no support to read previous logic state
or previous memory state achieved when a power domain transitions
to RET. Instead there are module level context registers.
In order to support the powerdomain level logic/mem_off_counters
on OMAP4,
From: Rajendra Nayak rna...@ti.com
OMAP4 has module specific context lost registers which makes it now
possible to have module level context loss count, instead of relying
on the powerdomain level context count.
Add 2 private hwmod api's to update/clear the hwmod/module specific
context lost
Hi,
First version for this work. Applies on top of mainline + iochain set +
OMAP4 core retention set. Working tree available here:
tree: git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
branch: mainline-3.4-omap4-dev-off
Tested on omap4430 EMU blaze + omap4460 GP panda boards.
Some drivers
From: Rajendra Nayak rna...@ti.com
Restore all CM1/2 module registers as they are lost in OFF mode.
[n...@ti.com: minor clean ups]
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Axel
From: Santosh Shilimkar santosh.shilim...@ti.com
L3INIT powerdomain has USB HOST and USB TLL modules which support
hardware save-and-restore (HW SAR) mechanism.
This patch updates the L3INIT power domain to mark them as capable
of doing H/w save and restore and provides functions to do them
SAR layout contents are now generated automatically based on SAR ROM
contents during boot.
u32 offset description
-- -
0 pointer to next entry
1 size of DMA transfer in bytes
2 SAR RAM address for save / restore
3
Added in preparation for device off mode. SAR ROM contains the mapping
from SAR RAM to IO registers, and this will eventually be parsed during
init time to do the reverse before device off.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/plat-omap/include/plat/omap44xx.h |1 +
1
Added similar PM errata flag support as omap3 has. A few errata flags
will be added in subsequent patches.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/pm.h |7 +++
arch/arm/mach-omap2/pm44xx.c |1 +
2 files changed, 8 insertions(+), 0 deletions(-)
diff
From: Rajendra Nayak rna...@ti.com
SAR/ROM code restores only CORE DPLL to its original state
post wakeup from OFF mode.
The rest of the DPLL's in OMAP4 platform (MPU/IVA/ABE/USB/PER)
are saved and restored here during an OFF transition.
[n...@ti.com: minor cleanups]
Signed-off-by: Nishanth
From: Santosh Shilimkar santosh.shilim...@ti.com
The ROM BUG is when MPU Domain OFF wake up sequence that can compromise
IVA and Tesla execution.
At wakeup from MPU OFF on HS device only (not GP device), when
restoring the Secure RAM, the ROM Code reconfigures the clocks the
same way it is done
From: Santosh Shilimkar santosh.shilim...@ti.com
The SAR RAM is maintained during Device OFF mode. The register layout
is fixed in SAR ROM. SAR is split into 4 banks with different
privilege accesses based on device type
---
Access
omap_sar_overwrite() now uses offsets detected during init time from
the SAR ROM contents.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/omap-sar.c | 158
1 files changed, 112 insertions(+), 46 deletions(-)
diff --git
save_secure_all needs l3_main_3_ick and l4_secure_clkdm enabled,
otherwise the secure ROM code will crash.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/omap-wakeupgen.c | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git
If AUX_CORE_BOOT0 does not indicate wakeup request for cpu1, put it back
to off. This is needed during wakeup from device off to prevent cpu1
from being stuck indefinitely in the wakeup loop and also to prevent
wakeup problem on GP chips with device off mode.
Signed-off-by: Tero Kristo
During device off, the off-mode voltage transitions are enabled on reset.
Because the voltage control logic is not still completely functional for
OMAP4, we must disable the voltage transitions for device off for now.
This can only be done by disabling the I2C channel it seems.
This patch does
From: Axel Haslam axelhas...@gmail.com
ROM code restores part of the GIC context during wakeup from device
off mode from the SAR RAM. If the PPI and SPI interrupts are not
marked as non-secure on GP chips, this crashes the device during
wakeup, thus mark them as non-secure.
Signed-off-by: Axel
Without this, CPU0 will crash in the ROM code during wakeup from
device off. This patch also clears the GIC save area, to prevent
ROM code from writing garbage to the GIC registers during wakeup.
The actual GIC restore is done by kernel.
This bug fix applies only to OMAP4460, it is fixed on
Currently device off does not have any counters / timers of its own
and it is impossible to track the time spent in this state. In device
off, MPU / CORE powerdomains enter OSWR, so normally the RETENTION
state times / counts are increased during device off.
This patch adds a new field to the
From: Santosh Shilimkar santosh.shilim...@ti.com
Work around for Errata ID: i632 LPDDR2 Corruption After OFF Mode
Transition When CS1 Is Used On EMIF which impacts OMAP443x silicon
The issue occurs when EMIF_SDRAM_CONFIG is restored first before
EMIF_SDRAM_CONFIG_2 is not yet restored, the
From: Carlos Leija cile...@ti.com
At wakeup from OFF/OSWR CPU1 will call secure HAL service through a local
secure dispatcher with MMU off, thus ROM will save a PA return address.
Later in the wakeup, when SMC driver calls an RPC through
omap4_secure_dispatcher (MMU is on now), ROM code won't log
This patch adds device off support to OMAP4 device type.
OFF mode is disabled by default, however, there are two ways to enable
OFF mode:
a) In the board file, call omap4_pm_off_mode_enable(1)
b) Enable OFF mode using the debugfs entry
echo 1/sys/kernel/debug/pm_debug/enable_off_mode
(conversely
From: Rajendra Nayak rna...@ti.com
On HS devices on the way out of MPU OSWR and OFF ROM code wrongly
overwrites the CM L3INSTR registers. So to avoid this, save them and
restore on the way out from MPU OSWR/OFF.
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Santosh Shilimkar
Add displays to panel-generic-dpi.c
Prime View PD050VL1 (640 x 480)
Prime View PD104SLF (800 x 600)
Prime View PM070WL4 (800 x 480)
Signed-off-by: Jan Weitzel j.weit...@phytec.de
---
v2: Add primeview prefix
drivers/video/omap2/displays/panel-generic-dpi.c | 63 ++
1
On Fri, 2012-04-20 at 11:41 +0200, Jan Weitzel wrote:
Add displays to panel-generic-dpi.c
Prime View PD050VL1 (640 x 480)
Prime View PD104SLF (800 x 600)
Prime View PM070WL4 (800 x 480)
Signed-off-by: Jan Weitzel j.weit...@phytec.de
---
v2: Add primeview prefix
Thanks, I'll apply.
Hello,
This patch provides hardware NAND BCH ecc support for OMAP3 boards.
It depends on the following patches:
new GPMC BCH api (linux-omap):
http://lists.infradead.org/pipermail/linux-mtd/2012-April/040757.html
race condition fix in OMAP mtd driver:
On Thu, Apr 19, 2012 at 11:56 PM, Simon Knopp
simon.kn...@pg.canterbury.ac.nz wrote:
Hi all,
I have a camera module capable of outputting YUV422 over a parallel
interface. I've been having some issues interfacing this to a Gumstix.
Reading through the OMAP3530 tech ref, I'm now beginning to
On Fri, Apr 20, 2012 at 11:38 AM, Tomi Valkeinen tomi.valkei...@ti.com wrote:
On Thu, 2012-03-29 at 02:45 +0300, Grazvydas Ignotas wrote:
VENC type (composite/svideo) doesn't have to be fixed by board wiring,
it is possible to provide both connectors, which is what pandora does.
Having to
From: Govindraj.R govindraj.r...@ti.com
Currently all low level uart driver register to serial_core layer
this core layer exposes various serial uart ops.
Currently the core layer provides startup and shutdown hooks
to low level driver, but in port suspend case the shutdown gets called
from
From: Govindraj.R govindraj.r...@ti.com
On omap2/3 module level wakeup is handled using PM_WKEN registers.
Expand the hwmod framework to handle the module level wakeup enable
registers.
Tested on Beagle-xm by enabling and disabling uart wakeups from sysfs
Series depends on following patch for
From: Govindraj.R govindraj.r...@ti.com
On 24xx/34xx/36xx Module level wakeup events are enabled/disabled using
PM_WKEN1_CORE/PM_WKEN_PER regs. The module level wakeups are enabled by
default, by PRM soft reset default value of PM_WKEN reg is all one's which means
all module level wakeups are
From: Govindraj.R govindraj.r...@ti.com
On 24xx/34xx/36xx Module level wakeup events are enabled/disabled using
PM_WKEN1_CORE/PM_WKEN_PER regs.
Add api to control the module level wakeup mechanism from info provided from
hwmod data. If module level wakeups are available from hwmod data then they
From: Govindraj.R govindraj.r...@ti.com
The uart module level wakeups enabling and disabling
are now handled from uart driver itself remove the uart module
level configurations from pm code.
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc:
On Fri, Apr 20, 2012 at 12:48 PM, Ivan Djelic ivan.dje...@parrot.com wrote:
Hello,
This patch provides hardware NAND BCH ecc support for OMAP3 boards.
It depends on the following patches:
new GPMC BCH api (linux-omap):
http://lists.infradead.org/pipermail/linux-mtd/2012-April/040757.html
On Fri, Apr 20, 2012 at 12:12:27PM +0100, Grazvydas Ignotas wrote:
On Fri, Apr 20, 2012 at 12:48 PM, Ivan Djelic ivan.dje...@parrot.com wrote:
Hello,
This patch provides hardware NAND BCH ecc support for OMAP3 boards.
It depends on the following patches:
new GPMC BCH api (linux-omap):
On Fri, 2012-04-20 at 13:49 +0300, Grazvydas Ignotas wrote:
On Fri, Apr 20, 2012 at 11:38 AM, Tomi Valkeinen tomi.valkei...@ti.com
wrote:
On Thu, 2012-03-29 at 02:45 +0300, Grazvydas Ignotas wrote:
VENC type (composite/svideo) doesn't have to be fixed by board wiring,
it is possible to
On Thu, Apr 19, 2012 at 11:01:16AM -0400, Alan Stern wrote:
On Thu, 19 Apr 2012, Igor Grinberg wrote:
ping
Alan, Felipe,
Can this go into 3.5?
It's okay with me.
Acked-by: Alan Stern st...@rowland.harvard.edu
Also fine from my side:
Acked-by: Felipe Balbi ba...@ti.com
The
On Wed, 2012-03-28 at 15:51 -0600, Ricardo Neri wrote:
There exist several display technologies and standards that support audio as
well. Hence, it is relevant to update the DSS device driver to provide an
audio
interface that may be used by an audio or any other driver interested in the
On Fri, Apr 20, 2012 at 3:03 PM, Tero Kristo t-kri...@ti.com wrote:
Hi,
First version for this work. Applies on top of mainline + iochain set +
OMAP4 core retention set. Working tree available here:
tree: git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
branch: mainline-3.4-omap4-dev-off
On Tue, Jun 21, 2011 at 14:45, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, Jun 21, 2011 at 04:31:19PM +0800, TAO HU wrote:
We got an issue on our OMAP4 SMP system.
Looks like __und_user(), which was triggered by a user space
exception, got a page fault hence lead to
We do not use iclk anywhere in the dmtimer driver and so removing it.
Hence removing the timer iclk entries from OMAP4 clkdev table as well.
Cc: Cousson, Benoit b-cous...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
Cc: Kevin Hilman khil...@ti.com
Cc: Rajendra Nayak
With omap_hwmod_get_main_clk() now available, this can be passed to
clk_get() to extract the fclk and thus avoid construction of fclk name.
Corrected the timer fck name mis-match between clock44xx_data.c and
omap_hwmod_44xx_data.c. For other platforms this is already taken care.
Cc: Cousson,
The devm API usage in probe() simplifies error handling operation.
Since iclk is not used in the driver it is removed from wherever
not needed.
Corrected the timer fck name mis-match between clock44xx_data.c and
omap_hwmod_44xx_data.c.
Added omap_hwmod_get_main_clk() API. There is no more need to
Replace the regular kzalloc and ioremap with the devm_ equivalent
to simplify error handling. We don't need kree() any more in
omap_dm_timer_remove().
Also added *dev* pointer to reference pdev-dev which makes the
usage shorter in code.
Cc: Cousson, Benoit b-cous...@ti.com
Cc: Paul Walmsley
Add an API to get main clock name associated with a given @oh.
This will avoid the need to construct fclk names during early
initialization in order to get fclk handle using clk_get().
Cc: Cousson, Benoit b-cous...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
Cc:
If an IP is configured in Smart-Standby-Wakeup, when disabling wakeup feature
the
IP will not go back to Smart-Standby, but will remain in Smart-Standby-Wakeup.
Signed-off-by: Djamil Elaidi d-ela...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c |2 +-
1 files changed, 1 insertions(+), 1
On Fri, 2012-04-20 at 17:50 +0530, T Krishnamoorthy, Balaji wrote:
On Fri, Apr 20, 2012 at 3:03 PM, Tero Kristo t-kri...@ti.com wrote:
Hi,
First version for this work. Applies on top of mainline + iochain set +
OMAP4 core retention set. Working tree available here:
tree:
On Thu, Apr 19, 2012 at 07:00:55PM +0300, Ujfalusi, Peter wrote:
If the playback preallocation fails, or if only capture is supported
on the dai link
this is not needed.
It only applies if we have both playback and capture streams and the capture
preallocation fails.
Luckily the
On Wed, Apr 18, 2012 at 8:43 PM, Shubhrajyoti shubhrajy...@ti.com wrote:
Kevin
Yes agree completely. Will describe that in the changelog.
--
Does the following changelog look ok?
From 37fdc2d40c9b2b19b8c5a9a4b8f7dd547d420f55 Mon Sep 17 00:00:00 2001
From: Shubhrajyoti D shubhrajy...@ti.com
diff --git a/drivers/tty/serial/serial_core.c
b/drivers/tty/serial/serial_core.c
index 9c4c05b..0dc246d 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -1284,6 +1284,8 @@ static void uart_close(struct tty_struct *tty, struct
file *filp)
DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling
calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC.
DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC
divisor LCD.
Signed-off-by: Chandrabhanu Mahapatra cmahapa...@ti.com
---
Shubhrajyoti Datta omaplinuxker...@gmail.com writes:
On Wed, Apr 18, 2012 at 8:43 PM, Shubhrajyoti shubhrajy...@ti.com wrote:
Kevin
Yes agree completely. Will describe that in the changelog.
--
Does the following changelog look ok?
A little better, but still doesn't explain things so that
Tero Kristo t-kri...@ti.com writes:
[...]
I tried your branch on gp/emu devices but could not reproduce this issue.
My observation is that while resuming, omap_hsmmc.1 eMMC is
trying to turn on phoenix vaux1 regulator via i2c which fails due
to controller timeout.
Note: eMMC is present only
On Fri, Apr 20, 2012 at 7:43 PM, Datta, Shubhrajyoti
shubhrajy...@ti.com wrote:
On Wed, Apr 18, 2012 at 7:38 PM, Kevin Hilman khil...@ti.com wrote:
#define OMAP_I2C_SYSTEST_SDA_O (1 0) /* SDA
line drive out */
-/* OCP_SYSSTATUS bit definitions */
-#define
On Fri, 2012-04-20 at 19:01 +0530, Chandrabhanu Mahapatra wrote:
DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling
calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC.
DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC
divisor LCD.
On Fri, 2012-04-20 at 06:55 -0700, Kevin Hilman wrote:
Tero Kristo t-kri...@ti.com writes:
[...]
I tried your branch on gp/emu devices but could not reproduce this issue.
My observation is that while resuming, omap_hsmmc.1 eMMC is
trying to turn on phoenix vaux1 regulator via i2c which
On Fri, Apr 20, 2012 at 8:13 PM, Tero Kristo t-kri...@ti.com wrote:
On Fri, 2012-04-20 at 06:55 -0700, Kevin Hilman wrote:
Tero Kristo t-kri...@ti.com writes:
[...]
I tried your branch on gp/emu devices but could not reproduce this issue.
My observation is that while resuming,
On Fri, 2012-04-20 at 20:21 +0530, Datta, Shubhrajyoti wrote:
On Fri, Apr 20, 2012 at 8:13 PM, Tero Kristo t-kri...@ti.com wrote:
On Fri, 2012-04-20 at 06:55 -0700, Kevin Hilman wrote:
Tero Kristo t-kri...@ti.com writes:
[...]
I tried your branch on gp/emu devices but could not
Hi Tarun,
Thanks for this series, it will help us cleaning a little bit more the
legacy stuff we have inside our data files.
On 4/20/2012 2:39 PM, Tarun Kanti DebBarma wrote:
Add an API to get main clock name associated with a given @oh.
This will avoid the need to construct fclk names
On Thu, Apr 19, 2012 at 11:07:42AM -0700, Tony Lindgren wrote:
* Russell King - ARM Linux li...@arm.linux.org.uk [120419 10:46]:
On Wed, Apr 18, 2012 at 06:39:14PM -0700, Tony Lindgren wrote:
Cool, you almost got it. Got it working for n800 and 770 with the
following
patch. Only
* Russell King - ARM Linux li...@arm.linux.org.uk [120420 08:15]:
On Thu, Apr 19, 2012 at 11:07:42AM -0700, Tony Lindgren wrote:
* Russell King - ARM Linux li...@arm.linux.org.uk [120419 10:46]:
On Wed, Apr 18, 2012 at 06:39:14PM -0700, Tony Lindgren wrote:
Cool, you almost got it. Got
On Fri, Apr 20, 2012 at 08:26:25AM -0700, Tony Lindgren wrote:
* Russell King - ARM Linux li...@arm.linux.org.uk [120420 08:15]:
On Thu, Apr 19, 2012 at 11:07:42AM -0700, Tony Lindgren wrote:
There's some information in the omap5912 trm on pages 717 and 718:
On Fri, Mar 30, 2012 at 02:39:32PM -0700, Tony Lindgren wrote:
* Kumar Gala ga...@kernel.crashing.org [120330 14:14]:
On Mar 30, 2012, at 1:48 PM, Tony Lindgren wrote:
Hi,
* Kumar Gala ga...@kernel.crashing.org [120329 12:24]:
As I'm new to the OMAP community this might be a
* Russell King - ARM Linux li...@arm.linux.org.uk [120420 08:41]:
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -83,11 +84,11 @@ static void omap_dma_start_sg(struct omap_chan *c, struct
omap_desc *d,
struct omap_sg *sg = d-sg + idx;
if (d-dir ==
* Russell King - ARM Linux li...@arm.linux.org.uk [120420 08:41]:
So, with this patch plus my original patch to omap's mmc host driver, this
should result in something which works without all the overhead of drivers
supplying the port information. Please confirm, and I'll merge this into
* Tero Kristo t-kri...@ti.com [120420 01:24]:
Hi,
What happened with this pull request? It doesn't seem to be in 3.4 at
least.
There was a boot issue on omap3 evm and that branch got dropped.
Will merge it again after Paul has figured out the issue.
Regards,
Tony
--
To unsubscribe from
* Matt Porter mpor...@ti.com [120420 09:04]:
On Fri, Mar 30, 2012 at 02:39:32PM -0700, Tony Lindgren wrote:
* Kumar Gala ga...@kernel.crashing.org [120330 14:14]:
On Mar 30, 2012, at 1:48 PM, Tony Lindgren wrote:
Hi,
* Kumar Gala ga...@kernel.crashing.org [120329 12:24]:
Hi Tomi,
Thanks for your comments!
On 04/20/2012 07:03 AM, Tomi Valkeinen wrote:
On Wed, 2012-03-28 at 15:51 -0600, Ricardo Neri wrote:
There exist several display technologies and standards that support audio as
well. Hence, it is relevant to update the DSS device driver to provide an audio
From: Mark Brown [broo...@opensource.wolfsonmicro.com]
Sent: Friday, April 20, 2012 6:08 AM
To: Ujfalusi, Peter
Cc: Matcovschi, Oleg; alsa-de...@alsa-project.org; linux-omap@vger.kernel.org
Subject: Re: [alsa-devel] [PATCH] ASoC: omap-pcm: Free dma buffers in case of
error.
On Thu, Apr 19, 2012
On Fri, 20 Apr 2012, Djamil Elaidi wrote:
If an IP is configured in Smart-Standby-Wakeup, when disabling wakeup feature
the
IP will not go back to Smart-Standby, but will remain in Smart-Standby-Wakeup.
Signed-off-by: Djamil Elaidi d-ela...@ti.com
Thanks, queued for 3.4-rc fixes.
- Paul
On Thu, 19 Apr 2012, Mark A. Greer wrote:
From: Mark A. Greer mgr...@animalcreek.com
Clean up clockdomains3xxx_data.c a bit by removing the
superfluous commas in gfx_sgx_3xxx_wkdeps[].
Signed-off-by: Mark A. Greer mgr...@animalcreek.com
Thanks for doing this, Mark; queued for 3.5.
-
Use omap_disable_channel_irq() function instead of directly accessing CICR.
The omap_disable_chanel_irq() function clears pending interrupts
and disables interrupt on channel.
Functions omap2_enable_irq_lch()/omap2_disable_irq_lch() clear interrupt
status register.
Signed-off-by: Oleg Matcovschi
cc Santosh
Hi Kevin,
Nice changelog!
On Fri, 13 Apr 2012, Kevin Hilman wrote:
Without runtime PM enabled, hwmod needs to leave all IP blocks in an
enabled state by default so any driver access to the HW will succeed.
This is accomplished by seting the postsetup_state to enabled for all
Resolve this build warning:
drivers/usb/otg/isp1301_omap.c: In function 'isp1301_set_peripheral':
drivers/usb/otg/isp1301_omap.c:1340:6: warning: unused variable 'l'
This shows up when building with the 'omap1_defconfig' and
'5912osk_testconfig' configs from git://git.pwsan.com/omap_kconfigs.
arch/arm/plat-omap/devices.c: In function 'omap_dsp_reserve_sdram_memblock':
arch/arm/plat-omap/devices.c:170: warning: format '%x' expects type 'unsigned
int', but argument 3 has type 'phys_addr_t'
arch/arm/mach-omap2/dsp.c: In function 'omap_dsp_init':
arch/arm/mach-omap2/dsp.c:60: warning:
On Fri, Apr 20, 2012 at 09:43:07AM -0700, Tony Lindgren wrote:
* Russell King - ARM Linux li...@arm.linux.org.uk [120420 08:41]:
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -83,11 +84,11 @@ static void omap_dma_start_sg(struct omap_chan *c,
struct omap_desc *d,
* Russell King - ARM Linux li...@arm.linux.org.uk [120420 15:13]:
On Fri, Apr 20, 2012 at 09:43:07AM -0700, Tony Lindgren wrote:
* Russell King - ARM Linux li...@arm.linux.org.uk [120420 08:41]:
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -83,11 +84,11 @@ static void
* Russell King rmk+ker...@arm.linux.org.uk [120418 03:14]:
Using coherent DMA memory with the OMAP DMA engine results in
unpredictable behaviour due to memory ordering issues; as things stand,
there is no guarantee that data written to coherent DMA memory will be
visible to the DMA hardware.
* Russell King rmk+ker...@arm.linux.org.uk [120418 03:15]:
res can be one of several resources, as this variable is re-used several
times during probe. This can cause the wrong resource parameters to be
passed to release_mem_region().
Get the original memory resource before calling
Hi,
On Fri, Apr 20 2012, Tony Lindgren wrote:
* Russell King rmk+ker...@arm.linux.org.uk [120418 03:15]:
res can be one of several resources, as this variable is re-used several
times during probe. This can cause the wrong resource parameters to be
passed to release_mem_region().
Get the
On Sat, Apr 21, 2012 at 01:04:18AM +0300, Felipe Contreras wrote:
arch/arm/plat-omap/devices.c: In function 'omap_dsp_reserve_sdram_memblock':
arch/arm/plat-omap/devices.c:170: warning: format '%x' expects type 'unsigned
int', but argument 3 has type 'phys_addr_t'
arch/arm/mach-omap2/dsp.c:
On Sat, Apr 21, 2012 at 2:34 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -57,8 +57,9 @@ static int __init omap_dsp_init(void)
if (pdata-phys_mempool_base) {
pdata-phys_mempool_size =
Hi,
On Fri, Apr 20 2012, Chris Ball wrote:
On Fri, Apr 20 2012, Tony Lindgren wrote:
* Russell King rmk+ker...@arm.linux.org.uk [120418 03:15]:
res can be one of several resources, as this variable is re-used several
times during probe. This can cause the wrong resource parameters to be
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