On Tue, Apr 29, 2014 at 10:17:01AM -0600, Stephen Warren wrote:
On 04/28/2014 06:02 PM, Simon Horman wrote:
On Mon, Apr 28, 2014 at 08:30:32PM +0100, Russell King wrote:
Since we now automatically enable early BRESP in core L2C-310 code when
we detect a Cortex-A9, we don't need
On 29/04/14 20:38, Tony Lindgren wrote:
* Tomi Valkeinen tomi.valkei...@ti.com [140429 09:33]:
On 29/04/14 19:19, Tomi Valkeinen wrote:
On 29/04/14 18:05, Tony Lindgren wrote:
omap4_padconf_global is a syscon node, not pinctrl. As syscon just gives
a raw regmap to its memory area, the driver
On 30/04/14 04:24, Joachim Eastwood wrote:
Do you plan to push the patch that add hpd-gpios to the
hdmi-connector for 3.16? (nodes for my board below)
https://patchwork.kernel.org/patch/4006021/
Also in the patch set I am using your DT bindings for panel-dpi. See
patch [2 of 4] for nodes.
On 04/29/2014 07:16 PM, Felipe Balbi wrote:
On Tue, Apr 29, 2014 at 11:14:20AM -0500, Felipe Balbi wrote:
On Tue, Apr 29, 2014 at 10:50:39AM +0300, Roger Quadros wrote:
+Nishant
Hi,
On 04/28/2014 07:03 PM, Felipe Balbi wrote:
Hi,
On Mon, Apr 28, 2014 at 05:01:23PM +0300, Roger Quadros
Hi Dan,
Am Dienstag, den 29.04.2014, 15:19 -0500 schrieb Dan Murphy:
The TI SoC reset controller support utilizes the
reset controller framework to give device drivers or
function drivers a common set of APIs to call to reset
a module.
The reset-ti is a common interface to the reset
On 28/04/14 14:17, Jingoo Han wrote:
On Monday, April 28, 2014 7:54 PM, Masanari Iida wrote:
Fix two format string mismatch in display-sysfs.c
Signed-off-by: Masanari Iida standby2...@gmail.com
---
drivers/video/fbdev/omap2/dss/display-sysfs.c | 4 ++--
1 file changed, 2 insertions(+), 2
On Tue, Apr 29, 2014 at 09:53:47PM -0500, Joel Fernandes wrote:
Here's a redo of the patch [1] that effectively does the same
thing but is the right way to do things by using ENDPROC instead.
The firmware correctly switches to THUMB before entry.
The patch applies ontop of the earlier patch
Confirm your Donation of £2,000.000.00 Contact Kindly contact claims office via
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In order to get correct clock dividers for AESS/ABE we need to set the
dpll_abe_m2x2_ck rate to be double of dpll_abe_ck.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
drivers/clk/ti/clk-54xx.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/ti/clk-54xx.c
In OMAP5 bit 8 in PRCM registers are not defined (Reserved) unlike their
counterpart in OMAP4.
It is better to not write to these bits.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/omap54xx-clocks.dtsi | 48 --
1 file changed, 48
abe_iclk's parent is aess_fclk and not abe_clk.
Also correct the parameters for clock rate calculation as used for OMAP4
since in PRCM level there's no difference between the two platform
regarding to AESS/ABE clocking.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
Add HWMOD_SWSUP_SIDLE to flags.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index
Add the needed hwmod entries which is needed for AESS (Audio Engine
SubSystem) and ABE.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 64 ++
1 file changed, 64 insertions(+)
diff --git
On Mon, Apr 28, 2014 at 9:40 AM, Andreas Fenkart afenk...@gmail.com wrote:
@@ -2201,11 +2346,16 @@ static int omap_hsmmc_suspend(struct device *dev)
pm_runtime_get_sync(host-dev);
if (!(host-mmc-pm_flags MMC_PM_KEEP_POWER)) {
- omap_hsmmc_disable_irq(host);
+
On 04/30/2014 02:41 PM, Peter Ujfalusi wrote:
In OMAP5 bit 8 in PRCM registers are not defined (Reserved) unlike their
counterpart in OMAP4.
It is better to not write to these bits.
Yeah, looks like this bug was copied over from the legacy clock data.
Acked-by: Tero Kristo t-kri...@ti.com
On 04/30/2014 02:41 PM, Peter Ujfalusi wrote:
abe_iclk's parent is aess_fclk and not abe_clk.
Also correct the parameters for clock rate calculation as used for OMAP4
since in PRCM level there's no difference between the two platform
regarding to AESS/ABE clocking.
Signed-off-by: Peter Ujfalusi
Hi Benoit Tony,
These patches add I2C touch screen support for am43x-epos-evm
and am437x-gp-evm.
Relevant driver side changes are here.
http://thread.gmane.org/gmane.linux.kernel.input/35803
Please queue this for -next (3.16). Thanks.
cheers,
-roger
---
Roger Quadros (1):
ARM: dts:
Fixup Y resolution and add default pin state. Also update
the compatible id.
CC: Benoit Cousson bcous...@baylibre.com
CC: Tony Lindgren t...@atomide.com
CC: Mugunthan V N mugunthan...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 12 ++--
1
From: Sekhar Nori nsek...@ti.com
Add touchscreen support for AM437x GP EVM using pixcir
touchscreen controller.
CC: Benoit Cousson bcous...@baylibre.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Sekhar Nori nsek...@ti.com
Acked-by: Roger Quadros rog...@ti.com
---
On Tue, Apr 29, 2014 at 11:16 AM, Felipe Balbi ba...@ti.com wrote:
On Tue, Apr 29, 2014 at 11:14:20AM -0500, Felipe Balbi wrote:
On Tue, Apr 29, 2014 at 10:50:39AM +0300, Roger Quadros wrote:
+Nishant
Hi,
On 04/28/2014 07:03 PM, Felipe Balbi wrote:
Hi,
On Mon, Apr 28, 2014 at
Hi Mike/Paul,
(sorry for top-posting)
any comments here, what do we do ? Do we split this patch ? Use v1 ? Use
v2 ?
cheers
On Wed, Mar 05, 2014 at 03:50:33PM +0200, Tomi Valkeinen wrote:
On 20/02/14 21:30, Paul Walmsley wrote:
On Wed, 19 Feb 2014, Paul Walmsley wrote:
On Fri, 17 Jan
Tomi,
On Wed, Mar 5, 2014 at 7:50 AM, Tomi Valkeinen tomi.valkei...@ti.com wrote:
[...]
From f5a78303411e9192899a6a681acac37f09f4cc3b Mon Sep 17 00:00:00 2001
From: Tomi Valkeinen tomi.valkei...@ti.com
Date: Wed, 15 Jan 2014 11:45:07 +0200
Subject: [PATCH] ARM: OMAP2+: fix dpll
Hi,
On Tue, Apr 29, 2014 at 11:10:42AM -0500, Felipe Balbi wrote:
Hi,
On Tue, Apr 29, 2014 at 05:21:42PM -0400, Zhuang Jin Can wrote:
On Mon, Apr 28, 2014 at 10:55:36AM -0500, Felipe Balbi wrote:
On Mon, Apr 28, 2014 at 04:49:23PM -0400, Zhuang Jin Can wrote:
Adds a debugfs file
Hi,
On Thu, May 01, 2014 at 01:06:25AM -0400, Zhuang Jin Can wrote:
Hi,
On Tue, Apr 29, 2014 at 11:10:42AM -0500, Felipe Balbi wrote:
Hi,
On Tue, Apr 29, 2014 at 05:21:42PM -0400, Zhuang Jin Can wrote:
On Mon, Apr 28, 2014 at 10:55:36AM -0500, Felipe Balbi wrote:
On Mon, Apr 28,
On Wed, Apr 30, 2014 at 12:14:42PM -0500, Felipe Balbi wrote:
sorry but your patch is not good for acceptance in mainline.
Thanks your time.
Jincan
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* Joachim Eastwood manab...@gmail.com [140429 18:08]:
On 30 April 2014 01:52, Tony Lindgren t...@atomide.com wrote:
Looks like quite a few omaps have sharp ls037v7dw01 that's configured
as various panel dpi entries for whatever legacy reasons. For device
tree based support, let's just
Philipp and Arnd
Thank you for the comments
On 04/30/2014 03:20 AM, Philipp Zabel wrote:
Hi Dan,
Am Dienstag, den 29.04.2014, 15:19 -0500 schrieb Dan Murphy:
The TI SoC reset controller support utilizes the
reset controller framework to give device drivers or
function drivers a common set
* Tomi Valkeinen tomi.valkei...@ti.com [140429 23:14]:
On 29/04/14 20:38, Tony Lindgren wrote:
* Tomi Valkeinen tomi.valkei...@ti.com [140429 09:33]:
On 29/04/14 19:19, Tomi Valkeinen wrote:
On 29/04/14 18:05, Tony Lindgren wrote:
omap4_padconf_global is a syscon node, not pinctrl. As
Tony and Arnd
Thanks for the comments
On 04/29/2014 07:22 PM, Tony Lindgren wrote:
* Arnd Bergmann a...@arndb.de [140429 13:35]:
On Tuesday 29 April 2014 15:19:47 Dan Murphy wrote:
+ * AM33xx reset index for PRCM Module
+ *
+ * Copyright 2014 Texas Instruments Inc.
+ *
+ * This program is
* Dan Murphy dmur...@ti.com [140430 11:00]:
Tony and Arnd
Thanks for the comments
On 04/29/2014 07:22 PM, Tony Lindgren wrote:
* Arnd Bergmann a...@arndb.de [140429 13:35]:
On Tuesday 29 April 2014 15:19:47 Dan Murphy wrote:
+ * AM33xx reset index for PRCM Module
+ *
+ * Copyright
Tony
On 04/30/2014 01:10 PM, Tony Lindgren wrote:
* Dan Murphy dmur...@ti.com [140430 11:00]:
Tony and Arnd
Thanks for the comments
On 04/29/2014 07:22 PM, Tony Lindgren wrote:
* Arnd Bergmann a...@arndb.de [140429 13:35]:
On Tuesday 29 April 2014 15:19:47 Dan Murphy wrote:
+ * AM33xx
At least we should giveback the current request to the
gadget. Otherwise, the gadget will be stuck without knowing
anything.
It was oberved that the failure can happen if the request is
queued when the run/stop bit of controller is not set.
Signed-off-by: Zhuang Jin Can jin.can.zhu...@intel.com
endpoint.maxburst may be 0 if a gadget doesn't call config_ep_by_speed()
to update it from the companion descriptor.
And endpoint.maxburst - 1 returns 1b which wrongly sets bit
26 of endpoint parameter 0.
This sets a wrong endpoint state and will cause Get Endpoint State
command can't get the
Hi,
On Thu, May 01, 2014 at 02:36:08AM -0400, Zhuang Jin Can wrote:
At least we should giveback the current request to the
gadget. Otherwise, the gadget will be stuck without knowing
anything.
It was oberved that the failure can happen if the request is
queued when the run/stop bit of
On Thu, May 01, 2014 at 03:16:04AM -0400, Zhuang Jin Can wrote:
endpoint.maxburst may be 0 if a gadget doesn't call config_ep_by_speed()
to update it from the companion descriptor.
And endpoint.maxburst - 1 returns 1b which wrongly sets bit
26 of endpoint parameter 0.
This sets a wrong
Hi Andreas,
2014-04-30 14:23 GMT+02:00 Andreas Müller schnitzelt...@googlemail.com:
On Mon, Apr 28, 2014 at 9:40 AM, Andreas Fenkart afenk...@gmail.com wrote:
@@ -2201,11 +2346,16 @@ static int omap_hsmmc_suspend(struct device *dev)
pm_runtime_get_sync(host-dev);
if
Hi Ulf and Geert,
On Thursday 24 April 2014 15:11:24 Ulf Hansson wrote:
On 24 April 2014 12:13, Geert Uytterhoeven geert+rene...@glider.be wrote:
When adding a device from DT, check if its clocks are suitable for Runtime
PM, and register them with the PM core.
If Runtime PM is disabled,
On Tuesday 29 April 2014 14:16:10 Grant Likely wrote:
On Fri, 25 Apr 2014 16:44:58 -0700, Kevin Hilman khil...@linaro.org wrote:
Geert Uytterhoeven geert+rene...@glider.be writes:
When adding a device from DT, check if its clocks are suitable for
Runtime PM, and register them with the PM
Hi Geert,
On Thursday 24 April 2014 12:13:19 Geert Uytterhoeven wrote:
On SoCs like ARM/SH-mobile, gate clocks are available for modules, allowing
Runtime PM for a device controlled by a gate clock.
On legacy shmobile kernels, this is handled by the PM runtime code in
On 30/04/14 14:25, Laurent Pinchart wrote:
On Tuesday 29 April 2014 14:16:10 Grant Likely wrote:
On Fri, 25 Apr 2014 16:44:58 -0700, Kevin Hilman khil...@linaro.org wrote:
Geert Uytterhoeven geert+rene...@glider.be writes:
When adding a device from DT, check if its clocks are suitable for
Hi Kevin,
On Sat, Apr 26, 2014 at 1:44 AM, Kevin Hilman khil...@linaro.org wrote:
Geert Uytterhoeven geert+rene...@glider.be writes:
When adding a device from DT, check if its clocks are suitable for Runtime
PM, and register them with the PM core.
If Runtime PM is disabled, just enable the
Hi Grant,
On Tue, Apr 29, 2014 at 3:16 PM, Grant Likely grant.lik...@secretlab.ca wrote:
On Fri, 25 Apr 2014 16:44:58 -0700, Kevin Hilman khil...@linaro.org wrote:
Geert Uytterhoeven geert+rene...@glider.be writes:
When adding a device from DT, check if its clocks are suitable for Runtime
Hi Laurent,
On Wed, Apr 30, 2014 at 11:23 PM, Laurent Pinchart
laurent.pinch...@ideasonboard.com wrote:
On Thursday 24 April 2014 15:11:24 Ulf Hansson wrote:
On 24 April 2014 12:13, Geert Uytterhoeven geert+rene...@glider.be wrote:
When adding a device from DT, check if its clocks are
Hi Laurent,
On Wed, Apr 30, 2014 at 11:29 PM, Laurent Pinchart
laurent.pinch...@ideasonboard.com wrote:
On Thursday 24 April 2014 12:13:19 Geert Uytterhoeven wrote:
On SoCs like ARM/SH-mobile, gate clocks are available for modules, allowing
Runtime PM for a device controlled by a gate clock.
* Dan Murphy dmur...@ti.com [140430 11:14]:
On 04/30/2014 01:10 PM, Tony Lindgren wrote:
* Dan Murphy dmur...@ti.com [140430 11:00]:
Tony and Arnd
Thanks for the comments
On 04/29/2014 07:22 PM, Tony Lindgren wrote:
* Arnd Bergmann a...@arndb.de [140429 13:35]:
On Tuesday 29 April
The HwSpinlock core allows requesting either a specific lock or
an available normal lock. The specific locks are usually reserved
during board init time, while the normal available locks are
intended to be assigned at runtime.
This patch prepares the hwspinlock core to support this concept
of
The various hwspin_lock_request* interfaces return a NULL pointer
on error, or a valid hwlock pointer on success. It is standard
practice to pass the error value back to the consumers on failure
cases, so change the functions to return an equivalent ERR_PTR()
value instead of NULL. The regular
Retrieve the number of reserved locks for OMAP by using the
of_hwspin_lock_get_num_reserved_locks() OF helper function
provided by the hwspinlock core. The range sanity check will
be performed by the hwspinlock core during the registration.
Signed-off-by: Suman Anna s-a...@ti.com
---
Changed the return statements to return an ERR_PTR instead of NULL
in case of an error. This patch helps with deferred probing of any
client users if the corresponding hwspinlock bank is not yet registered
with the hwspinlock core.
Signed-off-by: Suman Anna s-a...@ti.com
---
TODO: Collapse into
HwSpinlocks are supported on AM33xx, AM43xx and DRA7xx SoC
device families as well. The IPs are identical to that of
OMAP4/OMAP5, except for the number of locks.
Add a depends on to the above family of SoCs to enable the
build support for OMAP hwspinlock driver for any of the above
SoC configs.
Rearrange the code between hwspin_lock_unregister() and the underlying
hwspin_lock_unregister_single() functions so that the semantics are
similar to the _register_ functions. This change prepares the hwspinlock
driver core to support unregistration of reserved locks better.
Signed-off-by: Suman
The HwSpinlock core allows requesting either a specific lock or an
available normal lock. The specific locks are usually reserved during
board init time, while the normal available locks are intended to be
assigned at runtime.
The HwSpinlock core has been enhanced to:
1. allow the platform
The number of hwspinlocks are determined based on the value read
from the IP block's SYSSTATUS register. However, the module may
not be enabled and clocked, and the read may result in a bus error.
This particular issue is seen rather easily on AM33XX, since the
module wakeup is software
The HwSpinlock core requires a base id for registering a bank
of hwspinlocks. This base id needs to be unique across multiple
IP instances of a hwspinlock device, so that each hwlock can be
represented uniquely in a system.
Support has been added to represent this in DT through a common
property
This patch adds the generic common bindings used to represent
a hwlock device and use/request locks in a device-tree build.
All the platform-specific hwlock driver implementations need the
number of locks and associated base id for registering the locks
present within the device with the driver
This patch adds three new OF helper functions to use/request
locks from a hwspinlock device instantiated through a
device-tree blob.
1. The of_hwspin_lock_get_num_locks() is a common helper
function to read the common 'hwlock-num-locks' property.
2. The of_hwspin_lock_simple_xlate() is a
The hwspinlock_device structure is used for registering a bank of
locks with the driver core. The structure already contains the
necessary members to identify the bank of locks. The core does not
maintain the hwspinlock_devices itself, but maintains only a radix
tree for all the registered locks.
HwSpinlock IP is present only on OMAP4 and other newer SoCs,
which are all device-tree boot only. This patch adds the
base support for parsing the DT nodes, and removes the code
dealing with the traditional platform device instantiation.
Signed-off-by: Suman Anna s-a...@ti.com
[t...@atomide.com:
HwSpinlock IP is present only on OMAP4 and other newer SoCs,
which are all device-tree boot only. This patch adds the
DT bindings information for OMAP hwspinlock module.
Cc: Rob Herring robh...@kernel.org
Signed-off-by: Suman Anna s-a...@ti.com
---
Hi Ohad,
This is a refresh/update of the hwspinlock dt support series. The
series is rebased onto v3.15-rc3, and adds 8 new patches (RFC) to
handle various discussion points arised on v4.
Following are the main changes in v5:
- Base DT patches (Patches 1 to 7, except for 4) are identical to v4.
On Wed, Apr 30, 2014 at 12:08 AM, Vinod Koul vinod.k...@intel.com wrote:
On Tue, Apr 29, 2014 at 11:25:02PM -0500, Joel Fernandes wrote:
On 04/29/2014 03:46 AM, Vinod Koul wrote:
[..]
commit 770f0f3a20188b7e17db2790803b9da925dc0b94
Author: Thomas Gleixner t...@linutronix.de
Date: Mon
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