Re: [PATCHv4 30/35] ARM: dts: omap4: add system control module node
On 03/19/2015 10:25 PM, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [150318 14:35]:
* Tero Kristo t-kri...@ti.com [150318 07:45]:
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -167,36 +167,65 @@
+ scm: scm@4a002000 {
+ compatible = ti,omap4-ctrl, simple-bus;
+ reg = 0x4a002000 0x1000,
+ 0x4a10 0x1000;
+ #address-cells = 2;
+ #size-cells = 1;
+ ranges = 0 0 0x4a002000 0x1000,
+1 0 0x4a10 0x1000;
Oops I still have a bit of an issue with this, sorry I should have
been more clear last time.
Now it's hard to figure out which children belong to l4_cfg and which
ones to l4_wkup. I suggest we set them up as completely separate blocks
as that's what they are.
Below is an example of what I think things should look like for omap4,
maybe take a look at that and see if that makes sense for you?
It may need to be patched in separate parts to keep the patches readable
though :)
The example I posted has some l4_cfg vs SCM confusion as pointed out by
Tero while we chatted about it. Also l4_wkup is a child of l4_cfg on
omap4, while on omap5 they are separate.
Below are some examples of what we came up with that now follows omap4460
TRM Figure 2-1. Interconnect Overview and Table 2-3. L4_CFG Memory
Space Mapping. Also an example for omap3 is included.
Tero, maybe just do the minimal changes for now as we don't need to move
all of it at once?
Yes, I will be looking at this today.
-Tero
Regards,
Tony
Example for omap4.dtsi, which ocp being the l3 interconnect:
ocp {
compatible = ti,omap4-l3-noc, simple-bus;
#address-cells = 1;
#size-cells = 1;
ranges;
ti,hwmods = l3_main_1, l3_main_2, l3_main_3;
reg = 0x4400 0x1000,
0x4480 0x2000,
0x4500 0x1000;
interrupts = GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH,
GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
l4_cfg: l4@4a00 {
compatible = ti,omap4-l4-cfg, simple-bus;
#address-cells = 1;
#size-cells = 1;
ranges = 0 0x4a00 0x100;
cm1: cm1@4000 {
compatible = ti,omap4-cm1;
reg = 0x4000 0x2000;
cm1_clocks: clocks {
#address-cells = 1;
#size-cells = 0;
};
cm1_clockdomains: clockdomains {
};
};
cm2: cm2@8000 {
compatible = ti,omap4-cm2;
reg = 0x8000 0x3000;
cm2_clocks: clocks {
#address-cells = 1;
#size-cells = 0;
};
cm2_clockdomains: clockdomains {
};
};
omap4_scm_core: scm@10 {
compatible = ti,omap4-scm-core, simple-bus;
#address-cells = 1;
#size-cells = 1;
ranges = 0 0x10 0x1000;
omap4_pmx_core: pinmux@40 {
compatible = ti,omap4-padconf,
pinctrl-single;
reg = 0x40 0x0196;
#address-cells = 1;
#size-cells = 0;
#interrupt-cells = 1;
interrupt-controller;
pinctrl-single,register-width = 16;
pinctrl-single,function-mask = 0x7fff;
};
omap4_padconf_global: tisyscon@5a0 {
compatible = syscon;
reg = 0x5a0 0x170;
#address-cells = 1;
#size-cells = 1;
pbias_regulator: pbias_regulator {
compatible = ti,pbias-omap;
reg = 0x60 0x4;
syscon =
omap4_padconf_global;
Re: [RFC][PATCH 3/9] usb: otg: add OTG core
On Thu, Mar 19, 2015 at 12:18:55PM +0200, Roger Quadros wrote:
On 19/03/15 05:40, Peter Chen wrote:
On Wed, Mar 18, 2015 at 03:55:57PM +0200, Roger Quadros wrote:
The OTG core instantiates the OTG Finite State Machine
per OTG controller and manages starting/stopping the
host and gadget controllers based on the bus state.
It provides APIs for the following tasks
- Registering an OTG capable controller
- Registering Host and Gadget controllers to OTG core
- Providing inputs to and kicking the OTG state machine
TODO:
- sysfs interface to allow application inputs to OTG state machine
- otg class?
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/usb/Makefile | 1 +
drivers/usb/common/Makefile | 1 +
drivers/usb/common/usb-otg.c | 732
+++
drivers/usb/common/usb-otg.h | 71 +
drivers/usb/core/Kconfig | 8 +
include/linux/usb/usb-otg.h | 86 +
6 files changed, 899 insertions(+)
create mode 100644 drivers/usb/common/usb-otg.c
create mode 100644 drivers/usb/common/usb-otg.h
create mode 100644 include/linux/usb/usb-otg.h
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index 2f1e2aa..07f59a5 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -60,5 +60,6 @@ obj-$(CONFIG_USB_RENESAS_USBHS) += renesas_usbhs/
obj-$(CONFIG_USB_GADGET) += gadget/
obj-$(CONFIG_USB_COMMON) += common/
+obj-$(CONFIG_USB_OTG_CORE)+= common/
obj-$(CONFIG_USBIP_CORE) += usbip/
diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
index ca2f8bd..573fc75 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -7,3 +7,4 @@ usb-common-y += common.o
usb-common-$(CONFIG_USB_LED_TRIG) += led.o
obj-$(CONFIG_USB_OTG_FSM) += usb-otg-fsm.o
+obj-$(CONFIG_USB_OTG_CORE) += usb-otg.o
diff --git a/drivers/usb/common/usb-otg.c b/drivers/usb/common/usb-otg.c
new file mode 100644
index 000..1433fc9
--- /dev/null
+++ b/drivers/usb/common/usb-otg.c
@@ -0,0 +1,732 @@
+/**
+ * drivers/usb/common/usb-otg.c - USB OTG core
+ *
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Roger Quadros rog...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/list.h
+#include linux/timer.h
+#include linux/usb/otg.h
+#include linux/usb/phy.h/* enum usb_otg_state */
+#include linux/usb/gadget.h
+#include linux/usb/usb-otg.h
+#include linux/workqueue.h
+
+#include usb-otg.h
+
+/* to link timer with callback data */
+struct otg_timer {
+ struct timer_list timer;
+ /* callback data */
+ int *timeout_bit;
+ struct otg_data *otgd;
+};
+
+struct otg_data {
+ struct device *dev; /* HCD GCD's parent device */
+
+ struct otg_fsm fsm;
+ /* HCD, GCD and usb_otg_state are present in otg_fsm-otg
+ * HCD is bus_to_hcd(fsm-otg-host)
+ * GCD is fsm-otg-gadget
+ */
+ struct otg_fsm_ops fsm_ops; /* private copy for override */
+ struct usb_otg otg;
+ struct usb_hcd *shared_hcd; /* if shared HCD registered */
+
+ /* saved hooks to OTG device */
+ int (*start_host)(struct otg_fsm *fsm, int on);
+ int (*start_gadget)(struct otg_fsm *fsm, int on);
+
+ struct list_head list;
+
+ struct work_struct work;/* OTG FSM work */
+ struct workqueue_struct *wq;
+
+ struct otg_timer timers[NUM_OTG_FSM_TIMERS];
+
+ bool fsm_running;
+ bool gadget_can_start; /* OTG FSM says gadget can start */
+ bool host_can_start;/* OTG FSM says host can start */
+
+ /* use otg-fsm.lock for serializing access */
+};
What's the relationship between struct usb_otg otg and this one?
Did you mean why struct usb_otg otg is there in struct otg_data?
Just for easy allocation. fsm_ops only contains the pointer to struct usb_otg.
The reason why I ask this question is the most structures at usb_otg
(only enum usb_otg_state)are useless for otg_fsm, this structure may
only for hardware otg fsm driver, so your OTG framework should only
for software FSM drivers, right?
Peter
+
+/* OTG device list */
+LIST_HEAD(otg_list);
+static DEFINE_MUTEX(otg_list_mutex);
+
+/**
+ * check if device is in our OTG list and return
+ * otg_data, else NULL.
+ *
+ * otg_list_mutex must be held.
+ */
+static struct otg_data
Re: [RFC][PATCH 1/9] usb: hcd: Introduce usb_start/stop_hcd()
On Thu, Mar 19, 2015 at 01:38:32PM +0200, Roger Quadros wrote:
On 18/03/15 21:49, Alan Stern wrote:
On Wed, 18 Mar 2015, Roger Quadros wrote:
To support OTG we want a mechanism to start and stop
the HCD from the OTG state machine. Add usb_start_hcd()
and usb_stop_hcd().
Signed-off-by: Roger Quadros rog...@ti.com
There are a few problems in this proposed patch.
+int usb_start_hcd(struct usb_hcd *hcd)
+{
+ int retval;
+ struct usb_device *rhdev = hcd-self.root_hub;
+
+ if (hcd-state != HC_STATE_HALT) {
+ dev_err(hcd-self.controller, not starting a running HCD\n);
+ return -EINVAL;
+ }
+
+ hcd-state = HC_STATE_RUNNING;
+ retval = hcd-driver-start(hcd);
+ if (retval 0) {
+ dev_err(hcd-self.controller, startup error %d\n, retval);
+ hcd-state = HC_STATE_HALT;
+ return retval;
+ }
+
+ /* starting here, usbcore will pay attention to this root hub */
+ if ((retval = register_root_hub(hcd)) != 0)
+ goto err_register_root_hub;
If the host controller is started more than once, you will end up
unregistering and re-registering the root hub. The device core does
not allow this. Once a device has been unregistered, you must not try
to register it again -- you have to allocate a new device and register
it instead.
Understood.
Also, although you call the driver's -start method multiple times, the
-reset method is called only once, when the controller is first
probed. It's not clear that this will work in a situation where the HC
and the UDC share hardware state; after the UDC is stopped it may be
necessary to reset the HC before it can run again.
Yes, good point.
It might be possible to make this work, but I suspect quite a few
drivers would need rewriting first. As another example of the problems
you face, consider how stopping a host controller will interact with
the driver's PM support (both system suspend and runtime suspend).
Right. This needs more work than I thought.
It would be a lot simpler to unbind the host controller driver
completely when switching to device mode and rebind it when switching
back. I guess that is the sort of heavy-duty approach you want to
avoid, but it may be the only practical way forward.
So you mean directly calling usb_add/remove_hcd() from the OTG core?
I don't see any issues with that other than it being a heavy-duty operation
like you said and hope that it doesn't violate the OTG spec timing.
Looking at Figure 5-3: HNP Sequence of Events (FS) of the OTG 2.0 spec
we have about 150ms (X10) to switch from B-Device detected A connect
(b_wait_acon state)
to driving bus reset (b_host state). I don't think this should be an issue in
modern SoCs
but I'm not very sure.
It is not related toadd/remove hcd, it is the time from receiving PCD
to issue BUS_RESET, the Linux stack can't satisfy OTG spec (150ms) due
to there are some de-bounce waitings.
In any case I can migrate to the add/remove hcd approach to simplify things.
It should be no problem, we use it more than 1 years.
--
Best Regards,
Peter Chen
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [alsa-devel] Patches to bind the SGTL5000 chip to AM33XX McASP
On 03/19/2015 08:06 PM, Nikolay Dimitrov wrote: Slight clarification here - I can't find any such reference in the SGTL5000 datasheet where it's explicitly written that the I2C bus *requires* the MCLK running. Unfortunately, all of us found this obscure dependency empirically. It is not spelled out as such, but in: http://cache.freescale.com/files/analog/doc/data_sheet/SGTL5000.pdf?pspll=1 bottom of page9 (note 1) and the power up sequence in page10. See also page13, RESET section. If you change audio controls while you don't have audio activity, you will still need to have the MCLK running. Correct. And this is a big issue. As far as I know, the kernel drivers control separately the clock domains, and separately i2c devices, so the basic expectation on the kernel side is that there's no connection between these 2. In this specific case, because of the SGTL5000's implementation, there's a dependency. Right now as I see it, there are several ways to resolve it: 1. Run the reference clock all the time, so the SGTL5000 codec is happy, and DAPM widgets can work as-is. We've been doing this all the time - the reference clocks are routinely configured either in the bootloader, or in the DTS iomuxc node. While this can work in some cases (or until someone touches the same clock or one of its parents :D), there are other cases (like battery-powered devices) where people would want more aggressive power management, which means controlling the reference clock at runtime (see #2). Note the the codec driver will enable the clock and will not let it to be turned off. You need to work on the codec driver to sort this out. 2. Add hacks in the DAPM widgets that add control to the codec's reference clocks. While this seems the preferred route to many, the general feeling is that such approach is not very welcome in upstream. SND_SOC_DAPM_CLOCK_SUPPLY() 3. Add explicit support in the kernel's audio subsystem for dependencies between i2c devices and clocks, maybe via DAPM clock widget or something like this. Provided that the DAPM graphs are defined properly, this will work out-of-the-box for all use cases, without the hacks (until we see even more twisted cases). This can be handled within the codec driver with some changes. If you have external clock which can be enabled/diabled with a GPIO, then you can use that. We already have binding for this type of external clocks (in linux-next): look for gpio-gate-clock You define your external GPIO controlled clock with this binding and use the phandle in the codec driver. Change the codec driver to enable/disable the clock when needed. When you do not have audio activity, set the regmap to cache only so any change in the controls will not reach the HW. When you power up next time the regmap will sync the changes to the chip, so you will have the changes commited. -- Péter -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Patches to bind the SGTL5000 chip to AM33XX McASP
Greg, On 03/19/2015 07:48 PM, Greg Knight wrote: For a codec such as the SGTL5000 I would connect a clock, which is running all the time. If you take a look at the driver, it enables the clock at probe and leaves it running as long as the driver is loaded. Speaking briefly to my electrical colleague, he's a bit concerned about the extra power load that a crystal oscillator might incur, while I'm concerned about audio quality from a source like CLKOUT2. Is there a straightforward way we could enable the clock on-demand - when we're communicating with the codec/mixer or actually using the audio subsystem - while keeping it disabled when not in use? We don't expect to be using the audio subsystem frequently. Worst-case we can set up a GPIO and enable/disable it as needed in user-space - acceptable, if annoying, for our application. See my reply to Nikolay. -- Péter -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 5/6] ARM: dts: add wl12xx/wl18xx bindings
Tony Lindgren t...@atomide.com writes: Tested OK (boot, scan, join, ping) on Pandaboard ES. thanks for testing it! Great. As suggested by Kalle, I'll apply all these into omap-for-v4.1/wl12xx branch and send a pull request for the arm-soc probably on Friday if no issues are found. Great, thank you. Just in case you want this: Acked-by: Kalle Valo kv...@codeaurora.org -- Kalle Valo -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv3 08/35] clk: ti: fix ti_clk_get_reg_addr error handling
On 03/06/2015 09:18 PM, Mike Turquette wrote:
Quoting Tero Kristo (2015-02-25 11:04:18)
There is a case where NULL can be a valid return value for
ti_clk_get_reg_addr, specifically the case where both the provider index
and register offsets are zero. In this case, the current error checking
against a NULL pointer will fail. Thus, change the API to return a
ERR_PTR value in an error case, and change all the users of this API to
check against IS_ERR instead.
Signed-off-by: Tero Kristo t-kri...@ti.com
Cc: Michael Turquette mturque...@linaro.org
Looks good to me.
I'll interpret this as an Acked-by, will add this tag to the latest
version of the set I will post later today, thanks.
-Tero
Regards,
Mike
---
drivers/clk/ti/apll.c |5 +++--
drivers/clk/ti/autoidle.c |2 +-
drivers/clk/ti/clk.c |7 ---
drivers/clk/ti/divider.c |4 ++--
drivers/clk/ti/dpll.c |6 +++---
drivers/clk/ti/gate.c |4 ++--
drivers/clk/ti/interface.c |2 +-
drivers/clk/ti/mux.c |4 ++--
8 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 72d9727..49baf38 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -203,7 +203,7 @@ static void __init of_dra7_apll_setup(struct device_node
*node)
ad-control_reg = ti_clk_get_reg_addr(node, 0);
ad-idlest_reg = ti_clk_get_reg_addr(node, 1);
- if (!ad-control_reg || !ad-idlest_reg)
+ if (IS_ERR(ad-control_reg) || IS_ERR(ad-idlest_reg))
goto cleanup;
ad-idlest_mask = 0x1;
@@ -384,7 +384,8 @@ static void __init of_omap2_apll_setup(struct device_node
*node)
ad-autoidle_reg = ti_clk_get_reg_addr(node, 1);
ad-idlest_reg = ti_clk_get_reg_addr(node, 2);
- if (!ad-control_reg || !ad-autoidle_reg || !ad-idlest_reg)
+ if (IS_ERR(ad-control_reg) || IS_ERR(ad-autoidle_reg) ||
+ IS_ERR(ad-idlest_reg))
goto cleanup;
clk = clk_register(NULL, clk_hw-hw);
diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
index 8912ff8..e75c64c 100644
--- a/drivers/clk/ti/autoidle.c
+++ b/drivers/clk/ti/autoidle.c
@@ -119,7 +119,7 @@ int __init of_ti_clk_autoidle_setup(struct device_node
*node)
clk-name = node-name;
clk-reg = ti_clk_get_reg_addr(node, 0);
- if (!clk-reg) {
+ if (IS_ERR(clk-reg)) {
kfree(clk);
return -EINVAL;
}
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index e22b956..0ebe5c5 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -103,7 +103,8 @@ int __init ti_clk_retry_init(struct device_node *node,
struct clk_hw *hw,
* @index: register index from the clock node
*
* Builds clock register address from device tree information. This
- * is a struct of type clk_omap_reg.
+ * is a struct of type clk_omap_reg. Returns a pointer to the register
+ * address, or a pointer error value in failure.
*/
void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index)
{
@@ -121,14 +122,14 @@ void __iomem *ti_clk_get_reg_addr(struct device_node
*node, int index)
if (i == CLK_MAX_MEMMAPS) {
pr_err(clk-provider not found for %s!\n, node-name);
- return NULL;
+ return ERR_PTR(-ENOENT);
}
reg-index = i;
if (of_property_read_u32_index(node, reg, index, val)) {
pr_err(%s must have reg[%d]!\n, node-name, index);
- return NULL;
+ return ERR_PTR(-EINVAL);
}
reg-offset = val;
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index 6211893..ff5f117 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -530,8 +530,8 @@ static int __init ti_clk_divider_populate(struct
device_node *node,
u32 val;
*reg = ti_clk_get_reg_addr(node, 0);
- if (!*reg)
- return -EINVAL;
+ if (IS_ERR(*reg))
+ return PTR_ERR(*reg);
if (!of_property_read_u32(node, ti,bit-shift, val))
*shift = val;
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 81dc469..11478a5 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -390,18 +390,18 @@ static void __init of_ti_dpll_setup(struct device_node
*node,
#endif
} else {
dd-idlest_reg = ti_clk_get_reg_addr(node, 1);
- if (!dd-idlest_reg)
+ if (IS_ERR(dd-idlest_reg))
goto cleanup;
dd-mult_div1_reg = ti_clk_get_reg_addr(node, 2);
}
- if (!dd-control_reg || !dd-mult_div1_reg)
+ if (IS_ERR(dd-control_reg) || IS_ERR(dd-mult_div1_reg))
goto cleanup;
if (dd-autoidle_mask) {
dd-autoidle_reg = ti_clk_get_reg_addr(node, 3);
- if (!dd-autoidle_reg)
+
Re: [RFC][PATCH 2/9] usb: gadget: add usb_gadget_start/stop()
On Thu, Mar 19, 2015 at 04:50:31PM +0200, Roger Quadros wrote: On 19/03/15 16:09, Li Jun wrote: On Thu, Mar 19, 2015 at 12:14:39PM +0200, Roger Quadros wrote: On 19/03/15 05:30, Peter Chen wrote: On Wed, Mar 18, 2015 at 03:55:56PM +0200, Roger Quadros wrote: The OTG state machine needs a mechanism to start and stop the gadget controller. Add usb_gadget_start() and usb_gadget_stop(). Signed-off-by: Roger Quadros rog...@ti.com --- drivers/usb/gadget/udc/udc-core.c | 166 +++--- include/linux/usb/gadget.h| 3 + 2 files changed, 158 insertions(+), 11 deletions(-) diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c index 5a81cb0..69b4123 100644 --- a/drivers/usb/gadget/udc/udc-core.c +++ b/drivers/usb/gadget/udc/udc-core.c @@ -35,6 +35,8 @@ * @dev - the child device to the actual controller * @gadget - the gadget. For use by the class code * @list - for use by the udc class driver + * @running - udc is running Doesn't OTG FSM should know it? Not really, as the gadget driver might not have been loaded yet or userspace might have disabled softconnect when the OTG FSM wants UDC to start. So only UDC knows if it has really started or not based on this flag. why this can not be known by check the otg fsm state? i.e. if the device in b_peripheral or a_peripheral state, udc should had started, isn't it? If gadget function driver (which is different from UDC driver) is not yet loaded then we can't start UDC even if otg fsm is in b_peripheral. Also, if userspace has disabled softconnect we can't start UDC. So, b_peripheral != UDC_started. I've tried to address this issue by adding the checks in usb_gadget_start(). Ok, maybe we have different understanding for 'B-Device' at software, In spec, it says the Micro-AB receptacle with nothing connected can be 'B-Device', but in fact, we may not enable device mode before loading gadget driver, in chipidea fsm design, if the gadget driver is not loaded, the FSM will not start, and it is at OTG_STATE_UNDEFINED. One more thing is we may need to find a place to issue SRP when we load gadget driver, since we may at b_idle at that time due to host closes the vbus (timeout for a_wait_bcon). What is the softconnect used for? In otg fsm, we use b_bus_req for FSM. -- Best Regards, Peter Chen -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC][PATCH 3/9] usb: otg: add OTG core
On 20/03/15 09:45, Peter Chen wrote:
On Thu, Mar 19, 2015 at 12:18:55PM +0200, Roger Quadros wrote:
On 19/03/15 05:40, Peter Chen wrote:
On Wed, Mar 18, 2015 at 03:55:57PM +0200, Roger Quadros wrote:
The OTG core instantiates the OTG Finite State Machine
per OTG controller and manages starting/stopping the
host and gadget controllers based on the bus state.
It provides APIs for the following tasks
- Registering an OTG capable controller
- Registering Host and Gadget controllers to OTG core
- Providing inputs to and kicking the OTG state machine
TODO:
- sysfs interface to allow application inputs to OTG state machine
- otg class?
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/usb/Makefile | 1 +
drivers/usb/common/Makefile | 1 +
drivers/usb/common/usb-otg.c | 732
+++
drivers/usb/common/usb-otg.h | 71 +
drivers/usb/core/Kconfig | 8 +
include/linux/usb/usb-otg.h | 86 +
6 files changed, 899 insertions(+)
create mode 100644 drivers/usb/common/usb-otg.c
create mode 100644 drivers/usb/common/usb-otg.h
create mode 100644 include/linux/usb/usb-otg.h
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index 2f1e2aa..07f59a5 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -60,5 +60,6 @@ obj-$(CONFIG_USB_RENESAS_USBHS) += renesas_usbhs/
obj-$(CONFIG_USB_GADGET) += gadget/
obj-$(CONFIG_USB_COMMON) += common/
+obj-$(CONFIG_USB_OTG_CORE)+= common/
obj-$(CONFIG_USBIP_CORE) += usbip/
diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
index ca2f8bd..573fc75 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -7,3 +7,4 @@ usb-common-y += common.o
usb-common-$(CONFIG_USB_LED_TRIG) += led.o
obj-$(CONFIG_USB_OTG_FSM) += usb-otg-fsm.o
+obj-$(CONFIG_USB_OTG_CORE) += usb-otg.o
diff --git a/drivers/usb/common/usb-otg.c b/drivers/usb/common/usb-otg.c
new file mode 100644
index 000..1433fc9
--- /dev/null
+++ b/drivers/usb/common/usb-otg.c
@@ -0,0 +1,732 @@
+/**
+ * drivers/usb/common/usb-otg.c - USB OTG core
+ *
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Roger Quadros rog...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/list.h
+#include linux/timer.h
+#include linux/usb/otg.h
+#include linux/usb/phy.h/* enum usb_otg_state */
+#include linux/usb/gadget.h
+#include linux/usb/usb-otg.h
+#include linux/workqueue.h
+
+#include usb-otg.h
+
+/* to link timer with callback data */
+struct otg_timer {
+ struct timer_list timer;
+ /* callback data */
+ int *timeout_bit;
+ struct otg_data *otgd;
+};
+
+struct otg_data {
+ struct device *dev; /* HCD GCD's parent device */
+
+ struct otg_fsm fsm;
+ /* HCD, GCD and usb_otg_state are present in otg_fsm-otg
+ * HCD is bus_to_hcd(fsm-otg-host)
+ * GCD is fsm-otg-gadget
+ */
+ struct otg_fsm_ops fsm_ops; /* private copy for override */
+ struct usb_otg otg;
+ struct usb_hcd *shared_hcd; /* if shared HCD registered */
+
+ /* saved hooks to OTG device */
+ int (*start_host)(struct otg_fsm *fsm, int on);
+ int (*start_gadget)(struct otg_fsm *fsm, int on);
+
+ struct list_head list;
+
+ struct work_struct work;/* OTG FSM work */
+ struct workqueue_struct *wq;
+
+ struct otg_timer timers[NUM_OTG_FSM_TIMERS];
+
+ bool fsm_running;
+ bool gadget_can_start; /* OTG FSM says gadget can start */
+ bool host_can_start;/* OTG FSM says host can start */
+
+ /* use otg-fsm.lock for serializing access */
+};
What's the relationship between struct usb_otg otg and this one?
Did you mean why struct usb_otg otg is there in struct otg_data?
Just for easy allocation. fsm_ops only contains the pointer to struct
usb_otg.
The reason why I ask this question is the most structures at usb_otg
(only enum usb_otg_state)are useless for otg_fsm, this structure may
only for hardware otg fsm driver, so your OTG framework should only
for software FSM drivers, right?
right. we only need it for enum usb_otg_state.
Do you see how we can improve it?
cheers,
-roger
Peter
+
+/* OTG device list */
+LIST_HEAD(otg_list);
+static DEFINE_MUTEX(otg_list_mutex);
+
+/**
+ * check if device is in our OTG list and return
+ * otg_data, else NULL.
+ *
+ * otg_list_mutex must be held.
+ */
+static struct otg_data
RE: [RFC][PATCH 3/9] usb: otg: add OTG core
- Registering an OTG capable controller
- Registering Host and Gadget controllers to OTG core
- Providing inputs to and kicking the OTG state machine
TODO:
- sysfs interface to allow application inputs to OTG state machine
- otg class?
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/usb/Makefile | 1 +
drivers/usb/common/Makefile | 1 +
drivers/usb/common/usb-otg.c | 732
+++
drivers/usb/common/usb-otg.h | 71 +
drivers/usb/core/Kconfig | 8 +
include/linux/usb/usb-otg.h | 86 +
6 files changed, 899 insertions(+) create mode 100644
drivers/usb/common/usb-otg.c create mode 100644
drivers/usb/common/usb-otg.h create mode 100644
include/linux/usb/usb-otg.h
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile index
2f1e2aa..07f59a5 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -60,5 +60,6 @@ obj-$(CONFIG_USB_RENESAS_USBHS)+=
renesas_usbhs/
obj-$(CONFIG_USB_GADGET)+= gadget/
obj-$(CONFIG_USB_COMMON)+= common/
+obj-$(CONFIG_USB_OTG_CORE) += common/
obj-$(CONFIG_USBIP_CORE)+= usbip/
diff --git a/drivers/usb/common/Makefile
b/drivers/usb/common/Makefile index ca2f8bd..573fc75 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -7,3 +7,4 @@ usb-common-y += common.o
usb-common-$(CONFIG_USB_LED_TRIG) += led.o
obj-$(CONFIG_USB_OTG_FSM) += usb-otg-fsm.o
+obj-$(CONFIG_USB_OTG_CORE) += usb-otg.o
diff --git a/drivers/usb/common/usb-otg.c
b/drivers/usb/common/usb-otg.c new file mode 100644 index
000..1433fc9
--- /dev/null
+++ b/drivers/usb/common/usb-otg.c
@@ -0,0 +1,732 @@
+/**
+ * drivers/usb/common/usb-otg.c - USB OTG core
+ *
+ * Copyright (C) 2015 Texas Instruments Incorporated -
+http://www.ti.com
+ * Author: Roger Quadros rog...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or
+modify
+ * it under the terms of the GNU General Public License version 2
+as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/list.h
+#include linux/timer.h
+#include linux/usb/otg.h
+#include linux/usb/phy.h /* enum usb_otg_state */
+#include linux/usb/gadget.h
+#include linux/usb/usb-otg.h
+#include linux/workqueue.h
+
+#include usb-otg.h
+
+/* to link timer with callback data */ struct otg_timer {
+struct timer_list timer;
+/* callback data */
+int *timeout_bit;
+struct otg_data *otgd;
+};
+
+struct otg_data {
+struct device *dev; /* HCD GCD's parent device */
+
+struct otg_fsm fsm;
+/* HCD, GCD and usb_otg_state are present in otg_fsm-otg
+ * HCD is bus_to_hcd(fsm-otg-host)
+ * GCD is fsm-otg-gadget
+ */
+struct otg_fsm_ops fsm_ops; /* private copy for override */
+struct usb_otg otg;
+struct usb_hcd *shared_hcd; /* if shared HCD registered */
+
+/* saved hooks to OTG device */
+int (*start_host)(struct otg_fsm *fsm, int on);
+int (*start_gadget)(struct otg_fsm *fsm, int on);
+
+struct list_head list;
+
+struct work_struct work;/* OTG FSM work */
+struct workqueue_struct *wq;
+
+struct otg_timer timers[NUM_OTG_FSM_TIMERS];
+
+bool fsm_running;
+bool gadget_can_start; /* OTG FSM says gadget can
start */
+bool host_can_start;/* OTG FSM says host can start
*/
+
+/* use otg-fsm.lock for serializing access */ };
What's the relationship between struct usb_otg otg and this one?
Did you mean why struct usb_otg otg is there in struct otg_data?
Just for easy allocation. fsm_ops only contains the pointer to struct
usb_otg.
The reason why I ask this question is the most structures at usb_otg
(only enum usb_otg_state)are useless for otg_fsm, this structure may
only for hardware otg fsm driver, so your OTG framework should only
for software FSM drivers, right?
right. we only need it for enum usb_otg_state.
Do you see how we can improve it?
Felipe Roger, if we need to go on supporting legacies otg driver, we need to
keep struct usb_otg unchanged, and teach new otg driver using Roger's framework.
Peter
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC][PATCH 2/9] usb: gadget: add usb_gadget_start/stop()
On 20/03/15 09:18, Peter Chen wrote: On Thu, Mar 19, 2015 at 04:50:31PM +0200, Roger Quadros wrote: On 19/03/15 16:09, Li Jun wrote: On Thu, Mar 19, 2015 at 12:14:39PM +0200, Roger Quadros wrote: On 19/03/15 05:30, Peter Chen wrote: On Wed, Mar 18, 2015 at 03:55:56PM +0200, Roger Quadros wrote: The OTG state machine needs a mechanism to start and stop the gadget controller. Add usb_gadget_start() and usb_gadget_stop(). Signed-off-by: Roger Quadros rog...@ti.com --- drivers/usb/gadget/udc/udc-core.c | 166 +++--- include/linux/usb/gadget.h| 3 + 2 files changed, 158 insertions(+), 11 deletions(-) diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c index 5a81cb0..69b4123 100644 --- a/drivers/usb/gadget/udc/udc-core.c +++ b/drivers/usb/gadget/udc/udc-core.c @@ -35,6 +35,8 @@ * @dev - the child device to the actual controller * @gadget - the gadget. For use by the class code * @list - for use by the udc class driver + * @running - udc is running Doesn't OTG FSM should know it? Not really, as the gadget driver might not have been loaded yet or userspace might have disabled softconnect when the OTG FSM wants UDC to start. So only UDC knows if it has really started or not based on this flag. why this can not be known by check the otg fsm state? i.e. if the device in b_peripheral or a_peripheral state, udc should had started, isn't it? If gadget function driver (which is different from UDC driver) is not yet loaded then we can't start UDC even if otg fsm is in b_peripheral. Also, if userspace has disabled softconnect we can't start UDC. So, b_peripheral != UDC_started. I've tried to address this issue by adding the checks in usb_gadget_start(). Ok, maybe we have different understanding for 'B-Device' at software, In spec, it says the Micro-AB receptacle with nothing connected can be 'B-Device', but in fact, we may not enable device mode before loading gadget driver, in chipidea fsm design, if the gadget driver is not loaded, the FSM will not start, and it is at OTG_STATE_UNDEFINED. Right. I mixed up into thinking that we should respect the softconnect while in OTG mode. It seems that we should ignore it. One more thing is we may need to find a place to issue SRP when we load gadget driver, since we may at b_idle at that time due to host closes the vbus (timeout for a_wait_bcon). Issuing SRP should be done by the otg-fsm and not udc-core. The udc-core can at the least call usb_otg_kick_fsm() after setting the gadget driver so that otg-fsm knows that we now have a valid gadget and can take necessary action. i.e. change from b_idle to b_srp_init and then to b_peripheral. What is the softconnect used for? In otg fsm, we use b_bus_req for FSM. I understand now that we shouldn't bother with softconnect when we are in OTG fsm mode. That solves our problem with the running flags. So now, b_peripheral == UDC_started. I will address this in v2. cheers, -roger -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3] ASoC: davinci-mcasp: Set rule constraints if implicit BCLK divider is used
Set rule constraints to allow only combinations of sample-rate,
sample-format, and channels counts that can be played/captured with
reasonable sample-rate accuracy.
The logic with tdm-slots and serializers (=i2s data wires) goes like
this: The first wire will take all channels up to number of tdm-slots,
before following wires (if any) are used. If the first wire is used
fully, the remaining wires share the same clocks and the divider can
be calculated for the first wire.
Also, takes the number of tdm-slots into account when implicitly
selecting the BLCK divider.
Signed-off-by: Jyri Sarha jsa...@ti.com
---
Previous version of the patch:
http://mailman.alsa-project.org/pipermail/alsa-devel/2015-March/089319.html
Since v2 I changed the SNDRV_PCM_HW_PARAM_SAMPLE_BITS rule in the to
SNDRV_PCM_HW_PARAM_FORMAT rule.
Somehow the constraints with a SNDRV_PCM_HW_PARAM_SAMPLE_BITS rule
using snd_interval_list() converged to an empty set when ever I tried
to play a format that could not pass the rule with any channel count
or rate, resulting all too familiar assertion in alsa-lib. However,
the direct tampering with SNDRV_PCM_HW_PARAM_FORMAT mask appears to
work as it should.
In addition to SAMPLE_BITS- to FORMAT-rule change I optimized the rate
rule a bit so that it does not try the rates that are outside current
range. According to my tests this does not affect the behavior in any
other way but slightly speeds up the decision making.
sound/soc/davinci/davinci-mcasp.c | 207 --
1 file changed, 197 insertions(+), 10 deletions(-)
diff --git a/sound/soc/davinci/davinci-mcasp.c
b/sound/soc/davinci/davinci-mcasp.c
index d40b392..76156d18 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -27,6 +27,7 @@
#include linux/of_platform.h
#include linux/of_device.h
#include linux/platform_data/davinci_asp.h
+#include linux/math64.h
#include sound/asoundef.h
#include sound/core.h
@@ -65,6 +66,11 @@ struct davinci_mcasp_context {
boolpm_state;
};
+struct davinci_mcasp_ruledata {
+ struct davinci_mcasp *mcasp;
+ int serializers;
+};
+
struct davinci_mcasp {
struct snd_dmaengine_dai_dma_data dma_data[2];
void __iomem *base;
@@ -99,6 +105,8 @@ struct davinci_mcasp {
#ifdef CONFIG_PM_SLEEP
struct davinci_mcasp_context context;
#endif
+
+ struct davinci_mcasp_ruledata ruledata[2];
};
static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
@@ -868,6 +876,30 @@ static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
return 0;
}
+static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
+ unsigned int bclk_freq,
+ int *error_ppm)
+{
+ int div = mcasp-sysclk_freq / bclk_freq;
+ int rem = mcasp-sysclk_freq % bclk_freq;
+
+ if (rem != 0) {
+ if (div == 0 ||
+ ((mcasp-sysclk_freq / div) - bclk_freq)
+ (bclk_freq - (mcasp-sysclk_freq / (div+1 {
+ div++;
+ rem = rem - bclk_freq;
+ }
+ }
+ if (error_ppm)
+ *error_ppm =
+ (div*100 + (int)div64_long(100LL*rem,
+ (int)bclk_freq))
+ /div - 100;
+
+ return div;
+}
+
static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
@@ -883,16 +915,20 @@ static int davinci_mcasp_hw_params(struct
snd_pcm_substream *substream,
* the machine driver, we need to calculate the ratio.
*/
if (mcasp-bclk_master mcasp-bclk_div == 0 mcasp-sysclk_freq) {
- unsigned int bclk_freq = snd_soc_params_to_bclk(params);
- unsigned int div = mcasp-sysclk_freq / bclk_freq;
- if (mcasp-sysclk_freq % bclk_freq != 0) {
- if (((mcasp-sysclk_freq / div) - bclk_freq)
- (bclk_freq - (mcasp-sysclk_freq / (div+1
- div++;
- dev_warn(mcasp-dev,
-Inaccurate BCLK: %u Hz / %u != %u Hz\n,
-mcasp-sysclk_freq, div, bclk_freq);
- }
+ int channels = params_channels(params);
+ int rate = params_rate(params);
+ int sbits = params_width(params);
+ int ppm, div;
+
+ if (channels mcasp-tdm_slots)
+ channels = mcasp-tdm_slots;
+
+ div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*channels,
+ppm);
+ if (ppm)
+ dev_info(mcasp-dev,
Re: [PATCH] drm/omap: tiler: add hibernation callback
On 18/03/15 16:56, grygorii.stras...@linaro.org wrote:
Hi All,
On 02/25/2015 08:08 PM, grygorii.stras...@linaro.org wrote:
From: Grygorii Strashko grygorii.stras...@linaro.org
Setting a dev_pm_ops resume callback but not a set of
hibernation handler means that pm function will not be
called upon hibernation.
Fix this by using SIMPLE_DEV_PM_OPS, which appropriately
assigns the suspend and hibernation handlers and move
omap_dmm_resume under CONFIG_PM_SLEEP to avoid build warnings.
Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org
---
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
index 56c6055..afb8cfc 100644
--- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
+++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
@@ -941,7 +941,7 @@ error:
}
#endif
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
static int omap_dmm_resume(struct device *dev)
{
struct tcm_area area;
@@ -965,12 +965,10 @@ static int omap_dmm_resume(struct device *dev)
return 0;
}
-
-static const struct dev_pm_ops omap_dmm_pm_ops = {
-.resume = omap_dmm_resume,
-};
#endif
+SIMPLE_DEV_PM_OPS(omap_dmm_pm_ops, NULL, omap_dmm_resume);
+
#if defined(CONFIG_OF)
static const struct of_device_id dmm_of_match[] = {
{ .compatible = ti,omap4-dmm, },
@@ -986,9 +984,7 @@ struct platform_driver omap_dmm_driver = {
.owner = THIS_MODULE,
.name = DMM_DRIVER_NAME,
.of_match_table = of_match_ptr(dmm_of_match),
-#ifdef CONFIG_PM
.pm = omap_dmm_pm_ops,
-#endif
},
};
Any comments on this?
Sorry, I missed this. I'll add it to my omapdrm branch.
Tomi
signature.asc
Description: OpenPGP digital signature
Re: [RFC][PATCH 2/9] usb: gadget: add usb_gadget_start/stop()
On 20/03/15 11:46, Roger Quadros wrote: On 20/03/15 09:18, Peter Chen wrote: On Thu, Mar 19, 2015 at 04:50:31PM +0200, Roger Quadros wrote: On 19/03/15 16:09, Li Jun wrote: On Thu, Mar 19, 2015 at 12:14:39PM +0200, Roger Quadros wrote: On 19/03/15 05:30, Peter Chen wrote: On Wed, Mar 18, 2015 at 03:55:56PM +0200, Roger Quadros wrote: The OTG state machine needs a mechanism to start and stop the gadget controller. Add usb_gadget_start() and usb_gadget_stop(). Signed-off-by: Roger Quadros rog...@ti.com --- drivers/usb/gadget/udc/udc-core.c | 166 +++--- include/linux/usb/gadget.h| 3 + 2 files changed, 158 insertions(+), 11 deletions(-) diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c index 5a81cb0..69b4123 100644 --- a/drivers/usb/gadget/udc/udc-core.c +++ b/drivers/usb/gadget/udc/udc-core.c @@ -35,6 +35,8 @@ * @dev - the child device to the actual controller * @gadget - the gadget. For use by the class code * @list - for use by the udc class driver + * @running - udc is running Doesn't OTG FSM should know it? Not really, as the gadget driver might not have been loaded yet or userspace might have disabled softconnect when the OTG FSM wants UDC to start. So only UDC knows if it has really started or not based on this flag. why this can not be known by check the otg fsm state? i.e. if the device in b_peripheral or a_peripheral state, udc should had started, isn't it? If gadget function driver (which is different from UDC driver) is not yet loaded then we can't start UDC even if otg fsm is in b_peripheral. Also, if userspace has disabled softconnect we can't start UDC. So, b_peripheral != UDC_started. I've tried to address this issue by adding the checks in usb_gadget_start(). Ok, maybe we have different understanding for 'B-Device' at software, In spec, it says the Micro-AB receptacle with nothing connected can be 'B-Device', but in fact, we may not enable device mode before loading gadget driver, in chipidea fsm design, if the gadget driver is not loaded, the FSM will not start, and it is at OTG_STATE_UNDEFINED. Right. I mixed up into thinking that we should respect the softconnect while in OTG mode. It seems that we should ignore it. One more thing is we may need to find a place to issue SRP when we load gadget driver, since we may at b_idle at that time due to host closes the vbus (timeout for a_wait_bcon). Issuing SRP should be done by the otg-fsm and not udc-core. The udc-core can at the least call usb_otg_kick_fsm() after setting the gadget driver so that otg-fsm knows that we now have a valid gadget and can take necessary action. i.e. change from b_idle to b_srp_init and then to b_peripheral. To clarify further. Is it right to assume that OTG FSM will not be started till both gadget UDC driver _AND_ gadget function driver are loaded? And it will be stopped when either of them unloads. This simplifies things a lot. cheers, -roger What is the softconnect used for? In otg fsm, we use b_bus_req for FSM. I understand now that we shouldn't bother with softconnect when we are in OTG fsm mode. That solves our problem with the running flags. So now, b_peripheral == UDC_started. I will address this in v2. cheers, -roger -- To unsubscribe from this list: send the line unsubscribe linux-usb in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 1/3] of/device: manage resources similar to platform_device_add
On Thu, 22 Jan 2015 15:49:59 -0600 , Suman Anna s-a...@ti.com wrote: Hi Grant, On 01/13/2015 05:04 PM, Suman Anna wrote: On 01/13/2015 04:00 PM, Rob Herring wrote: On Tue, Jan 13, 2015 at 3:25 PM, Suman Anna s-a...@ti.com wrote: Hi Rob, On 01/13/2015 02:38 PM, Rob Herring wrote: On Wed, Jan 7, 2015 at 11:30 AM, Suman Anna s-a...@ti.com wrote: Drivers can use of_platform_populate() to create platform devices for children of the device main node, and a complementary API of_platform_depopulate() is provided to delete these child platform devices. The of_platform_depopulate() leverages the platform API for performing the cleanup of these devices. The platform device resources are managed differently between of_device_add and platform_device_add, and this asymmetry causes a kernel oops in platform_device_del during removal of the resources. Manage the platform device resources similar to platform_device_add to fix this kernel oops. This is a known issue and has been attempted to be fixed before (I believe there is a revert in mainline). The problem is there are known devicetrees which have overlapping resources and they will break with your change. Are you referring to 02bbde7849e6 (Revert of: use platform_device_add)? I believe that's the one. That one seems to be in registration path, and this crash is in the unregistration path. If so, to fix the crash, should we be skipping the release_resource() for now in platform_device_del for DT nodes, or replace platform_device_unregister with of_device_unregister in of_platform_device_destroy()? IIRC, the problem is inserting a resource twice on add from 2 different nodes, not the removal path. Perhaps we could make a collision non-fatal for in the DT case. We may be talking two different things here, I understand that this patch would create an issue with inserting a resource twice in the devicetrees with overlapping resources (just like the commit that was reverted above), but the crash is on devices with resources whose parent, child, sibling pointers have never been initialized (the of_device_add path does not touch these at all), and get dereferenced in platform_device_del()-release_resource(). See the following that has a better explanation [1]. regards Suman [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/274412.html Grant may have some ideas on what's needed here. Ping, any suggestions here? Do we ought to replace platform_device_unregister() with of_device_unregister() similar to the approach taken in 02bbde7849e6 (Revert of: use platform_device_add)? Hi Suman, Yes, I think the solution to both problems is to create an of_device_unregister() function. It's not the prettiest thing, but I think it is for the best. g. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC][PATCH 1/9] usb: hcd: Introduce usb_start/stop_hcd()
On 20/03/15 08:32, Peter Chen wrote:
On Thu, Mar 19, 2015 at 01:38:32PM +0200, Roger Quadros wrote:
On 18/03/15 21:49, Alan Stern wrote:
On Wed, 18 Mar 2015, Roger Quadros wrote:
To support OTG we want a mechanism to start and stop
the HCD from the OTG state machine. Add usb_start_hcd()
and usb_stop_hcd().
Signed-off-by: Roger Quadros rog...@ti.com
There are a few problems in this proposed patch.
+int usb_start_hcd(struct usb_hcd *hcd)
+{
+ int retval;
+ struct usb_device *rhdev = hcd-self.root_hub;
+
+ if (hcd-state != HC_STATE_HALT) {
+ dev_err(hcd-self.controller, not starting a running HCD\n);
+ return -EINVAL;
+ }
+
+ hcd-state = HC_STATE_RUNNING;
+ retval = hcd-driver-start(hcd);
+ if (retval 0) {
+ dev_err(hcd-self.controller, startup error %d\n, retval);
+ hcd-state = HC_STATE_HALT;
+ return retval;
+ }
+
+ /* starting here, usbcore will pay attention to this root hub */
+ if ((retval = register_root_hub(hcd)) != 0)
+ goto err_register_root_hub;
If the host controller is started more than once, you will end up
unregistering and re-registering the root hub. The device core does
not allow this. Once a device has been unregistered, you must not try
to register it again -- you have to allocate a new device and register
it instead.
Understood.
Also, although you call the driver's -start method multiple times, the
-reset method is called only once, when the controller is first
probed. It's not clear that this will work in a situation where the HC
and the UDC share hardware state; after the UDC is stopped it may be
necessary to reset the HC before it can run again.
Yes, good point.
It might be possible to make this work, but I suspect quite a few
drivers would need rewriting first. As another example of the problems
you face, consider how stopping a host controller will interact with
the driver's PM support (both system suspend and runtime suspend).
Right. This needs more work than I thought.
It would be a lot simpler to unbind the host controller driver
completely when switching to device mode and rebind it when switching
back. I guess that is the sort of heavy-duty approach you want to
avoid, but it may be the only practical way forward.
So you mean directly calling usb_add/remove_hcd() from the OTG core?
I don't see any issues with that other than it being a heavy-duty operation
like you said and hope that it doesn't violate the OTG spec timing.
Looking at Figure 5-3: HNP Sequence of Events (FS) of the OTG 2.0 spec
we have about 150ms (X10) to switch from B-Device detected A connect
(b_wait_acon state)
to driving bus reset (b_host state). I don't think this should be an issue
in modern SoCs
but I'm not very sure.
It is not related toadd/remove hcd, it is the time from receiving PCD
to issue BUS_RESET, the Linux stack can't satisfy OTG spec (150ms) due
to there are some de-bounce waitings.
OK.
In any case I can migrate to the add/remove hcd approach to simplify things.
It should be no problem, we use it more than 1 years.
Good to know this.
cheers,
-roger
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv5 27/35] ARM: dts: am33xx: add minimal l4 bus layout with control module support
* Suman Anna s-a...@ti.com [150320 16:24]:
On 03/20/2015 05:35 PM, Tony Lindgren wrote:
* Suman Anna s-a...@ti.com [150320 14:44]:
On 03/20/2015 01:44 PM, Kristo, Tero wrote:
+ scm: scm@21 {
+ compatible = ti,am3-scm, simple-bus;
+ reg = 0x21 0x2000;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x21 0x2000;
+
+ am33xx_pinmux: pinmux@800 {
+ compatible = pinctrl-single;
+ reg = 0x800 0x238;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-single,register-width = 32;
+ pinctrl-single,function-mask = 0x7f;
+ };
+
+ scm_conf: scm_conf@0 {
+ compatible = syscon;
+ reg = 0x0 0x7fc;
Hmm, you are consolidating the am33xx_control_module and cm nodes, so is
this supposed to be 0x800 or 0x7fc? I would think it should be 0x800.
Seems correct to me, it's offset 0, size 0x7fc. So that's the scm_conf
syscon area before pinctrl-single at 0x44c0 + 0x21 + 0.
The io area for pinctrl-single starts at 0x800, so the scm_conf should
be before it in the dts file.
Well, I understand that it is how it was before, but we won't be mapping
or covering the last register efuse_sma before the pinctrl cfg
registers. Any reason for just leaving out that register?
Oh I see yeah that looks like a bug to me.
Tony
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFT OMAP1 PATCH 7/8] gpio: omap: get rid of omap_irq_to_gpio()
Hello Grygorii, On Fri, Mar 20, 2015 at 9:39 PM, grygorii.stras...@linaro.org grygorii.stras...@linaro.org wrote: On 03/20/2015 08:56 PM, Javier Martinez Canillas wrote: Hello Grygorii, On Thu, Mar 19, 2015 at 6:25 PM, grygorii.stras...@linaro.org wrote: From: Grygorii Strashko grygorii.stras...@linaro.org Now OMAP GPIO driver prepared for omap_irq_to_gpio() removing. Do it ;) Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org I don't have access to OMAP1 boards to test but Tony did it o an osk5912 and Aaro can confirm that it doesn't cause regressions on other OMAP1 boards. Thanks. But could you clarify one point to me please? Aaro can confirm that it doesn't cause regressions on other OMAP1 boards - Does It mean I can add his Tested-by? Or I still have to wait for his direct reply? Just to avoid any confusions ;) I meant that as far as I know Aaro has access to more OMAP1 systems so he should be able to test that no regressions are added for those. But I don't know if he would be able to test and I think your cleanups are good so that's why I acked the patches. Sorry for the confusion. Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv5 27/35] ARM: dts: am33xx: add minimal l4 bus layout with control module support
On 03/20/2015 05:35 PM, Tony Lindgren wrote:
* Suman Anna s-a...@ti.com [150320 14:44]:
On 03/20/2015 01:44 PM, Kristo, Tero wrote:
+ scm: scm@21 {
+ compatible = ti,am3-scm, simple-bus;
+ reg = 0x21 0x2000;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x21 0x2000;
+
+ am33xx_pinmux: pinmux@800 {
+ compatible = pinctrl-single;
+ reg = 0x800 0x238;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-single,register-width = 32;
+ pinctrl-single,function-mask = 0x7f;
+ };
+
+ scm_conf: scm_conf@0 {
+ compatible = syscon;
+ reg = 0x0 0x7fc;
Hmm, you are consolidating the am33xx_control_module and cm nodes, so is
this supposed to be 0x800 or 0x7fc? I would think it should be 0x800.
Seems correct to me, it's offset 0, size 0x7fc. So that's the scm_conf
syscon area before pinctrl-single at 0x44c0 + 0x21 + 0.
The io area for pinctrl-single starts at 0x800, so the scm_conf should
be before it in the dts file.
Well, I understand that it is how it was before, but we won't be mapping
or covering the last register efuse_sma before the pinctrl cfg
registers. Any reason for just leaving out that register?
regards
Suman
Also, are we ordering the child nodes of scm by node names or addresses.
I have to add the wkup_m3 node, and prefer ordering by addresses.
Yeah address ordering makes most sense here IMO.
Note that you should follow the TRM Table 2-2. L4_WKUP Peripheral Memory
Map and set up things as separate devices as shown there. Pretty much
each row in that table is a separate device on the interconnect. That's
especially true if the device has registers like revision, sysc, syss
and so on. In that case they can be clocked and idled separately.
So with these changes we follow the hardware mapping, although only
partially have it populated now for l4_wkup:
l3 (ocp) +- l4_per +- ...
| |- ...
|
+- l4_wkup +- prcm
| |- scm
| |- ...
|
+- ... +- ...
Regards,
Tony
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC][PATCH 2/9] usb: gadget: add usb_gadget_start/stop()
On Fri, Mar 20, 2015 at 01:08:25PM +0200, Roger Quadros wrote: On 20/03/15 11:46, Roger Quadros wrote: On 20/03/15 09:18, Peter Chen wrote: On Thu, Mar 19, 2015 at 04:50:31PM +0200, Roger Quadros wrote: On 19/03/15 16:09, Li Jun wrote: On Thu, Mar 19, 2015 at 12:14:39PM +0200, Roger Quadros wrote: On 19/03/15 05:30, Peter Chen wrote: On Wed, Mar 18, 2015 at 03:55:56PM +0200, Roger Quadros wrote: The OTG state machine needs a mechanism to start and stop the gadget controller. Add usb_gadget_start() and usb_gadget_stop(). Signed-off-by: Roger Quadros rog...@ti.com --- drivers/usb/gadget/udc/udc-core.c | 166 +++--- include/linux/usb/gadget.h| 3 + 2 files changed, 158 insertions(+), 11 deletions(-) diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c index 5a81cb0..69b4123 100644 --- a/drivers/usb/gadget/udc/udc-core.c +++ b/drivers/usb/gadget/udc/udc-core.c @@ -35,6 +35,8 @@ * @dev - the child device to the actual controller * @gadget - the gadget. For use by the class code * @list - for use by the udc class driver + * @running - udc is running Doesn't OTG FSM should know it? Not really, as the gadget driver might not have been loaded yet or userspace might have disabled softconnect when the OTG FSM wants UDC to start. So only UDC knows if it has really started or not based on this flag. why this can not be known by check the otg fsm state? i.e. if the device in b_peripheral or a_peripheral state, udc should had started, isn't it? If gadget function driver (which is different from UDC driver) is not yet loaded then we can't start UDC even if otg fsm is in b_peripheral. Also, if userspace has disabled softconnect we can't start UDC. So, b_peripheral != UDC_started. I've tried to address this issue by adding the checks in usb_gadget_start(). Ok, maybe we have different understanding for 'B-Device' at software, In spec, it says the Micro-AB receptacle with nothing connected can be 'B-Device', but in fact, we may not enable device mode before loading gadget driver, in chipidea fsm design, if the gadget driver is not loaded, the FSM will not start, and it is at OTG_STATE_UNDEFINED. Right. I mixed up into thinking that we should respect the softconnect while in OTG mode. It seems that we should ignore it. One more thing is we may need to find a place to issue SRP when we load gadget driver, since we may at b_idle at that time due to host closes the vbus (timeout for a_wait_bcon). Issuing SRP should be done by the otg-fsm and not udc-core. The udc-core can at the least call usb_otg_kick_fsm() after setting the gadget driver so that otg-fsm knows that we now have a valid gadget and can take necessary action. i.e. change from b_idle to b_srp_init and then to b_peripheral. To clarify further. Is it right to assume that OTG FSM will not be started till both gadget UDC driver _AND_ gadget function driver are loaded? And it will be stopped when either of them unloads. This simplifies things a lot. Yes, you are right. cheers, -roger What is the softconnect used for? In otg fsm, we use b_bus_req for FSM. I understand now that we shouldn't bother with softconnect when we are in OTG fsm mode. That solves our problem with the running flags. So now, b_peripheral == UDC_started. I will address this in v2. cheers, -roger -- To unsubscribe from this list: send the line unsubscribe linux-usb in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- Best Regards, Peter Chen -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Serious memory leak in TI EDMA driver (drivers/dma/edma.c)
Petr, On 03/18/2015 11:33 PM, Petr Kulhavy wrote: Hi Peter, Yes, we do not use DT. Our board design is very close to the da850evm reference board. So if you have a chance of getting hold of it you could try on that one. I have been trying to reproduce this on my OMAP-L138-EVM (da850evm) but was not able. There is a big difference in your an my setup: the MMC on my EVM is connected to MMC/SD0 interface while in your setup it seams to be connected to MMC/SD1. The DMA requests for MMC/SD0 is eDMA CC0 16/17, while the MMC/SD1 is eDMA CC1 28/29. So they are handled by different channel controllers. I would not rule out that the support for the second CC has issues. The information from you logs just points to this direction also: You are writing to the MMC, so CC1 ch29 is active most of the time. In your log the channel number sometimes 65565 ((1 16) | 29) sometimes it is 29. In my case it is 17 every time. I think there is something funny regarding to how these channels on CC1 are working and this might be causing the leak for you. Unfortunately I do not have HW where I could use any channel on CC1 so I can not debug this further, but I'll look at the code to see if anything obvious stands out. And something does stand out: arch/arm/common/edma.c: dma_irq_handler() It calls the callback with a wrong interrupt number since it does not take into account the different CC. Can you try something similar to see if it helps: diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c index 6c49887d326e..e1d413c61e9e 100644 --- a/arch/arm/common/edma.c +++ b/arch/arm/common/edma.c @@ -405,7 +405,8 @@ static irqreturn_t dma_irq_handler(int irq, void *data) BIT(slot)); if (edma_cc[ctlr]-intr_data[channel].callback) edma_cc[ctlr]-intr_data[channel].callback( - channel, EDMA_DMA_COMPLETE, + EDMA_CTLR_CHAN(ctlr, channel), + EDMA_DMA_COMPLETE, edma_cc[ctlr]-intr_data[channel].data); } } while (sh_ipr); -- Péter The wrong channel number justmeans that it's on the second controller (pdev-id is 1), the debug is just printing the compound number channel+controller. I believe that the problem is in edma_terminate_all(), the active edesc is not freed by the vchan_dma_desc_free_list() according to the below debug trace. The first alloc/free pair is correct, the other alloc has no free - see the Terminate all line. I also enabled debug in common/edma.c and virt-dma.c. Note that the Terminate all message is printed at the end of edma_terminate_all() function just before return. Printing it earlier was disturbing my test. So the critical sequence is: - submit transaction - issue pending - IRQ handler (int 3 ???) - doesn't seem to be relevant - terminate all transfers - dma stop - this doesn't free - IRQ handler (int 29) - callback - probably harmless The issue is that edma_execute() calls vchan_next_desc() which removes the request from vc-dest_issued list and while the transaction is being processed it's not on any list and terminate_all_transfers calling vchan_get_all_descriptors doesn't find it and therefore doesn't free it. Is that a plausible explanation? Cheers Petr Mar 18 20:38:09 barix user.debug kernel: edma-dma-engine edma-dma-engine.1: ALLOC edesc: 0xc34d5b80 (channel: 65565, sg_len: 9) Mar 18 20:38:09 barix user.debug kernel: edma-dma-engine edma-dma-engine.1: vchan c781bc70: txd c34d5b80[1c91]: submitted Mar 18 20:38:09 barix user.debug kernel: edma-dma-engine edma-dma-engine.1: first transfer starting on channel 65565 Mar 18 20:38:09 barix user.debug kernel: EDMA: ER0 Mar 18 20:38:09 barix user.debug kernel: EDMA: EER0 2000 Mar 18 20:38:09 barix user.debug kernel: edma edma: dma_irq_handler Mar 18 20:38:09 barix user.debug kernel: edma edma: IPR0 0008 Mar 18 20:38:09 barix user.debug kernel: edma edma: dma_irq_handler Mar 18 20:38:09 barix user.debug kernel: edma edma: IPR0 2000 Mar 18 20:38:09 barix user.debug kernel: edma-dma-engine edma-dma-engine.1: Edma callback: edesc 0xc34d5b80 Mar 18 20:38:09 barix user.debug kernel: edma-dma-engine edma-dma-engine.1: Pausing channel 29 Mar 18 20:38:09 barix user.debug kernel: edma-dma-engine edma-dma-engine.1: Transfer complete, stopping channel 29 Mar 18 20:38:09 barix user.debug kernel: EDMA: EER0 Mar 18 20:38:09 barix user.debug kernel: edma-dma-engine edma-dma-engine.1: Setting edesc 0xc34d5b80 to NULL Mar 18 20:38:09 barix user.debug kernel: edma-dma-engine edma-dma-engine.1: txd c34d5b80: freeing Mar 18 20:38:09 barix user.debug kernel: edma-dma-engine edma-dma-engine.1: FREE edesc: 0xc34d5b80 (channel: 65565) Mar 18 20:38:09 barix user.debug kernel: edma-dma-engine edma-dma-engine.1:
Re: am335x: GPMC: reading speed with prefetch mode
+Tony and l-o
On 20/03/15 15:37, Yegor Yefremov wrote:
On Fri, Mar 20, 2015 at 1:37 PM, Roger Quadros rog...@ti.com wrote:
On 20/03/15 13:24, Yegor Yefremov wrote:
On Thu, Mar 19, 2015 at 4:56 PM, Daniel Mack zon...@gmail.com wrote:
On 03/19/2015 04:13 PM, Yegor Yefremov wrote:
Strange. Have tried with nand read command, but still the same
result with and without CONFIG_NAND_OMAP_GPMC_PREFETCH :
[2.150655 0.001006] NAND read: device 0 offset 0x26, size 0x120
[15.978943 13.828288] 18874368 bytes read: OK
What about adding some debug prints to the prefetch setup function and
see if it is executed at all?
I2C: ready
DRAM: 256 MiB
NAND: prefetch enabled
NAND: 256 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
Using default environment
I've added NAND: prefetch enabled output for:
#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
else {
printf(NAND: prefetch enabled\n);
nand-read_buf = omap_nand_read_prefetch8;
}
#else
I've also put printf() into omap_nand_read_prefetch8() just to make
sure it is called - it was called.
Further ideas?
Daniel, do you have the numbers? Images size and load time? What can I
expect?
I don't currently have the setup at hand, sorry. But the number I recall
from an email conversation back then is: The time from power-on, loading
SPL, loading U-Boot, leeching a 6MB uImage, jumping into it waiting for
the console to start dumping the kernel boot messages was less than 5
seconds in total.
I Linux I had ti,nand-xfer-type = polled;. After replacing it with
ti,nand-xfer-type = prefetch-polled; I now get
# dd if=/dev/mtdblock5 of=/dev/null bs=2M count=8
8+0 records in
8+0 records out
16777216 bytes (17 MB) copied, 2.58744 s, 6.5 MB/s
instead of:
# dd if=/dev/mtdblock5 of=/dev/null bs=2M count=8
8+0 records in
8+0 records out
16777216 bytes (17 MB) copied, 6.05157 s, 2.8 MB/s
Do I see it right, that DMA support is not implemented in am33xx.dtsi?
DMA support will have to be enabled in the board dts. e.g. am335x-bone.dts.
if ti,nand-xfer-type is not specified (like in mainline kernel) then it
defaults to prefetch-polled
I get following error:
omap-gpmc 5000.gpmc: GPMC revision 6.0
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
nand: Micron MT29F2G08ABAEAWP
nand: 256MiB, SLC, page size: 2048, OOB size: 64
omap2-nand omap2-nand.0: DMA engine request failed
Kernel: 3.18.1
GPMC config:
gpmc {
pinctrl-names = default;
pinctrl-0 = nandflash_pins_s0;
ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
status = okay;
nand@0,0 {
reg = 0 0 4; /* CS0, offset 0 */
nand-bus-width = 8;
ti,nand-ecc-opt = bch8;
ti,nand-xfer-type = prefetch-dma;
gpmc,device-nand = true;
gpmc,device-width = 1;
gpmc,sync-clk-ps = 0;
gpmc,cs-on-ns = 0;
gpmc,cs-rd-off-ns = 44;
gpmc,cs-wr-off-ns = 44;
gpmc,adv-on-ns = 6;
gpmc,adv-rd-off-ns = 34;
gpmc,adv-wr-off-ns = 44;
gpmc,we-on-ns = 0;
gpmc,we-off-ns = 40;
gpmc,oe-on-ns = 0;
gpmc,oe-off-ns = 54;
gpmc,access-ns = 64;
gpmc,rd-cycle-ns = 82;
gpmc,wr-cycle-ns = 82;
gpmc,wait-on-read = true;
gpmc,wait-on-write = true;
gpmc,bus-turnaround-ns = 0;
gpmc,cycle2cycle-delay-ns = 0;
gpmc,clk-activation-ns = 0;
gpmc,wait-monitoring-ns = 0;
gpmc,wr-access-ns = 40;
gpmc,wr-data-mux-bus-ns = 0;
#address-cells = 1;
#size-cells = 1;
elm_id = elm;
};
};
Any idea?
Btw. where DMA support should be configured? GPMC config has no dmas
like other components like mmc, uart, USB etc.
I've never tested dma on omap-nand in mainline. We've been solely relying on
prefetch-polled mode there.
someone needs to work on it and test dma support.
looks like the driver is hardcoding the DMA channel
sig = OMAP24XX_DMA_GPMC;
info-dma = dma_request_channel(mask, omap_dma_filter_fn, sig);
this will have to be fixed.
I'm not sure what else is missing on DMA side. But you could try to use a
free channel and see if it works?
Tony any insights?
cheers,
-roger
gpmc: gpmc@5000 {
compatible = ti,am3352-gpmc;
ti,hwmods = gpmc;
ti,no-idle-on-init;
reg = 0x5000 0x2000;
interrupts = 100;
gpmc,num-cs = 7;
gpmc,num-waitpins = 2;
#address-cells =
Re: [PATCH] omapdss: extend pm notifier to handle hibernation
On 25/02/15 19:03, grygorii.stras...@linaro.org wrote:
From: Grygorii Strashko grygorii.stras...@linaro.org
Add handling of missed events in omap_dss_pm_notif which are
needed to support hibernation (suspend to disk).
Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org
---
drivers/video/fbdev/omap2/dss/core.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/video/fbdev/omap2/dss/core.c
b/drivers/video/fbdev/omap2/dss/core.c
index 6b74f73..e60976a 100644
--- a/drivers/video/fbdev/omap2/dss/core.c
+++ b/drivers/video/fbdev/omap2/dss/core.c
@@ -178,11 +178,15 @@ static int omap_dss_pm_notif(struct notifier_block *b,
unsigned long v, void *d)
DSSDBG(pm notif %lu\n, v);
switch (v) {
+ case PM_HIBERNATION_PREPARE:
case PM_SUSPEND_PREPARE:
+ case PM_RESTORE_PREPARE:
DSSDBG(suspending displays\n);
return dss_suspend_all_devices();
case PM_POST_SUSPEND:
+ case PM_POST_HIBERNATION:
+ case PM_POST_RESTORE:
DSSDBG(resuming displays\n);
return dss_resume_all_devices();
Why suspend displays when PM_RESTORE_PREPARE happens? Why resume when
PM_POST_RESTORE happens?
Tomi
signature.asc
Description: OpenPGP digital signature
Re: Patch to parameterize DMA_MIN_BYTES for omap2-mcspi
On 03/19/2015 07:28 PM, Greg Knight wrote: Changing DMA_MIN_BYTES to, say, dma_min_time_ms sounds reasonable to me. I don't know how to compute it completely accurately as some SPI implementations I've seen seem to like to inject little delays between bytes for some reason, but a reasonable enough estimate should just be spi_transfer_time_ms = (bits * 1000) / spi_clock_speed. I would like to have the ability to configure it without a kernel recompile, though. Would a kernel param (module_param) be acceptable for this application? Or sysfs interface as Mark suggested? But module_param should work as well. You don't happen to know the WL12xx SPI clock speed off the top of your head, do you? In case of n900 it is 4800 (board-rx51-peripherals.c). It is using 32bit words over SPI. Based on this and your experience I guess it is possible to come up with a formula which satisfy both. Regards, Greg -- Péter -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 2/6] wl12xx: use frequency instead of enumerations for pdata clocks
Tony Lindgren t...@atomide.com writes: I prefer these going through the omap tree. Like Eliad said, drivers/net/wireless/ti does not get that many changes nowadays so the chances of this patchset conflicting with something is very small. OK great. In that case no need to rearrange the patches, I can apply them into an immutable branch once the pending issues have been fixed if Kalle acks them. To avoid merge conflicts that branch is easiest done against v4.0-rc4. Kalle and Arnd, does that work for you guys? I can also base it on 5b7610f23562 (ARM: OMAP2+: Fix wl12xx on dm3730-evm with mainline u-boot) that's on top of -rc2 plus few other fixes now merged to -rc4 mainline if we need a branch based on an earlier tag. Sorry, it seems I forgot to answer this one: Either baseline is good for me, I can't think of any problems with either one. But please do remember that I'm a new maintainer, I might very well miss something ;) -- Kalle Valo -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Patch to parameterize DMA_MIN_BYTES for omap2-mcspi
On 03/19/2015 08:51 PM, Mark Brown wrote: On Thu, Mar 19, 2015 at 01:28:00PM -0400, Greg Knight wrote: Changing DMA_MIN_BYTES to, say, dma_min_time_ms sounds reasonable to me. I don't know how to compute it completely accurately as some SPI You probably need both - there's often a hard limit where the FIFO size in the hardware becomes a limit for DMA as well as a soft limit on top of that for performance reasons. The FIFO is only going to be enabled when the DMA is used for transfer so we should have some lower limit for the PIO/DMA threshold. The FIFO in McSPI is a tricky one anyways, since it has only one FIFO but several channels and the FIFO can be enabled for only one channel, if it is enabled for more channels it is not going to be used by either channel. -- Péter -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] omapdss: extend pm notifier to handle hibernation
Hi Tomi,
On 03/20/2015 02:20 PM, Tomi Valkeinen wrote:
On 25/02/15 19:03, grygorii.stras...@linaro.org wrote:
From: Grygorii Strashko grygorii.stras...@linaro.org
Add handling of missed events in omap_dss_pm_notif which are
needed to support hibernation (suspend to disk).
Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org
---
drivers/video/fbdev/omap2/dss/core.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/video/fbdev/omap2/dss/core.c
b/drivers/video/fbdev/omap2/dss/core.c
index 6b74f73..e60976a 100644
--- a/drivers/video/fbdev/omap2/dss/core.c
+++ b/drivers/video/fbdev/omap2/dss/core.c
@@ -178,11 +178,15 @@ static int omap_dss_pm_notif(struct notifier_block *b,
unsigned long v, void *d)
DSSDBG(pm notif %lu\n, v);
switch (v) {
+case PM_HIBERNATION_PREPARE:
case PM_SUSPEND_PREPARE:
+case PM_RESTORE_PREPARE:
DSSDBG(suspending displays\n);
return dss_suspend_all_devices();
case PM_POST_SUSPEND:
+case PM_POST_HIBERNATION:
+case PM_POST_RESTORE:
DSSDBG(resuming displays\n);
return dss_resume_all_devices();
Why suspend displays when PM_RESTORE_PREPARE happens? Why resume when
PM_POST_RESTORE happens?
We have following sequence when system is restored from hibernation:
- original kernel booted;
- late_initcall_sync(software_resume);
- pm_notifier_call_chain(PM_RESTORE_PREPARE);
- freeze_processes
- check read hibernation image
- suspend all devices (.freeze())
- jump to stored kernel
- restore devices
...
So, all devices should be in frozen/suspended state when we will jump to stored
kernel
(device's state should be the same as before creating hib image).
Without this patch I can see a lot of log messages like below:
[3.642499] Freezing user space processes ...
[3.647029] mmcblk1boot1: unknown partition table
[3.647043] (elapsed 0.000 seconds) done.
[3.686414] mmcblk1boot0: unknown partition table
[3.714552] PM: Using 1 thread(s) for decompression.
[3.714552] PM: Loading and decompressing image data (144641 pages)...
[4.520388] PM: Image loading progress: 0%
[5.153715] PM: Image loading progress: 10%
[5.847731] PM: Image loading progress: 20%
[6.622024] PM: Image loading progress: 30%
[7.023830] PM: Image loading progress: 40%
[7.455959] PM: Image loading progress: 50%
[8.137186] PM: Image loading progress: 60%
[8.567899] PM: Image loading progress: 70%
[9.670371] PM: Image loading progress: 80%
[ 10.130646] PM: Image loading progress: 90%
[ 10.525035] PM: Image loading progress: 100%
[ 10.529565] PM: Image loading done.
[ 10.533262] PM: Read 578564 kbytes in 6.80 seconds (85.08 MB/s)
[ 10.545313] Suspending console(s) (use no_console_suspend to debug)
[ 193.721284] PM: freeze of devices complete after 7.891 msecs
[ 193.722618] PM: late freeze of devices complete after 1.325 msecs
[ 193.723969] PM: noirq freeze of devices complete after 1.343 msecs
[ 193.724133] Disabling non-boot CPUs ...
[ 193.724792] CPU1: shutdown
[ 193.725387] PM: Creating hibernation image:
[ 193.725387] PM: Need to copy 144499 pages
[ 193.725439] Enabling non-boot CPUs ...
[ 193.725783] CPU1: smp_ops.cpu_die() returned, trying to resuscitate
[ 193.725790] CPU1: Booted secondary processor
[ 193.726069] CPU1 is up
[ 193.743772] PM: noirq restore of devices complete after 17.693 msecs
[ 193.744691] PM: early restore of devices complete after 0.634 msecs
[ 193.951382] [drm:omap_crtc_error_irq] *ERROR* tv: errors: 8000
[ 193.951389] [drm:omap_plane_error_irq] *ERROR* gfx: errors: 0040
[ 193.951402] [drm:omap_crtc_error_irq] *ERROR* tv: errors: 8000
[ 193.951413] [drm:omap_crtc_error_irq] *ERROR* tv: errors: 8000
[ 193.951424] [drm:omap_crtc_error_irq] *ERROR* tv: errors: 8000
[ 193.951435] [drm:omap_crtc_error_irq] *ERROR* tv: errors: 8000
[ 193.951445] [drm:omap_crtc_error_irq] *ERROR* tv: errors: 8000
[ 193.951455] [drm:omap_crtc_error_irq] *ERROR* tv: errors: 8000
[ 193.951465] [drm:omap_crtc_error_irq] *ERROR* tv: errors: 8000
[ 193.951475] [drm:omap_crtc_error_irq] *ERROR* tv: errors: 8000
[ 193.951484] [drm:omap_crtc_error_irq] *ERROR* tv: errors: 8000
[ 193.951567] omap_l3_noc 4400.ocp: L3 application error: target 2 mod:1
(unclearable)
[ 193.951605] omap_l3_noc 4400.ocp: L3 debug error: target 2 mod:1
(unclearable)
[ 194.293226] ata1: SATA link down (SStatus 0 SControl 300)
[ 194.560684] PM: restore of devices complete after 610.740 msecs
--
regards,
-grygorii
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] drm/omap: tiler: add hibernation callback
On 03/20/2015 01:43 PM, Tomi Valkeinen wrote:
On 18/03/15 16:56, grygorii.stras...@linaro.org wrote:
Hi All,
On 02/25/2015 08:08 PM, grygorii.stras...@linaro.org wrote:
From: Grygorii Strashko grygorii.stras...@linaro.org
Setting a dev_pm_ops resume callback but not a set of
hibernation handler means that pm function will not be
called upon hibernation.
Fix this by using SIMPLE_DEV_PM_OPS, which appropriately
assigns the suspend and hibernation handlers and move
omap_dmm_resume under CONFIG_PM_SLEEP to avoid build warnings.
Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org
---
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
index 56c6055..afb8cfc 100644
--- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
+++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
@@ -941,7 +941,7 @@ error:
}
#endif
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
static int omap_dmm_resume(struct device *dev)
{
struct tcm_area area;
@@ -965,12 +965,10 @@ static int omap_dmm_resume(struct device *dev)
return 0;
}
-
-static const struct dev_pm_ops omap_dmm_pm_ops = {
-.resume = omap_dmm_resume,
-};
#endif
+SIMPLE_DEV_PM_OPS(omap_dmm_pm_ops, NULL, omap_dmm_resume);
+
#if defined(CONFIG_OF)
static const struct of_device_id dmm_of_match[] = {
{ .compatible = ti,omap4-dmm, },
@@ -986,9 +984,7 @@ struct platform_driver omap_dmm_driver = {
.owner = THIS_MODULE,
.name = DMM_DRIVER_NAME,
.of_match_table = of_match_ptr(dmm_of_match),
-#ifdef CONFIG_PM
.pm = omap_dmm_pm_ops,
-#endif
},
};
Any comments on this?
Sorry, I missed this. I'll add it to my omapdrm branch.
Thanks.
--
regards,
-grygorii
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/8] gpio: omap: cleanup: get rid of system GPIO - GPIO offset converseations
On 03/20/2015 01:00 AM, Tony Lindgren wrote: * grygorii.stras...@linaro.org grygorii.stras...@linaro.org [150319 10:26]: From: Grygorii Strashko grygorii.stras...@linaro.org Now in TI OMAP GPIO driver there are a lot of places where System GPIO number calculated and then converted to GPIO offset. What is worse is that in many place such conversation performed twice or even three times. But actually, we don't need to do that at all, because - gpiolib always passes GPIO offset to GPIO controller - OMAP GPIO driver converted to use IRQ domain, so struct irq_data-hwirq contains GPIO offset Hence, it is safe to convert all GPIO OMAP functions to use GPIO offset instead of system GPIO numbers. Also, this allows to remove unneeded conversations routines #define GPIO_INDEX(bank, gpio) #define GPIO_BIT(bank, gpio) int omap_irq_to_gpio() Right on! This is excellent news. I've tested this set on top of -rc4 plus the patch mentioned below, and I'm not seeing regressions on the platforms I tested with. Wake up to smsc911x ping with off-idle still works on omap3. I only briefly tested on omap1 (osk5912), so I'like to wait for Aaro's ack before this gets merged. I found one build error, other than that, for the whole series please feel free to add: Tested-by: Tony Lindgren t...@atomide.com Thanks Tony. Yep. I'll wait for news from Aaro then will re-send if ok. -- regards, -grygorii -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: am335x: GPMC: reading speed with prefetch mode
* Roger Quadros rog...@ti.com [150320 07:59]: On 20/03/15 15:37, Yegor Yefremov wrote: Btw. where DMA support should be configured? GPMC config has no dmas like other components like mmc, uart, USB etc. I've never tested dma on omap-nand in mainline. We've been solely relying on prefetch-polled mode there. someone needs to work on it and test dma support. looks like the driver is hardcoding the DMA channel sig = OMAP24XX_DMA_GPMC; info-dma = dma_request_channel(mask, omap_dma_filter_fn, sig); this will have to be fixed. I'm not sure what else is missing on DMA side. But you could try to use a free channel and see if it works? Tony any insights? There are six external DMA request pins on omaps that can be used for devices on GPMC for DMA. These are the sys_ndmareq0 to 5. So far the only the old tusb6010 driver is the only one using that, and it's still not using the DMA engine API. I've been meaning to update it, but have not had a chance yet.. Anyways, all the new DMA code should use the dmaengine API instead of the omap legacy DMA calls. Note that the onenand driver is wrongly using the external gpio request pin as a GPIO. That's not what the pin is supposed to do, it needs to be muxed to the external gpio request mode. So I suggest we either rip out the DMA code from onenand, or update it to use the sys_ndmareq and DMA engine API. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [alsa-devel] Patches to bind the SGTL5000 chip to AM33XX McASP
Hi Peter, On 03/20/2015 10:05 AM, Peter Ujfalusi wrote: On 03/19/2015 08:06 PM, Nikolay Dimitrov wrote: Slight clarification here - I can't find any such reference in the SGTL5000 datasheet where it's explicitly written that the I2C bus *requires* the MCLK running. Unfortunately, all of us found this obscure dependency empirically. It is not spelled out as such, but in: http://cache.freescale.com/files/analog/doc/data_sheet/SGTL5000.pdf?pspll=1 bottom of page9 (note 1) and the power up sequence in page10. See also page13, RESET section. If you change audio controls while you don't have audio activity, you will still need to have the MCLK running. Correct. And this is a big issue. As far as I know, the kernel drivers control separately the clock domains, and separately i2c devices, so the basic expectation on the kernel side is that there's no connection between these 2. In this specific case, because of the SGTL5000's implementation, there's a dependency. Right now as I see it, there are several ways to resolve it: 1. Run the reference clock all the time, so the SGTL5000 codec is happy, and DAPM widgets can work as-is. We've been doing this all the time - the reference clocks are routinely configured either in the bootloader, or in the DTS iomuxc node. While this can work in some cases (or until someone touches the same clock or one of its parents :D), there are other cases (like battery-powered devices) where people would want more aggressive power management, which means controlling the reference clock at runtime (see #2). Note the the codec driver will enable the clock and will not let it to be turned off. You need to work on the codec driver to sort this out. 2. Add hacks in the DAPM widgets that add control to the codec's reference clocks. While this seems the preferred route to many, the general feeling is that such approach is not very welcome in upstream. SND_SOC_DAPM_CLOCK_SUPPLY() 3. Add explicit support in the kernel's audio subsystem for dependencies between i2c devices and clocks, maybe via DAPM clock widget or something like this. Provided that the DAPM graphs are defined properly, this will work out-of-the-box for all use cases, without the hacks (until we see even more twisted cases). This can be handled within the codec driver with some changes. If you have external clock which can be enabled/diabled with a GPIO, then you can use that. We already have binding for this type of external clocks (in linux-next): look for gpio-gate-clock You define your external GPIO controlled clock with this binding and use the phandle in the codec driver. Change the codec driver to enable/disable the clock when needed. When you do not have audio activity, set the regmap to cache only so any change in the controls will not reach the HW. When you power up next time the regmap will sync the changes to the chip, so you will have the changes commited. Thanks a lot for your detailed explanation! Kind regards, Nikolay -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 2/6] wl12xx: use frequency instead of enumerations for pdata clocks
* Kalle Valo kv...@codeaurora.org [150320 07:01]: Tony Lindgren t...@atomide.com writes: I prefer these going through the omap tree. Like Eliad said, drivers/net/wireless/ti does not get that many changes nowadays so the chances of this patchset conflicting with something is very small. OK great. In that case no need to rearrange the patches, I can apply them into an immutable branch once the pending issues have been fixed if Kalle acks them. To avoid merge conflicts that branch is easiest done against v4.0-rc4. Kalle and Arnd, does that work for you guys? I can also base it on 5b7610f23562 (ARM: OMAP2+: Fix wl12xx on dm3730-evm with mainline u-boot) that's on top of -rc2 plus few other fixes now merged to -rc4 mainline if we need a branch based on an earlier tag. Sorry, it seems I forgot to answer this one: Either baseline is good for me, I can't think of any problems with either one. But please do remember that I'm a new maintainer, I might very well miss something ;) OK, I'll base it on -rc4 unless Arnd needs something earlier. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] omapdss: extend pm notifier to handle hibernation
On 20/03/15 16:57, grygorii.stras...@linaro.org wrote:
Hi Tomi,
On 03/20/2015 02:20 PM, Tomi Valkeinen wrote:
On 25/02/15 19:03, grygorii.stras...@linaro.org wrote:
From: Grygorii Strashko grygorii.stras...@linaro.org
Add handling of missed events in omap_dss_pm_notif which are
needed to support hibernation (suspend to disk).
Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org
---
drivers/video/fbdev/omap2/dss/core.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/video/fbdev/omap2/dss/core.c
b/drivers/video/fbdev/omap2/dss/core.c
index 6b74f73..e60976a 100644
--- a/drivers/video/fbdev/omap2/dss/core.c
+++ b/drivers/video/fbdev/omap2/dss/core.c
@@ -178,11 +178,15 @@ static int omap_dss_pm_notif(struct notifier_block
*b, unsigned long v, void *d)
DSSDBG(pm notif %lu\n, v);
switch (v) {
+ case PM_HIBERNATION_PREPARE:
case PM_SUSPEND_PREPARE:
+ case PM_RESTORE_PREPARE:
DSSDBG(suspending displays\n);
return dss_suspend_all_devices();
case PM_POST_SUSPEND:
+ case PM_POST_HIBERNATION:
+ case PM_POST_RESTORE:
DSSDBG(resuming displays\n);
return dss_resume_all_devices();
Why suspend displays when PM_RESTORE_PREPARE happens? Why resume when
PM_POST_RESTORE happens?
We have following sequence when system is restored from hibernation:
- original kernel booted;
- late_initcall_sync(software_resume);
- pm_notifier_call_chain(PM_RESTORE_PREPARE);
- freeze_processes
- check read hibernation image
- suspend all devices (.freeze())
- jump to stored kernel
- restore devices
...
So, all devices should be in frozen/suspended state when we will jump to
stored kernel
(device's state should be the same as before creating hib image).
Without this patch I can see a lot of log messages like below:
Yes, I am sure a fix is needed for hibernation. But I still don't quite
understand PM_RESTORE_PREPARE and PM_POST_RESTORE.
When we enter hibernation, there's only PM_HIBERNATION_PREPARE?
When waking from hibernation, there's first PM_RESTORE_PREPARE, where we
need to disable displays that were enabled during boot. Then either
PM_POST_HIBERNATION if all went well, or PM_POST_RESTORE if there was an
error, and in both cases we want to enable the displays?
Tomi
signature.asc
Description: OpenPGP digital signature
[PATCH] ARM: OMAP2: HSMMC: explicit fields to declare cover/card detect pin
board-rx51 has no card detect pin in the mmc slot, but can detect that
the (cell-phone) cover has been removed and the card is accessible.
The semantics between cover/card detect differ, the gpio on the slot
informs you after the card has been removed, cover removal does not
necessarily mean that the card has been removed.
This means different code paths are necessary. To complete this we
also want different fields in the platform data for cover and card
detect. This separation is not pushed all the way down into struct
omap2_hsmmc_info which is used to initialize the platform data.
If we did that we had to go over all board files and set the new
gpio_cod pin to -EINVAL. If we forget one board or some out-of-tree
archicture forgets that the default '0' is used which is a valid pin
number.
Signed-off-by: Andreas Fenkart afenk...@gmail.com
---
arch/arm/mach-omap2/hsmmc.c | 33
drivers/mmc/host/omap_hsmmc.c| 11 ++-
include/linux/platform_data/hsmmc-omap.h | 6 ++
3 files changed, 33 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index dc6e79c..9a8611a 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -150,9 +150,13 @@ static int nop_mmc_set_power(struct device *dev, int
power_on, int vdd)
static inline void omap_hsmmc_mux(struct omap_hsmmc_platform_data
*mmc_controller, int controller_nr)
{
- if (gpio_is_valid(mmc_controller-switch_pin)
- (mmc_controller-switch_pin OMAP_MAX_GPIO_LINES))
- omap_mux_init_gpio(mmc_controller-switch_pin,
+ if (gpio_is_valid(mmc_controller-gpio_cd)
+ (mmc_controller-gpio_cd OMAP_MAX_GPIO_LINES))
+ omap_mux_init_gpio(mmc_controller-gpio_cd,
+ OMAP_PIN_INPUT_PULLUP);
+ if (gpio_is_valid(mmc_controller-gpio_cod)
+ (mmc_controller-gpio_cod OMAP_MAX_GPIO_LINES))
+ omap_mux_init_gpio(mmc_controller-gpio_cod,
OMAP_PIN_INPUT_PULLUP);
if (gpio_is_valid(mmc_controller-gpio_wp)
(mmc_controller-gpio_wp OMAP_MAX_GPIO_LINES))
@@ -250,15 +254,20 @@ static int __init omap_hsmmc_pdata_init(struct
omap2_hsmmc_info *c,
mmc-internal_clock = !c-ext_clock;
mmc-reg_offset = 0;
- mmc-switch_pin = c-gpio_cd;
+ if (c-cover_only) {
+ /* detect if mobile phone cover removed */
+ mmc-gpio_cd = -EINVAL;
+ mmc-gpio_cod = c-gpio_cd;
+ } else {
+ /* card detect pin on the mmc socket itself */
+ mmc-gpio_cd = c-gpio_cd;
+ mmc-gpio_cod = -EINVAL;
+ }
mmc-gpio_wp = c-gpio_wp;
mmc-remux = c-remux;
mmc-init_card = c-init_card;
- if (c-cover_only)
- mmc-cover = 1;
-
if (c-nonremovable)
mmc-nonremovable = 1;
@@ -358,7 +367,15 @@ void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
if (!mmc_pdata)
continue;
- mmc_pdata-switch_pin = c-gpio_cd;
+ if (c-cover_only) {
+ /* detect if mobile phone cover removed */
+ mmc_pdata-gpio_cd = -EINVAL;
+ mmc_pdata-gpio_cod = c-gpio_cd;
+ } else {
+ /* card detect pin on the mmc socket itself */
+ mmc_pdata-gpio_cd = c-gpio_cd;
+ mmc_pdata-gpio_cod = -EINVAL;
+ }
mmc_pdata-gpio_wp = c-gpio_wp;
res = omap_device_register(pdev);
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 053cd38..265391f 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -427,15 +427,15 @@ static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
{
int ret;
- if (pdata-cover gpio_is_valid(pdata-switch_pin)) {
- ret = mmc_gpio_request_cd(mmc, pdata-switch_pin, 0);
+ if (gpio_is_valid(pdata-gpio_cod)) {
+ ret = mmc_gpio_request_cd(mmc, pdata-gpio_cod, 0);
if (ret)
return ret;
host-get_cover_state = omap_hsmmc_get_cover_state;
mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
- } else if (!pdata-cover gpio_is_valid(pdata-switch_pin)) {
- ret = mmc_gpio_request_cd(mmc, pdata-switch_pin, 0);
+ } else if (gpio_is_valid(pdata-gpio_cd)) {
+ ret = mmc_gpio_request_cd(mmc, pdata-gpio_cd, 0);
if (ret)
return ret;
@@ -1932,7 +1932,8 @@ static struct omap_hsmmc_platform_data
*of_get_hsmmc_pdata(struct device *dev)
if (of_find_property(np, ti,dual-volt, NULL))
pdata-controller_flags |=
Re: [PATCH 5/8] gpio: omap: convert gpio irq functions to use GPIO offset
On 03/20/2015 01:03 AM, Tony Lindgren wrote:
* grygorii.stras...@linaro.org grygorii.stras...@linaro.org [150319 10:26]:
From: Grygorii Strashko grygorii.stras...@linaro.org
Convert GPIO IRQ functions to use GPIO offset instead of system
GPIO numbers. This allows to drop unneeded conversations between
system GPIO - GPIO offset which are done in many places and
many times.
It is safe to do now because:
- gpiolib always passes GPIO offset to GPIO controller
- OMAP GPIO driver converted to use IRQ domain, so
struct irq_data-hwirq contains GPIO offset
This is preparation step before removing:
#define GPIO_INDEX(bank, gpio)
#define GPIO_BIT(bank, gpio)
int omap_irq_to_gpio()
...
static void omap_gpio_unmask_irq(struct irq_data *d)
{
struct gpio_bank *bank = omap_irq_data_get_bank(d);
- unsigned int gpio = omap_irq_to_gpio(bank, d-hwirq);
+ unsigned offset = d-hwirq;
unsigned int irq_mask = GPIO_BIT(bank, gpio);
u32 trigger = irqd_get_trigger_type(d);
unsigned long flags;
This series up to this patch produces a build error that
would break git bisect:
drivers/gpio/gpio-omap.c: In function ‘omap_gpio_unmask_irq’:
drivers/gpio/gpio-omap.c:866:37: error: ‘gpio’ undeclared (first use in this
function)
unsigned int irq_mask = GPIO_BIT(bank, gpio);
Oh. Thanks for catching that :) - splitting/rebasing issue.
--
regards,
-grygorii
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
no opp match error
Hello, I get in boot of board the following error: omap_target: cpu0: no opp match for freq 90. I see that the failure is in function cpufreq-opp_find_freq_exact(). Does is mean that cpufreq fails and do nothing ? How can I fix this error ? Regards, Ran -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 5/6] ARM: dts: add wl12xx/wl18xx bindings
Tony Lindgren t...@atomide.com writes: * Kalle Valo kv...@codeaurora.org [150319 23:04]: Tony Lindgren t...@atomide.com writes: Tested OK (boot, scan, join, ping) on Pandaboard ES. thanks for testing it! Great. As suggested by Kalle, I'll apply all these into omap-for-v4.1/wl12xx branch and send a pull request for the arm-soc probably on Friday if no issues are found. Great, thank you. Just in case you want this: Acked-by: Kalle Valo kv...@codeaurora.org Thanks, I can push out a new branch omap-for-v4.1/wl12xx-v2 with your acks assuming you or somebody else have not merged the existing omap-for-v4.1/wl12xx branch yet into the wireless tree? In that case I can scrap omap-for-v4.1/wl12xx and then will reply with a commit that we can consider immutable that can be merged into various trees as needed in case of merge conflicts. But I'll wait for your confirmation first :) After John retired we actually have two set of trees now: mac80211 maintained by Johannes and wireless-drivers maintained by me. I haven't pulled anything from your tree and I'm 100% sure Johannes hasn't either. So green light from me. -- Kalle Valo -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 14/15] omap3isp: Add support for the Device Tree
Hi Laurent,
Thanks for the review.
On Tue, Mar 17, 2015 at 02:48:54AM +0200, Laurent Pinchart wrote:
Hi Sakari,
Thank you for the patch.
On Monday 16 March 2015 02:26:09 Sakari Ailus wrote:
Add the ISP device to omap3 DT include file and add support to the driver to
use it.
Also obtain information on the external entities and the ISP configuration
related to them through the Device Tree in addition to the platform data.
Signed-off-by: Sakari Ailus sakari.ai...@iki.fi
---
drivers/media/platform/omap3isp/isp.c | 209 ++--
drivers/media/platform/omap3isp/isp.h | 11 ++
drivers/media/platform/omap3isp/ispcsiphy.c |7 +
3 files changed, 215 insertions(+), 12 deletions(-)
diff --git a/drivers/media/platform/omap3isp/isp.c
b/drivers/media/platform/omap3isp/isp.c index 992e74c..0d6012a 100644
--- a/drivers/media/platform/omap3isp/isp.c
+++ b/drivers/media/platform/omap3isp/isp.c
@@ -64,6 +64,7 @@
#include media/v4l2-common.h
#include media/v4l2-device.h
+#include media/v4l2-of.h
#include isp.h
#include ispreg.h
@@ -1991,6 +1992,14 @@ static int isp_register_entities(struct isp_device
*isp) if (ret 0)
goto done;
+ /*
+* Device Tree --- the external of the sub-devices will be
What do you mean by the external of the sub-devices ?
This is probably a mind'o. I removed of the , and added the article to the
second sentence, so it becomes:
/*
* Device Tree --- the external sub-devices will be registered
* later. The same goes for the sub-device node registration.
*/
+* registered later. Same goes for the sub-device node
+* registration.
+*/
+ if (isp-dev-of_node)
+ return 0;
+
/* Register external entities */
for (isp_subdev = pdata ? pdata-subdevs : NULL;
isp_subdev isp_subdev-board_info; isp_subdev++) {
@@ -2016,8 +2025,10 @@ static int isp_register_entities(struct isp_device
*isp) ret = v4l2_device_register_subdev_nodes(isp-v4l2_dev);
done:
- if (ret 0)
+ if (ret 0) {
isp_unregister_entities(isp);
+ v4l2_async_notifier_unregister(isp-notifier);
+ }
return ret;
}
@@ -2232,6 +2243,7 @@ static int isp_remove(struct platform_device *pdev)
{
struct isp_device *isp = platform_get_drvdata(pdev);
+ v4l2_async_notifier_unregister(isp-notifier);
isp_unregister_entities(isp);
isp_cleanup_modules(isp);
isp_xclk_cleanup(isp);
@@ -2243,6 +2255,151 @@ static int isp_remove(struct platform_device *pdev)
return 0;
}
+enum isp_of_phy {
+ ISP_OF_PHY_PARALLEL = 0,
+ ISP_OF_PHY_CSIPHY1,
+ ISP_OF_PHY_CSIPHY2,
+};
+
+static int isp_of_parse_node(struct device *dev, struct device_node *node,
+struct isp_async_subdev *isd)
+{
+ struct isp_bus_cfg *buscfg = isd-bus;
+ struct v4l2_of_endpoint vep;
+ unsigned int i;
+
+ v4l2_of_parse_endpoint(node, vep);
+
+ dev_dbg(dev, interface %u\n, vep.base.port);
The message seems a bit terse to me, I would also print the endpoint node
name
to give a bit of context.
dev_dbg(dev, parsing endpoint %s, interface %u\n, node-full_name,
vep.base.port);
I'll use this as-is.
+
+ switch (vep.base.port) {
+ case ISP_OF_PHY_PARALLEL:
+ buscfg-interface = ISP_INTERFACE_PARALLEL;
+ buscfg-bus.parallel.data_lane_shift =
+ vep.bus.parallel.data_shift;
+ buscfg-bus.parallel.clk_pol =
+ !!(vep.bus.parallel.flags
+ V4L2_MBUS_PCLK_SAMPLE_FALLING);
+ buscfg-bus.parallel.hs_pol =
+ !!(vep.bus.parallel.flags V4L2_MBUS_VSYNC_ACTIVE_LOW);
+ buscfg-bus.parallel.vs_pol =
+ !!(vep.bus.parallel.flags V4L2_MBUS_HSYNC_ACTIVE_LOW);
+ buscfg-bus.parallel.fld_pol =
+ !!(vep.bus.parallel.flags V4L2_MBUS_FIELD_EVEN_LOW);
+ buscfg-bus.parallel.data_pol =
+ !!(vep.bus.parallel.flags V4L2_MBUS_DATA_ACTIVE_LOW);
+ break;
+
+ case ISP_OF_PHY_CSIPHY1:
+ case ISP_OF_PHY_CSIPHY2:
+ /* FIXME: always assume CSI-2 for now. */
+ switch (vep.base.port) {
+ case ISP_OF_PHY_CSIPHY1:
I'd use an if - else here, but that's up to you.
I do prefer switch. I think it's easier to see that way what's done here.
+ buscfg-interface = ISP_INTERFACE_CSI2C_PHY1;
+ break;
+ case ISP_OF_PHY_CSIPHY2:
+ buscfg-interface = ISP_INTERFACE_CSI2A_PHY2;
+ break;
+ }
+ buscfg-bus.csi2.lanecfg.clk.pos = vep.bus.mipi_csi2.clock_lane;
+ buscfg-bus.csi2.lanecfg.clk.pol =
+
Re: [PATCH v7 5/6] ARM: dts: add wl12xx/wl18xx bindings
* Kalle Valo kv...@codeaurora.org [150319 23:04]: Tony Lindgren t...@atomide.com writes: Tested OK (boot, scan, join, ping) on Pandaboard ES. thanks for testing it! Great. As suggested by Kalle, I'll apply all these into omap-for-v4.1/wl12xx branch and send a pull request for the arm-soc probably on Friday if no issues are found. Great, thank you. Just in case you want this: Acked-by: Kalle Valo kv...@codeaurora.org Thanks, I can push out a new branch omap-for-v4.1/wl12xx-v2 with your acks assuming you or somebody else have not merged the existing omap-for-v4.1/wl12xx branch yet into the wireless tree? In that case I can scrap omap-for-v4.1/wl12xx and then will reply with a commit that we can consider immutable that can be merged into various trees as needed in case of merge conflicts. But I'll wait for your confirmation first :) Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/8] gpio: omap: simplify omap_set_gpio_dataout_x()
On Fri, Mar 20, 2015 at 5:45 PM, santosh.shilim...@oracle.com santosh.shilim...@oracle.com wrote: On 3/19/15 10:25 AM, grygorii.stras...@linaro.org wrote: From: Grygorii Strashko grygorii.stras...@linaro.org Both functions omap_set_gpio_dataout_reg() and omap_set_gpio_dataout_mask() accept GPIO offset as 'gpio' input parameter, so rename it to 'offset' and drop usage of GPIO_BIT() macro. Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org --- Acked-by: Santosh Shilimkar ssant...@kernel.org Acked-by: Javier Martinez Canillas jav...@dowhile0.org -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 18/35] ARM: OMAP2+: CM: move SoC specific init calls within a generic API
This gets rid of need for some exported driver APIs, and simplifies the
initialization of the CM driver. Done in preparation to make CM a
separate driver. The init data is now also passed to the SoC specific
implementations, allowing future expansion to add feature flags etc.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/cm2xxx.c |3 +-
arch/arm/mach-omap2/cm2xxx.h |2 +-
arch/arm/mach-omap2/cm33xx.c |3 +-
arch/arm/mach-omap2/cm33xx.h |3 +-
arch/arm/mach-omap2/cm3xxx.c |3 +-
arch/arm/mach-omap2/cm3xxx.h |2 +-
arch/arm/mach-omap2/cm44xx.h |2 +-
arch/arm/mach-omap2/cm_common.c | 64 --
arch/arm/mach-omap2/cminst44xx.c |3 +-
arch/arm/mach-omap2/io.c | 16 +++---
arch/arm/mach-omap2/prm_common.c |8 -
11 files changed, 75 insertions(+), 34 deletions(-)
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index f18c844..3e5fd35 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -393,9 +393,8 @@ static struct cm_ll_data omap2xxx_cm_ll_data = {
.wait_module_ready = omap2xxx_cm_wait_module_ready,
};
-int __init omap2xxx_cm_init(void)
+int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data)
{
- omap2_cm_base_init();
return cm_register(omap2xxx_cm_ll_data);
}
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 83b6c59..7b8c79c 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -63,7 +63,7 @@ extern u32 omap2xxx_cm_get_core_pll_config(void);
extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
u32 mdm);
-extern int __init omap2xxx_cm_init(void);
+int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data);
#endif
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 221bca3..7b181f9 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -352,9 +352,8 @@ static struct cm_ll_data am33xx_cm_ll_data = {
.module_disable = am33xx_cm_module_disable,
};
-int __init am33xx_cm_init(void)
+int __init am33xx_cm_init(const struct omap_prcm_init_data *data)
{
- omap2_cm_base_init();
return cm_register(am33xx_cm_ll_data);
}
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 046b4b2..a91f7d2 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -19,6 +19,7 @@
#include cm.h
#include cm-regbits-33xx.h
+#include prcm-common.h
/* CM base address */
#define AM33XX_CM_BASE 0x44e0
@@ -374,6 +375,6 @@
#ifndef __ASSEMBLER__
-int am33xx_cm_init(void);
+int am33xx_cm_init(const struct omap_prcm_init_data *data);
#endif /* ASSEMBLER */
#endif
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 88e6cb6..187fa43 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -671,10 +671,9 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
.wait_module_ready = omap3xxx_cm_wait_module_ready,
};
-int __init omap3xxx_cm_init(void)
+int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
{
omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD);
- omap2_cm_base_init();
return cm_register(omap3xxx_cm_ll_data);
}
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 734a858..bc444e2 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -72,7 +72,7 @@ extern void omap3_cm_save_context(void);
extern void omap3_cm_restore_context(void);
extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
-extern int __init omap3xxx_cm_init(void);
+int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data);
#endif
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index ad6e263..309a4c9 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -23,6 +23,6 @@
#define OMAP4_CM_CLKSTCTRL 0x
#define OMAP4_CM_STATICDEP 0x0004
-int omap4_cm_init(void);
+int omap4_cm_init(const struct omap_prcm_init_data *data);
#endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 32af8fc..ff24fdf 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -20,6 +20,7 @@
#include cm2xxx.h
#include cm3xxx.h
+#include cm33xx.h
#include cm44xx.h
#include clock.h
@@ -37,6 +38,7 @@ void __iomem *cm_base;
void __iomem *cm2_base;
#define CM_NO_CLOCKS 0x1
+#define CM_SINGLE_INSTANCE 0x2
/**
* omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
@@ -218,21 +220,32 @@ int cm_unregister(struct cm_ll_data *cld)
return 0;
}
-static struct
[PATCHv5 21/35] ARM: OMAP2+: clock: add low-level support for regmap
Some of the TI clock providers will be converted to use syscon, thus
low-level regmap support is needed for the clock drivers also. This
patch adds this support, which can be enabled for individual drivers
in later patches.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clock.c | 39 --
arch/arm/mach-omap2/clock.h |4 +++-
arch/arm/mach-omap2/cm_common.c |2 +-
arch/arm/mach-omap2/control.c|2 +-
arch/arm/mach-omap2/prm_common.c |2 +-
5 files changed, 39 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 3327128..d9885b8 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -23,6 +23,7 @@
#include linux/clk-provider.h
#include linux/io.h
#include linux/bitops.h
+#include linux/regmap.h
#include linux/of_address.h
#include asm/cpu.h
@@ -73,20 +74,37 @@ struct ti_clk_features ti_clk_features;
static bool clkdm_control = true;
static LIST_HEAD(clk_hw_omap_clocks);
-static void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
+
+struct clk_iomap {
+ struct regmap *regmap;
+ void __iomem *mem;
+};
+
+static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS];
static void clk_memmap_writel(u32 val, void __iomem *reg)
{
struct clk_omap_reg *r = (struct clk_omap_reg *)reg;
+ struct clk_iomap *io = clk_memmaps[r-index];
- writel_relaxed(val, clk_memmaps[r-index] + r-offset);
+ if (io-regmap)
+ regmap_write(io-regmap, r-offset, val);
+ else
+ writel_relaxed(val, io-mem + r-offset);
}
static u32 clk_memmap_readl(void __iomem *reg)
{
+ u32 val;
struct clk_omap_reg *r = (struct clk_omap_reg *)reg;
+ struct clk_iomap *io = clk_memmaps[r-index];
+
+ if (io-regmap)
+ regmap_read(io-regmap, r-offset, val);
+ else
+ val = readl_relaxed(io-mem + r-offset);
- return readl_relaxed(clk_memmaps[r-index] + r-offset);
+ return val;
}
void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
@@ -119,18 +137,27 @@ static struct ti_clk_ll_ops omap_clk_ll_ops = {
* @match_table: DT device table to match for devices to init
* @np: device node pointer for the this clock provider
* @index: index for the clock provider
- * @mem: iomem pointer for the clock provider memory area
+ + @syscon: syscon regmap pointer
+ * @mem: iomem pointer for the clock provider memory area, only used if
+ * syscon is not provided
*
* Initializes a clock provider module (CM/PRM etc.), registering
* the memory mapping at specified index and initializing the
* low level driver infrastructure. Returns 0 in success.
*/
int __init omap2_clk_provider_init(struct device_node *np, int index,
- void __iomem *mem)
+ struct regmap *syscon, void __iomem *mem)
{
+ struct clk_iomap *io;
+
ti_clk_ll_ops = omap_clk_ll_ops;
- clk_memmaps[index] = mem;
+ io = kzalloc(sizeof(*io), GFP_KERNEL);
+
+ io-regmap = syscon;
+ io-mem = mem;
+
+ clk_memmaps[index] = io;
ti_dt_clk_init_provider(np, index);
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b6433fc..652ed0a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -274,8 +274,10 @@ extern const struct clksel_rate div31_1to31_rates[];
extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
+struct regmap;
+
int __init omap2_clk_provider_init(struct device_node *np, int index,
- void __iomem *mem);
+ struct regmap *syscon, void __iomem *mem);
void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem);
void __init ti_clk_init_features(void);
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index ff24fdf..23e8bce 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -361,7 +361,7 @@ int __init omap_cm_init(void)
if (data-flags CM_NO_CLOCKS)
continue;
- ret = omap2_clk_provider_init(np, data-index, data-mem);
+ ret = omap2_clk_provider_init(np, data-index, NULL, data-mem);
if (ret)
return ret;
}
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 21ff32c..4b40946 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -676,7 +676,7 @@ int __init omap_control_init(void)
for_each_matching_node_and_match(np, omap_scrm_dt_match_table, match) {
data = match-data;
- ret = omap2_clk_provider_init(np, data-index, data-mem);
+ ret = omap2_clk_provider_init(np, data-index,
[PATCHv5 15/35] ARM: OMAP2+: control: determine control module base address from DT
There is no need to provide the control module base address through a
low-level API from the low-level IO init, as this information is
available through DT. This patch adds a new API to initialize the
control module though, but mostly makes the old API obsolete. The
old API can be completely removed once OMAP3 is made DT only.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/control.c| 49 +-
arch/arm/mach-omap2/control.h|2 ++
arch/arm/mach-omap2/io.c | 34 +-
arch/arm/mach-omap2/prm.h|1 -
arch/arm/mach-omap2/prm_common.c |5
5 files changed, 61 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index e881824..21ff32c 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -616,6 +616,7 @@ void __init omap3_ctrl_init(void)
struct control_init_data {
int index;
+ void __iomem *mem;
};
static struct control_init_data ctrl_data = {
@@ -627,10 +628,39 @@ static const struct of_device_id
omap_scrm_dt_match_table[] = {
{ .compatible = ti,am4-scrm, .data = ctrl_data },
{ .compatible = ti,omap2-scrm, .data = ctrl_data },
{ .compatible = ti,omap3-scrm, .data = ctrl_data },
+ { .compatible = ti,dm816-scrm, .data = ctrl_data },
{ }
};
/**
+ * omap2_control_base_init - initialize iomappings for the control driver
+ *
+ * Detects and initializes the iomappings for the control driver, based
+ * on the DT data. Returns 0 in success, negative error value
+ * otherwise.
+ */
+int __init omap2_control_base_init(void)
+{
+ struct device_node *np;
+ const struct of_device_id *match;
+ struct control_init_data *data;
+ void __iomem *mem;
+
+ for_each_matching_node_and_match(np, omap_scrm_dt_match_table, match) {
+ data = (struct control_init_data *)match-data;
+
+ mem = of_iomap(np, 0);
+ if (!mem)
+ return -ENOMEM;
+
+ omap2_ctrl_base = mem;
+ data-mem = mem;
+ }
+
+ return 0;
+}
+
+/**
* omap_control_init - low level init for the control driver
*
* Initializes the low level clock infrastructure for control driver.
@@ -639,7 +669,6 @@ static const struct of_device_id omap_scrm_dt_match_table[]
= {
int __init omap_control_init(void)
{
struct device_node *np;
- void __iomem *mem;
const struct of_device_id *match;
const struct omap_prcm_init_data *data;
int ret;
@@ -647,14 +676,22 @@ int __init omap_control_init(void)
for_each_matching_node_and_match(np, omap_scrm_dt_match_table, match) {
data = match-data;
- mem = of_iomap(np, 0);
- if (!mem)
- return -ENOMEM;
-
- ret = omap2_clk_provider_init(np, data-index, mem);
+ ret = omap2_clk_provider_init(np, data-index, data-mem);
if (ret)
return ret;
}
return 0;
}
+
+/**
+ * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
+ *
+ * Legacy iomap init for clock provider. Needed only by legacy boot mode,
+ * where the base addresses are not parsed from DT, but still required
+ * by the clock driver to be setup properly.
+ */
+void __init omap3_control_legacy_iomap_init(void)
+{
+ omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
+}
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index baf5783..c1057eb 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -464,9 +464,11 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
extern void omap3630_ctrl_disable_rta(void);
extern int omap3_ctrl_save_padconf(void);
void omap3_ctrl_init(void);
+int omap2_control_base_init(void);
int omap_control_init(void);
extern void omap2_set_globals_control(void __iomem *ctrl,
void __iomem *ctrl_pad);
+void __init omap3_control_legacy_iomap_init(void);
#else
#define omap_ctrl_base_get() 0
#define omap_ctrl_readb(x) 0
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 712dd42..622ee3b 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -384,8 +384,7 @@ void __init omap2420_init_early(void)
omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
- omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
- NULL);
+ omap2_control_base_init();
omap2xxx_check_revision();
omap2xxx_prm_init();
omap2xxx_cm_init();
@@ -412,8 +411,7 @@ void __init
[PATCHv5 17/35] ARM: OMAP4+: PRM: determine prm_device_inst based on DT compatibility
PRM device instance offset is now provided through the prm_init_data.
This gets rid of some cpu_is_X / soc_is_X calls from PRM core code,
preparing for PRM to be its own separate driver.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/prcm-common.h |2 ++
arch/arm/mach-omap2/prm44xx.c |2 ++
arch/arm/mach-omap2/prm_common.c | 37 -
arch/arm/mach-omap2/prminst44xx.c | 18 +-
arch/arm/mach-omap2/prminst44xx.h |1 +
5 files changed, 42 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-omap2/prcm-common.h
b/arch/arm/mach-omap2/prcm-common.h
index 461bdc4..6ae0b3a 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -524,6 +524,7 @@ struct omap_prcm_irq_setup {
* @mem: IO mem pointer for this module
* @offset: module base address offset from the IO base
* @flags: PRCM module init flags
+ * @device_inst_offset: device instance offset within the module address space
* @init: low level PRCM init function for this module
* @np: device node for this PRCM module
*/
@@ -532,6 +533,7 @@ struct omap_prcm_init_data {
void __iomem *mem;
s16 offset;
u16 flags;
+ s32 device_inst_offset;
int (*init)(const struct omap_prcm_init_data *data);
struct device_node *np;
};
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index e3f2d31..a980d245 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -713,6 +713,8 @@ int __init omap44xx_prm_init(const struct
omap_prcm_init_data *data)
if (!soc_is_dra7xx())
prm_features |= PRM_HAS_VOLTAGE;
+ omap4_prminst_set_prm_dev_inst(data-device_inst_offset);
+
return prm_register(omap44xx_prm_ll_data);
}
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 96002ef..71732b0 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -34,6 +34,9 @@
#include prm3xxx.h
#include prm33xx.h
#include prm44xx.h
+#include prm54xx.h
+#include prm7xx.h
+#include prcm43xx.h
#include common.h
#include clock.h
#include cm.h
@@ -661,11 +664,35 @@ static struct omap_prcm_init_data am3_prm_data __initdata
= {
};
#endif
-#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
- defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
+#ifdef CONFIG_ARCH_OMAP4
static struct omap_prcm_init_data omap4_prm_data __initdata = {
.index = TI_CLKM_PRM,
.init = omap44xx_prm_init,
+ .device_inst_offset = OMAP4430_PRM_DEVICE_INST,
+};
+#endif
+
+#ifdef CONFIG_SOC_OMAP5
+static struct omap_prcm_init_data omap5_prm_data __initdata = {
+ .index = TI_CLKM_PRM,
+ .init = omap44xx_prm_init,
+ .device_inst_offset = OMAP54XX_PRM_DEVICE_INST,
+};
+#endif
+
+#ifdef CONFIG_SOC_DRA7XX
+static struct omap_prcm_init_data dra7_prm_data __initdata = {
+ .index = TI_CLKM_PRM,
+ .init = omap44xx_prm_init,
+ .device_inst_offset = DRA7XX_PRM_DEVICE_INST,
+};
+#endif
+
+#ifdef CONFIG_SOC_AM43XX
+static struct omap_prcm_init_data am4_prm_data __initdata = {
+ .index = TI_CLKM_PRM,
+ .init = omap44xx_prm_init,
+ .device_inst_offset = AM43XX_PRM_DEVICE_INST,
};
#endif
@@ -678,7 +705,7 @@ static const struct of_device_id omap_prcm_dt_match_table[]
__initconst = {
{ .compatible = ti,am3-prcm, .data = am3_prm_data },
#endif
#ifdef CONFIG_SOC_AM43XX
- { .compatible = ti,am4-prcm, .data = omap4_prm_data },
+ { .compatible = ti,am4-prcm, .data = am4_prm_data },
#endif
#ifdef CONFIG_SOC_TI81XX
{ .compatible = ti,dm814-prcm, .data = am3_prm_data },
@@ -695,11 +722,11 @@ static const struct of_device_id
omap_prcm_dt_match_table[] __initconst = {
{ .compatible = ti,omap4-scrm, .data = scrm_data },
#endif
#ifdef CONFIG_SOC_OMAP5
- { .compatible = ti,omap5-prm, .data = omap4_prm_data },
+ { .compatible = ti,omap5-prm, .data = omap5_prm_data },
{ .compatible = ti,omap5-scrm, .data = scrm_data },
#endif
#ifdef CONFIG_SOC_DRA7XX
- { .compatible = ti,dra7-prm, .data = omap4_prm_data },
+ { .compatible = ti,dra7-prm, .data = dra7_prm_data },
#endif
{ }
};
diff --git a/arch/arm/mach-omap2/prminst44xx.c
b/arch/arm/mach-omap2/prminst44xx.c
index 8adf7b1..c4859c4 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -47,22 +47,14 @@ void omap_prm_base_init(void)
s32 omap4_prmst_get_prm_dev_inst(void)
{
- if (prm_dev_inst != PRM_INSTANCE_UNKNOWN)
- return prm_dev_inst;
-
- /* This cannot be done way early at boot.. as things are not setup */
- if (cpu_is_omap44xx())
- prm_dev_inst = OMAP4430_PRM_DEVICE_INST;
- else if (soc_is_omap54xx())
- prm_dev_inst = OMAP54XX_PRM_DEVICE_INST;
- else if (soc_is_dra7xx())
-
[PATCHv5 14/35] ARM: OMAP2+: PRM: determine PRM base address from device tree
There is no need to provide the PRM base address through a low-level API from the low-level IO init, as this information is available through DT. Re-routed the parsing function to be called from the PRM drivers also to simplify the implementation under io.c. Signed-off-by: Tero Kristo t-kri...@ti.com --- arch/arm/mach-omap2/io.c | 12 + arch/arm/mach-omap2/prm.h|1 + arch/arm/mach-omap2/prm2xxx.c|1 + arch/arm/mach-omap2/prm33xx.c|1 + arch/arm/mach-omap2/prm3xxx.c|5 arch/arm/mach-omap2/prm44xx.c|1 + arch/arm/mach-omap2/prm_common.c | 51 +++--- 7 files changed, 52 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index b43e09d..712dd42 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -386,7 +386,6 @@ void __init omap2420_init_early(void) OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), NULL); - omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE)); omap2xxx_check_revision(); omap2xxx_prm_init(); omap2xxx_cm_init(); @@ -415,7 +414,6 @@ void __init omap2430_init_early(void) OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), NULL); - omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE)); omap2xxx_check_revision(); omap2xxx_prm_init(); omap2xxx_cm_init(); @@ -448,9 +446,8 @@ void __init omap3_init_early(void) OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), NULL); + /* XXX: remove these two once OMAP3 is DT only */ omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); - - /* XXX: remove this once OMAP3 is DT only */ omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); omap3xxx_check_revision(); omap3xxx_check_features(); @@ -551,7 +548,6 @@ void __init ti814x_init_early(void) OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), NULL); - omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); omap3xxx_check_revision(); ti81xx_check_features(); am33xx_prm_init(); @@ -571,7 +567,6 @@ void __init ti816x_init_early(void) OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), NULL); - omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); omap3xxx_check_revision(); ti81xx_check_features(); am33xx_prm_init(); @@ -593,7 +588,6 @@ void __init am33xx_init_early(void) AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), NULL); - omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE)); omap3xxx_check_revision(); am33xx_check_features(); am33xx_prm_init(); @@ -618,7 +612,6 @@ void __init am43xx_init_early(void) AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), NULL); - omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE)); omap3xxx_check_revision(); am33xx_check_features(); omap44xx_prm_init(); @@ -644,7 +637,6 @@ void __init omap4430_init_early(void) OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE)); - omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE)); omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); omap4xxx_check_revision(); omap4xxx_check_features(); @@ -675,7 +667,6 @@ void __init omap5_init_early(void) OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE)); - omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); omap4_pm_init_early(); omap44xx_prm_init(); @@ -703,7 +694,6 @@ void __init dra7xx_init_early(void) omap2_set_globals_tap(-1,
[PATCHv5 19/35] ARM: OMAP4+: PRM: setup prm_features from the PRM init time flags
Currently some cpu_is_X checks are used to setup prm_features, however
the same can be accomplished by just passing these flags from the PRM
init data. This is done in preparation to make PRM a separate driver.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/prm44xx.c|4 ++--
arch/arm/mach-omap2/prm_common.c |3 +++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a980d245..243133c 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -707,10 +707,10 @@ int __init omap44xx_prm_init(const struct
omap_prcm_init_data *data)
{
omap_prm_base_init();
- if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
+ if (data-flags PRM_HAS_IO_WAKEUP)
prm_features |= PRM_HAS_IO_WAKEUP;
- if (!soc_is_dra7xx())
+ if (data-flags PRM_HAS_VOLTAGE)
prm_features |= PRM_HAS_VOLTAGE;
omap4_prminst_set_prm_dev_inst(data-device_inst_offset);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index b11b10d..ebb24ad 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -669,6 +669,7 @@ static struct omap_prcm_init_data omap4_prm_data __initdata
= {
.index = TI_CLKM_PRM,
.init = omap44xx_prm_init,
.device_inst_offset = OMAP4430_PRM_DEVICE_INST,
+ .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE,
};
#endif
@@ -677,6 +678,7 @@ static struct omap_prcm_init_data omap5_prm_data __initdata
= {
.index = TI_CLKM_PRM,
.init = omap44xx_prm_init,
.device_inst_offset = OMAP54XX_PRM_DEVICE_INST,
+ .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE,
};
#endif
@@ -685,6 +687,7 @@ static struct omap_prcm_init_data dra7_prm_data __initdata
= {
.index = TI_CLKM_PRM,
.init = omap44xx_prm_init,
.device_inst_offset = DRA7XX_PRM_DEVICE_INST,
+ .flags = PRM_HAS_IO_WAKEUP,
};
#endif
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 16/35] ARM: OMAP2+: PRM: move SoC specific init calls within a generic API
This gets rid of need for some exported driver APIs, and simplifies the initialization of the PRM driver. Done in preparation to make PRM a separate driver. The init data is now also passed to the SoC specific implementations, allowing future expansion to add feature flags etc. Signed-off-by: Tero Kristo t-kri...@ti.com --- arch/arm/mach-omap2/io.c | 21 ++- arch/arm/mach-omap2/prcm-common.h |4 ++ arch/arm/mach-omap2/prm.h |1 + arch/arm/mach-omap2/prm2xxx.c |3 +- arch/arm/mach-omap2/prm2xxx.h |2 +- arch/arm/mach-omap2/prm33xx.c |3 +- arch/arm/mach-omap2/prm33xx.h |2 +- arch/arm/mach-omap2/prm3xxx.c |4 +- arch/arm/mach-omap2/prm3xxx.h |2 +- arch/arm/mach-omap2/prm44xx.c |3 +- arch/arm/mach-omap2/prm44xx.h |1 - arch/arm/mach-omap2/prm44xx_54xx.h |4 +- arch/arm/mach-omap2/prm54xx.h |1 - arch/arm/mach-omap2/prm7xx.h |2 +- arch/arm/mach-omap2/prm_common.c | 72 ++-- 15 files changed, 87 insertions(+), 38 deletions(-) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 622ee3b..7632dfe 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -386,7 +386,7 @@ void __init omap2420_init_early(void) OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); omap2_control_base_init(); omap2xxx_check_revision(); - omap2xxx_prm_init(); + omap2_prcm_base_init(); omap2xxx_cm_init(); omap2xxx_voltagedomains_init(); omap242x_powerdomains_init(); @@ -413,7 +413,7 @@ void __init omap2430_init_early(void) OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); omap2_control_base_init(); omap2xxx_check_revision(); - omap2xxx_prm_init(); + omap2_prcm_base_init(); omap2xxx_cm_init(); omap2xxx_voltagedomains_init(); omap243x_powerdomains_init(); @@ -453,7 +453,8 @@ void __init omap3_init_early(void) omap2_control_base_init(); omap3xxx_check_revision(); omap3xxx_check_features(); - omap3xxx_prm_init(); + omap2_prcm_base_init(); + omap3xxx_prm_init(NULL); omap3xxx_cm_init(); omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); @@ -551,7 +552,7 @@ void __init ti814x_init_early(void) omap2_control_base_init(); omap3xxx_check_revision(); ti81xx_check_features(); - am33xx_prm_init(); + omap2_prcm_base_init(); am33xx_cm_init(); omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); @@ -569,7 +570,7 @@ void __init ti816x_init_early(void) omap2_control_base_init(); omap3xxx_check_revision(); ti81xx_check_features(); - am33xx_prm_init(); + omap2_prcm_base_init(); am33xx_cm_init(); omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); @@ -589,7 +590,7 @@ void __init am33xx_init_early(void) omap2_control_base_init(); omap3xxx_check_revision(); am33xx_check_features(); - am33xx_prm_init(); + omap2_prcm_base_init(); am33xx_cm_init(); am33xx_powerdomains_init(); am33xx_clockdomains_init(); @@ -612,7 +613,7 @@ void __init am43xx_init_early(void) omap2_control_base_init(); omap3xxx_check_revision(); am33xx_check_features(); - omap44xx_prm_init(); + omap2_prcm_base_init(); omap4_cm_init(); am43xx_powerdomains_init(); am43xx_clockdomains_init(); @@ -638,7 +639,7 @@ void __init omap4430_init_early(void) omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); omap4xxx_check_revision(); omap4xxx_check_features(); - omap44xx_prm_init(); + omap2_prcm_base_init(); omap4_cm_init(); omap4_pm_init_early(); omap44xx_voltagedomains_init(); @@ -667,7 +668,7 @@ void __init omap5_init_early(void) OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE)); omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); omap4_pm_init_early(); - omap44xx_prm_init(); + omap2_prcm_base_init(); omap5xxx_check_revision(); omap4_cm_init(); omap54xx_voltagedomains_init(); @@ -694,7 +695,7 @@ void __init dra7xx_init_early(void) OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE)); omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); omap4_pm_init_early(); - omap44xx_prm_init(); + omap2_prcm_base_init(); dra7xxx_check_revision(); omap4_cm_init(); dra7xx_powerdomains_init(); diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 9e4dd0b..461bdc4 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++
[PATCHv5 03/35] ARM: OMAP3: PRM: invert the wkst_mask for the prm_clear_mod_irqs
This makes the API the same as used with OMAP2, and makes it possible
to implement a generic driver API for the functionality.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/pm34xx.c | 18 +-
arch/arm/mach-omap2/prm3xxx.c |8
arch/arm/mach-omap2/prm3xxx.h |2 +-
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 88721df..2581329 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -137,9 +137,8 @@ static irqreturn_t _prcm_int_handle_io(int irq, void
*unused)
{
int c;
- c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
- ~(OMAP3430_ST_IO_MASK |
- OMAP3430_ST_IO_CHAIN_MASK));
+ c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
+ OMAP3430_ST_IO_CHAIN_MASK);
return c ? IRQ_HANDLED : IRQ_NONE;
}
@@ -154,13 +153,14 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void
*unused)
* IO events before parsing in mux code
*/
c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
- OMAP3430_ST_IO_MASK |
- OMAP3430_ST_IO_CHAIN_MASK);
- c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0);
- c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
+ ~(OMAP3430_ST_IO_MASK |
+ OMAP3430_ST_IO_CHAIN_MASK));
+ c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
+ c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
if (omap_rev() OMAP3430_REV_ES1_0) {
- c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0);
- c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
+ c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
+ c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1,
+~0);
}
return c ? IRQ_HANDLED : IRQ_NONE;
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 5713bbd..4cc72e8 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -217,7 +217,7 @@ static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
* omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
* @module: PRM module to clear wakeups from
* @regs: register set to clear, 1 or 3
- * @ignore_bits: wakeup status bits to ignore
+ * @wkst_mask: wkst bits to clear
*
* The purpose of this function is to clear any wake-up events latched
* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
@@ -226,7 +226,7 @@ static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
* that any peripheral wake-up events occurring while attempting to
* clear the PM_WKST_x are detected and cleared.
*/
-int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
+int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
{
u32 wkst, fclk, iclk, clken;
u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
@@ -238,7 +238,7 @@ int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32
ignore_bits)
wkst = omap2_prm_read_mod_reg(module, wkst_off);
wkst = omap2_prm_read_mod_reg(module, grpsel_off);
- wkst = ~ignore_bits;
+ wkst = wkst_mask;
if (wkst) {
iclk = omap2_cm_read_mod_reg(module, iclk_off);
fclk = omap2_cm_read_mod_reg(module, fclk_off);
@@ -254,7 +254,7 @@ int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32
ignore_bits)
omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
omap2_prm_write_mod_reg(wkst, module, wkst_off);
wkst = omap2_prm_read_mod_reg(module, wkst_off);
- wkst = ~ignore_bits;
+ wkst = wkst_mask;
c++;
}
omap2_cm_write_mod_reg(iclk, module, iclk_off);
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index ed8a3d8..856f3c5 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -145,7 +145,7 @@ extern void omap3_prm_vcvp_write(u32 val, u8 offset);
extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
extern int __init omap3xxx_prm_init(void);
-int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
+int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
void omap3xxx_prm_iva_idle(void);
void omap3_prm_reset_modem(void);
int omap3xxx_prm_clear_global_cold_reset(void);
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at
[PATCHv5 13/35] ARM: OMAP2+: CM: determine CM base address from device tree
There is no need to provide the CM base address through a low-level API
from the low-level IO init, as this information is available through DT.
Re-routed the parsing function to be called from the CM drivers also to
simplify the implementation under io.c.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/cm.h |1 +
arch/arm/mach-omap2/cm2xxx.c |1 +
arch/arm/mach-omap2/cm33xx.c |1 +
arch/arm/mach-omap2/cm3xxx.c |2 +
arch/arm/mach-omap2/cm_common.c | 73 ++---
arch/arm/mach-omap2/cminst44xx.c |1 +
arch/arm/mach-omap2/io.c | 14 +--
arch/arm/mach-omap2/prcm-common.h |6 +++
arch/arm/mach-omap2/prm_common.c |1 -
9 files changed, 81 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 748ac33..1fe3e6b 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -71,6 +71,7 @@ int omap_cm_module_disable(u8 part, u16 inst, u16
clkctrl_offs);
extern int cm_register(struct cm_ll_data *cld);
extern int cm_unregister(struct cm_ll_data *cld);
int omap_cm_init(void);
+int omap2_cm_base_init(void);
# endif
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index ef62ac9..f18c844 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -395,6 +395,7 @@ static struct cm_ll_data omap2xxx_cm_ll_data = {
int __init omap2xxx_cm_init(void)
{
+ omap2_cm_base_init();
return cm_register(omap2xxx_cm_ll_data);
}
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index cc5aac7..221bca3 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -354,6 +354,7 @@ static struct cm_ll_data am33xx_cm_ll_data = {
int __init am33xx_cm_init(void)
{
+ omap2_cm_base_init();
return cm_register(am33xx_cm_ll_data);
}
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index ebead8f..88e6cb6 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -673,6 +673,8 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
int __init omap3xxx_cm_init(void)
{
+ omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD);
+ omap2_cm_base_init();
return cm_register(omap3xxx_cm_ll_data);
}
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index f3d578b..32af8fc 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -36,6 +36,8 @@ void __iomem *cm_base;
/* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
void __iomem *cm2_base;
+#define CM_NO_CLOCKS 0x1
+
/**
* omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
* @cm: CM base virtual address
@@ -224,18 +226,79 @@ static struct omap_prcm_init_data cm2_data = {
.index = TI_CLKM_CM2,
};
+static struct omap_prcm_init_data omap2_prcm_data = {
+ .index = TI_CLKM_CM,
+ .flags = CM_NO_CLOCKS,
+};
+
+static struct omap_prcm_init_data omap3_cm_data = {
+ .index = TI_CLKM_CM,
+
+ /*
+* IVA2 offset is a negative value, must offset the cm_base address
+* by this to get it to positive side on the iomap
+*/
+ .offset = -OMAP3430_IVA2_MOD,
+};
+
+static struct omap_prcm_init_data am3_prcm_data = {
+ .index = TI_CLKM_CM,
+ .flags = CM_NO_CLOCKS,
+};
+
+static struct omap_prcm_init_data am4_prcm_data = {
+ .index = TI_CLKM_CM,
+ .flags = CM_NO_CLOCKS,
+};
+
static const struct of_device_id omap_cm_dt_match_table[] = {
- { .compatible = ti,omap3-cm, .data = cm_data },
+ { .compatible = ti,omap2-prcm, .data = omap2_prcm_data },
+ { .compatible = ti,omap3-cm, .data = omap3_cm_data },
{ .compatible = ti,omap4-cm1, .data = cm_data },
{ .compatible = ti,omap4-cm2, .data = cm2_data },
{ .compatible = ti,omap5-cm-core-aon, .data = cm_data },
{ .compatible = ti,omap5-cm-core, .data = cm2_data },
{ .compatible = ti,dra7-cm-core-aon, .data = cm_data },
{ .compatible = ti,dra7-cm-core, .data = cm2_data },
+ { .compatible = ti,am3-prcm, .data = am3_prcm_data },
+ { .compatible = ti,am4-prcm, .data = am4_prcm_data },
{ }
};
/**
+ * omap2_cm_base_init - initialize iomappings for the CM drivers
+ *
+ * Detects and initializes the iomappings for the CM driver, based
+ * on the DT data. Returns 0 in success, negative error value
+ * otherwise.
+ */
+int __init omap2_cm_base_init(void)
+{
+ struct device_node *np;
+ const struct of_device_id *match;
+ struct omap_prcm_init_data *data;
+ void __iomem *mem;
+
+ for_each_matching_node_and_match(np, omap_cm_dt_match_table, match) {
+ data = (struct omap_prcm_init_data *)match-data;
+
+ mem = of_iomap(np, 0);
+ if (!mem)
+
[PATCHv5 12/35] ARM: OMAP2+: PRCM: split PRCM module init to their own driver files
Splits the clock related provider module inits under their own driver files.
Previously this was done for all modules under the common PRM driver.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/cm.h |1 +
arch/arm/mach-omap2/cm_common.c | 51 ++
arch/arm/mach-omap2/control.c| 47 +++
arch/arm/mach-omap2/control.h|1 +
arch/arm/mach-omap2/io.c |4 +++
arch/arm/mach-omap2/prm_common.c | 23 ++---
include/linux/clk/ti.h |5 ++--
7 files changed, 108 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 6222e87..748ac33 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -70,6 +70,7 @@ int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16
clkctrl_offs);
int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
extern int cm_register(struct cm_ll_data *cld);
extern int cm_unregister(struct cm_ll_data *cld);
+int omap_cm_init(void);
# endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 8fe02fce..f3d578b 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -15,10 +15,13 @@
#include linux/init.h
#include linux/errno.h
#include linux/bug.h
+#include linux/of.h
+#include linux/of_address.h
#include cm2xxx.h
#include cm3xxx.h
#include cm44xx.h
+#include clock.h
/*
* cm_ll_data: function pointers to SoC-specific implementations of
@@ -212,3 +215,51 @@ int cm_unregister(struct cm_ll_data *cld)
return 0;
}
+
+static struct omap_prcm_init_data cm_data = {
+ .index = TI_CLKM_CM,
+};
+
+static struct omap_prcm_init_data cm2_data = {
+ .index = TI_CLKM_CM2,
+};
+
+static const struct of_device_id omap_cm_dt_match_table[] = {
+ { .compatible = ti,omap3-cm, .data = cm_data },
+ { .compatible = ti,omap4-cm1, .data = cm_data },
+ { .compatible = ti,omap4-cm2, .data = cm2_data },
+ { .compatible = ti,omap5-cm-core-aon, .data = cm_data },
+ { .compatible = ti,omap5-cm-core, .data = cm2_data },
+ { .compatible = ti,dra7-cm-core-aon, .data = cm_data },
+ { .compatible = ti,dra7-cm-core, .data = cm2_data },
+ { }
+};
+
+/**
+ * omap_cm_init - low level init for the CM drivers
+ *
+ * Initializes the low level clock infrastructure for CM drivers.
+ * Returns 0 in success, negative error value in failure.
+ */
+int __init omap_cm_init(void)
+{
+ struct device_node *np;
+ void __iomem *mem;
+ const struct of_device_id *match;
+ const struct omap_prcm_init_data *data;
+ int ret;
+
+ for_each_matching_node_and_match(np, omap_cm_dt_match_table, match) {
+ data = match-data;
+
+ mem = of_iomap(np, 0);
+ if (!mem)
+ return -ENOMEM;
+
+ ret = omap2_clk_provider_init(np, data-index, mem);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index da041b4..e881824 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -14,6 +14,7 @@
#include linux/kernel.h
#include linux/io.h
+#include linux/of_address.h
#include soc.h
#include iomap.h
@@ -25,6 +26,7 @@
#include sdrc.h
#include pm.h
#include control.h
+#include clock.h
/* Used by omap3_ctrl_save_padconf() */
#define START_PADCONF_SAVE 0x2
@@ -611,3 +613,48 @@ void __init omap3_ctrl_init(void)
omap3_ctrl_setup_d2d_padconf();
}
#endif /* CONFIG_ARCH_OMAP3 CONFIG_PM */
+
+struct control_init_data {
+ int index;
+};
+
+static struct control_init_data ctrl_data = {
+ .index = TI_CLKM_CTRL,
+};
+
+static const struct of_device_id omap_scrm_dt_match_table[] = {
+ { .compatible = ti,am3-scrm, .data = ctrl_data },
+ { .compatible = ti,am4-scrm, .data = ctrl_data },
+ { .compatible = ti,omap2-scrm, .data = ctrl_data },
+ { .compatible = ti,omap3-scrm, .data = ctrl_data },
+ { }
+};
+
+/**
+ * omap_control_init - low level init for the control driver
+ *
+ * Initializes the low level clock infrastructure for control driver.
+ * Returns 0 in success, negative error value in failure.
+ */
+int __init omap_control_init(void)
+{
+ struct device_node *np;
+ void __iomem *mem;
+ const struct of_device_id *match;
+ const struct omap_prcm_init_data *data;
+ int ret;
+
+ for_each_matching_node_and_match(np, omap_scrm_dt_match_table, match) {
+ data = match-data;
+
+ mem = of_iomap(np, 0);
+ if (!mem)
+ return -ENOMEM;
+
+ ret = omap2_clk_provider_init(np, data-index, mem);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff
[PATCHv5 06/35] ARM: OMAP4+: PRM: move omap_prm_base_init under OMAP4 PRM driver
There is no need to call this separately from io.c, rather this can be
done commonly under the PRM driver.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/io.c |4
arch/arm/mach-omap2/prm44xx.c |2 ++
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index f504f71..5569c2f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -623,7 +623,6 @@ void __init am43xx_init_early(void)
NULL);
omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
- omap_prm_base_init();
omap_cm_base_init();
omap3xxx_check_revision();
am33xx_check_features();
@@ -654,7 +653,6 @@ void __init omap4430_init_early(void)
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
- omap_prm_base_init();
omap_cm_base_init();
omap4xxx_check_revision();
omap4xxx_check_features();
@@ -690,7 +688,6 @@ void __init omap5_init_early(void)
OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap4_pm_init_early();
- omap_prm_base_init();
omap_cm_base_init();
omap44xx_prm_init();
omap5xxx_check_revision();
@@ -722,7 +719,6 @@ void __init dra7xx_init_early(void)
OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap4_pm_init_early();
- omap_prm_base_init();
omap_cm_base_init();
omap44xx_prm_init();
dra7xxx_check_revision();
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 1af0137..6f647f6 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -705,6 +705,8 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
int __init omap44xx_prm_init(void)
{
+ omap_prm_base_init();
+
if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
prm_features |= PRM_HAS_IO_WAKEUP;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 01/35] clk: ti: fix ti_clk_get_reg_addr error handling
There is a case where NULL can be a valid return value for
ti_clk_get_reg_addr, specifically the case where both the provider index
and register offsets are zero. In this case, the current error checking
against a NULL pointer will fail. Thus, change the API to return a
ERR_PTR value in an error case, and change all the users of this API to
check against IS_ERR instead.
Signed-off-by: Tero Kristo t-kri...@ti.com
Acked-by: Michael Turquette mturque...@linaro.org
---
drivers/clk/ti/apll.c |5 +++--
drivers/clk/ti/autoidle.c |2 +-
drivers/clk/ti/clk.c |7 ---
drivers/clk/ti/divider.c |4 ++--
drivers/clk/ti/dpll.c |6 +++---
drivers/clk/ti/gate.c |4 ++--
drivers/clk/ti/interface.c |2 +-
drivers/clk/ti/mux.c |4 ++--
8 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 72d9727..49baf38 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -203,7 +203,7 @@ static void __init of_dra7_apll_setup(struct device_node
*node)
ad-control_reg = ti_clk_get_reg_addr(node, 0);
ad-idlest_reg = ti_clk_get_reg_addr(node, 1);
- if (!ad-control_reg || !ad-idlest_reg)
+ if (IS_ERR(ad-control_reg) || IS_ERR(ad-idlest_reg))
goto cleanup;
ad-idlest_mask = 0x1;
@@ -384,7 +384,8 @@ static void __init of_omap2_apll_setup(struct device_node
*node)
ad-autoidle_reg = ti_clk_get_reg_addr(node, 1);
ad-idlest_reg = ti_clk_get_reg_addr(node, 2);
- if (!ad-control_reg || !ad-autoidle_reg || !ad-idlest_reg)
+ if (IS_ERR(ad-control_reg) || IS_ERR(ad-autoidle_reg) ||
+ IS_ERR(ad-idlest_reg))
goto cleanup;
clk = clk_register(NULL, clk_hw-hw);
diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
index 8912ff8..e75c64c 100644
--- a/drivers/clk/ti/autoidle.c
+++ b/drivers/clk/ti/autoidle.c
@@ -119,7 +119,7 @@ int __init of_ti_clk_autoidle_setup(struct device_node
*node)
clk-name = node-name;
clk-reg = ti_clk_get_reg_addr(node, 0);
- if (!clk-reg) {
+ if (IS_ERR(clk-reg)) {
kfree(clk);
return -EINVAL;
}
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index e22b956..0ebe5c5 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -103,7 +103,8 @@ int __init ti_clk_retry_init(struct device_node *node,
struct clk_hw *hw,
* @index: register index from the clock node
*
* Builds clock register address from device tree information. This
- * is a struct of type clk_omap_reg.
+ * is a struct of type clk_omap_reg. Returns a pointer to the register
+ * address, or a pointer error value in failure.
*/
void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index)
{
@@ -121,14 +122,14 @@ void __iomem *ti_clk_get_reg_addr(struct device_node
*node, int index)
if (i == CLK_MAX_MEMMAPS) {
pr_err(clk-provider not found for %s!\n, node-name);
- return NULL;
+ return ERR_PTR(-ENOENT);
}
reg-index = i;
if (of_property_read_u32_index(node, reg, index, val)) {
pr_err(%s must have reg[%d]!\n, node-name, index);
- return NULL;
+ return ERR_PTR(-EINVAL);
}
reg-offset = val;
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index 6211893..ff5f117 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -530,8 +530,8 @@ static int __init ti_clk_divider_populate(struct
device_node *node,
u32 val;
*reg = ti_clk_get_reg_addr(node, 0);
- if (!*reg)
- return -EINVAL;
+ if (IS_ERR(*reg))
+ return PTR_ERR(*reg);
if (!of_property_read_u32(node, ti,bit-shift, val))
*shift = val;
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 81dc469..11478a5 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -390,18 +390,18 @@ static void __init of_ti_dpll_setup(struct device_node
*node,
#endif
} else {
dd-idlest_reg = ti_clk_get_reg_addr(node, 1);
- if (!dd-idlest_reg)
+ if (IS_ERR(dd-idlest_reg))
goto cleanup;
dd-mult_div1_reg = ti_clk_get_reg_addr(node, 2);
}
- if (!dd-control_reg || !dd-mult_div1_reg)
+ if (IS_ERR(dd-control_reg) || IS_ERR(dd-mult_div1_reg))
goto cleanup;
if (dd-autoidle_mask) {
dd-autoidle_reg = ti_clk_get_reg_addr(node, 3);
- if (!dd-autoidle_reg)
+ if (IS_ERR(dd-autoidle_reg))
goto cleanup;
}
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
index d493307..0c6fdfc 100644
--- a/drivers/clk/ti/gate.c
+++ b/drivers/clk/ti/gate.c
@@ -225,7 +225,7 @@ static void __init
[PATCHv5 10/35] ARM: OMAP2+: PRCM: add support for static clock memmap indices
All clock provider related drivers will now register their iomaps
with a static index. This makes it easier to split up the individual
drivers to their own files in subsequent patches.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/prcm-common.h |8
arch/arm/mach-omap2/prm_common.c | 79 +++--
include/linux/clk/ti.h|1 +
3 files changed, 59 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-omap2/prcm-common.h
b/arch/arm/mach-omap2/prcm-common.h
index 6163d66..ee38356 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -518,6 +518,14 @@ struct omap_prcm_irq_setup {
.priority = _priority \
}
+/**
+ * struct omap_prcm_init_data - PRCM driver init data
+ * @index: clock memory mapping index to be used
+ */
+struct omap_prcm_init_data {
+ int index;
+};
+
extern void omap_prcm_irq_cleanup(void);
extern int omap_prcm_register_chain_handler(
struct omap_prcm_irq_setup *irq_setup);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 79cee11..8ec5201 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -633,31 +633,47 @@ int prm_unregister(struct prm_ll_data *pld)
return 0;
}
+static struct omap_prcm_init_data prm_data = {
+ .index = TI_CLKM_PRM,
+};
+
+static struct omap_prcm_init_data cm_data = {
+ .index = TI_CLKM_CM,
+};
+
+static struct omap_prcm_init_data cm2_data = {
+ .index = TI_CLKM_CM2,
+};
+
+static struct omap_prcm_init_data scrm_data = {
+ .index = TI_CLKM_SCRM,
+};
+
static const struct of_device_id omap_prcm_dt_match_table[] = {
- { .compatible = ti,am3-prcm },
- { .compatible = ti,am3-scrm },
- { .compatible = ti,am4-prcm },
- { .compatible = ti,am4-scrm },
- { .compatible = ti,dm814-prcm },
- { .compatible = ti,dm814-scrm },
- { .compatible = ti,dm816-prcm },
- { .compatible = ti,dm816-scrm },
- { .compatible = ti,omap2-prcm },
- { .compatible = ti,omap2-scrm },
- { .compatible = ti,omap3-prm },
- { .compatible = ti,omap3-cm },
- { .compatible = ti,omap3-scrm },
- { .compatible = ti,omap4-cm1 },
- { .compatible = ti,omap4-prm },
- { .compatible = ti,omap4-cm2 },
- { .compatible = ti,omap4-scrm },
- { .compatible = ti,omap5-prm },
- { .compatible = ti,omap5-cm-core-aon },
- { .compatible = ti,omap5-scrm },
- { .compatible = ti,omap5-cm-core },
- { .compatible = ti,dra7-prm },
- { .compatible = ti,dra7-cm-core-aon },
- { .compatible = ti,dra7-cm-core },
+ { .compatible = ti,am3-prcm, .data = prm_data },
+ { .compatible = ti,am3-scrm, .data = scrm_data },
+ { .compatible = ti,am4-prcm, .data = prm_data },
+ { .compatible = ti,am4-scrm, .data = scrm_data },
+ { .compatible = ti,dm814-prcm, .data = prm_data },
+ { .compatible = ti,dm814-scrm, .data = scrm_data },
+ { .compatible = ti,dm816-prcm, .data = prm_data },
+ { .compatible = ti,dm816-scrm, .data = scrm_data },
+ { .compatible = ti,omap2-prcm, .data = prm_data },
+ { .compatible = ti,omap2-scrm, .data = scrm_data },
+ { .compatible = ti,omap3-prm, .data = prm_data },
+ { .compatible = ti,omap3-cm, .data = cm_data },
+ { .compatible = ti,omap3-scrm, .data = scrm_data },
+ { .compatible = ti,omap4-cm1, .data = cm_data },
+ { .compatible = ti,omap4-prm, .data = prm_data },
+ { .compatible = ti,omap4-cm2, .data = cm2_data },
+ { .compatible = ti,omap4-scrm, .data = scrm_data },
+ { .compatible = ti,omap5-prm, .data = prm_data },
+ { .compatible = ti,omap5-cm-core-aon, .data = cm_data },
+ { .compatible = ti,omap5-scrm, .data = scrm_data },
+ { .compatible = ti,omap5-cm-core, .data = cm2_data },
+ { .compatible = ti,dra7-prm, .data = prm_data },
+ { .compatible = ti,dra7-cm-core-aon, .data = cm_data },
+ { .compatible = ti,dra7-cm-core, .data = cm2_data },
{ }
};
@@ -690,15 +706,20 @@ int __init omap_prcm_init(void)
{
struct device_node *np;
void __iomem *mem;
- int memmap_index = 0;
+ const struct of_device_id *match;
+ const struct omap_prcm_init_data *data;
ti_clk_ll_ops = omap_clk_ll_ops;
- for_each_matching_node(np, omap_prcm_dt_match_table) {
+ for_each_matching_node_and_match(np, omap_prcm_dt_match_table, match) {
+ data = match-data;
+
mem = of_iomap(np, 0);
- clk_memmaps[memmap_index] = mem;
- ti_dt_clk_init_provider(np, memmap_index);
- memmap_index++;
+ if (!mem)
+ return -ENOMEM;
+
+ clk_memmaps[data-index] = mem;
+ ti_dt_clk_init_provider(np, data-index);
[PATCHv5 08/35] ARM: OMAP4: PRM: move omap4xxx_prm_init earlier in init order
OMAP4 has different ordering of PRM and CM init calls in the early init. Re-oder these accordingly for OMAP4 also. This is needed so that we can do some optimizations in the following patches for the PRCM init. Signed-off-by: Tero Kristo t-kri...@ti.com --- arch/arm/mach-omap2/io.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 364b530..460da22 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -654,9 +654,9 @@ void __init omap4430_init_early(void) omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); omap4xxx_check_revision(); omap4xxx_check_features(); + omap44xx_prm_init(); omap4_cm_init(); omap4_pm_init_early(); - omap44xx_prm_init(); omap44xx_voltagedomains_init(); omap44xx_powerdomains_init(); omap44xx_clockdomains_init(); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 09/35] Documentation: DT: document PRCM compatible strings for dm81x SoCs
These PRCM nodes were earlier added in patch 7800064ba5 (ARM: dts: Add basic dm816x device tree configuration), but the documentation for the same wasn't added. Fix this by adding the missing compatible strings under the generic prcm.txt document. Signed-off-by: Tero Kristo t-kri...@ti.com --- .../devicetree/bindings/arm/omap/prcm.txt |4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt index 79074da..68f96f8 100644 --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt @@ -29,6 +29,10 @@ Required properties: ti,dra7-prm ti,dra7-cm-core-aon ti,dra7-cm-core + ti,dm814-prcm + ti,dm814-scrm + ti,dm816-prcm + ti,dm816-scrm - reg: Contains PRCM module register address range (base address and length) - clocks: clocks for this module -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 05/35] ARM: OMAP3+: PRM: add common APIs for prm_vp_check/clear_txdone
PRM driver now only exports a generic API for clearing / checking
VP txdone status.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/prm.h | 14 ++
arch/arm/mach-omap2/prm3xxx.c |6 --
arch/arm/mach-omap2/prm3xxx.h |4
arch/arm/mach-omap2/prm44xx.c |6 --
arch/arm/mach-omap2/prm44xx_54xx.h |4
arch/arm/mach-omap2/prm_common.c | 34 ++
arch/arm/mach-omap2/vp.h |9 -
arch/arm/mach-omap2/vp3xxx_data.c |4 ++--
arch/arm/mach-omap2/vp44xx_data.c |4 ++--
9 files changed, 60 insertions(+), 25 deletions(-)
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 2a01a58..4e390ec 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -147,6 +147,8 @@ struct prm_ll_data {
u16 offset);
void (*reset_system)(void);
int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask);
+ u32 (*vp_check_txdone)(u8 vp_id);
+ void (*vp_clear_txdone)(u8 vp_id);
};
extern int prm_register(struct prm_ll_data *pld);
@@ -164,6 +166,18 @@ void omap_prm_reset_system(void);
void omap_prm_reconfigure_io_chain(void);
int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
+/*
+ * Voltage Processor (VP) identifiers
+ */
+#define OMAP3_VP_VDD_MPU_ID0
+#define OMAP3_VP_VDD_CORE_ID 1
+#define OMAP4_VP_VDD_CORE_ID 0
+#define OMAP4_VP_VDD_IVA_ID1
+#define OMAP4_VP_VDD_MPU_ID2
+
+u32 omap_prm_vp_check_txdone(u8 vp_id);
+void omap_prm_vp_clear_txdone(u8 vp_id);
+
#endif
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index a444334..2b478adc 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -96,7 +96,7 @@ static struct omap3_vp omap3_vp[] = {
#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
-u32 omap3_prm_vp_check_txdone(u8 vp_id)
+static u32 omap3_prm_vp_check_txdone(u8 vp_id)
{
struct omap3_vp *vp = omap3_vp[vp_id];
u32 irqstatus;
@@ -106,7 +106,7 @@ u32 omap3_prm_vp_check_txdone(u8 vp_id)
return irqstatus vp-tranxdone_status;
}
-void omap3_prm_vp_clear_txdone(u8 vp_id)
+static void omap3_prm_vp_clear_txdone(u8 vp_id)
{
struct omap3_vp *vp = omap3_vp[vp_id];
@@ -665,6 +665,8 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
.is_hardreset_asserted = omap2_prm_is_hardreset_asserted,
.reset_system = omap3xxx_prm_dpll3_reset,
.clear_mod_irqs = omap3xxx_prm_clear_mod_irqs,
+ .vp_check_txdone = omap3_prm_vp_check_txdone,
+ .vp_clear_txdone = omap3_prm_vp_clear_txdone,
};
int __init omap3xxx_prm_init(void)
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index 5a09a74..55e4c89 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -132,10 +132,6 @@
#ifndef __ASSEMBLER__
-/* OMAP3-specific VP functions */
-u32 omap3_prm_vp_check_txdone(u8 vp_id);
-void omap3_prm_vp_clear_txdone(u8 vp_id);
-
/*
* OMAP3 access functions for voltage controller (VC) and
* voltage proccessor (VP) in the PRM.
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a08a617..1af0137 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -138,7 +138,7 @@ static struct omap4_vp omap4_vp[] = {
},
};
-u32 omap4_prm_vp_check_txdone(u8 vp_id)
+static u32 omap4_prm_vp_check_txdone(u8 vp_id)
{
struct omap4_vp *vp = omap4_vp[vp_id];
u32 irqstatus;
@@ -149,7 +149,7 @@ u32 omap4_prm_vp_check_txdone(u8 vp_id)
return irqstatus vp-tranxdone_status;
}
-void omap4_prm_vp_clear_txdone(u8 vp_id)
+static void omap4_prm_vp_clear_txdone(u8 vp_id)
{
struct omap4_vp *vp = omap4_vp[vp_id];
@@ -699,6 +699,8 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
.deassert_hardreset = omap4_prminst_deassert_hardreset,
.is_hardreset_asserted = omap4_prminst_is_hardreset_asserted,
.reset_system = omap4_prminst_global_warm_sw_reset,
+ .vp_check_txdone= omap4_prm_vp_check_txdone,
+ .vp_clear_txdone= omap4_prm_vp_clear_txdone,
};
int __init omap44xx_prm_init(void)
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h
b/arch/arm/mach-omap2/prm44xx_54xx.h
index 7143295..a470185 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -26,10 +26,6 @@
/* Function prototypes */
#ifndef __ASSEMBLER__
-/* OMAP4/OMAP5-specific VP functions */
-u32 omap4_prm_vp_check_txdone(u8 vp_id);
-void omap4_prm_vp_clear_txdone(u8 vp_id);
-
/*
* OMAP4/OMAP5 access functions for voltage controller (VC) and
* voltage proccessor (VP) in the PRM.
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 2c2e7ed..79cee11 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@
[PATCHv5 04/35] ARM: OMAP2+: PRM: add generic API for clear_mod_irqs
OMAP2/3 now use generic API for the prm_clear_mod_irqs, the SoC specific
implementation details are provided through prm_ll_data.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/pm24xx.c | 24 +++-
arch/arm/mach-omap2/pm34xx.c | 18 --
arch/arm/mach-omap2/prm.h|2 ++
arch/arm/mach-omap2/prm2xxx.c|4 +++-
arch/arm/mach-omap2/prm2xxx.h|2 --
arch/arm/mach-omap2/prm3xxx.c|3 ++-
arch/arm/mach-omap2/prm3xxx.h|1 -
arch/arm/mach-omap2/prm_common.c | 21 +
8 files changed, 47 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index fe01c5a..b1aad7e 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void)
/* Clear old wake-up events */
/* REVISIT: These write to reserved bits? */
- omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
- omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
- omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
+ omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+ omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
+ omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
@@ -104,18 +104,16 @@ no_sleep:
clk_enable(osc_ck);
/* clear CORE wake-up events */
- omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
- omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
+ omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+ omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
- omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
+ omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
/* MPU domain wake events */
- omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
- 0x1);
+ omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x1);
- omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
- 0x20);
+ omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x20);
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
@@ -143,9 +141,9 @@ static void omap2_enter_mpu_retention(void)
* it is in retention mode. */
if (omap2_allow_mpu_retention()) {
/* REVISIT: These write to reserved bits? */
- omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
- omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
- omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
+ omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+ omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
+ omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
/* Try to enter MPU retention */
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2581329..87b98bf9 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -137,8 +137,8 @@ static irqreturn_t _prcm_int_handle_io(int irq, void
*unused)
{
int c;
- c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
- OMAP3430_ST_IO_CHAIN_MASK);
+ c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
+ OMAP3430_ST_IO_CHAIN_MASK);
return c ? IRQ_HANDLED : IRQ_NONE;
}
@@ -152,15 +152,13 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void
*unused)
* these are handled in a separate handler to avoid acking
* IO events before parsing in mux code
*/
- c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
- ~(OMAP3430_ST_IO_MASK |
- OMAP3430_ST_IO_CHAIN_MASK));
- c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
- c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
+ c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
+ OMAP3430_ST_IO_CHAIN_MASK));
+ c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
+ c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
if (omap_rev() OMAP3430_REV_ES1_0) {
- c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
- c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1,
-~0);
+ c +=
[PATCHv5 07/35] ARM: OMAP4+: CM: move omap_cm_base_init under OMAP4 CM driver
There is no need to call this separately from io.c, rather this can be
done commonly under the CM driver. Also, this patch makes the API static,
as it is no longer used outside the driver file.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/cm44xx.h |1 -
arch/arm/mach-omap2/cminst44xx.c |4 +++-
arch/arm/mach-omap2/io.c |4
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 728d06a..ad6e263 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -23,7 +23,6 @@
#define OMAP4_CM_CLKSTCTRL 0x
#define OMAP4_CM_STATICDEP 0x0004
-void omap_cm_base_init(void);
int omap4_cm_init(void);
#endif
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 95a8cff..9319034 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -63,7 +63,7 @@ static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
* Populates the base addresses of the _cm_bases
* array used for read/write of cm module registers.
*/
-void omap_cm_base_init(void)
+static void omap_cm_base_init(void)
{
_cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
_cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
@@ -516,6 +516,8 @@ static struct cm_ll_data omap4xxx_cm_ll_data = {
int __init omap4_cm_init(void)
{
+ omap_cm_base_init();
+
return cm_register(omap4xxx_cm_ll_data);
}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5569c2f..364b530 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -623,7 +623,6 @@ void __init am43xx_init_early(void)
NULL);
omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
- omap_cm_base_init();
omap3xxx_check_revision();
am33xx_check_features();
omap44xx_prm_init();
@@ -653,7 +652,6 @@ void __init omap4430_init_early(void)
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
- omap_cm_base_init();
omap4xxx_check_revision();
omap4xxx_check_features();
omap4_cm_init();
@@ -688,7 +686,6 @@ void __init omap5_init_early(void)
OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap4_pm_init_early();
- omap_cm_base_init();
omap44xx_prm_init();
omap5xxx_check_revision();
omap4_cm_init();
@@ -719,7 +716,6 @@ void __init dra7xx_init_early(void)
OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap4_pm_init_early();
- omap_cm_base_init();
omap44xx_prm_init();
dra7xxx_check_revision();
omap4_cm_init();
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 02/35] ARM: OMAP2+: PRCM: rename of_prcm_init to omap_prcm_init
This avoids conflicts in the global namespace, and is more descriptive
of the purpose anyway.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/io.c |2 +-
arch/arm/mach-omap2/prm.h|2 +-
arch/arm/mach-omap2/prm_common.c |8 +++-
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index c4871c5..f504f71 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -764,7 +764,7 @@ int __init omap_clk_init(void)
ti_clk_init_features();
if (of_have_populated_dt()) {
- ret = of_prcm_init();
+ ret = omap_prcm_init();
if (ret)
return ret;
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index b9061a6..ba9b933 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -19,7 +19,7 @@
extern void __iomem *prm_base;
extern u16 prm_features;
extern void omap2_set_globals_prm(void __iomem *prm);
-int of_prcm_init(void);
+int omap_prcm_init(void);
void omap3_prcm_legacy_iomaps_init(void);
# endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index bfaa7ba..c5cfaa9 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -625,7 +625,13 @@ static struct ti_clk_ll_ops omap_clk_ll_ops = {
.clk_writel = prm_clk_writel,
};
-int __init of_prcm_init(void)
+/**
+ * omap_prcm_init - low level init for the PRCM drivers
+ *
+ * Initializes the low level clock infrastructure for PRCM drivers.
+ * Returns 0 in success, negative error value in failure.
+ */
+int __init omap_prcm_init(void)
{
struct device_node *np;
void __iomem *mem;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 00/35] ARM: OMAP2+: PRCM/SCM cleanups against 4.0-rc
Hi, v5 contains the following changes still: - re-ordered patches a bit, the single clock driver fix moved to beginning of the set, waiting for a separate merge from Mike - Changed patch #23 to fix the slightly misleading logic (removed the extra +1) - Changed patches #16 and #18 to fix OMAP2/3/4 etc. only builds - Fixed ti81xx boot issues (hopefully, I don't have access to hardware to test it) - Changed control module DTS layout based on discussions with Tony, this includes addition of minimal l4 bus (patch #25+) Testing done for v5: 1: am335x-evm : boot 2: am335x-evmsk: boot 3: am3517-evm : boot 4: am43x-epos-evm : boot 5: am437x-gp-evm : boot 6: omap3-beagle-xm : boot 7: omap3-beagle: boot, suspend (ret/off), cpuidle (ret/off) 8: am335x-boneblack: boot 9: am335x-bone : boot 10: dra7xx-evm : boot 11: omap3-n900 : boot 12: omap5-uevm : boot 13: omap4-panda-es : boot, suspend (ret), cpuidle (ret) 14: omap4-panda : boot 15: omap2430-sdp: boot 16: omap3430-sdp: boot 17: omap4-sdp-es23plus: boot Branch available at: - tree: https://github.com/t-kristo/linux-pm.git - branch: 4.0-rc1-prcm-cleanup-v5 -Tero -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 11/35] ARM: OMAP2+: clock: move clock provider infrastructure to clock driver
Splits the clock provider init out of the PRM driver and moves it to
clock driver. This is needed so that once the PRCM drivers are separated,
they can logically just access the clock driver not needing to go through
common PRM code. This would be wrong in the case of control module for
example.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clock.c | 75 --
arch/arm/mach-omap2/clock.h |6 ++-
arch/arm/mach-omap2/prm_common.c | 36 --
3 files changed, 76 insertions(+), 41 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 6124db5..3327128 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -23,6 +23,7 @@
#include linux/clk-provider.h
#include linux/io.h
#include linux/bitops.h
+#include linux/of_address.h
#include asm/cpu.h
#include trace/events/power.h
@@ -72,32 +73,84 @@ struct ti_clk_features ti_clk_features;
static bool clkdm_control = true;
static LIST_HEAD(clk_hw_omap_clocks);
-void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
+static void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
+
+static void clk_memmap_writel(u32 val, void __iomem *reg)
+{
+ struct clk_omap_reg *r = (struct clk_omap_reg *)reg;
+
+ writel_relaxed(val, clk_memmaps[r-index] + r-offset);
+}
+
+static u32 clk_memmap_readl(void __iomem *reg)
+{
+ struct clk_omap_reg *r = (struct clk_omap_reg *)reg;
+
+ return readl_relaxed(clk_memmaps[r-index] + r-offset);
+}
void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
{
- if (clk-flags MEMMAP_ADDRESSING) {
- struct clk_omap_reg *r = (struct clk_omap_reg *)reg;
- writel_relaxed(val, clk_memmaps[r-index] + r-offset);
- } else {
+ if (clk-flags MEMMAP_ADDRESSING)
+ clk_memmap_writel(val, reg);
+ else
writel_relaxed(val, reg);
- }
}
u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
{
u32 val;
- if (clk-flags MEMMAP_ADDRESSING) {
- struct clk_omap_reg *r = (struct clk_omap_reg *)reg;
- val = readl_relaxed(clk_memmaps[r-index] + r-offset);
- } else {
+ if (clk-flags MEMMAP_ADDRESSING)
+ val = clk_memmap_readl(reg);
+ else
val = readl_relaxed(reg);
- }
return val;
}
+static struct ti_clk_ll_ops omap_clk_ll_ops = {
+ .clk_readl = clk_memmap_readl,
+ .clk_writel = clk_memmap_writel,
+};
+
+/**
+ * omap2_clk_provider_init - initialize a clock provider
+ * @match_table: DT device table to match for devices to init
+ * @np: device node pointer for the this clock provider
+ * @index: index for the clock provider
+ * @mem: iomem pointer for the clock provider memory area
+ *
+ * Initializes a clock provider module (CM/PRM etc.), registering
+ * the memory mapping at specified index and initializing the
+ * low level driver infrastructure. Returns 0 in success.
+ */
+int __init omap2_clk_provider_init(struct device_node *np, int index,
+ void __iomem *mem)
+{
+ ti_clk_ll_ops = omap_clk_ll_ops;
+
+ clk_memmaps[index] = mem;
+
+ ti_dt_clk_init_provider(np, index);
+
+ return 0;
+}
+
+/**
+ * omap2_clk_legacy_provider_init - initialize a legacy clock provider
+ * @index: index for the clock provider
+ * @mem: iomem pointer for the clock provider memory area
+ *
+ * Initializes a legacy clock provider memory mapping.
+ */
+void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem)
+{
+ ti_clk_ll_ops = omap_clk_ll_ops;
+
+ clk_memmaps[index] = mem;
+}
+
/*
* OMAP2+ specific clock functions
*/
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index a56742f..b6433fc 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -271,10 +271,12 @@ extern const struct clksel_rate div_1_3_rates[];
extern const struct clksel_rate div_1_4_rates[];
extern const struct clksel_rate div31_1to31_rates[];
-extern void __iomem *clk_memmaps[];
-
extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
+int __init omap2_clk_provider_init(struct device_node *np, int index,
+ void __iomem *mem);
+void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem);
+
void __init ti_clk_init_features(void);
#endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 8ec5201..1bfd00e 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -677,25 +677,6 @@ static const struct of_device_id
omap_prcm_dt_match_table[] = {
{ }
};
-static struct clk_hw_omap memmap_dummy_ck = {
- .flags = MEMMAP_ADDRESSING,
-};
-
-static u32 prm_clk_readl(void __iomem *reg)
-{
- return
Re: [RFT OMAP1 PATCH 7/8] gpio: omap: get rid of omap_irq_to_gpio()
Hello Grygorii, On Thu, Mar 19, 2015 at 6:25 PM, grygorii.stras...@linaro.org wrote: From: Grygorii Strashko grygorii.stras...@linaro.org Now OMAP GPIO driver prepared for omap_irq_to_gpio() removing. Do it ;) Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org I don't have access to OMAP1 boards to test but Tony did it o an osk5912 and Aaro can confirm that it doesn't cause regressions on other OMAP1 boards. Thanks a lot for the cleanup. Acked-by: Javier Martinez Canillas jav...@dowhile0.org Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFT OMAP1 PATCH 8/8] gpio: omap: get rid of GPIO_INDEX() macro
On Thu, Mar 19, 2015 at 6:25 PM, grygorii.stras...@linaro.org wrote: From: Grygorii Strashko grygorii.stras...@linaro.org Now OMAP GPIO driver prepared for GPIO_INDEX() macro removing. Do It ;) Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org Acked-by: Javier Martinez Canillas jav...@dowhile0.org -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/8] gpio: omap: convert debounce functions switch to use gpio offset
On Thu, Mar 19, 2015 at 6:25 PM, grygorii.stras...@linaro.org wrote: From: Grygorii Strashko grygorii.stras...@linaro.org Convert debounce functions to use GPIO offset instead of system GPIO numbers. This allows to drop unneeded conversations between system GPIO - GPIO offset which are done in many places and many times. It is safe to do now because: - gpiolib always passes GPIO offset to GPIO controller - OMAP GPIO driver converted to use IRQ domain This is preparation step before removing: #define GPIO_INDEX(bank, gpio) #define GPIO_BIT(bank, gpio) int omap_irq_to_gpio() Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org --- Acked-by: Javier Martinez Canillas jav...@dowhile0.org -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 33/35] ARM: dts: omap5: add minimal l4 bus layout with control module support
This patch creates the l4_cfg and l4_wkup interconnects for OMAP5, and
moves some of the generic peripherals under it. System control module
support is added to the device tree also, and the existing SCM related
functionality is moved under it.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/arm/omap/ctrl.txt |2 +
Documentation/devicetree/bindings/arm/omap/l4.txt |2 +
arch/arm/boot/dts/omap5.dtsi | 182
3 files changed, 116 insertions(+), 70 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt
b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
index 2675881..acb68ed 100644
--- a/Documentation/devicetree/bindings/arm/omap/ctrl.txt
+++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
@@ -21,6 +21,8 @@ Required properties:
ti,omap3-scm
ti,omap4-scm-core
ti,omap4-scm-padconf-core
+ ti,omap5-scm-core
+ ti,omap5-scm-padconf-core
- reg: Contains Control Module register address range
(base address and length)
diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt
b/Documentation/devicetree/bindings/arm/omap/l4.txt
index de18cfa..2fe4211 100644
--- a/Documentation/devicetree/bindings/arm/omap/l4.txt
+++ b/Documentation/devicetree/bindings/arm/omap/l4.txt
@@ -8,6 +8,8 @@ Required properties:
Should be ti,omap3-l4-core for OMAP3 family l4 core bus
Should be ti,omap4-l4-cfg for OMAP4 family l4 cfg bus
Should be ti,omap4-l4-wkup for OMAP4 family l4 wkup bus
+ Should be ti,omap5-l4-cfg for OMAP5 family l4 cfg bus
+ Should be ti,omap5-l4-wkup for OMAP5 family l4 wkup bus
Should be ti,am3-l4-wkup for AM33xx family l4 wkup bus
Should be ti,am4-l4-wkup for AM43xx family l4 wkup bus
- ranges : contains the IO map range for the bus
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index b321fdf..326a429 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -129,99 +129,141 @@
interrupts = GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH,
GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
- prm: prm@4ae06000 {
- compatible = ti,omap5-prm;
- reg = 0x4ae06000 0x3000;
- interrupts = GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH;
+ l4_cfg: l4@4a00 {
+ compatible = ti,omap5-l4-cfg, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x4a00 0x22a000;
- prm_clocks: clocks {
+ scm_core: scm@2000 {
+ compatible = ti,omap5-scm-core, simple-bus;
+ reg = 0x2000 0x1000;
#address-cells = 1;
- #size-cells = 0;
+ #size-cells = 1;
+ ranges = 0 0x2000 0x800;
+
+ scm_conf: scm_conf@0 {
+ compatible = syscon;
+ reg = 0x0 0x800;
+ #address-cells = 1;
+ #size-cells = 1;
+ };
};
- prm_clockdomains: clockdomains {
+ scm_padconf_core: scm@2800 {
+ compatible = ti,omap5-scm-padconf-core,
+simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x2800 0x800;
+
+ omap5_pmx_core: pinmux@40 {
+ compatible = ti,omap5-padconf,
+pinctrl-single;
+ reg = 0x40 0x01b6;
+ #address-cells = 1;
+ #size-cells = 0;
+ #interrupt-cells = 1;
+ interrupt-controller;
+ pinctrl-single,register-width = 16;
+ pinctrl-single,function-mask = 0x7fff;
+ };
+
+ omap5_padconf_global: omap5_padconf_global@5a0 {
+ compatible = syscon;
+ reg = 0x5a0 0xec;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ pbias_regulator:
[PATCHv5 24/35] ARM: OMAP2+: control: add syscon support for register accesses
Control module driver needs to support syscon for register accesses, as
the DT hierarchy for control module driver is going to be changed. All
the control module related features will be moved under control module
node, including clocks, pinctrl, and generic configuration register
access. Temporary iomap is still provided very early in the boot for
access while syscon is not yet ready.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/control.c | 101 ++---
1 file changed, 84 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 202fc72..65a4211 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -15,6 +15,8 @@
#include linux/kernel.h
#include linux/io.h
#include linux/of_address.h
+#include linux/regmap.h
+#include linux/mfd/syscon.h
#include soc.h
#include iomap.h
@@ -33,7 +35,9 @@
#define PADCONF_SAVE_DONE 0x1
static void __iomem *omap2_ctrl_base;
+static s16 omap2_ctrl_offset;
static void __iomem *omap4_ctrl_pad_base;
+static struct regmap *omap2_ctrl_syscon;
#if defined(CONFIG_ARCH_OMAP3) defined(CONFIG_PM)
struct omap3_scratchpad {
@@ -135,7 +139,6 @@ struct omap3_control_regs {
static struct omap3_control_regs control_context;
#endif /* CONFIG_ARCH_OMAP3 CONFIG_PM */
-#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
#define OMAP4_CTRL_PAD_REGADDR(reg)(omap4_ctrl_pad_base + (reg))
void __init omap2_set_globals_control(void __iomem *ctrl,
@@ -147,32 +150,72 @@ void __init omap2_set_globals_control(void __iomem *ctrl,
u8 omap_ctrl_readb(u16 offset)
{
- return readb_relaxed(OMAP_CTRL_REGADDR(offset));
+ u32 val;
+ u8 byte_offset = offset 0x3;
+
+ val = omap_ctrl_readl(offset);
+
+ return (val (byte_offset * 8)) 0xff;
}
u16 omap_ctrl_readw(u16 offset)
{
- return readw_relaxed(OMAP_CTRL_REGADDR(offset));
+ u32 val;
+ u16 byte_offset = offset 0x2;
+
+ val = omap_ctrl_readl(offset);
+
+ return (val (byte_offset * 8)) 0x;
}
u32 omap_ctrl_readl(u16 offset)
{
- return readl_relaxed(OMAP_CTRL_REGADDR(offset));
+ u32 val;
+
+ offset = 0xfffc;
+ if (!omap2_ctrl_syscon)
+ val = readl_relaxed(omap2_ctrl_base + offset);
+ else
+ regmap_read(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
+ val);
+
+ return val;
}
void omap_ctrl_writeb(u8 val, u16 offset)
{
- writeb_relaxed(val, OMAP_CTRL_REGADDR(offset));
+ u32 tmp;
+ u8 byte_offset = offset 0x3;
+
+ tmp = omap_ctrl_readl(offset);
+
+ tmp = 0x ^ (0xff (byte_offset * 8));
+ tmp |= val (byte_offset * 8);
+
+ omap_ctrl_writel(tmp, offset);
}
void omap_ctrl_writew(u16 val, u16 offset)
{
- writew_relaxed(val, OMAP_CTRL_REGADDR(offset));
+ u32 tmp;
+ u8 byte_offset = offset 0x2;
+
+ tmp = omap_ctrl_readl(offset);
+
+ tmp = 0x ^ (0x (byte_offset * 8));
+ tmp |= val (byte_offset * 8);
+
+ omap_ctrl_writel(tmp, offset);
}
void omap_ctrl_writel(u32 val, u16 offset)
{
- writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
+ offset = 0xfffc;
+ if (!omap2_ctrl_syscon)
+ writel_relaxed(val, omap2_ctrl_base + offset);
+ else
+ regmap_write(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
+val);
}
/*
@@ -611,7 +654,7 @@ void __init omap3_ctrl_init(void)
struct control_init_data {
int index;
- void __iomem *mem;
+ s16 offset;
};
static struct control_init_data ctrl_data = {
@@ -639,17 +682,15 @@ int __init omap2_control_base_init(void)
struct device_node *np;
const struct of_device_id *match;
struct control_init_data *data;
- void __iomem *mem;
for_each_matching_node_and_match(np, omap_scrm_dt_match_table, match) {
data = (struct control_init_data *)match-data;
- mem = of_iomap(np, 0);
- if (!mem)
+ omap2_ctrl_base = of_iomap(np, 0);
+ if (!omap2_ctrl_base)
return -ENOMEM;
- omap2_ctrl_base = mem;
- data-mem = mem;
+ omap2_ctrl_offset = data-offset;
}
return 0;
@@ -663,17 +704,43 @@ int __init omap2_control_base_init(void)
*/
int __init omap_control_init(void)
{
- struct device_node *np;
+ struct device_node *np, *scm_conf;
const struct of_device_id *match;
const struct omap_prcm_init_data *data;
int ret;
+ struct regmap *syscon;
for_each_matching_node_and_match(np, omap_scrm_dt_match_table, match) {
data = match-data;
- ret = omap2_clk_provider_init(np, data-index, NULL, data-mem);
- if
[PATCHv5 26/35] ARM: dts: omap3: add minimal l4 bus layout with control module support
This patch creates an l4_core interconnect for OMAP3, and moves some
of the generic peripherals under it. System control module nodes are
moved under this new interconnect also, and the SCM clock layout
is changed to use the renamed SCM node as the clock provider.
Signed-off-by: Tero Kristo t-kri...@ti.com
Reported-by: Tony Lindgren t...@atomide.com
---
Documentation/devicetree/bindings/arm/omap/l4.txt |1 +
.../devicetree/bindings/arm/omap/prcm.txt |2 +-
arch/arm/boot/dts/am3517.dtsi |2 +-
arch/arm/boot/dts/am35xx-clocks.dtsi |2 +-
arch/arm/boot/dts/omap3.dtsi | 96 +++-
arch/arm/boot/dts/omap3xxx-clocks.dtsi | 13 +--
arch/arm/mach-omap2/control.c |2 +-
7 files changed, 67 insertions(+), 51 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt
b/Documentation/devicetree/bindings/arm/omap/l4.txt
index 57569cc8..6402022 100644
--- a/Documentation/devicetree/bindings/arm/omap/l4.txt
+++ b/Documentation/devicetree/bindings/arm/omap/l4.txt
@@ -5,6 +5,7 @@ These bindings describe the OMAP SoCs L4 interconnect bus.
Required properties:
- compatible : Should be ti,omap2-l4 for OMAP2 family l4 core bus
Should be ti,omap2-l4-wkup for OMAP2 family l4 wkup bus
+ Should be ti,omap3-l4-core for OMAP3 family l4 core bus
- ranges : contains the IO map range for the bus
Examples:
diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt
b/Documentation/devicetree/bindings/arm/omap/prcm.txt
index cce8365..ef5a74b 100644
--- a/Documentation/devicetree/bindings/arm/omap/prcm.txt
+++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
@@ -17,7 +17,7 @@ Required properties:
ti,omap2-scm
ti,omap3-prm
ti,omap3-cm
- ti,omap3-scrm
+ ti,omap3-scm
ti,omap4-cm1
ti,omap4-prm
ti,omap4-cm2
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index c90724b..f164dce 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -31,7 +31,7 @@
status = disabled;
reg = 0x5c00 0x3;
interrupts = 67 68 69 70;
- syscon = omap3_scm_general;
+ syscon = scm_conf;
ti,davinci-ctrl-reg-offset = 0x1;
ti,davinci-ctrl-mod-reg-offset = 0;
ti,davinci-ctrl-ram-offset = 0x2;
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi
b/arch/arm/boot/dts/am35xx-clocks.dtsi
index df489d3..518b8fd 100644
--- a/arch/arm/boot/dts/am35xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-scrm_clocks {
+scm_clocks {
emac_ick: emac_ick {
#clock-cells = 0;
compatible = ti,am35xx-gate-clock;
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 01b7111..0020a7a8 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -87,6 +87,60 @@
ranges;
ti,hwmods = l3_main;
+ l4_core: l4@4800 {
+ compatible = ti,omap3-l4-core, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x4800 0x100;
+
+ scm: scm@2000 {
+ compatible = ti,omap3-scm, simple-bus;
+ reg = 0x2000 0x2000;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x2000 0x2000;
+
+ omap3_pmx_core: pinmux@30 {
+ compatible = ti,omap3-padconf,
+pinctrl-single;
+ reg = 0x30 0x230;
+ #address-cells = 1;
+ #size-cells = 0;
+ #interrupt-cells = 1;
+ interrupt-controller;
+ pinctrl-single,register-width = 16;
+ pinctrl-single,function-mask = 0xff1f;
+ };
+
+ scm_conf: scm_conf@270 {
+ compatible = syscon;
+ reg = 0x270 0x330;
+ #address-cells = 1;
+ #size-cells = 1;
+
+
[PATCHv5 29/35] ARM: dts: am4372: add minimal l4 bus layout with control module support
This patch creates an l4_wkup interconnect for AM43xx, and moves some of
the generic peripherals under it. System control module nodes are moved
under this new interconnect also, and the SCM clock layout is changed
to use the renamed SCM nodea as the clock provider.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
Documentation/devicetree/bindings/arm/omap/l4.txt |1 +
.../devicetree/bindings/arm/omap/prcm.txt |2 +-
arch/arm/boot/dts/am4372.dtsi | 85 +++-
arch/arm/boot/dts/am43xx-clocks.dtsi |2 +-
arch/arm/mach-omap2/control.c |2 +-
5 files changed, 53 insertions(+), 39 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt
b/Documentation/devicetree/bindings/arm/omap/l4.txt
index d333f0a..941b914 100644
--- a/Documentation/devicetree/bindings/arm/omap/l4.txt
+++ b/Documentation/devicetree/bindings/arm/omap/l4.txt
@@ -7,6 +7,7 @@ Required properties:
Should be ti,omap2-l4-wkup for OMAP2 family l4 wkup bus
Should be ti,omap3-l4-core for OMAP3 family l4 core bus
Should be ti,am3-l4-wkup for AM33xx family l4 wkup bus
+ Should be ti,am4-l4-wkup for AM43xx family l4 wkup bus
- ranges : contains the IO map range for the bus
Examples:
diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt
b/Documentation/devicetree/bindings/arm/omap/prcm.txt
index c8e2027..8af4f32 100644
--- a/Documentation/devicetree/bindings/arm/omap/prcm.txt
+++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
@@ -12,7 +12,7 @@ Required properties:
ti,am3-prcm
ti,am3-scm
ti,am4-prcm
- ti,am4-scrm
+ ti,am4-scm
ti,omap2-prcm
ti,omap2-scm
ti,omap3-prm
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 1943fc3..9ed58115 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -57,22 +57,6 @@
cache-level = 2;
};
- am43xx_control_module: control_module@4a002000 {
- compatible = syscon;
- reg = 0x44e1 0x7f4;
- };
-
- am43xx_pinmux: pinmux@44e10800 {
- compatible = ti,am437-padconf, pinctrl-single;
- reg = 0x44e10800 0x31c;
- #address-cells = 1;
- #size-cells = 0;
- #interrupt-cells = 1;
- interrupt-controller;
- pinctrl-single,register-width = 32;
- pinctrl-single,function-mask = 0x;
- };
-
ocp {
compatible = ti,am4372-l3-noc, simple-bus;
#address-cells = 1;
@@ -84,29 +68,58 @@
interrupts = GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH,
GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
- prcm: prcm@44df {
- compatible = ti,am4-prcm;
- reg = 0x44df 0x11000;
-
- prcm_clocks: clocks {
- #address-cells = 1;
- #size-cells = 0;
- };
+ l4_wkup: l4_wkup@44c0 {
+ compatible = ti,am4-l4-wkup, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x44c0 0x287000;
- prcm_clockdomains: clockdomains {
- };
- };
+ prcm: prcm@1f {
+ compatible = ti,am4-prcm;
+ reg = 0x1f 0x11000;
- scrm: scrm@44e1 {
- compatible = ti,am4-scrm;
- reg = 0x44e1 0x2000;
+ prcm_clocks: clocks {
+ #address-cells = 1;
+ #size-cells = 0;
+ };
- scrm_clocks: clocks {
- #address-cells = 1;
- #size-cells = 0;
+ prcm_clockdomains: clockdomains {
+ };
};
- scrm_clockdomains: clockdomains {
+ scm: scm@21 {
+ compatible = ti,am4-scm, simple-bus;
+ reg = 0x21 0x1000;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x21 0x1000;
+
+ am43xx_pinmux: pinmux@800 {
+ compatible = ti,am437-padconf,
+pinctrl-single;
+
Re: [PATCH 4/8] gpio: omap: drop 'gpio' param from omap_gpio_init_irq()
On Thu, Mar 19, 2015 at 6:25 PM, grygorii.stras...@linaro.org wrote: From: Grygorii Strashko grygorii.stras...@linaro.org The 'gpio' parameter isn't needed any more as it duplicates 'offset' parameter, so drop it. Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org Acked-by: Javier Martinez Canillas jav...@dowhile0.org -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 23/35] ARM: OMAP2+: id: cache omap_type value
There is no need to read the register with every invocation of the function,
as the value is constant. Thus, cache the value in a static variable.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/id.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 2a2f4d5..f8121db 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -52,7 +52,10 @@ EXPORT_SYMBOL(omap_rev);
int omap_type(void)
{
- u32 val = 0;
+ static u32 val = OMAP2_DEVICETYPE_MASK;
+
+ if (val OMAP2_DEVICETYPE_MASK)
+ return val;
if (cpu_is_omap24xx()) {
val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 35/35] ARM: OMAP4+: control: add support for initializing control module via DT
OMAP4, OMAP5 and DRA7 now parse DT entries for control module address spaces,
and set up syscon mappings appropriately. Low level IO init is updated to
remove the legacy control module mappings for these devices also.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/control.c |3 +++
arch/arm/mach-omap2/io.c |6 +++---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 5c16953..aeaf1e6 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -650,6 +650,9 @@ static const struct of_device_id omap_scrm_dt_match_table[]
= {
{ .compatible = ti,omap2-scm, .data = omap2_ctrl_data },
{ .compatible = ti,omap3-scm, .data = omap2_ctrl_data },
{ .compatible = ti,dm816-scrm, .data = ctrl_data },
+ { .compatible = ti,omap4-scm-core, .data = ctrl_data },
+ { .compatible = ti,omap5-scm-core, .data = ctrl_data },
+ { .compatible = ti,dra7-scm-core, .data = ctrl_data },
{ }
};
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 6c39cc0..7743e367 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -631,8 +631,8 @@ void __init omap4430_init_early(void)
{
omap2_set_globals_tap(OMAP443X_CLASS,
OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
- omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
+ omap2_control_base_init();
omap4xxx_check_revision();
omap4xxx_check_features();
omap2_prcm_base_init();
@@ -659,8 +659,8 @@ void __init omap5_init_early(void)
{
omap2_set_globals_tap(OMAP54XX_CLASS,
OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
- omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+ omap2_control_base_init();
omap4_pm_init_early();
omap2_prcm_base_init();
omap5xxx_check_revision();
@@ -684,8 +684,8 @@ void __init omap5_init_late(void)
void __init dra7xx_init_early(void)
{
omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
- omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+ omap2_control_base_init();
omap4_pm_init_early();
omap2_prcm_base_init();
dra7xxx_check_revision();
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 27/35] ARM: dts: am33xx: add minimal l4 bus layout with control module support
This patch creates an l4_wkup interconnect for AM33xx, and moves some of
the generic peripherals under it. System control module nodes are moved
under this new interconnect also, and the SCM clock layout is changed
to use the renamed SCM node as the clock provider.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
Documentation/devicetree/bindings/arm/omap/l4.txt |1 +
.../devicetree/bindings/arm/omap/prcm.txt |2 +-
arch/arm/boot/dts/am33xx-clocks.dtsi |2 +-
arch/arm/boot/dts/am33xx.dtsi | 87 +++-
arch/arm/mach-omap2/control.c |2 +-
5 files changed, 51 insertions(+), 43 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt
b/Documentation/devicetree/bindings/arm/omap/l4.txt
index 6402022..d333f0a 100644
--- a/Documentation/devicetree/bindings/arm/omap/l4.txt
+++ b/Documentation/devicetree/bindings/arm/omap/l4.txt
@@ -6,6 +6,7 @@ Required properties:
- compatible : Should be ti,omap2-l4 for OMAP2 family l4 core bus
Should be ti,omap2-l4-wkup for OMAP2 family l4 wkup bus
Should be ti,omap3-l4-core for OMAP3 family l4 core bus
+ Should be ti,am3-l4-wkup for AM33xx family l4 wkup bus
- ranges : contains the IO map range for the bus
Examples:
diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt
b/Documentation/devicetree/bindings/arm/omap/prcm.txt
index ef5a74b..c8e2027 100644
--- a/Documentation/devicetree/bindings/arm/omap/prcm.txt
+++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
@@ -10,7 +10,7 @@ documentation about the individual clock/clockdomain nodes.
Required properties:
- compatible: Must be one of:
ti,am3-prcm
- ti,am3-scrm
+ ti,am3-scm
ti,am4-prcm
ti,am4-scrm
ti,omap2-prcm
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi
b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 712edce..236c78a 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-scrm_clocks {
+scm_clocks {
sys_clkin_ck: sys_clkin_ck {
#clock-cells = 0;
compatible = ti,mux-clock;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index acd3705..8d26261 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -83,20 +83,6 @@
};
};
- am33xx_control_module: control_module@4a002000 {
- compatible = syscon;
- reg = 0x44e1 0x7fc;
- };
-
- am33xx_pinmux: pinmux@44e10800 {
- compatible = pinctrl-single;
- reg = 0x44e10800 0x0238;
- #address-cells = 1;
- #size-cells = 0;
- pinctrl-single,register-width = 32;
- pinctrl-single,function-mask = 0x7f;
- };
-
/*
* XXX: Use a flat representation of the AM33XX interconnect.
* The real AM33XX interconnect network is quite complex. Since
@@ -111,37 +97,58 @@
ranges;
ti,hwmods = l3_main;
- prcm: prcm@44e0 {
- compatible = ti,am3-prcm;
- reg = 0x44e0 0x4000;
-
- prcm_clocks: clocks {
- #address-cells = 1;
- #size-cells = 0;
- };
+ l4_wkup: l4_wkup@44c0 {
+ compatible = ti,am3-l4-wkup, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x44c0 0x28;
- prcm_clockdomains: clockdomains {
- };
- };
+ prcm: prcm@20 {
+ compatible = ti,am3-prcm;
+ reg = 0x20 0x4000;
- scrm: scrm@44e1 {
- compatible = ti,am3-scrm;
- reg = 0x44e1 0x2000;
+ prcm_clocks: clocks {
+ #address-cells = 1;
+ #size-cells = 0;
+ };
- scrm_clocks: clocks {
- #address-cells = 1;
- #size-cells = 0;
+ prcm_clockdomains: clockdomains {
+ };
};
- scrm_clockdomains: clockdomains {
+ scm: scm@21 {
+ compatible = ti,am3-scm, simple-bus;
+ reg = 0x21 0x2000;
+
[PATCHv5 25/35] ARM: dts: omap24xx: add minimal l4 bus layout with control module support
This patch creates an l4 / l4-wkup interconnects for omap2420 / omap2430
SoCs, and moves some of the generic peripherals under it. System control
module nodes are moved under this new interconnect also, and the SCM
clock layout is changed to use the new SCM node as the clock provider.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
Documentation/devicetree/bindings/arm/omap/l4.txt | 17
.../devicetree/bindings/arm/omap/prcm.txt |2 +-
arch/arm/boot/dts/omap2420.dtsi| 80 +--
arch/arm/boot/dts/omap2430-clocks.dtsi |8 +-
arch/arm/boot/dts/omap2430.dtsi| 107 +++-
arch/arm/boot/dts/omap24xx-clocks.dtsi |6 +-
arch/arm/mach-omap2/control.c |7 +-
7 files changed, 140 insertions(+), 87 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/omap/l4.txt
diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt
b/Documentation/devicetree/bindings/arm/omap/l4.txt
new file mode 100644
index 000..57569cc8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/l4.txt
@@ -0,0 +1,17 @@
+L4 interconnect bindings
+
+These bindings describe the OMAP SoCs L4 interconnect bus.
+
+Required properties:
+- compatible : Should be ti,omap2-l4 for OMAP2 family l4 core bus
+ Should be ti,omap2-l4-wkup for OMAP2 family l4 wkup bus
+- ranges : contains the IO map range for the bus
+
+Examples:
+
+l4: l4@4800 {
+ compatible ti,omap2-l4, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x4800 0x10;
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt
b/Documentation/devicetree/bindings/arm/omap/prcm.txt
index 68f96f8..cce8365 100644
--- a/Documentation/devicetree/bindings/arm/omap/prcm.txt
+++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
@@ -14,7 +14,7 @@ Required properties:
ti,am4-prcm
ti,am4-scrm
ti,omap2-prcm
- ti,omap2-scrm
+ ti,omap2-scm
ti,omap3-prm
ti,omap3-cm
ti,omap3-scrm
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index e2b2e93..5b9a376 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -14,47 +14,65 @@
compatible = ti,omap2420, ti,omap2;
ocp {
- prcm: prcm@48008000 {
- compatible = ti,omap2-prcm;
- reg = 0x48008000 0x1000;
+ l4: l4@4800 {
+ compatible = ti,omap2-l4, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x4800 0x10;
- prcm_clocks: clocks {
- #address-cells = 1;
- #size-cells = 0;
- };
+ prcm: prcm@8000 {
+ compatible = ti,omap2-prcm;
+ reg = 0x8000 0x1000;
- prcm_clockdomains: clockdomains {
- };
- };
+ prcm_clocks: clocks {
+ #address-cells = 1;
+ #size-cells = 0;
+ };
- scrm: scrm@4800 {
- compatible = ti,omap2-scrm;
- reg = 0x4800 0x1000;
+ prcm_clockdomains: clockdomains {
+ };
+ };
- scrm_clocks: clocks {
+ scm: scm@0 {
+ compatible = ti,omap2-scm, simple-bus;
+ reg = 0x0 0x1000;
#address-cells = 1;
- #size-cells = 0;
+ #size-cells = 1;
+ ranges = 0 0x0 0x1000;
+
+ omap2420_pmx: pinmux@30 {
+ compatible = ti,omap2420-padconf,
+pinctrl-single;
+ reg = 0x30 0x0113;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-single,register-width = 8;
+ pinctrl-single,function-mask = 0x3f;
+ };
+
+ scm_conf: scm_conf@270 {
+ compatible = syscon;
+ reg = 0x270 0x100;
+ #address-cells = 1;
+
Re: [PATCH 6/8] gpio: omap: get rid of GPIO_BIT() macro
On Fri, Mar 20, 2015 at 5:50 PM, santosh.shilim...@oracle.com santosh.shilim...@oracle.com wrote: On 3/19/15 10:25 AM, grygorii.stras...@linaro.org wrote: From: Grygorii Strashko grygorii.stras...@linaro.org Now OMAP GPIO driver prepared for GPIO_BIT() macro removing. Do it ;) Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org --- Thanks for the cleanup Grygorii. Acked-by: Santosh Shilimkar ssant...@kernel.org Indeed! Acked-by: Javier Martinez Canillas jav...@dowhile0.org -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/8] gpio: omap: convert omap_gpio_is_input() to use gpio offset
On Fri, Mar 20, 2015 at 5:42 PM, santosh.shilim...@oracle.com santosh.shilim...@oracle.com wrote: On 3/19/15 10:25 AM, grygorii.stras...@linaro.org wrote: From: Grygorii Strashko grygorii.stras...@linaro.org Convert omap_gpio_is_input() to use GPIO offset instead of mask and, in such way, make code simpler and remove few lines of code. Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org --- Acked-by: Santosh Shilimkar ssant...@kernel.org Acked-by: Javier Martinez Canillas jav...@dowhile0.org -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 28/35] ARM: dts: am43xx-epos-evm: fix pinmux node layout
Pinmux node should be a reference to the base one, not a complete re-write
of it. Having the node like this also prevents modifying the node layout
in the base am4372.dtsi file, which is needed for control module changes.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 84 +-
1 file changed, 42 insertions(+), 42 deletions(-)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 257c099..72f01bb 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -69,7 +69,48 @@
};
};
- am43xx_pinmux: pinmux@44e10800 {
+ matrix_keypad: matrix_keypad@0 {
+ compatible = gpio-matrix-keypad;
+ debounce-delay-ms = 5;
+ col-scan-delay-us = 2;
+
+ row-gpios = gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12
*/
+gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13
*/
+gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14
*/
+gpio0 15 GPIO_ACTIVE_HIGH; /* Bank0, pin15
*/
+
+ col-gpios = gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9
*/
+gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10
*/
+gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18
*/
+gpio2 19 GPIO_ACTIVE_HIGH; /* Bank2, pin19
*/
+
+ linux,keymap = 0x0201 /* P1 */
+ 0x01000204 /* P4 */
+ 0x02000207 /* P7 */
+ 0x0300020a /* NUMERIC_STAR */
+ 0x00010202 /* P2 */
+ 0x01010205 /* P5 */
+ 0x02010208 /* P8 */
+ 0x03010200 /* P0 */
+ 0x00020203 /* P3 */
+ 0x01020206 /* P6 */
+ 0x02020209 /* P9 */
+ 0x0302020b /* NUMERIC_POUND */
+ 0x00030067 /* UP */
+ 0x0103006a /* RIGHT */
+ 0x0203006c /* DOWN */
+ 0x03030069;/* LEFT */
+ };
+
+ backlight {
+ compatible = pwm-backlight;
+ pwms = ecap0 0 5 PWM_POLARITY_INVERTED;
+ brightness-levels = 0 51 53 56 62 75 101 152 255;
+ default-brightness-level = 8;
+ };
+};
+
+am43xx_pinmux {
cpsw_default: cpsw_default {
pinctrl-single,pins =
/* Slave 1 */
@@ -279,47 +320,6 @@
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN |
MUX_MODE7)
;
};
- };
-
- matrix_keypad: matrix_keypad@0 {
- compatible = gpio-matrix-keypad;
- debounce-delay-ms = 5;
- col-scan-delay-us = 2;
-
- row-gpios = gpio0 12 GPIO_ACTIVE_HIGH /*
Bank0, pin12 */
-gpio0 13 GPIO_ACTIVE_HIGH /*
Bank0, pin13 */
-gpio0 14 GPIO_ACTIVE_HIGH /*
Bank0, pin14 */
-gpio0 15 GPIO_ACTIVE_HIGH; /*
Bank0, pin15 */
-
- col-gpios = gpio3 9 GPIO_ACTIVE_HIGH /*
Bank3, pin9 */
-gpio3 10 GPIO_ACTIVE_HIGH /*
Bank3, pin10 */
-gpio2 18 GPIO_ACTIVE_HIGH /*
Bank2, pin18 */
-gpio2 19 GPIO_ACTIVE_HIGH; /*
Bank2, pin19 */
-
- linux,keymap = 0x0201 /* P1 */
- 0x01000204 /* P4 */
- 0x02000207 /* P7 */
- 0x0300020a /* NUMERIC_STAR */
- 0x00010202 /* P2 */
- 0x01010205 /* P5 */
- 0x02010208 /* P8 */
- 0x03010200 /* P0 */
- 0x00020203 /* P3 */
- 0x01020206 /* P6 */
- 0x02020209 /* P9 */
- 0x0302020b /* NUMERIC_POUND */
- 0x00030067 /* UP */
- 0x0103006a /* RIGHT */
- 0x0203006c /* DOWN */
- 0x03030069;/* LEFT */
- };
-
- backlight {
- compatible = pwm-backlight;
- pwms = ecap0 0 5 PWM_POLARITY_INVERTED;
- brightness-levels = 0 51 53 56 62
[PATCHv5 32/35] ARM: OMAP4+: control: remove support for legacy pad read/write
omap4_ctrl_pad_readl/writel are no longer used by anybody, so remove
these. Syscon / pinctrl should be used to access the padconf area
instead.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/control.c | 24 +---
arch/arm/mach-omap2/control.h |5 +
arch/arm/mach-omap2/io.c | 11 ---
3 files changed, 6 insertions(+), 34 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index c673854..5c16953 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -36,7 +36,6 @@
static void __iomem *omap2_ctrl_base;
static s16 omap2_ctrl_offset;
-static void __iomem *omap4_ctrl_pad_base;
static struct regmap *omap2_ctrl_syscon;
#if defined(CONFIG_ARCH_OMAP3) defined(CONFIG_PM)
@@ -139,13 +138,9 @@ struct omap3_control_regs {
static struct omap3_control_regs control_context;
#endif /* CONFIG_ARCH_OMAP3 CONFIG_PM */
-#define OMAP4_CTRL_PAD_REGADDR(reg)(omap4_ctrl_pad_base + (reg))
-
-void __init omap2_set_globals_control(void __iomem *ctrl,
- void __iomem *ctrl_pad)
+void __init omap2_set_globals_control(void __iomem *ctrl)
{
omap2_ctrl_base = ctrl;
- omap4_ctrl_pad_base = ctrl_pad;
}
u8 omap_ctrl_readb(u16 offset)
@@ -218,23 +213,6 @@ void omap_ctrl_writel(u32 val, u16 offset)
val);
}
-/*
- * On OMAP4 control pad are not addressable from control
- * core base. So the common omap_ctrl_read/write APIs breaks
- * Hence export separate APIs to manage the omap4 pad control
- * registers. This APIs will work only for OMAP4
- */
-
-u32 omap4_ctrl_pad_readl(u16 offset)
-{
- return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
-}
-
-void omap4_ctrl_pad_writel(u32 val, u16 offset)
-{
- writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset));
-}
-
#ifdef CONFIG_ARCH_OMAP3
/**
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 5353ff4..80d2b7d 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -443,11 +443,9 @@
extern u8 omap_ctrl_readb(u16 offset);
extern u16 omap_ctrl_readw(u16 offset);
extern u32 omap_ctrl_readl(u16 offset);
-extern u32 omap4_ctrl_pad_readl(u16 offset);
extern void omap_ctrl_writeb(u8 val, u16 offset);
extern void omap_ctrl_writew(u16 val, u16 offset);
extern void omap_ctrl_writel(u32 val, u16 offset);
-extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
extern void omap3_save_scratchpad_contents(void);
extern void omap3_clear_scratchpad_contents(void);
@@ -465,8 +463,7 @@ extern int omap3_ctrl_save_padconf(void);
void omap3_ctrl_init(void);
int omap2_control_base_init(void);
int omap_control_init(void);
-extern void omap2_set_globals_control(void __iomem *ctrl,
- void __iomem *ctrl_pad);
+void omap2_set_globals_control(void __iomem *ctrl);
void __init omap3_control_legacy_iomap_init(void);
#else
#define omap_ctrl_readb(x) 0
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index c3fa739..6c39cc0 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -443,7 +443,7 @@ void __init omap3_init_early(void)
/* XXX: remove these once OMAP3 is DT only */
if (!of_have_populated_dt()) {
omap2_set_globals_control(
- OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), NULL);
+ OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
NULL);
@@ -631,8 +631,7 @@ void __init omap4430_init_early(void)
{
omap2_set_globals_tap(OMAP443X_CLASS,
OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
- omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
- OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
+ omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
omap4xxx_check_revision();
omap4xxx_check_features();
@@ -660,8 +659,7 @@ void __init omap5_init_early(void)
{
omap2_set_globals_tap(OMAP54XX_CLASS,
OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
- omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
- OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
+ omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap4_pm_init_early();
omap2_prcm_base_init();
@@ -686,8 +684,7 @@ void __init omap5_init_late(void)
void __init dra7xx_init_early(void)
{
omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
-
[PATCHv5 31/35] ARM: OMAP4: display: convert display to use syscon for dsi muxing
The legacy control module APIs will be gone, thus convert the display
driver to use syscon. This change should eventually be moved to
display driver from the board directory.
Signed-off-by: Tero Kristo t-kri...@ti.com
Cc: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/mach-omap2/display.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 7a050f9..f492ae1 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -26,6 +26,8 @@
#include linux/of.h
#include linux/of_platform.h
#include linux/slab.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
#include video/omapdss.h
#include omap_hwmod.h
@@ -104,6 +106,10 @@ static const struct omap_dss_hwmod_data
omap4_dss_hwmod_data[] __initconst = {
{ dss_hdmi, omapdss_hdmi, -1 },
};
+#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
+
+static struct regmap *omap4_dsi_mux_syscon;
+
static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
{
u32 enable_mask, enable_shift;
@@ -124,7 +130,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
return -ENODEV;
}
- reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
+ regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
reg = ~enable_mask;
reg = ~pipd_mask;
@@ -132,7 +138,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
reg |= (lanes enable_shift) enable_mask;
reg |= (lanes pipd_shift) pipd_mask;
- omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
+ regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
return 0;
}
@@ -665,5 +671,10 @@ int __init omapdss_init_of(void)
return r;
}
+ /* add DSI info for omap4 */
+ node = of_find_node_by_name(NULL, omap4_padconf_global);
+ if (node)
+ omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
+
return 0;
}
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 22/35] ARM: OMAP2+: control: remove API for getting control module base address
This shall not be used anymore, as control module driver is converted
into using regmap.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/control.c |5 -
arch/arm/mach-omap2/control.h |2 --
2 files changed, 7 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 4b40946..202fc72 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -145,11 +145,6 @@ void __init omap2_set_globals_control(void __iomem *ctrl,
omap4_ctrl_pad_base = ctrl_pad;
}
-void __iomem *omap_ctrl_base_get(void)
-{
- return omap2_ctrl_base;
-}
-
u8 omap_ctrl_readb(u16 offset)
{
return readb_relaxed(OMAP_CTRL_REGADDR(offset));
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index c1057eb..5353ff4 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -440,7 +440,6 @@
#ifndef __ASSEMBLY__
#ifdef CONFIG_ARCH_OMAP2PLUS
-extern void __iomem *omap_ctrl_base_get(void);
extern u8 omap_ctrl_readb(u16 offset);
extern u16 omap_ctrl_readw(u16 offset);
extern u32 omap_ctrl_readl(u16 offset);
@@ -470,7 +469,6 @@ extern void omap2_set_globals_control(void __iomem *ctrl,
void __iomem *ctrl_pad);
void __init omap3_control_legacy_iomap_init(void);
#else
-#define omap_ctrl_base_get() 0
#define omap_ctrl_readb(x) 0
#define omap_ctrl_readw(x) 0
#define omap_ctrl_readl(x) 0
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 34/35] ARM: dts: dra7: add minimal l4 bus layout with control module support
This patch creates the l4_cfg and l4_wkup interconnects for DRA7, and
moves some of the generic peripherals under it. System control module
support is added to the device tree also, and the existing SCM related
functionality is moved under it.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/arm/omap/ctrl.txt |1 +
Documentation/devicetree/bindings/arm/omap/l4.txt |2 +
arch/arm/boot/dts/dra7.dtsi| 166 +++-
3 files changed, 96 insertions(+), 73 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt
b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
index acb68ed..3a4e590 100644
--- a/Documentation/devicetree/bindings/arm/omap/ctrl.txt
+++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
@@ -23,6 +23,7 @@ Required properties:
ti,omap4-scm-padconf-core
ti,omap5-scm-core
ti,omap5-scm-padconf-core
+ ti,dra7-scm-core
- reg: Contains Control Module register address range
(base address and length)
diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt
b/Documentation/devicetree/bindings/arm/omap/l4.txt
index 2fe4211..b4f8a16 100644
--- a/Documentation/devicetree/bindings/arm/omap/l4.txt
+++ b/Documentation/devicetree/bindings/arm/omap/l4.txt
@@ -10,6 +10,8 @@ Required properties:
Should be ti,omap4-l4-wkup for OMAP4 family l4 wkup bus
Should be ti,omap5-l4-cfg for OMAP5 family l4 cfg bus
Should be ti,omap5-l4-wkup for OMAP5 family l4 wkup bus
+ Should be ti,dra7-l4-cfg for DRA7 family l4 cfg bus
+ Should be ti,dra7-l4-wkup for DRA7 family l4 wkup bus
Should be ti,am3-l4-wkup for AM33xx family l4 wkup bus
Should be ti,am4-l4-wkup for AM43xx family l4 wkup bus
- ranges : contains the IO map range for the bus
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5827fed..8e50ca3 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -94,17 +94,101 @@
interrupts = GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH,
GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH;
- prm: prm@4ae06000 {
- compatible = ti,dra7-prm;
- reg = 0x4ae06000 0x3000;
- interrupts = GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH;
+ l4_cfg: l4@4a00 {
+ compatible = ti,dra7-l4-cfg, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x4a00 0x22c000;
- prm_clocks: clocks {
+ scm: scm@2000 {
+ compatible = ti,dra7-scm-core, simple-bus;
+ reg = 0x2000 0x2000;
#address-cells = 1;
- #size-cells = 0;
+ #size-cells = 1;
+ ranges = 0 0x2000 0x2000;
+
+ scm_conf: scm_conf@0 {
+ compatible = syscon;
+ reg = 0x0 0x1400;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ pbias_regulator: pbias_regulator {
+ compatible = ti,pbias-omap;
+ reg = 0xe00 0x4;
+ syscon = scm_conf;
+ pbias_mmc_reg: pbias_mmc_omap5 {
+ regulator-name =
pbias_mmc_omap5;
+ regulator-min-microvolt
= 180;
+ regulator-max-microvolt
= 300;
+ };
+ };
+ };
+
+ dra7_pmx_core: pinmux@1400 {
+ compatible = ti,dra7-padconf,
+pinctrl-single;
+ reg = 0x1400 0x0464;
+ #address-cells = 1;
+ #size-cells = 0;
+ #interrupt-cells = 1;
+ interrupt-controller;
+ pinctrl-single,register-width = 32;
+ pinctrl-single,function-mask =
0x3fff;
+ };
+ };
+
+ cm_core_aon: cm_core_aon@5000 {
+
Re: [PATCH 5/8] gpio: omap: convert gpio irq functions to use GPIO offset
On Fri, Mar 20, 2015 at 5:49 PM, santosh.shilim...@oracle.com santosh.shilim...@oracle.com wrote: On 3/19/15 10:25 AM, grygorii.stras...@linaro.org wrote: From: Grygorii Strashko grygorii.stras...@linaro.org Convert GPIO IRQ functions to use GPIO offset instead of system GPIO numbers. This allows to drop unneeded conversations between system GPIO - GPIO offset which are done in many places and many times. It is safe to do now because: - gpiolib always passes GPIO offset to GPIO controller - OMAP GPIO driver converted to use IRQ domain, so struct irq_data-hwirq contains GPIO offset This is preparation step before removing: #define GPIO_INDEX(bank, gpio) #define GPIO_BIT(bank, gpio) int omap_irq_to_gpio() Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org --- Once you take care of the bisect/build issue, feel free to add Acked-by: Santosh Shilimkar ssant...@kernel.org Same for me, after the rebase/split fixup: Acked-by: Javier Martinez Canillas jav...@dowhile0.org -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv5 30/35] ARM: dts: omap4: add minimal l4 bus layout with control module support
This patch creates the l4_cfg and l4_wkup interconnects for OMAP4, and
moves some of the generic peripherals under it. System control module
support is added to the device tree also, and the existing SCM related
functionality is moved under it.
Signed-off-by: Tero Kristo t-kri...@ti.com
Reported-by: Tony Lindgren t...@atomide.com
---
.../devicetree/bindings/arm/omap/ctrl.txt | 76
Documentation/devicetree/bindings/arm/omap/l4.txt |2 +
.../devicetree/bindings/arm/omap/prcm.txt |6 -
arch/arm/boot/dts/omap4.dtsi | 200
4 files changed, 199 insertions(+), 85 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/omap/ctrl.txt
diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt
b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
new file mode 100644
index 000..2675881
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
@@ -0,0 +1,76 @@
+OMAP Control Module bindings
+
+Control Module contains miscellaneous features under it based on SoC type.
+Pincontrol is one common feature, and it has a specialized support
+described in [1]. Typically some clock nodes are also under control module.
+Syscon is used to share register level access to drivers external to
+control module driver itself.
+
+See [2] for documentation about clock/clockdomain nodes.
+
+[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+[2] Documentation/devicetree/bindings/clock/ti/*
+
+Required properties:
+- compatible: Must be one of:
+ ti,am3-scm
+ ti,am4-scm
+ ti,dm814-scrm
+ ti,dm816-scrm
+ ti,omap2-scm
+ ti,omap3-scm
+ ti,omap4-scm-core
+ ti,omap4-scm-padconf-core
+- reg: Contains Control Module register address range
+ (base address and length)
+
+Optional properties:
+- clocks: clocks for this module
+- clockdomains:clockdomains for this module
+
+Examples:
+
+scm: scm@2000 {
+ compatible = ti,omap3-scm, simple-bus;
+ reg = 0x2000 0x2000;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x2000 0x2000;
+
+ omap3_pmx_core: pinmux@30 {
+ compatible = ti,omap3-padconf,
+pinctrl-single;
+ reg = 0x30 0x230;
+ #address-cells = 1;
+ #size-cells = 0;
+ #interrupt-cells = 1;
+ interrupt-controller;
+ pinctrl-single,register-width = 16;
+ pinctrl-single,function-mask = 0xff1f;
+ };
+
+ scm_conf: scm_conf@270 {
+ compatible = syscon;
+ reg = 0x270 0x330;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ scm_clocks: clocks {
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+ };
+
+ scm_clockdomains: clockdomains {
+ };
+}
+
+scm_clocks {
+ mcbsp5_mux_fck: mcbsp5_mux_fck {
+ #clock-cells = 0;
+ compatible = ti,composite-mux-clock;
+ clocks = core_96m_fck, mcbsp_clks;
+ ti,bit-shift = 4;
+ reg = 0x02d8;
+ };
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt
b/Documentation/devicetree/bindings/arm/omap/l4.txt
index 941b914..de18cfa 100644
--- a/Documentation/devicetree/bindings/arm/omap/l4.txt
+++ b/Documentation/devicetree/bindings/arm/omap/l4.txt
@@ -6,6 +6,8 @@ Required properties:
- compatible : Should be ti,omap2-l4 for OMAP2 family l4 core bus
Should be ti,omap2-l4-wkup for OMAP2 family l4 wkup bus
Should be ti,omap3-l4-core for OMAP3 family l4 core bus
+ Should be ti,omap4-l4-cfg for OMAP4 family l4 cfg bus
+ Should be ti,omap4-l4-wkup for OMAP4 family l4 wkup bus
Should be ti,am3-l4-wkup for AM33xx family l4 wkup bus
Should be ti,am4-l4-wkup for AM43xx family l4 wkup bus
- ranges : contains the IO map range for the bus
diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt
b/Documentation/devicetree/bindings/arm/omap/prcm.txt
index 8af4f32..3eb6d7a 100644
--- a/Documentation/devicetree/bindings/arm/omap/prcm.txt
+++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
@@ -10,14 +10,10 @@ documentation about the individual clock/clockdomain nodes.
Required properties:
- compatible: Must be one of:
ti,am3-prcm
- ti,am3-scm
ti,am4-prcm
- ti,am4-scm
ti,omap2-prcm
- ti,omap2-scm
ti,omap3-prm
ti,omap3-cm
- ti,omap3-scm
ti,omap4-cm1
ti,omap4-prm
ti,omap4-cm2
@@ -30,9 +26,7 @@ Required properties:
ti,dra7-cm-core-aon
[PATCHv5 20/35] ARM: OMAP4+: PRM: get rid of cpu_is_omap44xx calls from interrupt init
The compatible DT node is now passed with the prm init, so there is no
need to do node matching here again. Added a new flag to the init data
also, to detect default IRQ support for OMAP4. Also, any booting omap4
DT setup always has a PRM node, so there is no need to check against
the special case where it would be missing.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/prm.h|6 +++--
arch/arm/mach-omap2/prm44xx.c| 54 +++---
arch/arm/mach-omap2/prm_common.c |2 +-
3 files changed, 26 insertions(+), 36 deletions(-)
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 3936e6c..233bc84 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -29,9 +29,11 @@ int omap2_prcm_base_init(void);
*
* PRM_HAS_IO_WAKEUP: has IO wakeup capability
* PRM_HAS_VOLTAGE: has voltage domains
+ * PRM_IRQ_DEFAULT: use default irq number for PRM irq
*/
-#define PRM_HAS_IO_WAKEUP (1 0)
-#define PRM_HAS_VOLTAGE(1 1)
+#define PRM_HAS_IO_WAKEUP BIT(0)
+#define PRM_HAS_VOLTAGEBIT(1)
+#define PRM_IRQ_DEFAULTBIT(2)
/*
* MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 243133c..c35ad0b 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -703,10 +703,14 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
.vp_clear_txdone= omap4_prm_vp_clear_txdone,
};
+static const struct omap_prcm_init_data *prm_init_data;
+
int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
{
omap_prm_base_init();
+ prm_init_data = data;
+
if (data-flags PRM_HAS_IO_WAKEUP)
prm_features |= PRM_HAS_IO_WAKEUP;
@@ -718,16 +722,8 @@ int __init omap44xx_prm_init(const struct
omap_prcm_init_data *data)
return prm_register(omap44xx_prm_ll_data);
}
-static const struct of_device_id omap_prm_dt_match_table[] = {
- { .compatible = ti,omap4-prm },
- { .compatible = ti,omap5-prm },
- { .compatible = ti,dra7-prm },
- { }
-};
-
static int omap44xx_prm_late_init(void)
{
- struct device_node *np;
int irq_num;
if (!(prm_features PRM_HAS_IO_WAKEUP))
@@ -737,31 +733,23 @@ static int omap44xx_prm_late_init(void)
if (!of_have_populated_dt())
return 0;
- np = of_find_matching_node(NULL, omap_prm_dt_match_table);
-
- if (!np) {
- /* Default loaded up with OMAP4 values */
- if (!cpu_is_omap44xx())
- return 0;
- } else {
- irq_num = of_irq_get(np, 0);
- /*
-* Already have OMAP4 IRQ num. For all other platforms, we need
-* IRQ numbers from DT
-*/
- if (irq_num 0 !cpu_is_omap44xx()) {
- if (irq_num == -EPROBE_DEFER)
- return irq_num;
-
- /* Have nothing to do */
- return 0;
- }
-
- /* Once OMAP4 DT is filled as well */
- if (irq_num = 0) {
- omap4_prcm_irq_setup.irq = irq_num;
- omap4_prcm_irq_setup.xlate_irq = NULL;
- }
+ irq_num = of_irq_get(prm_init_data-np, 0);
+ /*
+* Already have OMAP4 IRQ num. For all other platforms, we need
+* IRQ numbers from DT
+*/
+ if (irq_num 0 !(prm_init_data-flags PRM_IRQ_DEFAULT)) {
+ if (irq_num == -EPROBE_DEFER)
+ return irq_num;
+
+ /* Have nothing to do */
+ return 0;
+ }
+
+ /* Once OMAP4 DT is filled as well */
+ if (irq_num = 0) {
+ omap4_prcm_irq_setup.irq = irq_num;
+ omap4_prcm_irq_setup.xlate_irq = NULL;
}
omap44xx_prm_enable_io_wakeup();
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index ebb24ad..e48241e 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -669,7 +669,7 @@ static struct omap_prcm_init_data omap4_prm_data __initdata
= {
.index = TI_CLKM_PRM,
.init = omap44xx_prm_init,
.device_inst_offset = OMAP4430_PRM_DEVICE_INST,
- .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE,
+ .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE | PRM_IRQ_DEFAULT,
};
#endif
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] omapdss: extend pm notifier to handle hibernation
On 03/20/2015 05:21 PM, Tomi Valkeinen wrote:
On 20/03/15 16:57, grygorii.stras...@linaro.org wrote:
On 03/20/2015 02:20 PM, Tomi Valkeinen wrote:
On 25/02/15 19:03, grygorii.stras...@linaro.org wrote:
From: Grygorii Strashko grygorii.stras...@linaro.org
Add handling of missed events in omap_dss_pm_notif which are
needed to support hibernation (suspend to disk).
Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org
---
drivers/video/fbdev/omap2/dss/core.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/video/fbdev/omap2/dss/core.c
b/drivers/video/fbdev/omap2/dss/core.c
index 6b74f73..e60976a 100644
--- a/drivers/video/fbdev/omap2/dss/core.c
+++ b/drivers/video/fbdev/omap2/dss/core.c
@@ -178,11 +178,15 @@ static int omap_dss_pm_notif(struct notifier_block
*b, unsigned long v, void *d)
DSSDBG(pm notif %lu\n, v);
switch (v) {
+ case PM_HIBERNATION_PREPARE:
case PM_SUSPEND_PREPARE:
+ case PM_RESTORE_PREPARE:
DSSDBG(suspending displays\n);
return dss_suspend_all_devices();
case PM_POST_SUSPEND:
+ case PM_POST_HIBERNATION:
+ case PM_POST_RESTORE:
DSSDBG(resuming displays\n);
return dss_resume_all_devices();
Why suspend displays when PM_RESTORE_PREPARE happens? Why resume when
PM_POST_RESTORE happens?
We have following sequence when system is restored from hibernation:
- original kernel booted;
- late_initcall_sync(software_resume);
- pm_notifier_call_chain(PM_RESTORE_PREPARE);
- freeze_processes
- check read hibernation image
- suspend all devices (.freeze())
- jump to stored kernel
- restore devices
...
So, all devices should be in frozen/suspended state when we will jump to
stored kernel
(device's state should be the same as before creating hib image).
Without this patch I can see a lot of log messages like below:
Yes, I am sure a fix is needed for hibernation. But I still don't quite
understand PM_RESTORE_PREPARE and PM_POST_RESTORE.
When we enter hibernation, there's only PM_HIBERNATION_PREPARE?
No. There is always PM_POST_HIBERNATION:
- original Kernel in case of failure
- restored Kernel on success
When waking from hibernation, there's first PM_RESTORE_PREPARE, where we
need to disable displays that were enabled during boot. Then either
PM_POST_HIBERNATION if all went well, or PM_POST_RESTORE if there was an
error, and in both cases we want to enable the displays?
Yes.
int hibernate(void)
error = pm_notifier_call_chain(PM_HIBERNATION_PREPARE);
...
error = hibernation_snapshot(hibernation_mode == HIBERNATION_PLATFORM);
^^^ restored kernel will start from here
if (error || freezer_test_done)
goto Free_bitmaps;
if (in_suspend) {
...
pr_debug(PM: writing image.\n);
error = swsusp_write(flags);
swsusp_free();
if (!error)
power_down();
in_suspend = 0;
pm_restore_gfp_mask();
^^ this part will be executed by Kernel requested Hibernation
} else {
pr_debug(PM: Image restored successfully.\n);
^^ this part will be executed by Kernel restored from
Hibernation
}
...
pm_notifier_call_chain(PM_POST_HIBERNATION);
^^^ Both Kernels will be notified here:
- original Kernel in case of failure
- restored Kernel on success
static int software_resume(void)
error = pm_notifier_call_chain(PM_RESTORE_PREPARE);
error = swsusp_read(flags);
swsusp_close(FMODE_READ);
if (!error)
hibernation_restore(flags SF_PLATFORM_MODE);
^^^ if ok we will never return from this function
printk(KERN_ERR PM: Failed to load hibernation image, recovering.\n);
pm_notifier_call_chain(PM_POST_RESTORE);
^^^
if fail - just continue work as usual
--
regards,
-grygorii
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/8] gpio: omap: convert omap_gpio_is_input() to use gpio offset
On 3/19/15 10:25 AM, grygorii.stras...@linaro.org wrote: From: Grygorii Strashko grygorii.stras...@linaro.org Convert omap_gpio_is_input() to use GPIO offset instead of mask and, in such way, make code simpler and remove few lines of code. Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org --- Acked-by: Santosh Shilimkar ssant...@kernel.org -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/8] gpio: omap: simplify omap_set_gpio_dataout_x()
On 3/19/15 10:25 AM, grygorii.stras...@linaro.org wrote: From: Grygorii Strashko grygorii.stras...@linaro.org Both functions omap_set_gpio_dataout_reg() and omap_set_gpio_dataout_mask() accept GPIO offset as 'gpio' input parameter, so rename it to 'offset' and drop usage of GPIO_BIT() macro. Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org --- Acked-by: Santosh Shilimkar ssant...@kernel.org -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/3] OMAP 3 ISP (and N9/N950 primary camera support) dts changes
On Thu, Mar 19, 2015 at 10:28:44AM -0700, Tony Lindgren wrote: * Sakari Ailus sakari.ai...@iki.fi [150318 16:51]: Hi folks, Since v1, I've rebased the set on Tero Kristo's PRCM / SCM cleanup patchset here: URL:http://www.spinics.net/lists/linux-omap/msg116949.html v1 can be found here: URL:http://www.spinics.net/lists/linux-omap/msg116753.html Changes since v1: - Fixed phy reference (number to name) in the example, - Dropped the first patch. This is already done by Tero's patch ARM: dts: omap3: merge control module features under scrm node. Applying these into omap-for-v4.1/dt thanks. Thank you! These patches had been around in some form for way too long already. It's great to see them going in finally! :-) -- Cheers, Sakari Ailus e-mail: sakari.ai...@iki.fi XMPP: sai...@retiisi.org.uk -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 5/6] ARM: dts: add wl12xx/wl18xx bindings
* Kalle Valo kv...@codeaurora.org [150320 08:51]: Tony Lindgren t...@atomide.com writes: * Kalle Valo kv...@codeaurora.org [150319 23:04]: Tony Lindgren t...@atomide.com writes: Tested OK (boot, scan, join, ping) on Pandaboard ES. thanks for testing it! Great. As suggested by Kalle, I'll apply all these into omap-for-v4.1/wl12xx branch and send a pull request for the arm-soc probably on Friday if no issues are found. Great, thank you. Just in case you want this: Acked-by: Kalle Valo kv...@codeaurora.org Thanks, I can push out a new branch omap-for-v4.1/wl12xx-v2 with your acks assuming you or somebody else have not merged the existing omap-for-v4.1/wl12xx branch yet into the wireless tree? In that case I can scrap omap-for-v4.1/wl12xx and then will reply with a commit that we can consider immutable that can be merged into various trees as needed in case of merge conflicts. But I'll wait for your confirmation first :) After John retired we actually have two set of trees now: mac80211 maintained by Johannes and wireless-drivers maintained by me. I haven't pulled anything from your tree and I'm 100% sure Johannes hasn't either. So green light from me. OK, I'll set up the new branch then. I take your ack is for the whole series? If it's just for the $subject patch, please let me know. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 6/8] gpio: omap: get rid of GPIO_BIT() macro
On 3/19/15 10:25 AM, grygorii.stras...@linaro.org wrote: From: Grygorii Strashko grygorii.stras...@linaro.org Now OMAP GPIO driver prepared for GPIO_BIT() macro removing. Do it ;) Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org --- Thanks for the cleanup Grygorii. Acked-by: Santosh Shilimkar ssant...@kernel.org -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/8] gpio: omap: convert gpio irq functions to use GPIO offset
On 3/19/15 10:25 AM, grygorii.stras...@linaro.org wrote: From: Grygorii Strashko grygorii.stras...@linaro.org Convert GPIO IRQ functions to use GPIO offset instead of system GPIO numbers. This allows to drop unneeded conversations between system GPIO - GPIO offset which are done in many places and many times. It is safe to do now because: - gpiolib always passes GPIO offset to GPIO controller - OMAP GPIO driver converted to use IRQ domain, so struct irq_data-hwirq contains GPIO offset This is preparation step before removing: #define GPIO_INDEX(bank, gpio) #define GPIO_BIT(bank, gpio) int omap_irq_to_gpio() Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org --- Once you take care of the bisect/build issue, feel free to add Acked-by: Santosh Shilimkar ssant...@kernel.org -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFT OMAP1 PATCH 7/8] gpio: omap: get rid of omap_irq_to_gpio()
On 03/20/2015 08:56 PM, Javier Martinez Canillas wrote: Hello Grygorii, On Thu, Mar 19, 2015 at 6:25 PM, grygorii.stras...@linaro.org wrote: From: Grygorii Strashko grygorii.stras...@linaro.org Now OMAP GPIO driver prepared for omap_irq_to_gpio() removing. Do it ;) Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org I don't have access to OMAP1 boards to test but Tony did it o an osk5912 and Aaro can confirm that it doesn't cause regressions on other OMAP1 boards. Thanks. But could you clarify one point to me please? Aaro can confirm that it doesn't cause regressions on other OMAP1 boards - Does It mean I can add his Tested-by? Or I still have to wait for his direct reply? Just to avoid any confusions ;) Acked-by: Javier Martinez Canillas jav...@dowhile0.org -- regards, -grygorii -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] ARM: omap5/dra7/x15: Thermal dts patches
Hi, Here are a few pending patches for DRA7/ OMAP5 and patch hooking the GPIO fan to the thermal framework. Tested on BeagleBoard-X15, uEVM with next-20150320. (just load up cpufreq_dt and gpio_fan modules with omap2plus_defconfig, run cpuburn to generate thermal and just wait for the fan to trigger - and it does- we dont hit the frequency throttling temps) The patches are based on git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git branch: omap-for-v4.1/dt-v2 10709c0858d8 ARM: dts: Update Nanobone dts file The patch #3(gpio fan-thermal hookup) depends on (from linus master): 12ca7188468e thermal: Introduce dummy functions when thermal is not defined and the following currently in linux-next(next-20150320) queued for future. b5cf88e46bad (gpio-fan): Add thermal control hooks Keerthy (1): ARM: dts: DRA7: Add bandgap and related thermal nodes Nishanth Menon (1): ARM: dts: am57xx-beagle-x15: Add thermal map Tero Kristo (1): ARM: dts: OMAP5+: separate the cpu thermal zone definition from omap4 arch/arm/boot/dts/am57xx-beagle-x15.dts | 49 ++ arch/arm/boot/dts/dra7.dtsi | 12 arch/arm/boot/dts/dra72x.dtsi|9 ++ arch/arm/boot/dts/dra74x.dtsi|9 ++ arch/arm/boot/dts/omap5-cpu-thermal.dtsi | 41 + arch/arm/boot/dts/omap5.dtsi |2 +- 6 files changed, 121 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/omap5-cpu-thermal.dtsi Regards, Nishanth Menon -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] ARM: dts: OMAP5+: separate the cpu thermal zone definition from omap4
From: Tero Kristo t-kri...@ti.com
OMAP4 has a finer counter granularity, which allows for a delay of 1000ms
in the thermal zone polling intervals. OMAP5/DRA7 have different counter
mechanism, which allows at maximum a 500ms timer. Adjust the cpu thermal
zone accordingly for OMAP5/DRA7.
Signed-off-by: Tero Kristo t-kri...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/boot/dts/omap5-cpu-thermal.dtsi | 41 ++
arch/arm/boot/dts/omap5.dtsi |2 +-
2 files changed, 42 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/omap5-cpu-thermal.dtsi
diff --git a/arch/arm/boot/dts/omap5-cpu-thermal.dtsi
b/arch/arm/boot/dts/omap5-cpu-thermal.dtsi
new file mode 100644
index ..4a6427c1e47e
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-cpu-thermal.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Device Tree Source for OMAP4/5 SoC CPU thermal
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Contact: Tero Kristo t-kri...@ti.com
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed as is without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include dt-bindings/thermal/thermal.h
+
+cpu_thermal: cpu_thermal {
+ polling-delay-passive = 250; /* milliseconds */
+ polling-delay = 500; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = bandgap 0;
+
+ cpu_trips: trips {
+ cpu_alert0: cpu_alert {
+ temperature = 10; /* millicelsius */
+ hysteresis = 2000; /* millicelsius */
+ type = passive;
+ };
+ cpu_crit: cpu_crit {
+ temperature = 125000; /* millicelsius */
+ hysteresis = 2000; /* millicelsius */
+ type = critical;
+ };
+ };
+
+ cpu_cooling_maps: cooling-maps {
+ map0 {
+ trip = cpu_alert0;
+ cooling-device =
+ cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index ddff674bd05e..e650d4eb59dd 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -67,7 +67,7 @@
};
thermal-zones {
- #include omap4-cpu-thermal.dtsi
+ #include omap5-cpu-thermal.dtsi
#include omap5-gpu-thermal.dtsi
#include omap5-core-thermal.dtsi
};
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] ARM: dts: am57xx-beagle-x15: Add thermal map
BeagleBoard-X15 has capability for a fan and has an onboard TMP102
temperature sensor as well. This allows us to create a new thermal
zone (called, un-imaginatively board), and allows us to use some
active cooling as temperatures start edge upward in the system by
creating a new alert temperature (emperically 50C) for cpu.
NOTE: Fan is NOT mounted by default on the platform, in such a case,
all we end up doing is switch on a regulator and leak very minimal
current.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/boot/dts/am57xx-beagle-x15.dts | 49 +++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 41642fe770a1..6a3621c23017 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -86,6 +86,7 @@
gpios = tps659038_gpio 1 GPIO_ACTIVE_HIGH;
gpio-fan,speed-map = 0 0,
13000 1;
+ #cooling-cells = 2;
};
extcon_usb1: extcon_usb1 {
@@ -441,6 +442,7 @@
pinctrl-0 = tmp102_pins_default;
interrupt-parent = gpio7;
interrupts = 16 IRQ_TYPE_LEVEL_LOW;
+ #thermal-sensor-cells = 1;
};
};
@@ -559,3 +561,50 @@
usb2 {
dr_mode = peripheral;
};
+
+cpu_trips {
+ cpu_alert1: cpu_alert1 {
+ temperature = 5; /* millicelsius */
+ hysteresis = 2000; /* millicelsius */
+ type = active;
+ };
+};
+
+cpu_cooling_maps {
+ map1 {
+ trip = cpu_alert1;
+ cooling-device = gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT;
+ };
+};
+
+thermal_zones {
+ board_thermal: board_thermal {
+ polling-delay-passive = 1250; /* milliseconds */
+ polling-delay = 1500; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = tmp102 0;
+
+ board_trips: trips {
+ board_alert0: board_alert {
+ temperature = 4; /* millicelsius */
+ hysteresis = 2000; /* millicelsius */
+ type = active;
+ };
+
+ board_crit: board_crit {
+ temperature = 105000; /* millicelsius */
+ hysteresis = 0; /* millicelsius */
+ type = critical;
+ };
+ };
+
+ board_cooling_maps: cooling-maps {
+ map0 {
+ trip = board_alert0;
+ cooling-device =
+ gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT;
+ };
+ };
+ };
+};
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] ARM: dts: DRA7: Add bandgap and related thermal nodes
From: Keerthy j-keer...@ti.com
Add bandgap and related thermal nodes. The patch adds 5 thermal
sensors. Only one cooling device for mpu as of now. The sensors are
the exact same on both dra72 and dra7.
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 12
arch/arm/boot/dts/dra72x.dtsi |9 +
arch/arm/boot/dts/dra74x.dtsi |9 +
3 files changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index eea4a54d6cb3..4b975cc377fd 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -177,6 +177,18 @@
};
};
+ bandgap: bandgap@4a0021e0 {
+ reg = 0x4a0021e0 0xc
+ 0x4a00232c 0xc
+ 0x4a002380 0x2c
+ 0x4a0023C0 0x3c
+ 0x4a002564 0x8
+ 0x4a002574 0x50;
+ compatible = ti,dra752-bandgap;
+ interrupts = GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH;
+ #thermal-sensor-cells = 1;
+ };
+
cm_core_aon: cm_core_aon@4a005000 {
compatible = ti,dra7-cm-core-aon;
reg = 0x4a005000 0x2000;
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index e5a3d23a3df1..43bd0709bde9 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -20,6 +20,11 @@
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
+
+ /* cooling options */
+ cooling-min-level = 0;
+ cooling-max-level = 2;
+ #cooling-cells = 2; /* min followed by max */
};
};
@@ -27,4 +32,8 @@
compatible = arm,cortex-a15-pmu;
interrupts = GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH;
};
+
+ thermal_zones: thermal-zones {
+ #include omap5-cpu-thermal.dtsi
+ };
};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 10173fab1a15..4f2c870836fe 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -31,6 +31,11 @@
clock-names = cpu;
clock-latency = 30; /* From omap-cpufreq driver */
+
+ /* cooling options */
+ cooling-min-level = 0;
+ cooling-max-level = 2;
+ #cooling-cells = 2; /* min followed by max */
};
cpu@1 {
device_type = cpu;
@@ -45,6 +50,10 @@
GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH;
};
+ thermal_zones: thermal-zones {
+ #include omap5-cpu-thermal.dtsi
+ };
+
ocp {
omap_dwc3_4: omap_dwc3_4@4894 {
compatible = ti,dwc3;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Serious memory leak in TI EDMA driver (drivers/dma/edma.c)
Hi Peter,
yes, that is one of the differences to the EVM that the SD card is on
MMCSD1. This is due to the pin multiplexer and other peripherals we're
using.
Your patch is correct, however the edma_callback() is using the channel
number parameter for debug messages only. For the actual work
echan-ch_num is used. BTW is that correct? Could there be a mismatch
between the echan-ch_num and the ch_num parameter?
Something else seems to be odd in edma_alloc_chan_resources():
/* Alloc channel resources */
static int edma_alloc_chan_resources(struct dma_chan *chan)
{
struct edma_chan *echan = to_edma_chan(chan);
struct device *dev = chan-device-dev;
int ret;
int a_ch_num;
LIST_HEAD(descs);
a_ch_num = edma_alloc_channel(echan-ch_num, edma_callback,
chan, EVENTQ_DEFAULT);
The third parameter to edma_alloc_channel() should be echan, not chan,
since the edma_callback() interprets the callback data parameter as
struct edma_chan *.
Let me know if you find something or if you have an advice for more debug.
Cheers
Petr
On 20.03.2015 14:59, Peter Ujfalusi wrote:
Petr,
On 03/18/2015 11:33 PM, Petr Kulhavy wrote:
Hi Peter,
Yes, we do not use DT.
Our board design is very close to the da850evm reference board. So if you have
a chance of getting hold of it you could try on that one.
I have been trying to reproduce this on my OMAP-L138-EVM (da850evm) but was
not able.
There is a big difference in your an my setup: the MMC on my EVM is connected
to MMC/SD0 interface while in your setup it seams to be connected to MMC/SD1.
The DMA requests for MMC/SD0 is eDMA CC0 16/17, while the MMC/SD1 is eDMA CC1
28/29.
So they are handled by different channel controllers. I would not rule out
that the support for the second CC has issues.
The information from you logs just points to this direction also:
You are writing to the MMC, so CC1 ch29 is active most of the time.
In your log the channel number sometimes 65565 ((1 16) | 29) sometimes it
is 29. In my case it is 17 every time.
I think there is something funny regarding to how these channels on CC1 are
working and this might be causing the leak for you.
Unfortunately I do not have HW where I could use any channel on CC1 so I can
not debug this further, but I'll look at the code to see if anything obvious
stands out.
And something does stand out:
arch/arm/common/edma.c: dma_irq_handler()
It calls the callback with a wrong interrupt number since it does not take
into account the different CC.
Can you try something similar to see if it helps:
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 6c49887d326e..e1d413c61e9e 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -405,7 +405,8 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
BIT(slot));
if (edma_cc[ctlr]-intr_data[channel].callback)
edma_cc[ctlr]-intr_data[channel].callback(
- channel, EDMA_DMA_COMPLETE,
+ EDMA_CTLR_CHAN(ctlr, channel),
+ EDMA_DMA_COMPLETE,
edma_cc[ctlr]-intr_data[channel].data);
}
} while (sh_ipr);
--
--
Petr Kulhavy, MSc
System Architect
*BARIX*
p...@barix.com mailto:p...@barix.com | Skype: brain.barix
Barix AG, Seefeldstrasse 303 | 8008 Zurich, Switzerland
T +41 43 43322 11 | www.barix.com http://www.barix.com
You have received this email because of your relationship Barix AG and
its affiliated companies. Barix AG and its affiliated companies do not
sell or exchange email addresses, or any other personal contact
information provided by you with any third parties. All email
distributions are managed and controlled by Barix AG and its affiliated
companies.
Barix AG, Seefeldstr. 303, 8008 Zürich, Switzerland. Company Reg. No:
CH-020.3.023.869-8, VAT Reg. No: CHE-105.687.663.
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] ARM: dts: DRA7: Add bandgap and related thermal nodes
On Fri, Mar 20, 2015 at 02:47:40PM -0500, Nishanth Menon wrote:
From: Keerthy j-keer...@ti.com
Add bandgap and related thermal nodes. The patch adds 5 thermal
sensors. Only one cooling device for mpu as of now. The sensors are
the exact same on both dra72 and dra7.
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Acked-by: Eduardo Valentin edubez...@gmail.com
---
arch/arm/boot/dts/dra7.dtsi | 12
arch/arm/boot/dts/dra72x.dtsi |9 +
arch/arm/boot/dts/dra74x.dtsi |9 +
3 files changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index eea4a54d6cb3..4b975cc377fd 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -177,6 +177,18 @@
};
};
+ bandgap: bandgap@4a0021e0 {
+ reg = 0x4a0021e0 0xc
+ 0x4a00232c 0xc
+ 0x4a002380 0x2c
+ 0x4a0023C0 0x3c
+ 0x4a002564 0x8
+ 0x4a002574 0x50;
+ compatible = ti,dra752-bandgap;
+ interrupts = GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH;
+ #thermal-sensor-cells = 1;
+ };
+
cm_core_aon: cm_core_aon@4a005000 {
compatible = ti,dra7-cm-core-aon;
reg = 0x4a005000 0x2000;
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index e5a3d23a3df1..43bd0709bde9 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -20,6 +20,11 @@
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
+
+ /* cooling options */
+ cooling-min-level = 0;
+ cooling-max-level = 2;
+ #cooling-cells = 2; /* min followed by max */
};
};
@@ -27,4 +32,8 @@
compatible = arm,cortex-a15-pmu;
interrupts = GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH;
};
+
+ thermal_zones: thermal-zones {
+ #include omap5-cpu-thermal.dtsi
+ };
};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 10173fab1a15..4f2c870836fe 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -31,6 +31,11 @@
clock-names = cpu;
clock-latency = 30; /* From omap-cpufreq driver */
+
+ /* cooling options */
+ cooling-min-level = 0;
+ cooling-max-level = 2;
+ #cooling-cells = 2; /* min followed by max */
};
cpu@1 {
device_type = cpu;
@@ -45,6 +50,10 @@
GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH;
};
+ thermal_zones: thermal-zones {
+ #include omap5-cpu-thermal.dtsi
+ };
+
ocp {
omap_dwc3_4: omap_dwc3_4@4894 {
compatible = ti,dwc3;
--
1.7.9.5
signature.asc
Description: Digital signature
Re: [PATCHv5 27/35] ARM: dts: am33xx: add minimal l4 bus layout with control module support
Hi Tero,
On 03/20/2015 01:44 PM, Kristo, Tero wrote:
This patch creates an l4_wkup interconnect for AM33xx, and moves some of
the generic peripherals under it. System control module nodes are moved
under this new interconnect also, and the SCM clock layout is changed
to use the renamed SCM node as the clock provider.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
Documentation/devicetree/bindings/arm/omap/l4.txt |1 +
.../devicetree/bindings/arm/omap/prcm.txt |2 +-
arch/arm/boot/dts/am33xx-clocks.dtsi |2 +-
arch/arm/boot/dts/am33xx.dtsi | 87
+++-
arch/arm/mach-omap2/control.c |2 +-
5 files changed, 51 insertions(+), 43 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt
b/Documentation/devicetree/bindings/arm/omap/l4.txt
index 6402022..d333f0a 100644
--- a/Documentation/devicetree/bindings/arm/omap/l4.txt
+++ b/Documentation/devicetree/bindings/arm/omap/l4.txt
@@ -6,6 +6,7 @@ Required properties:
- compatible : Should be ti,omap2-l4 for OMAP2 family l4 core bus
Should be ti,omap2-l4-wkup for OMAP2 family l4 wkup bus
Should be ti,omap3-l4-core for OMAP3 family l4 core bus
+Should be ti,am3-l4-wkup for AM33xx family l4 wkup bus
- ranges : contains the IO map range for the bus
Examples:
diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt
b/Documentation/devicetree/bindings/arm/omap/prcm.txt
index ef5a74b..c8e2027 100644
--- a/Documentation/devicetree/bindings/arm/omap/prcm.txt
+++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
@@ -10,7 +10,7 @@ documentation about the individual clock/clockdomain nodes.
Required properties:
- compatible:Must be one of:
ti,am3-prcm
- ti,am3-scrm
+ ti,am3-scm
ti,am4-prcm
ti,am4-scrm
ti,omap2-prcm
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi
b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 712edce..236c78a 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-scrm_clocks {
+scm_clocks {
sys_clkin_ck: sys_clkin_ck {
#clock-cells = 0;
compatible = ti,mux-clock;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index acd3705..8d26261 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -83,20 +83,6 @@
};
};
- am33xx_control_module: control_module@4a002000 {
- compatible = syscon;
- reg = 0x44e1 0x7fc;
- };
-
- am33xx_pinmux: pinmux@44e10800 {
- compatible = pinctrl-single;
- reg = 0x44e10800 0x0238;
- #address-cells = 1;
- #size-cells = 0;
- pinctrl-single,register-width = 32;
- pinctrl-single,function-mask = 0x7f;
- };
-
/*
* XXX: Use a flat representation of the AM33XX interconnect.
* The real AM33XX interconnect network is quite complex. Since
@@ -111,37 +97,58 @@
ranges;
ti,hwmods = l3_main;
- prcm: prcm@44e0 {
- compatible = ti,am3-prcm;
- reg = 0x44e0 0x4000;
-
- prcm_clocks: clocks {
- #address-cells = 1;
- #size-cells = 0;
- };
+ l4_wkup: l4_wkup@44c0 {
+ compatible = ti,am3-l4-wkup, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x44c0 0x28;
- prcm_clockdomains: clockdomains {
- };
- };
+ prcm: prcm@20 {
+ compatible = ti,am3-prcm;
+ reg = 0x20 0x4000;
- scrm: scrm@44e1 {
- compatible = ti,am3-scrm;
- reg = 0x44e1 0x2000;
+ prcm_clocks: clocks {
+ #address-cells = 1;
+ #size-cells = 0;
+ };
- scrm_clocks: clocks {
- #address-cells = 1;
- #size-cells = 0;
+ prcm_clockdomains: clockdomains {
+ };
};
- scrm_clockdomains: clockdomains {
+ scm: scm@21 {
+ compatible = ti,am3-scm, simple-bus;
+
Re: [PATCH 3/3] ARM: dts: am57xx-beagle-x15: Add thermal map
On Fri, Mar 20, 2015 at 02:47:41PM -0500, Nishanth Menon wrote:
BeagleBoard-X15 has capability for a fan and has an onboard TMP102
temperature sensor as well. This allows us to create a new thermal
zone (called, un-imaginatively board), and allows us to use some
active cooling as temperatures start edge upward in the system by
creating a new alert temperature (emperically 50C) for cpu.
NOTE: Fan is NOT mounted by default on the platform, in such a case,
all we end up doing is switch on a regulator and leak very minimal
current.
Signed-off-by: Nishanth Menon n...@ti.com
Acked-by: Eduardo Valentin edubez...@gmail.com
---
arch/arm/boot/dts/am57xx-beagle-x15.dts | 49
+++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 41642fe770a1..6a3621c23017 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -86,6 +86,7 @@
gpios = tps659038_gpio 1 GPIO_ACTIVE_HIGH;
gpio-fan,speed-map = 0 0,
13000 1;
+ #cooling-cells = 2;
};
extcon_usb1: extcon_usb1 {
@@ -441,6 +442,7 @@
pinctrl-0 = tmp102_pins_default;
interrupt-parent = gpio7;
interrupts = 16 IRQ_TYPE_LEVEL_LOW;
+ #thermal-sensor-cells = 1;
};
};
@@ -559,3 +561,50 @@
usb2 {
dr_mode = peripheral;
};
+
+cpu_trips {
+ cpu_alert1: cpu_alert1 {
+ temperature = 5; /* millicelsius */
+ hysteresis = 2000; /* millicelsius */
+ type = active;
+ };
+};
+
+cpu_cooling_maps {
+ map1 {
+ trip = cpu_alert1;
+ cooling-device = gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT;
+ };
+};
+
+thermal_zones {
+ board_thermal: board_thermal {
+ polling-delay-passive = 1250; /* milliseconds */
+ polling-delay = 1500; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = tmp102 0;
+
+ board_trips: trips {
+ board_alert0: board_alert {
+ temperature = 4; /* millicelsius */
+ hysteresis = 2000; /* millicelsius */
+ type = active;
+ };
+
+ board_crit: board_crit {
+ temperature = 105000; /* millicelsius */
+ hysteresis = 0; /* millicelsius */
+ type = critical;
+ };
+ };
+
+ board_cooling_maps: cooling-maps {
+ map0 {
+ trip = board_alert0;
+ cooling-device =
+ gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT;
+ };
+ };
+ };
+};
--
1.7.9.5
signature.asc
Description: Digital signature
Re: [PATCH 1/3] ARM: dts: OMAP5+: separate the cpu thermal zone definition from omap4
On Fri, Mar 20, 2015 at 02:47:39PM -0500, Nishanth Menon wrote:
From: Tero Kristo t-kri...@ti.com
OMAP4 has a finer counter granularity, which allows for a delay of 1000ms
in the thermal zone polling intervals. OMAP5/DRA7 have different counter
mechanism, which allows at maximum a 500ms timer. Adjust the cpu thermal
zone accordingly for OMAP5/DRA7.
Signed-off-by: Tero Kristo t-kri...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/boot/dts/omap5-cpu-thermal.dtsi | 41
++
arch/arm/boot/dts/omap5.dtsi |2 +-
2 files changed, 42 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/omap5-cpu-thermal.dtsi
diff --git a/arch/arm/boot/dts/omap5-cpu-thermal.dtsi
b/arch/arm/boot/dts/omap5-cpu-thermal.dtsi
new file mode 100644
index ..4a6427c1e47e
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-cpu-thermal.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Device Tree Source for OMAP4/5 SoC CPU thermal
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Contact: Tero Kristo t-kri...@ti.com
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed as is without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include dt-bindings/thermal/thermal.h
+
+cpu_thermal: cpu_thermal {
+ polling-delay-passive = 250; /* milliseconds */
+ polling-delay = 500; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = bandgap 0;
+
+ cpu_trips: trips {
+ cpu_alert0: cpu_alert {
+ temperature = 10; /* millicelsius */
+ hysteresis = 2000; /* millicelsius */
+ type = passive;
+ };
+ cpu_crit: cpu_crit {
+ temperature = 125000; /* millicelsius */
+ hysteresis = 2000; /* millicelsius */
+ type = critical;
+ };
+ };
+
+ cpu_cooling_maps: cooling-maps {
+ map0 {
+ trip = cpu_alert0;
+ cooling-device =
+ cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index ddff674bd05e..e650d4eb59dd 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -67,7 +67,7 @@
};
thermal-zones {
- #include omap4-cpu-thermal.dtsi
+ #include omap5-cpu-thermal.dtsi
Can't we simple change the polling value for the omap5 case and reuse
the omap4 file?
#include omap5-gpu-thermal.dtsi
#include omap5-core-thermal.dtsi
};
--
1.7.9.5
signature.asc
Description: Digital signature
