Re: [PATCH] usb: dwc3: core: continue probe even if usb3 phy is not available
Felipe Balbi ba...@ti.com writes:
On Wed, Jun 26, 2013 at 05:37:19PM +0530, George Cherian wrote:
On 6/26/2013 3:46 PM, Felipe Balbi wrote:
Hi,
On Wed, Jun 26, 2013 at 02:59:14PM +0530, George Cherian wrote:
There can be configurations in which DWC3 is hoooked up only to USB2 PHY.
In such cases we should not return -EPROBE_DEFER, rather continue probe
even if there is no USB3 PHY.
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/dwc3/core.c | 31 ---
1 file changed, 24 insertions(+), 7 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index c35d49d..d5e6f3e 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -100,7 +100,9 @@ static void dwc3_core_soft_reset(struct dwc3 *dwc)
dwc3_writel(dwc-regs, DWC3_GUSB2PHYCFG(0), reg);
usb_phy_init(dwc-usb2_phy);
- usb_phy_init(dwc-usb3_phy);
+
+ if (dwc-usb3_phy)
+ usb_phy_init(dwc-usb3_phy);
I would feel more comfortable if you would move our maximum_speed module
parameter to DT with a property such as:
snps,maximum_speed = highspeed;
then on driver you could:
okay
ret = of_property_read_string(np, snps,maximum_speed, maximum_speed);
if (ret 0)
bailout();
if (strncmp(maximum_speed, superspeed, 10) == 0) {
/* grab USB3 PHY, return EPROBE_DEFER if not found */
grab_usb3_phy();
}
if ((strncmp(maximum_speed, highspeed, 9) == 0) ||
(strncmp(maximum_speed, fullspeed, 9) == 0) ||
(strncmp(maximum_speed, lowspeed, 8) == 0)) {
/* grab USB2 PHY, return EPROBE_DEFER if not found */
grab_usb2_phy();
}
this way, we depend solely on setting maximum_speed to highspeed for
AM437x :-)
In dra7xx one instance is superspeed and one instance highspeed.
right, but in DT you will define both instances and each instance will
have a seaparate snps,maximum_speed attribute :-)
I'm now considering if we should make maximum_speed a generic attribute,
Kishon ? Alex ? Alan ?
anyone else needs such thing ?
We have a force-full-speed attibute for chipidea on the way. This
maximum_speed looks like a more generic alternative. Michael, what say
you?
Regards,
--
Alex
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Re: [PATCH 4/8] ARM: etm: Allow range selection
On Mon, Feb 14, 2011 at 10:11:12PM -0800, Arve Hjønnevåg wrote:
Trace kernel text segment by default as before, allow tracing of other
ranges by writing a range to /sys/devices/etm/trace_range, or to trace
everything by writing 0 0.
Since you're adding this, I think it might make sense to add a 3rd optional
ctx id field, so that userspace tracing is also possible, especially when
on-chip ETB sizes increase to something more sensible than what they are
these days.
Thanks!
Signed-off-by: Arve Hjønnevåg a...@android.com
---
arch/arm/kernel/etm.c | 49
++---
1 files changed, 46 insertions(+), 3 deletions(-)
diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c
index bc7d8f2..8a1c422 100644
--- a/arch/arm/kernel/etm.c
+++ b/arch/arm/kernel/etm.c
@@ -40,12 +40,17 @@ struct tracectx {
unsigned long flags;
int ncmppairs;
int etm_portsz;
+ unsigned long range_start;
+ unsigned long range_end;
struct device *dev;
struct clk *emu_clk;
struct mutexmutex;
};
-static struct tracectx tracer;
+static struct tracectx tracer = {
+ .range_start = (unsigned long)_stext,
+ .range_end = (unsigned long)_etext,
+};
static inline bool trace_isrunning(struct tracectx *t)
{
@@ -115,8 +120,12 @@ static int trace_start(struct tracectx *t)
return -EFAULT;
}
- etm_setup_address_range(t, 1, (unsigned long)_stext,
- (unsigned long)_etext, 0, 0);
+ if (t-range_start || t-range_end)
+ etm_setup_address_range(t, 1,
+ t-range_start, t-range_end, 0, 0);
+ else
+ etm_writel(t, ETMTE_INCLEXCL, ETMR_TRACEENCTRL);
+
etm_writel(t, 0, ETMR_TRACEENCTRL2);
etm_writel(t, 0, ETMR_TRACESSCTRL);
etm_writel(t, 0x6f, ETMR_TRACEENEVT);
@@ -525,6 +534,35 @@ static ssize_t trace_mode_store(struct kobject *kobj,
static struct kobj_attribute trace_mode_attr =
__ATTR(trace_mode, 0644, trace_mode_show, trace_mode_store);
+static ssize_t trace_range_show(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, %08lx %08lx\n,
+ tracer.range_start, tracer.range_end);
+}
+
+static ssize_t trace_range_store(struct kobject *kobj,
+struct kobj_attribute *attr,
+const char *buf, size_t n)
+{
+ unsigned long range_start, range_end;
+
+ if (sscanf(buf, %lx %lx, range_start, range_end) != 2)
+ return -EINVAL;
+
+ mutex_lock(tracer.mutex);
+ tracer.range_start = range_start;
+ tracer.range_end = range_end;
+ mutex_unlock(tracer.mutex);
+
+ return n;
+}
+
+
+static struct kobj_attribute trace_range_attr =
+ __ATTR(trace_range, 0644, trace_range_show, trace_range_store);
+
static int __init etm_probe(struct amba_device *dev, struct amba_id *id)
{
struct tracectx *t = tracer;
@@ -576,6 +614,10 @@ static int __init etm_probe(struct amba_device *dev,
struct amba_id *id)
if (ret)
dev_dbg(dev-dev, Failed to create trace_mode in sysfs\n);
+ ret = sysfs_create_file(dev-dev.kobj, trace_range_attr.attr);
+ if (ret)
+ dev_dbg(dev-dev, Failed to create trace_range in sysfs\n);
+
dev_dbg(t-dev, ETM AMBA driver initialized.\n);
out:
@@ -605,6 +647,7 @@ static int etm_remove(struct amba_device *dev)
sysfs_remove_file(dev-dev.kobj, trace_running_attr.attr);
sysfs_remove_file(dev-dev.kobj, trace_info_attr.attr);
sysfs_remove_file(dev-dev.kobj, trace_mode_attr.attr);
+ sysfs_remove_file(dev-dev.kobj, trace_range_attr.attr);
return 0;
}
--
1.7.3.1
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Try 3, ETM/JTAG components states across OFF modes
This is a rebased version of the previously posted patchset, only omap patches included this time. It depends on a etm patch [1] (won't compile without it), which is still in incoming queue of Russell's patch tracker. [1] http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6291/1 Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] omap3: move EMU peripheral addresses to a platform header
These addresses are also needed for the OFF code to save/restore the
contexts of the EMU peripherals correctly.
Signed-off-by: Alexander Shishkin virtu...@slind.org
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
---
arch/arm/mach-omap2/emu.c| 14 --
arch/arm/plat-omap/include/plat/io.h | 20
2 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
index 9c442e2..6b41745 100644
--- a/arch/arm/mach-omap2/emu.c
+++ b/arch/arm/mach-omap2/emu.c
@@ -24,19 +24,13 @@
MODULE_LICENSE(GPL);
MODULE_AUTHOR(Alexander Shishkin);
-/* Cortex CoreSight components within omap3xxx EMU */
-#define ETM_BASE (L4_EMU_34XX_PHYS + 0x1)
-#define DBG_BASE (L4_EMU_34XX_PHYS + 0x11000)
-#define ETB_BASE (L4_EMU_34XX_PHYS + 0x1b000)
-#define DAPCTL (L4_EMU_34XX_PHYS + 0x1d000)
-
static struct amba_device omap3_etb_device = {
.dev= {
.init_name = etb,
},
.res= {
- .start = ETB_BASE,
- .end= ETB_BASE + SZ_4K - 1,
+ .start = OMAP34XX_ETB_PHYS,
+ .end= OMAP34XX_ETB_PHYS + OMAP34XX_ETB_SIZE - 1,
.flags = IORESOURCE_MEM,
},
.periphid = 0x000bb907,
@@ -47,8 +41,8 @@ static struct amba_device omap3_etm_device = {
.init_name = etm,
},
.res= {
- .start = ETM_BASE,
- .end= ETM_BASE + SZ_4K - 1,
+ .start = OMAP34XX_ETM_PHYS,
+ .end= OMAP34XX_ETM_PHYS + OMAP34XX_ETM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
.periphid = 0x102bb921,
diff --git a/arch/arm/plat-omap/include/plat/io.h
b/arch/arm/plat-omap/include/plat/io.h
index 128b549..81f736a 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -185,6 +185,26 @@
/* 3430 IVA - currently unmapped */
+#define OMAP34XX_DBG_OFFSET(0x00011000)
+#define OMAP34XX_DBG_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_DBG_OFFSET)
+#define OMAP34XX_DBG_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_DBG_OFFSET)
+#define OMAP34XX_DBG_SIZE SZ_4K
+
+#define OMAP34XX_ETM_OFFSET(0x0001)
+#define OMAP34XX_ETM_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_ETM_OFFSET)
+#define OMAP34XX_ETM_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_ETM_OFFSET)
+#define OMAP34XX_ETM_SIZE SZ_4K
+
+#define OMAP34XX_ETB_OFFSET(0x0001b000)
+#define OMAP34XX_ETB_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_ETB_OFFSET)
+#define OMAP34XX_ETB_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_ETB_OFFSET)
+#define OMAP34XX_ETB_SIZE SZ_4K
+
+#define OMAP34XX_DAP_OFFSET(0x0001d000)
+#define OMAP34XX_DAP_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_DAP_OFFSET)
+#define OMAP34XX_DAP_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_DAP_OFFSET)
+#define OMAP34XX_DAP_SIZE SZ_4K
+
/*
*
* Omap4 specific IO mapping
--
1.7.2.1.45.gb66c2
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[PATCH 3/3] omap3: make coresight register save across OFF modes a sysfs option
This adds a sysfs file at /sys/power/coresight_save which is used to
control if the ETM and debug components' states should be saved and
restored across OFF modes.
Signed-off-by: Alexander Shishkin virtu...@slind.org
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
---
arch/arm/mach-omap2/Makefile|1 +
arch/arm/mach-omap2/debug34xx.c | 66 +++
arch/arm/mach-omap2/pm.h|6 +++
arch/arm/mach-omap2/pm34xx.c|3 ++
4 files changed, 76 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/debug34xx.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 88d3a1e..0545dd8 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o
+obj-$(CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG) += debug34xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
diff --git a/arch/arm/mach-omap2/debug34xx.c b/arch/arm/mach-omap2/debug34xx.c
new file mode 100644
index 000..698e83a
--- /dev/null
+++ b/arch/arm/mach-omap2/debug34xx.c
@@ -0,0 +1,66 @@
+/*
+ * Control saving and restoring of coresight components' state during
+ * OFF mode.
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/sysfs.h
+#include linux/kobject.h
+
+#include pm.h
+
+/*
+ * Pointer to a place in sram where the ETM/debug state save
+ * flag is. It can be calculated after the omap_sram_idle is
+ * pushed to sram.
+ */
+static unsigned int *_etm_save;
+
+/*
+ * sysfs file /sys/power/coresight_save controls whether the
+ * state of coresight components should be saved and restored
+ * across OFF modes.
+ */
+static ssize_t coresight_save_show(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, %u\n, *_etm_save);
+}
+
+static ssize_t coresight_save_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t n)
+{
+ unsigned int value;
+
+ if (sscanf(buf, %u, value) != 1)
+ return -EINVAL;
+
+ *_etm_save = !!value;
+
+ return n;
+}
+
+static struct kobj_attribute coresight_save_attr =
+ __ATTR(coresight_save, 0644, coresight_save_show, coresight_save_store);
+
+int omap3_coresight_pm_init(void *sram_addr)
+{
+ int ret;
+
+ /* the last word from the top of omap_sram_idle */
+ _etm_save = (unsigned *)((u8 *)sram_addr + omap34xx_cpu_suspend_sz - 4);
+
+ ret = sysfs_create_file(power_kobj, coresight_save_attr.attr);
+
+ return ret;
+}
+
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 3de6ece..0321834 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -76,6 +76,12 @@ extern void omap34xx_cpu_suspend(u32 *addr, int save_state);
extern void save_secure_ram_context(u32 *addr);
extern void omap3_save_scratchpad_contents(void);
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+int omap3_coresight_pm_init(void *sram_addr);
+#else
+#define omap3_coresight_pm_init(x) do {} while (0)
+#endif
+
extern unsigned int omap24xx_idle_loop_suspend_sz;
extern unsigned int omap34xx_suspend_sz;
extern unsigned int save_secure_ram_context_sz;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7b03426..8f925db 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -1098,6 +1098,9 @@ static int __init omap3_pm_init(void)
core_clkdm = clkdm_lookup(core_clkdm);
omap_push_sram_idle();
+
+ omap3_coresight_pm_init(_omap_sram_idle);
+
#ifdef CONFIG_SUSPEND
suspend_set_ops(omap_pm_ops);
#endif /* CONFIG_SUSPEND */
--
1.7.2.1.45.gb66c2
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[PATCH 2/3] save and restore etm state across core OFF modes
This prevents ETM stalls whenever core enters OFF mode. Original patch
author is Richard Woodruff r-woodru...@ti.com.
This version of the patch makes use of the ETM OS save/restore mechanism,
which takes about 55 words in omap3_arm_context[] instead of 128. Also,
saving ETM context can be switched on/off at runtime.
Signed-off-by: Alexander Shishkin virtu...@slind.org
Cc: Richard Woodruff r-woodru...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
---
arch/arm/mach-omap2/Kconfig | 12 +++
arch/arm/mach-omap2/control.c |2 +-
arch/arm/mach-omap2/sleep34xx.S | 135 +
arch/arm/plat-omap/include/plat/control.h |2 +-
4 files changed, 149 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b48bacf..b00d719 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -243,6 +243,18 @@ config MACH_OMAP4_PANDA
default y
depends on ARCH_OMAP4
+config ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+ bool Enable hardware emulation context save and restore
+ depends on ARCH_OMAP3
+ default y
+ help
+ This option enables the code that controls the capability to
+ save and restore JTAG ETM debugging across power states. It
+ may be required when using the ETM/ETB tracing driver or an
+ external debugging hardware.
+ Without this option emulation features' states are reset across
+ OFF mode state changes.
+
config OMAP3_EMU
bool OMAP3 debugging peripherals
depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index a8d20ee..22dd240 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -93,7 +93,7 @@ void *omap3_secure_ram_storage;
* The address is stored in scratchpad, so that it can be used
* during the restore path.
*/
-u32 omap3_arm_context[128];
+u32 omap3_arm_context[256];
struct omap3_control_regs {
u32 sysconfig;
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index ba53191..c7a77c5 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -28,6 +28,7 @@
#include asm/assembler.h
#include mach/io.h
#include plat/control.h
+#include asm/hardware/coresight.h
#include cm.h
#include prm.h
@@ -226,6 +227,18 @@ loop:
nop
bl wait_sdrc_ok
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+ /*
+* Restore Coresight debug registers
+*/
+ ldr r6, debug_vbase /* base Vaddr of CortexA8-Debug */
+ ldr r4, debug_xlar_key /* get lock key for OSLAR */
+ bl unlock_debug/* remove global lock if set */
+ ldr r6, etm_vbase /* base Vaddr of ETM */
+ bl unlock_debug/* remove global lock if set */
+ str r6, [r6, #ETMMR_OSLAR] /* clear OSLAR lock using non-key */
+#endif
+
ldmfd sp!, {r0-r12, pc} @ restore regs and return
restore_es3:
/*b restore_es3*/ @ Enable to debug restore code
@@ -385,6 +398,44 @@ logic_l1_restore:
/*normal memory remap register */
MCR p15, 0, r5, c10, c2, 1
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+ /*
+* Restore Coresight debug registers
+*/
+ ldr r6, debug_pbase /* base paddr of CortexA8-Debug */
+ ldr r4, debug_xlar_key /* get lock key for OSLAR */
+ bl unlock_debug/* remove global lock if set */
+ str r4, [r6, #ETMMR_OSLAR] /* reset-pointer (already locked) */
+ ldr r4, [r6, #ETMMR_OSSRR] /* dummy read */
+ ldr r4, [r3], #4/* load save size */
+ cmp r4, #0 /* check for zero */
+debug_restore:
+ itttne /* t2/compat if-then block */
+ ldrne r5, [r3], #4/* get saved value */
+ strne r5, [r6,#ETMMR_OSSRR] /* restore saved value */
+ subnes r4, r4, #1 /* decrement loop */
+ bne debug_restore /* loop till done */
+ str r5, [r6, #ETMMR_OSSRR] /* clear lock */
+ /*
+* Restore CoreSight ETM registers
+*/
+ ldr r6, etm_pbase /* base paddr of ETM */
+ ldr r4, debug_xlar_key /* get lock key for OSLAR */
+ bl unlock_debug/* remove global lock if set */
+ str r4, [r6, #ETMMR_OSLAR] /* reset-pointer (already locked) */
+ ldr r4, [r6, #ETMMR_OSSRR] /* dummy read */
+ ldr r4, [r3], #4/* load save size */
+ cmp r4, #0
Re: [PATCH 12/14] omap2/3: Fix initcalls for multi-omap
On Tue, Jan 26, 2010 at 12:13:04 -0800, Tony Lindgren wrote:
Otherwise the wrong initcalls can run.
Signed-off-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/clock2xxx.c |2 +-
arch/arm/mach-omap2/clock34xx.c |2 +-
arch/arm/mach-omap2/emu.c |3 +++
May I ask what stopped you from CCing me on this patch?
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index 43e7404..1a31b72 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -598,7 +598,7 @@ static int __init omap2_clk_arch_init(void)
struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck;
unsigned long sys_ck_rate;
- if (!mpurate)
+ if (!(cpu_is_omap24xx() mpurate))
return -EINVAL;
virt_prcm_set = clk_get(NULL, virt_prcm_set);
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index f485a89..03720bc 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -317,7 +317,7 @@ static int __init omap2_clk_arch_init(void)
struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
unsigned long osc_sys_rate;
- if (!mpurate)
+ if (!(cpu_is_omap34xx() mpurate))
return -EINVAL;
/* XXX test these for success */
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
index ec0d984..9c442e2 100644
--- a/arch/arm/mach-omap2/emu.c
+++ b/arch/arm/mach-omap2/emu.c
@@ -56,6 +56,9 @@ static struct amba_device omap3_etm_device = {
static int __init emu_init(void)
{
+ if (!cpu_is_omap34xx())
+ return -ENODEV;
+
amba_device_register(omap3_etb_device, iomem_resource);
amba_device_register(omap3_etm_device, iomem_resource);
Regards,
--
Alex
--
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Re: [PATCH 7/7] omap3: make coresight register save across OFF modes a sysfs option
On Sun, Jul 25, 2010 at 08:05:20 +0300, Alexander Shishkin wrote: This adds a sysfs file at /sys/power/coresight_save which is used to control if the ETM and debug components' states should be saved and restored across OFF modes. The non-omap patches are merged to Russell's tree, so these three are the only remaining. This one won't apply to linux-omap master any more because of the pm44xx in the makefile, but should be ok otherwise. It would still apply to linus' tree. So, should I rediff it, resend it or just drop it, because it's not needed? Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 6/7] save and restore etm state across core OFF modes
On Sun, Jul 25, 2010 at 08:05:19 +0300, Alexander Shishkin wrote: This prevents ETM stalls whenever core enters OFF mode. Original patch author is Richard Woodruff r-woodru...@ti.com. This version of the patch makes use of the ETM OS save/restore mechanism, which takes about 55 words in omap3_arm_context[] instead of 128. Also, saving ETM context can be switched on/off at runtime. Can I have some (n)acks on this one and 7/7 as well? Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] omap3: make coresight register save across OFF modes a sysfs option
On Mon, Jul 26, 2010 at 12:28:38 +0530, Shilimkar, Santosh wrote:
-Original Message-
From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-
ow...@vger.kernel.org] On Behalf Of Alexander Shishkin
Sent: Monday, July 26, 2010 2:34 AM
To: Hari Kanigeri
Cc: Alexander Shishkin; linux-arm-ker...@lists.infradead.org; Tony
Lindgren; Russell King; Paul Walmsley; Kevin Hilman; linux-
o...@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: [PATCH] omap3: make coresight register save across OFF modes a
sysfs option
This adds a sysfs file at /sys/power/coresight_save which is used to
control if the ETM and debug components' states should be saved and
restored across OFF modes.
Signed-off-by: Alexander Shishkin virtu...@slind.org
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
---
arch/arm/mach-omap2/Makefile|1 +
arch/arm/mach-omap2/debug34xx.c | 66
+++
arch/arm/mach-omap2/pm.h|6 +++
arch/arm/mach-omap2/pm34xx.c|3 ++
4 files changed, 76 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/debug34xx.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f5b4ff4..3a64ce4 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -49,6 +49,7 @@ ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o
+obj-$(CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG) += debug34xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
diff --git a/arch/arm/mach-omap2/debug34xx.c b/arch/arm/mach-
omap2/debug34xx.c
new file mode 100644
index 000..698e83a
--- /dev/null
+++ b/arch/arm/mach-omap2/debug34xx.c
@@ -0,0 +1,66 @@
+/*
+ * Control saving and restoring of coresight components' state during
+ * OFF mode.
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/sysfs.h
+#include linux/kobject.h
+
+#include pm.h
+
+/*
+ * Pointer to a place in sram where the ETM/debug state save
+ * flag is. It can be calculated after the omap_sram_idle is
+ * pushed to sram.
+ */
+static unsigned int *_etm_save;
+
+/*
+ * sysfs file /sys/power/coresight_save controls whether the
+ * state of coresight components should be saved and restored
+ * across OFF modes.
+ */
+static ssize_t coresight_save_show(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, %u\n, *_etm_save);
+}
+
+static ssize_t coresight_save_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t n)
+{
+ unsigned int value;
+
+ if (sscanf(buf, %u, value) != 1)
+ return -EINVAL;
+
+ *_etm_save = !!value;
+
+ return n;
+}
+
+static struct kobj_attribute coresight_save_attr =
+ __ATTR(coresight_save, 0644, coresight_save_show,
coresight_save_store);
+
+int omap3_coresight_pm_init(void *sram_addr)
+{
+ int ret;
+
+ /* the last word from the top of omap_sram_idle */
+ _etm_save = (unsigned *)((u8 *)sram_addr + omap34xx_cpu_suspend_sz -
4);
+
+ ret = sysfs_create_file(power_kobj, coresight_save_attr.attr);
+
+ return ret;
+}
Looking at content of this file, I think you can keep this under common
pm-debug.c file.
Any problems with that ?
I was trying to avoid #ifdeffing too much and I didn't want this code to
compile at all when CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG is not set.
Otherwise, no problems.
Regards,
--
Alex
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Re: [PATCH] omap3: make coresight register save across OFF modes a sysfs option
On Mon, Jul 26, 2010 at 02:01:14 +0530, Shilimkar, Santosh wrote:
-Original Message-
From: Alexander Shishkin [mailto:virtu...@slind.org]
Sent: Monday, July 26, 2010 1:02 PM
To: Shilimkar, Santosh
Cc: Hari Kanigeri; linux-arm-ker...@lists.infradead.org; Tony Lindgren;
Russell King; Paul Walmsley; Kevin Hilman; linux-omap@vger.kernel.org;
linux-ker...@vger.kernel.org
Subject: Re: [PATCH] omap3: make coresight register save across OFF modes
a sysfs option
On Mon, Jul 26, 2010 at 12:28:38 +0530, Shilimkar, Santosh wrote:
-Original Message-
From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-
ow...@vger.kernel.org] On Behalf Of Alexander Shishkin
Sent: Monday, July 26, 2010 2:34 AM
To: Hari Kanigeri
Cc: Alexander Shishkin; linux-arm-ker...@lists.infradead.org; Tony
Lindgren; Russell King; Paul Walmsley; Kevin Hilman; linux-
o...@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: [PATCH] omap3: make coresight register save across OFF modes
a
sysfs option
This adds a sysfs file at /sys/power/coresight_save which is used to
control if the ETM and debug components' states should be saved and
restored across OFF modes.
Signed-off-by: Alexander Shishkin virtu...@slind.org
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
---
arch/arm/mach-omap2/Makefile|1 +
arch/arm/mach-omap2/debug34xx.c | 66
+++
arch/arm/mach-omap2/pm.h|6 +++
arch/arm/mach-omap2/pm34xx.c|3 ++
4 files changed, 76 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/debug34xx.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-
omap2/Makefile
index f5b4ff4..3a64ce4 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -49,6 +49,7 @@ ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
cpuidle34xx.o
+obj-$(CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG) += debug34xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
diff --git a/arch/arm/mach-omap2/debug34xx.c b/arch/arm/mach-
omap2/debug34xx.c
new file mode 100644
index 000..698e83a
--- /dev/null
+++ b/arch/arm/mach-omap2/debug34xx.c
@@ -0,0 +1,66 @@
+/*
+ * Control saving and restoring of coresight components' state during
+ * OFF mode.
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or
modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/sysfs.h
+#include linux/kobject.h
+
+#include pm.h
+
+/*
+ * Pointer to a place in sram where the ETM/debug state save
+ * flag is. It can be calculated after the omap_sram_idle is
+ * pushed to sram.
+ */
+static unsigned int *_etm_save;
+
+/*
+ * sysfs file /sys/power/coresight_save controls whether the
+ * state of coresight components should be saved and restored
+ * across OFF modes.
+ */
+static ssize_t coresight_save_show(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, %u\n, *_etm_save);
+}
+
+static ssize_t coresight_save_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t n)
+{
+ unsigned int value;
+
+ if (sscanf(buf, %u, value) != 1)
+ return -EINVAL;
+
+ *_etm_save = !!value;
+
+ return n;
+}
+
+static struct kobj_attribute coresight_save_attr =
+ __ATTR(coresight_save, 0644, coresight_save_show,
coresight_save_store);
+
+int omap3_coresight_pm_init(void *sram_addr)
+{
+ int ret;
+
+ /* the last word from the top of omap_sram_idle */
+ _etm_save = (unsigned *)((u8 *)sram_addr +
omap34xx_cpu_suspend_sz -
4);
+
+ ret = sysfs_create_file(power_kobj, coresight_save_attr.attr);
+
+ return ret;
+}
Looking at content of this file, I think you can keep this under common
pm-debug.c file.
Any problems
[PATCH 6/7] save and restore etm state across core OFF modes
This prevents ETM stalls whenever core enters OFF mode. Original patch
author is Richard Woodruff r-woodru...@ti.com.
This version of the patch makes use of the ETM OS save/restore mechanism,
which takes about 55 words in omap3_arm_context[] instead of 128. Also,
saving ETM context can be switched on/off at runtime.
Signed-off-by: Alexander Shishkin virtu...@slind.org
Cc: Richard Woodruff r-woodru...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
---
arch/arm/mach-omap2/Kconfig |9 ++
arch/arm/mach-omap2/control.c |2 +-
arch/arm/mach-omap2/sleep34xx.S | 135 +
arch/arm/plat-omap/include/plat/control.h |2 +-
4 files changed, 146 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b48bacf..0413d88 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -243,6 +243,15 @@ config MACH_OMAP4_PANDA
default y
depends on ARCH_OMAP4
+config ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+ bool Enable hardware emulation context save and restore
+ depends on ARCH_OMAP3
+ default y
+ help
+ This option enables JTAG ETM debugging across power states.
+ With out this option emulation features are reset across OFF
+ mode state changes.
+
config OMAP3_EMU
bool OMAP3 debugging peripherals
depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index a8d20ee..22dd240 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -93,7 +93,7 @@ void *omap3_secure_ram_storage;
* The address is stored in scratchpad, so that it can be used
* during the restore path.
*/
-u32 omap3_arm_context[128];
+u32 omap3_arm_context[256];
struct omap3_control_regs {
u32 sysconfig;
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index d522cd7..cd6a1d4 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -28,6 +28,7 @@
#include asm/assembler.h
#include mach/io.h
#include plat/control.h
+#include asm/hardware/coresight.h
#include cm.h
#include prm.h
@@ -226,6 +227,18 @@ loop:
nop
bl wait_sdrc_ok
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+ /*
+* Restore Coresight debug registers
+*/
+ ldr r6, debug_vbase /* base Vaddr of CortexA8-Debug */
+ ldr r4, debug_xlar_key /* get lock key for OSLAR */
+ bl unlock_debug/* remove global lock if set */
+ ldr r6, etm_vbase /* base Vaddr of ETM */
+ bl unlock_debug/* remove global lock if set */
+ str r6, [r6, #ETMMR_OSLAR] /* clear OSLAR lock using non-key */
+#endif
+
ldmfd sp!, {r0-r12, pc} @ restore regs and return
restore_es3:
/*b restore_es3*/ @ Enable to debug restore code
@@ -385,6 +398,44 @@ logic_l1_restore:
/*normal memory remap register */
MCR p15, 0, r5, c10, c2, 1
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+ /*
+* Restore Coresight debug registers
+*/
+ ldr r6, debug_pbase /* base paddr of CortexA8-Debug */
+ ldr r4, debug_xlar_key /* get lock key for OSLAR */
+ bl unlock_debug/* remove global lock if set */
+ str r4, [r6, #ETMMR_OSLAR] /* reset-pointer (already locked) */
+ ldr r4, [r6, #ETMMR_OSSRR] /* dummy read */
+ ldr r4, [r3], #4/* load save size */
+ cmp r4, #0 /* check for zero */
+debug_restore:
+ itttne /* t2/compat if-then block */
+ ldrne r5, [r3], #4/* get saved value */
+ strne r5, [r6,#ETMMR_OSSRR] /* restore saved value */
+ subnes r4, r4, #1 /* decrement loop */
+ bne debug_restore /* loop till done */
+ str r5, [r6, #ETMMR_OSSRR] /* clear lock */
+ /*
+* Restore CoreSight ETM registers
+*/
+ ldr r6, etm_pbase /* base paddr of ETM */
+ ldr r4, debug_xlar_key /* get lock key for OSLAR */
+ bl unlock_debug/* remove global lock if set */
+ str r4, [r6, #ETMMR_OSLAR] /* reset-pointer (already locked) */
+ ldr r4, [r6, #ETMMR_OSSRR] /* dummy read */
+ ldr r4, [r3], #4/* load save size */
+ cmp r4, #0 /* check for zero */
+ beq etm_skip
+etm_restore:
+ ldrne r5, [r3], #4/* get saved value */
+ strne r5, [r6, #ETMMR_OSSRR] /* restore saved
[PATCH 5/7] omap3: move EMU peripheral addresses to a platform header
These addresses are also needed for the OFF code to save/restore the
contexts of the EMU peripherals correctly.
Signed-off-by: Alexander Shishkin virtu...@slind.org
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
---
arch/arm/mach-omap2/emu.c| 14 --
arch/arm/plat-omap/include/plat/io.h | 20
2 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
index 9c442e2..6b41745 100644
--- a/arch/arm/mach-omap2/emu.c
+++ b/arch/arm/mach-omap2/emu.c
@@ -24,19 +24,13 @@
MODULE_LICENSE(GPL);
MODULE_AUTHOR(Alexander Shishkin);
-/* Cortex CoreSight components within omap3xxx EMU */
-#define ETM_BASE (L4_EMU_34XX_PHYS + 0x1)
-#define DBG_BASE (L4_EMU_34XX_PHYS + 0x11000)
-#define ETB_BASE (L4_EMU_34XX_PHYS + 0x1b000)
-#define DAPCTL (L4_EMU_34XX_PHYS + 0x1d000)
-
static struct amba_device omap3_etb_device = {
.dev= {
.init_name = etb,
},
.res= {
- .start = ETB_BASE,
- .end= ETB_BASE + SZ_4K - 1,
+ .start = OMAP34XX_ETB_PHYS,
+ .end= OMAP34XX_ETB_PHYS + OMAP34XX_ETB_SIZE - 1,
.flags = IORESOURCE_MEM,
},
.periphid = 0x000bb907,
@@ -47,8 +41,8 @@ static struct amba_device omap3_etm_device = {
.init_name = etm,
},
.res= {
- .start = ETM_BASE,
- .end= ETM_BASE + SZ_4K - 1,
+ .start = OMAP34XX_ETM_PHYS,
+ .end= OMAP34XX_ETM_PHYS + OMAP34XX_ETM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
.periphid = 0x102bb921,
diff --git a/arch/arm/plat-omap/include/plat/io.h
b/arch/arm/plat-omap/include/plat/io.h
index 128b549..81f736a 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -185,6 +185,26 @@
/* 3430 IVA - currently unmapped */
+#define OMAP34XX_DBG_OFFSET(0x00011000)
+#define OMAP34XX_DBG_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_DBG_OFFSET)
+#define OMAP34XX_DBG_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_DBG_OFFSET)
+#define OMAP34XX_DBG_SIZE SZ_4K
+
+#define OMAP34XX_ETM_OFFSET(0x0001)
+#define OMAP34XX_ETM_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_ETM_OFFSET)
+#define OMAP34XX_ETM_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_ETM_OFFSET)
+#define OMAP34XX_ETM_SIZE SZ_4K
+
+#define OMAP34XX_ETB_OFFSET(0x0001b000)
+#define OMAP34XX_ETB_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_ETB_OFFSET)
+#define OMAP34XX_ETB_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_ETB_OFFSET)
+#define OMAP34XX_ETB_SIZE SZ_4K
+
+#define OMAP34XX_DAP_OFFSET(0x0001d000)
+#define OMAP34XX_DAP_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_DAP_OFFSET)
+#define OMAP34XX_DAP_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_DAP_OFFSET)
+#define OMAP34XX_DAP_SIZE SZ_4K
+
/*
*
* Omap4 specific IO mapping
--
1.7.1
--
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Re: [PATCH 6/7] save and restore etm state across core OFF modes
On Sun, Jul 25, 2010 at 12:34:22 -0600, Hari Kanigeri wrote: +config ENABLE_OFF_MODE_JTAG_ETM_DEBUG + bool Enable hardware emulation context save and restore + depends on ARCH_OMAP3 -- Shouldn't this be depends on OMAP3_EMU instead ? Not really. OMAP3_EMU will enable ETM/ETB drivers within omap, but this particular patch is also needed if you're using an external hardware debugger to debug code across OFF modes. + default y -- As this is debug option, can you keep this n by default ? This option allows for enabling certain debugging functionality in runtime (via a sysfs file), which is turned off by default. It is debatable whether this option should default to 'y' or 'n', seeing as it doesn't add much overhead to the normal usecase. + help + This option enables JTAG ETM debugging across power states. + With out this option emulation features are reset across OFF + mode state changes. But I see that the wording is misleading and unclear, so I'll try to come up with something more descriptive. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] omap3: make coresight register save across OFF modes a sysfs option
This adds a sysfs file at /sys/power/coresight_save which is used to
control if the ETM and debug components' states should be saved and
restored across OFF modes.
Signed-off-by: Alexander Shishkin virtu...@slind.org
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
---
arch/arm/mach-omap2/Makefile|1 +
arch/arm/mach-omap2/debug34xx.c | 66 +++
arch/arm/mach-omap2/pm.h|6 +++
arch/arm/mach-omap2/pm34xx.c|3 ++
4 files changed, 76 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/debug34xx.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f5b4ff4..3a64ce4 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -49,6 +49,7 @@ ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o
+obj-$(CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG) += debug34xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
diff --git a/arch/arm/mach-omap2/debug34xx.c b/arch/arm/mach-omap2/debug34xx.c
new file mode 100644
index 000..698e83a
--- /dev/null
+++ b/arch/arm/mach-omap2/debug34xx.c
@@ -0,0 +1,66 @@
+/*
+ * Control saving and restoring of coresight components' state during
+ * OFF mode.
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/sysfs.h
+#include linux/kobject.h
+
+#include pm.h
+
+/*
+ * Pointer to a place in sram where the ETM/debug state save
+ * flag is. It can be calculated after the omap_sram_idle is
+ * pushed to sram.
+ */
+static unsigned int *_etm_save;
+
+/*
+ * sysfs file /sys/power/coresight_save controls whether the
+ * state of coresight components should be saved and restored
+ * across OFF modes.
+ */
+static ssize_t coresight_save_show(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, %u\n, *_etm_save);
+}
+
+static ssize_t coresight_save_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t n)
+{
+ unsigned int value;
+
+ if (sscanf(buf, %u, value) != 1)
+ return -EINVAL;
+
+ *_etm_save = !!value;
+
+ return n;
+}
+
+static struct kobj_attribute coresight_save_attr =
+ __ATTR(coresight_save, 0644, coresight_save_show, coresight_save_store);
+
+int omap3_coresight_pm_init(void *sram_addr)
+{
+ int ret;
+
+ /* the last word from the top of omap_sram_idle */
+ _etm_save = (unsigned *)((u8 *)sram_addr + omap34xx_cpu_suspend_sz - 4);
+
+ ret = sysfs_create_file(power_kobj, coresight_save_attr.attr);
+
+ return ret;
+}
+
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 3de6ece..0321834 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -76,6 +76,12 @@ extern void omap34xx_cpu_suspend(u32 *addr, int save_state);
extern void save_secure_ram_context(u32 *addr);
extern void omap3_save_scratchpad_contents(void);
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+int omap3_coresight_pm_init(void *sram_addr);
+#else
+#define omap3_coresight_pm_init(x) do {} while (0)
+#endif
+
extern unsigned int omap24xx_idle_loop_suspend_sz;
extern unsigned int omap34xx_suspend_sz;
extern unsigned int save_secure_ram_context_sz;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fb4994a..c389e65 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -1096,6 +1096,9 @@ static int __init omap3_pm_init(void)
core_clkdm = clkdm_lookup(core_clkdm);
omap_push_sram_idle();
+
+ omap3_coresight_pm_init(_omap_sram_idle);
+
#ifdef CONFIG_SUSPEND
suspend_set_ops(omap_pm_ops);
#endif /* CONFIG_SUSPEND */
--
1.7.1
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Re: [PATCH] omap3: make coresight register save across OFF modes a sysfs option
On Mon, Jul 26, 2010 at 12:04:23 +0300, Alexander Shishkin wrote: This adds a sysfs file at /sys/power/coresight_save which is used to control if the ETM and debug components' states should be saved and restored across OFF modes. Oops, I wanted to resend the previous patch, but it's getting late here. Sorry for the spam. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] save and restore etm state across core OFF modes
This prevents ETM stalls whenever core enters OFF mode. Original patch
author is Richard Woodruff r-woodru...@ti.com.
This version of the patch makes use of the ETM OS save/restore mechanism,
which takes about 55 words in omap3_arm_context[] instead of 128. Also,
saving ETM context can be switched on/off at runtime.
Signed-off-by: Alexander Shishkin virtu...@slind.org
Cc: Richard Woodruff r-woodru...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
---
arch/arm/mach-omap2/Kconfig | 12 +++
arch/arm/mach-omap2/control.c |2 +-
arch/arm/mach-omap2/sleep34xx.S | 135 +
arch/arm/plat-omap/include/plat/control.h |2 +-
4 files changed, 149 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b48bacf..b00d719 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -243,6 +243,18 @@ config MACH_OMAP4_PANDA
default y
depends on ARCH_OMAP4
+config ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+ bool Enable hardware emulation context save and restore
+ depends on ARCH_OMAP3
+ default y
+ help
+ This option enables the code that controls the capability to
+ save and restore JTAG ETM debugging across power states. It
+ may be required when using the ETM/ETB tracing driver or an
+ external debugging hardware.
+ Without this option emulation features' states are reset across
+ OFF mode state changes.
+
config OMAP3_EMU
bool OMAP3 debugging peripherals
depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index a8d20ee..22dd240 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -93,7 +93,7 @@ void *omap3_secure_ram_storage;
* The address is stored in scratchpad, so that it can be used
* during the restore path.
*/
-u32 omap3_arm_context[128];
+u32 omap3_arm_context[256];
struct omap3_control_regs {
u32 sysconfig;
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index d522cd7..cd6a1d4 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -28,6 +28,7 @@
#include asm/assembler.h
#include mach/io.h
#include plat/control.h
+#include asm/hardware/coresight.h
#include cm.h
#include prm.h
@@ -226,6 +227,18 @@ loop:
nop
bl wait_sdrc_ok
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+ /*
+* Restore Coresight debug registers
+*/
+ ldr r6, debug_vbase /* base Vaddr of CortexA8-Debug */
+ ldr r4, debug_xlar_key /* get lock key for OSLAR */
+ bl unlock_debug/* remove global lock if set */
+ ldr r6, etm_vbase /* base Vaddr of ETM */
+ bl unlock_debug/* remove global lock if set */
+ str r6, [r6, #ETMMR_OSLAR] /* clear OSLAR lock using non-key */
+#endif
+
ldmfd sp!, {r0-r12, pc} @ restore regs and return
restore_es3:
/*b restore_es3*/ @ Enable to debug restore code
@@ -385,6 +398,44 @@ logic_l1_restore:
/*normal memory remap register */
MCR p15, 0, r5, c10, c2, 1
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+ /*
+* Restore Coresight debug registers
+*/
+ ldr r6, debug_pbase /* base paddr of CortexA8-Debug */
+ ldr r4, debug_xlar_key /* get lock key for OSLAR */
+ bl unlock_debug/* remove global lock if set */
+ str r4, [r6, #ETMMR_OSLAR] /* reset-pointer (already locked) */
+ ldr r4, [r6, #ETMMR_OSSRR] /* dummy read */
+ ldr r4, [r3], #4/* load save size */
+ cmp r4, #0 /* check for zero */
+debug_restore:
+ itttne /* t2/compat if-then block */
+ ldrne r5, [r3], #4/* get saved value */
+ strne r5, [r6,#ETMMR_OSSRR] /* restore saved value */
+ subnes r4, r4, #1 /* decrement loop */
+ bne debug_restore /* loop till done */
+ str r5, [r6, #ETMMR_OSSRR] /* clear lock */
+ /*
+* Restore CoreSight ETM registers
+*/
+ ldr r6, etm_pbase /* base paddr of ETM */
+ ldr r4, debug_xlar_key /* get lock key for OSLAR */
+ bl unlock_debug/* remove global lock if set */
+ str r4, [r6, #ETMMR_OSLAR] /* reset-pointer (already locked) */
+ ldr r4, [r6, #ETMMR_OSSRR] /* dummy read */
+ ldr r4, [r3], #4/* load save size */
+ cmp r4, #0
[PATCH v3] omap i2c: add a timeout to the busy waiting
The errata 1.153 workaround is busy waiting on XUDF bit in interrupt
context, which may lead to kernel hangs. The problem can be reproduced
by running the bus with wrong (too high) speed.
Signed-off-by: Alexander Shishkin virtu...@slind.org
---
drivers/i2c/busses/i2c-omap.c | 10 +-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index ef73483..00fd02e 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -763,17 +763,25 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
*/
static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
{
- while (!(*stat OMAP_I2C_STAT_XUDF)) {
+ unsigned long timeout = 1;
+
+ while (--timeout !(*stat OMAP_I2C_STAT_XUDF)) {
if (*stat (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
omap_i2c_ack_stat(dev, *stat (OMAP_I2C_STAT_XRDY |
OMAP_I2C_STAT_XDR));
*err |= OMAP_I2C_STAT_XUDF;
return -ETIMEDOUT;
}
+
cpu_relax();
*stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
}
+ if (!timeout) {
+ dev_err(dev-dev, timeout waiting on XUDF bit\n);
+ return 0;
+ }
+
return 0;
}
--
1.7.1.1.g15764
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Re: [RFC] ETM/JTAG components states across OFF modes
On Mon, May 03, 2010 at 06:54:57 -0500, Woodruff, Richard wrote: Hi Alex, Hi, From: virtu...@slind.org [mailto:virtu...@slind.org] Sent: Saturday, May 01, 2010 12:38 PM Do you have a web viewable git tree where your full patch is applied? Or could you send me on the side files? I've pushed these patches to http://github.com/virtuoso/linux-2.6/tree/omap-etm-off/0 Main bit I was looking to check was that you have bug fix which came late in my original hack where a failed OFF mode needs to unlock the coresight registers at the fall through of WFI. There actually might be some unnecessary unlocking around wfi, I'll double check that. I've finally got around to doing this. This is a rework of the previously posted [1] patch that implements ETM and JTAG context saving. There are two major changes since previous version: * coresight OS save/restore mechanism is used for saving the ETM context, so that it actually occupies ~54 words on omap3_arm_context instead of 128; Seems you found some nice optimization. I was thinking first patch was doing this in part. You read from a port address and it gives you internal registers as necessary. You written them back to port for restore. I came up with context size simply by inspecting # of times loop was necessary and looking at values written to save areas. I assume you would have done something similar to determine size. Good point, I'll double check with other omaps (at least 3430). I've only got to test this code with 3630. And beagle doesn't go to OFF mode at all for some reason. * a sysfs file is used to control if the ETM/JTAG context should be saved in OFF mode. Neat. This is much more friendly then a recompile. You still have the option to compile it out, which is also nice for some people, I guess. :) Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] save and restore etm state across core OFF modes
On Tue, Jan 12, 2010 at 04:53:51 -0600, Nishanth Menon wrote:
Tony Lindgren had written, on 01/12/2010 04:15 PM, the following:
* Nishanth Menon n...@ti.com [100112 14:06]:
Alexander Shishkin had written, on 01/12/2010 03:46 PM, the following:
On Tue, Jan 12, 2010 at 01:04:04 -0800, Tony Lindgren wrote:
* Nishanth Menon n...@ti.com [100112 09:31]:
Alexander Shishkin had written, on 01/12/2010 11:30 AM, the following:
On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
diff --git a/arch/arm/mach-omap2/sleep34xx.S
b/arch/arm/mach-omap2/sleep34xx.S
index 69521be..0a5ec86 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
[...]
/* Store current cpsr*/
mrs r2, cpsr
stmia r8!, {r2}
@@ -520,6 +616,7 @@ clean_caches:
cmp r9, #1 /* Check whether L2 inval is required or not*/
bne skip_l2_inval
clean_l2:
+#if 0
my aversion to #if 0 kicks in here :(.. do we have an alternative
like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
else?
Fair enough. I could replace it with #if !defined(...) as the first
thing that comes to mind. This way it will only take disabling the
config option to catch any possible regressions in between. Does this
sound reasonable?
sounds ok to me.. unless folks have ideas coz of clean_l2 label..
more comments might be useful before a rev2 of the patch..
The best solution would be to be able to toggle this via sysfs or
debugfs by swapping the sram code for idle loop when JTAG support
is needed.
Well, if you say, compile the ETM driver in, this will be needed most of
the time.
I can think of reasons for an against a sysfs entry (as part of
discussion -warning lot of self contradictions below- but I think
might save a bit of back and froth ;)):
for sysfs entry:
a) save and restore will have additional latency when you save a
chunk such as EMU domain regs - this will not be needed in
production phones, disabling it might pop up surprises
There's no overhead if you're just replacing the function
loaded to SRAM as needed. But for sure it's a debug tool only.
I should probably have been more clear -I agree function relocation
to SRAM is not a major factor here, my concern was the additional
latency incurred during scratchpad save and restore logic as seen by
the patch:
-u32 omap3_arm_context[128];
+u32 omap3_arm_context[256];
the arm context has doubled albiet 128bytes only.. it still changes
I've tried to address this and other concerns expressed in this thread
and I'll post a new patchset in a few minutes.
the latencies involved on the save and restore paths.. few
interesting behavior seen with EHCI save and restore comes to mind
here - but maybe irrelevant to the discussion..
Regards,
--
Alex
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[PATCH] cbus: fix comilation breakage
Just tried to build n8x0_defconfig on the current master and got cbus failing to compile due to implicit kzalloc() (and others from slab.h) references. I'm not sure that including slab.h directly is the right thing to do here, though. Signed-off-by: Alexander Shishkin a...@koowaldah.org --- drivers/cbus/cbus.c |1 + drivers/cbus/retu-headset.c |1 + drivers/cbus/retu-user.c|1 + drivers/cbus/retu-wdt.c |1 + drivers/cbus/tahvo-user.c |1 + 5 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/cbus/cbus.c b/drivers/cbus/cbus.c index 00c3c32..18260f2 100644 --- a/drivers/cbus/cbus.c +++ b/drivers/cbus/cbus.c @@ -26,6 +26,7 @@ #include linux/device.h #include linux/init.h #include linux/kernel.h +#include linux/slab.h #include linux/delay.h #include linux/spinlock.h #include linux/gpio.h diff --git a/drivers/cbus/retu-headset.c b/drivers/cbus/retu-headset.c index e798bc2..c38abf1 100644 --- a/drivers/cbus/retu-headset.c +++ b/drivers/cbus/retu-headset.c @@ -22,6 +22,7 @@ #include linux/module.h #include linux/init.h #include linux/kernel.h +#include linux/slab.h #include linux/delay.h #include linux/input.h #include linux/platform_device.h diff --git a/drivers/cbus/retu-user.c b/drivers/cbus/retu-user.c index 0f35dc5..1a29492 100644 --- a/drivers/cbus/retu-user.c +++ b/drivers/cbus/retu-user.c @@ -23,6 +23,7 @@ #include linux/types.h #include linux/kernel.h +#include linux/slab.h #include linux/interrupt.h #include linux/module.h #include linux/init.h diff --git a/drivers/cbus/retu-wdt.c b/drivers/cbus/retu-wdt.c index 35932dd..79585d8 100644 --- a/drivers/cbus/retu-wdt.c +++ b/drivers/cbus/retu-wdt.c @@ -22,6 +22,7 @@ */ #include linux/kernel.h +#include linux/slab.h #include linux/module.h #include linux/device.h #include linux/init.h diff --git a/drivers/cbus/tahvo-user.c b/drivers/cbus/tahvo-user.c index c0e8daf..01e7f20 100644 --- a/drivers/cbus/tahvo-user.c +++ b/drivers/cbus/tahvo-user.c @@ -23,6 +23,7 @@ #include linux/types.h #include linux/kernel.h +#include linux/slab.h #include linux/interrupt.h #include linux/module.h #include linux/init.h -- 1.5.6.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6] OMAP UART: Add omap-serial driver support.
On Wed, Feb 24, 2010 at 10:54:22 -0800, Tony Lindgren wrote: * Kevin Hilman khil...@deeprootsystems.com [100224 10:36]: After that and Olof's comments, it should be submitted to linux-serial and LKML. Also, it needs to be posted as a series with the related hwmod patches needed to actually test this driver with the mainline kernel. I was wondering, what are these hwmod patches? Is it something I should be looking for in Kevin's branch? Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/2] omap i2c: make errata 1.153 workaround a separate function
This is to avoid insanely long lines and levels of indentation.
Signed-off-by: Alexander Shishkin virtu...@slind.org
Acked-by: Tony Lindgren t...@atomide.com
CC: linux-...@vger.kernel.org
CC: linux-omap@vger.kernel.org
CC: n...@ti.com
---
drivers/i2c/busses/i2c-omap.c | 43 ++--
1 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 75bf3ad..2d146ac 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -671,6 +671,27 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
#define omap_i2c_rev1_isr NULL
#endif
+/*
+ * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
+ * data to DATA_REG. Otherwise some data bytes can be lost while transferring
+ * them from the memory to the I2C interface.
+ */
+static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
+{
+ while (!(*stat OMAP_I2C_STAT_XUDF)) {
+ if (*stat (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
+ omap_i2c_ack_stat(dev, *stat (OMAP_I2C_STAT_XRDY |
+ OMAP_I2C_STAT_XDR));
+ *err |= OMAP_I2C_STAT_XUDF;
+ return -ETIMEDOUT;
+ }
+ cpu_relax();
+ *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+ }
+
+ return 0;
+}
+
static irqreturn_t
omap_i2c_isr(int this_irq, void *dev_id)
{
@@ -794,25 +815,9 @@ complete:
break;
}
- /*
-* OMAP3430 Errata 1.153: When an XRDY/XDR
-* is hit, wait for XUDF before writing data
-* to DATA_REG. Otherwise some data bytes can
-* be lost while transferring them from the
-* memory to the I2C interface.
-*/
-
- if (dev-rev = OMAP_I2C_REV_ON_3430) {
- while (!(stat
OMAP_I2C_STAT_XUDF)) {
- if (stat
(OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
-
omap_i2c_ack_stat(dev, stat (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
- err |=
OMAP_I2C_STAT_XUDF;
- goto complete;
- }
- cpu_relax();
- stat =
omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
- }
- }
+ if ((dev-rev = OMAP_I2C_REV_ON_3430)
+ errata_omap3_1p153(dev, stat, err))
+ goto complete;
omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
}
--
1.6.3.3
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[PATCH v2 2/2] omap i2c: add a timeout to the busy waiting
The errata 1.153 workaround is busy waiting on XUDF bit in interrupt
context, which may lead to kernel hangs. The problem can be reproduced
by running the bus with wrong (too high) speed.
Signed-off-by: Alexander Shishkin virtu...@slind.org
Acked-by: Tony Lindgren t...@atomide.com
CC: linux-...@vger.kernel.org
CC: linux-omap@vger.kernel.org
CC: n...@ti.com
---
drivers/i2c/busses/i2c-omap.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 2d146ac..7d56a25 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -678,6 +678,8 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
*/
static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
{
+ unsigned long timeout = jiffies + msecs_to_jiffies(1);
+
while (!(*stat OMAP_I2C_STAT_XUDF)) {
if (*stat (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
omap_i2c_ack_stat(dev, *stat (OMAP_I2C_STAT_XRDY |
@@ -685,6 +687,12 @@ static int errata_omap3_1p153(struct omap_i2c_dev *dev,
u16 *stat, int *err)
*err |= OMAP_I2C_STAT_XUDF;
return -ETIMEDOUT;
}
+
+ if (time_after(jiffies, timeout)) {
+ dev_err(dev-dev, timeout waiting on XUDF bit\n);
+ return 0;
+ }
+
cpu_relax();
*stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
}
--
1.6.3.3
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Re: [PATCH 1/2] omap i2c: make errata 1.153 workaround a separate function
Can you please repost and I'll add those too into omap-testing first? Or maybe point to the right patchwork.kernel.org link. Resending. P.S. I think linux-i2c@ mailing list adds some vicious email headers that the email clients obey and don't include me in the to/cc in replies. I've only found Tony's reply in the archives because I suspected something wrong. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/2] omap i2c: add a timeout to the busy waiting
On Thu, Mar 25, 2010 at 04:38:09 +0200, Aaro Koskinen wrote:
Hi,
Alexander Shishkin wrote:
The errata 1.153 workaround is busy waiting on XUDF bit in interrupt
context, which may lead to kernel hangs. The problem can be reproduced
by running the bus with wrong (too high) speed.
Signed-off-by: Alexander Shishkin virtu...@slind.org
Acked-by: Tony Lindgren t...@atomide.com
CC: linux-...@vger.kernel.org
CC: linux-omap@vger.kernel.org
CC: n...@ti.com
---
drivers/i2c/busses/i2c-omap.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 2d146ac..7d56a25 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -678,6 +678,8 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
*/
static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int
*err)
{
+ unsigned long timeout = jiffies + msecs_to_jiffies(1);
+
while (!(*stat OMAP_I2C_STAT_XUDF)) {
if (*stat (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
omap_i2c_ack_stat(dev, *stat (OMAP_I2C_STAT_XRDY |
@@ -685,6 +687,12 @@ static int errata_omap3_1p153(struct omap_i2c_dev
*dev, u16 *stat, int *err)
*err |= OMAP_I2C_STAT_XUDF;
return -ETIMEDOUT;
}
+
+ if (time_after(jiffies, timeout)) {
This is called from hard interrupt context, so we cannot use jiffies.
Ahh, stupid me. Then we are left with the iteration counting, I guess.
Regards,
--
Alex
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Re: [PATCH 1/2] omap i2c: make errata 1.153 workaround a separate function
On Wed, Dec 16, 2009 at 04:02:23 +0200, Alexander Shishkin wrote: This is to avoid insanely long lines and levels of indentation. These seem to be forgotten. Is there any problem with these I should address? Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHV5 1/4] OMAP3: introduce DPLL4 Jtype
On Man, Jan 18, 2010 at 01:59:19 +0530, Vishwanath BS wrote: DPLL4 for 3630 introduces a changed block called j type dpll, requiring special divisor bits and additional reg fields. To allow for silicons to use this, this is introduced as a flag and is enabled for 3630 silicon. OMAP4 also has j type dpll for usb. Tested with 3630 ZOOM3 and OMAP3430 ZOOM2 [snip] +/* A new flag called flag has been added which indiciates what is the type + * of dpll (like j_type, no_dco_sel) + */ + I think this comment block violates coding style. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHV5 4/4] OMAP3: add support for 192Mhz DPLL4M2 output
On Mon, Jan 18, 2010 at 01:59:22 +0530, Vishwanath BS wrote: In 3630, DPLL4M2 o/p can be 96MH or 192MHz (for SGX to run at 192). This patch has changes to support this feature. 96MHz clock is generated by dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register. SGX can select Core Clock, 192MHz clock or CM_96M_FCLK as it's functional clock. In summary changes done are 1. Added a feature called omap3_has_192mhz_clk and enabled for 3630 2. Added a new clock node called omap_192m_alwon_ck 3. Made omap_96m_alwon_fck to derive it's clock from omap_192m_alwon_ck Cc: Paul Walmsley p...@pwsan.com Signed-off-by: Vishwanath BS vishwanath...@ti.com --- arch/arm/mach-omap2/clock34xx_data.c | 72 - arch/arm/mach-omap2/cm-regbits-34xx.h |2 + arch/arm/mach-omap2/id.c |3 + arch/arm/plat-omap/include/plat/cpu.h |2 + 4 files changed, 68 insertions(+), 11 deletions(-) [snip] diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 9a028bd..6718e40 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -500,6 +500,7 @@ extern u32 omap3_features; #define OMAP3_HAS_SGXBIT(2) #define OMAP3_HAS_NEON BIT(3) #define OMAP3_HAS_ISPBIT(4) +#define OMAP3_HAS_192MHZ_CLK BIT(5) Looks like it could use a couple more tabs before BIT(5). Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] save and restore etm state across core OFF modes
On Wed, Jan 13, 2010 at 06:58:28 -0600, Nishanth Menon wrote:
Alexander Shishkin said the following on 01/13/2010 05:36 AM:
On Tue, Jan 12, 2010 at 04:08:23 -0600, Nishanth Menon wrote:
Alexander Shishkin had written, on 01/12/2010 03:46 PM, the following:
On Tue, Jan 12, 2010 at 01:04:04 -0800, Tony Lindgren wrote:
* Nishanth Menon n...@ti.com [100112 09:31]:
Alexander Shishkin had written, on 01/12/2010 11:30 AM, the following:
On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
diff --git a/arch/arm/mach-omap2/sleep34xx.S
b/arch/arm/mach-omap2/sleep34xx.S
index 69521be..0a5ec86 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
[...]
/* Store current cpsr*/
mrs r2, cpsr
stmia r8!, {r2}
@@ -520,6 +616,7 @@ clean_caches:
cmp r9, #1 /* Check whether L2 inval is required or not*/
bne skip_l2_inval
clean_l2:
+#if 0
my aversion to #if 0 kicks in here :(.. do we have an alternative
like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
else?
Fair enough. I could replace it with #if !defined(...) as the first
thing that comes to mind. This way it will only take disabling the
config option to catch any possible regressions in between. Does this
sound reasonable?
sounds ok to me.. unless folks have ideas coz of clean_l2 label..
more comments might be useful before a rev2 of the patch..
The best solution would be to be able to toggle this via sysfs or
debugfs by swapping the sram code for idle loop when JTAG support
is needed.
Well, if you say, compile the ETM driver in, this will be needed most of
the time.
I can think of reasons for an against a sysfs entry (as part of
discussion -warning lot of self contradictions below- but I think
might save a bit of back and froth ;)):
for sysfs entry:
a) save and restore will have additional latency when you save a
chunk such as EMU domain regs - this will not be needed in
production phones, disabling it might pop up surprises
counter: having a disabled defconfig allows relevant folks to
enable on a need basis
counter to counter: what do you do when a user reports
an issue in a release and you'd want to debug it with
ETM on his platform other than doing a rebuild?
Well, my intention is to have it enabled for most of the cases only having
it disabled for testing purposes.
with a sysfs you can go either way, with proper #ifdeferry, you can
get the best of all worlds I guess.. I know in one of the products,
a similar patch was not taken in due to introduction of additional
scratchpad space and latencies - so there are folks who would like
this and those who would like to see this not present in the binary
they flash to thier device.
What would you suggest for a place in sysfs for such a file? I'm thinking
/sys/power.
Regards,
--
Alex
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Re: [PATCH 12/18] OMAP3 clock: split out DPLL3 M2 divider functions into clkt3xxx_dpll3m2.c
On Fri, Jan 15, 2010 at 02:07:04 -0700, Paul Walmsley wrote: Split the DPLL3 M2 divider clock functions out of clock34xx.c and move them into clkt3xxx_dpll3m2.c to improve maintainability. I'm not very familiar with maintainability issues of dpll3m2, so forgive me if it is ignorant for me to ask you to elaborate on this. It does look like a bit of an overkill to have a separate file for a divider. But again, I might well be missing the point. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] save and restore etm state across core OFF modes
This prevents ETM stalls whenever core enters OFF mode. Original patch
author is Richard Woodruff r-woodru...@ti.com.
This patch applies on top of pm branch.
Signed-off-by: Alexander Shishkin virtu...@slind.org
CC: Richard Woodruff r-woodru...@ti.com
---
arch/arm/mach-omap2/Kconfig |9 ++
arch/arm/mach-omap2/control.c |2 +-
arch/arm/mach-omap2/sleep34xx.S | 133 +
arch/arm/plat-omap/include/plat/control.h |2 +-
4 files changed, 144 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 606bf04..02ea136 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -153,6 +153,15 @@ config MACH_OMAP_4430SDP
bool OMAP 4430 SDP board
depends on ARCH_OMAP4
+config ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+ bool Enable hardware emulation context save and restore
+ depends on ARCH_OMAP3
+ default y
+ help
+ This option enables JTAG ETM debugging across power states.
+ With out this option emulation features are reset across OFF
+ mode state changes.
+
config OMAP3_EMU
bool OMAP3 debugging peripherals
depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index cdd1f35..78f4634 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -93,7 +93,7 @@ void *omap3_secure_ram_storage;
* The address is stored in scratchpad, so that it can be used
* during the restore path.
*/
-u32 omap3_arm_context[128];
+u32 omap3_arm_context[256];
struct omap3_control_regs {
u32 sysconfig;
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 69521be..0a5ec86 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -59,6 +59,13 @@
#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
+#define CORTEX_CORSIGHT_OFF (0x00011000)
+#define CORTEX_EMU_DEBUG_V (L4_EMU_34XX_VIRT + CORTEX_CORSIGHT_OFF)
+#define CORTEX_EMU_DEBUG_P (L4_EMU_34XX_PHYS + CORTEX_CORSIGHT_OFF)
+#define ETM_CORSIGHT_OFF(0x0001)
+#define CORTEX_EMU_ETM_V(L4_EMU_34XX_VIRT + ETM_CORSIGHT_OFF)
+#define CORTEX_EMU_ETM_P(L4_EMU_34XX_PHYS + ETM_CORSIGHT_OFF)
+
.text
/* Function to aquire the semaphore in scratchpad */
ENTRY(lock_scratchpad_sem)
@@ -226,6 +233,18 @@ loop:
nop
bl wait_sdrc_ok
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+ /*
+* Restore Coresight debug registers
+*/
+ ldr r6, debug_vbase /* base Vaddr of CortexA8-Debug */
+ ldr r4, debug_xlar_key /* get lock key for OSLAR */
+ bl unlock_debug /* remove global lock if set */
+ ldr r6, etm_vbase/* base Vaddr of ETM */
+ bl unlock_debug /* remove global lock if set */
+ str r6, [r6, #0x300] /* clear OSLAR lock using non-key */
+#endif
+
ldmfd sp!, {r0-r12, pc} @ restore regs and return
restore_es3:
/*b restore_es3*/ @ Enable to debug restore code
@@ -385,6 +404,50 @@ logic_l1_restore:
/*normal memory remap register */
MCR p15, 0, r5, c10, c2, 1
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+ /*
+* Restore Coresight debug registers
+*/
+ ldr r6, debug_pbase /* base paddr of CortexA8-Debug */
+ ldr r4, debug_xlar_key /* get lock key for OSLAR */
+ bl unlock_debug /* remove global lock if set */
+ str r4, [r6, #0x300] /* reset-pointer (already locked) */
+ ldr r4, [r6, #0x308] /* dummy read */
+ ldr r4, [r3], #4 /* load save size */
+ cmp r4, #0 /* check for zero */
+debug_restore:
+ itttne /* t2/compat if-then block */
+ ldrne r5, [r3], #4 /* get save value */
+ strne r5, [r6,#0x308] /* restore cp14 value */
+ subnes r4, r4, #1 /* decrement loop */
+ bne debug_restore/* loop till done */
+ str r5, [r6, #0x300] /* clear lock */
+ /*
+* Restore CoreSight ETM registers
+*/
+ ldr r6, etm_pbase/* base paddr of ETM */
+ ldr r4, debug_xlar_key /* get lock key for OSLAR */
+ bl unlock_debug /* remove global lock if set */
+ ldr r4, [r3], #4 /* load save size */
+ cmp r4, #0 /* check for zero */
+ beq etm_skip
+ sub r4, #1
+ ldr r7, [r3], #4 /* get/store first value to r7 */
+ mov r5, #0x3 /* enable programming in ETMCR*/
+ lsl r5, r5, #10
+ orr r5, r7
+ str r5,[r6], #4
+ cmp
Re: [PATCH] save and restore etm state across core OFF modes
On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
This prevents ETM stalls whenever core enters OFF mode. Original patch
author is Richard Woodruff r-woodru...@ti.com.
This patch applies on top of pm branch.
Signed-off-by: Alexander Shishkin virtu...@slind.org
CC: Richard Woodruff r-woodru...@ti.com
thanks..
---
arch/arm/mach-omap2/Kconfig |9 ++
arch/arm/mach-omap2/control.c |2 +-
arch/arm/mach-omap2/sleep34xx.S | 133
+
arch/arm/plat-omap/include/plat/control.h |2 +-
4 files changed, 144 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 606bf04..02ea136 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -153,6 +153,15 @@ config MACH_OMAP_4430SDP
bool OMAP 4430 SDP board
depends on ARCH_OMAP4
+config ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+bool Enable hardware emulation context save and restore
+depends on ARCH_OMAP3
+default y
+help
+ This option enables JTAG ETM debugging across power states.
+ With out this option emulation features are reset across OFF
+ mode state changes.
+
config OMAP3_EMU
bool OMAP3 debugging peripherals
depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index cdd1f35..78f4634 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -93,7 +93,7 @@ void *omap3_secure_ram_storage;
* The address is stored in scratchpad, so that it can be used
* during the restore path.
*/
-u32 omap3_arm_context[128];
+u32 omap3_arm_context[256];
struct omap3_control_regs {
u32 sysconfig;
diff --git a/arch/arm/mach-omap2/sleep34xx.S
b/arch/arm/mach-omap2/sleep34xx.S
index 69521be..0a5ec86 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -59,6 +59,13 @@
#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
#define SDRC_DLLA_CTRL_VOMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
+#define CORTEX_CORSIGHT_OFF (0x00011000)
+#define CORTEX_EMU_DEBUG_V (L4_EMU_34XX_VIRT + CORTEX_CORSIGHT_OFF)
+#define CORTEX_EMU_DEBUG_P (L4_EMU_34XX_PHYS + CORTEX_CORSIGHT_OFF)
+#define ETM_CORSIGHT_OFF(0x0001)
+#define CORTEX_EMU_ETM_V(L4_EMU_34XX_VIRT + ETM_CORSIGHT_OFF)
+#define CORTEX_EMU_ETM_P(L4_EMU_34XX_PHYS + ETM_CORSIGHT_OFF)
+
.text
/* Function to aquire the semaphore in scratchpad */
ENTRY(lock_scratchpad_sem)
@@ -226,6 +233,18 @@ loop:
nop
bl wait_sdrc_ok
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+/*
+ * Restore Coresight debug registers
+ */
+ldr r6, debug_vbase /* base Vaddr of CortexA8-Debug */
+ldr r4, debug_xlar_key /* get lock key for OSLAR */
+bl unlock_debug /* remove global lock if set */
+ldr r6, etm_vbase/* base Vaddr of ETM */
+bl unlock_debug /* remove global lock if set */
+str r6, [r6, #0x300] /* clear OSLAR lock using non-key */
+#endif
+
ldmfd sp!, {r0-r12, pc} @ restore regs and return
restore_es3:
/*b restore_es3*/ @ Enable to debug restore code
@@ -385,6 +404,50 @@ logic_l1_restore:
/*normal memory remap register */
MCR p15, 0, r5, c10, c2, 1
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+/*
+ * Restore Coresight debug registers
+ */
+ldr r6, debug_pbase /* base paddr of CortexA8-Debug */
+ldr r4, debug_xlar_key /* get lock key for OSLAR */
+bl unlock_debug /* remove global lock if set */
+str r4, [r6, #0x300] /* reset-pointer (already locked) */
+ldr r4, [r6, #0x308] /* dummy read */
+ldr r4, [r3], #4 /* load save size */
+cmp r4, #0 /* check for zero */
+debug_restore:
+itttne /* t2/compat if-then block */
+ldrne r5, [r3], #4 /* get save value */
+strne r5, [r6,#0x308] /* restore cp14 value */
+subnes r4, r4, #1 /* decrement loop */
+bne debug_restore/* loop till done */
+str r5, [r6, #0x300] /* clear lock */
+/*
+ * Restore CoreSight ETM registers
+ */
+ldr r6, etm_pbase/* base paddr of ETM */
+ldr r4, debug_xlar_key /* get lock key for OSLAR */
+bl unlock_debug /* remove global lock if set */
+ldr r4, [r3], #4 /* load save size */
+cmp r4, #0 /* check for zero */
+beq etm_skip
+sub r4, #1
+ldr r7, [r3], #4 /* get/store first value to r7 */
+mov r5, #0x3 /* enable programming in ETMCR*/
+lsl
Re: [PATCH] save and restore etm state across core OFF modes
On Tue, Jan 12, 2010 at 01:04:04 -0800, Tony Lindgren wrote:
* Nishanth Menon n...@ti.com [100112 09:31]:
Alexander Shishkin had written, on 01/12/2010 11:30 AM, the following:
On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
diff --git a/arch/arm/mach-omap2/sleep34xx.S
b/arch/arm/mach-omap2/sleep34xx.S
index 69521be..0a5ec86 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
[...]
/* Store current cpsr*/
mrs r2, cpsr
stmia r8!, {r2}
@@ -520,6 +616,7 @@ clean_caches:
cmp r9, #1 /* Check whether L2 inval is required or not*/
bne skip_l2_inval
clean_l2:
+#if 0
my aversion to #if 0 kicks in here :(.. do we have an alternative
like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
else?
Fair enough. I could replace it with #if !defined(...) as the first
thing that comes to mind. This way it will only take disabling the
config option to catch any possible regressions in between. Does this
sound reasonable?
sounds ok to me.. unless folks have ideas coz of clean_l2 label..
more comments might be useful before a rev2 of the patch..
The best solution would be to be able to toggle this via sysfs or
debugfs by swapping the sram code for idle loop when JTAG support
is needed.
Well, if you say, compile the ETM driver in, this will be needed most of
the time.
Regards,
--
Alex
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[PATCH] omap: make serial_in_override() address the right uart port
Commit f62349ee9788b1d94c55eb6c291d74a1f69bdd9e makes it possible to
have some other than first uart port as ttyS0, which breaks the workaround
serial_in_override() function which will try to address the first uart
port (for ttyS0) and not the one that was initialized.
Signed-off-by: Alexander Shishkin virtu...@slind.org
CC: Mika Westerberg ext-mika.1.westerb...@nokia.com
CC: Kevin Hilman khil...@deeprootsystems.com
---
arch/arm/mach-omap2/serial.c | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 19805a7..8c964be 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -125,6 +125,13 @@ static struct plat_serial8250_port serial_platform_data3[]
= {
}
};
#endif
+static inline unsigned int __serial_read_reg(struct uart_port *up,
+ int offset)
+{
+ offset = up-regshift;
+ return (unsigned int)__raw_readb(up-membase + offset);
+}
+
static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
int offset)
{
@@ -583,11 +590,12 @@ static unsigned int serial_in_override(struct uart_port
*up, int offset)
{
if (UART_RX == offset) {
unsigned int lsr;
- lsr = serial_read_reg(omap_uart[up-line].p, UART_LSR);
+ lsr = __serial_read_reg(up, UART_LSR);
if (!(lsr UART_LSR_DR))
return -EPERM;
}
- return serial_read_reg(omap_uart[up-line].p, offset);
+
+ return __serial_read_reg(up, offset);
}
void __init omap_serial_early_init(void)
--
1.6.3.3
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Re: [PATCH v2 1/2] omap i2c: make errata 1.153 workaround a separate function
On Mon, Dec 21, 2009 at 01:29:58 +0200, Alexander Shishkin wrote: This is to avoid insanely long lines and levels of indentation. Ben, do you want me to resend these with Tony's acks or can you consider applying them? Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] omap: make serial_in_override() address the right uart port
On Tue, Jan 05, 2010 at 10:03:01 -0800, Tony Lindgren wrote: * Alexander Shishkin virtu...@slind.org [100105 08:56]: Commit f62349ee9788b1d94c55eb6c291d74a1f69bdd9e makes it possible to have some other than first uart port as ttyS0, which breaks the workaround serial_in_override() function which will try to address the first uart port (for ttyS0) and not the one that was initialized. Nothing wrong with this patch.. But so we're back to having the ports move around again? That sucks. I wonder if we can initialize dummy 8250 ports somehow to keep the order correct to avoid confusion. It doesn't seem like any solution to this problem will suck less than the current one, but let's think about it. My patch only addresses the issue I'm having with the current solution. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/2] omap i2c interrupt handler fixes
Hi, This is the second version of the patchset, now addressing comments from Nishanth and changing the retry counter into a real timeout. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/2] omap i2c: add a timeout to the busy waiting
The errata 1.153 workaround is busy waiting on XUDF bit in interrupt
context, which may lead to kernel hangs. The problem can be reproduced
by running the bus with wrong (too high) speed.
Signed-off-by: Alexander Shishkin virtu...@slind.org
CC: linux-...@vger.kernel.org
CC: linux-omap@vger.kernel.org
CC: n...@ti.com
---
drivers/i2c/busses/i2c-omap.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 2d146ac..7d56a25 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -678,6 +678,8 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
*/
static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
{
+ unsigned long timeout = jiffies + msecs_to_jiffies(1);
+
while (!(*stat OMAP_I2C_STAT_XUDF)) {
if (*stat (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
omap_i2c_ack_stat(dev, *stat (OMAP_I2C_STAT_XRDY |
@@ -685,6 +687,12 @@ static int errata_omap3_1p153(struct omap_i2c_dev *dev,
u16 *stat, int *err)
*err |= OMAP_I2C_STAT_XUDF;
return -ETIMEDOUT;
}
+
+ if (time_after(jiffies, timeout)) {
+ dev_err(dev-dev, timeout waiting on XUDF bit\n);
+ return 0;
+ }
+
cpu_relax();
*stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
}
--
1.6.3.3
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Re: [PATCH 1/2] omap i2c: make errata 1.153 workaround a separate function
On Thu, Dec 17, 2009 at 08:36:30 +0530, Menon, Nishanth wrote:
Alexander Shishkin said the following on 12/16/2009 07:32 PM:
This is to avoid insanely long lines and levels of indentation.
Signed-off-by: Alexander Shishkin virtu...@slind.org
CC: linux-...@vger.kernel.org
CC: linux-omap@vger.kernel.org
---
drivers/i2c/busses/i2c-omap.c | 43
++--
1 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 75bf3ad..ad8242a 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -671,6 +671,27 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
#define omap_i2c_rev1_isr NULL
#endif
+/*
+ * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before
writing
+ * data to DATA_REG. Otherwise some data bytes can be lost while
transferring
+ * them from the memory to the I2C interface.
+ */
+static int omap3430_workaround(struct omap_i2c_dev *dev, u16 *stat, int
*err)
note, though this is identified as being part of 3430, it is not
really restricted to 3430 alone
we might want to rename this as errata_omap3_1p153() perhaps?
Ok, I don't see why not.
+{
+while (!(*stat OMAP_I2C_STAT_XUDF)) {
+if (*stat (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
+omap_i2c_ack_stat(dev, *stat (OMAP_I2C_STAT_XRDY |
+OMAP_I2C_STAT_XDR));
+*err |= OMAP_I2C_STAT_XUDF;
+return -1;
+}
+cpu_relax();
+*stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+}
+
+return 0;
+}
wonder if using an inline might help throw away the function call
overhead (considering it is used only once)?
objdump -S says it's implicitly inlined already. I actually had in mind
the conversation about generalizing the features/erratas for chips/IPs
and that somehow stopped me from explicitly inlining this. Do you think
it makes sense (for the next version of this patchset) to explicitly
inline this?
+
static irqreturn_t
omap_i2c_isr(int this_irq, void *dev_id)
{
@@ -794,25 +815,9 @@ complete:
break;
}
-/*
- * OMAP3430 Errata 1.153: When an XRDY/XDR
- * is hit, wait for XUDF before writing data
- * to DATA_REG. Otherwise some data bytes can
- * be lost while transferring them from the
- * memory to the I2C interface.
- */
-
-if (dev-rev = OMAP_I2C_REV_ON_3430) {
-while (!(stat
OMAP_I2C_STAT_XUDF)) {
-if (stat
(OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
-
omap_i2c_ack_stat(dev, stat (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
-err |=
OMAP_I2C_STAT_XUDF;
-goto complete;
-}
-cpu_relax();
-stat =
omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
-}
-}
+if (dev-rev = OMAP_I2C_REV_ON_3430
+omap3430_workaround(dev, stat, err))
+goto complete;
omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
}
Regards,
Nishanth Menon
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Re: [PATCH 2/2] omap i2c: add a timeout to the busy waiting
On Thu, Dec 17, 2009 at 08:38:39 +0530, Menon, Nishanth wrote:
Alexander Shishkin said the following on 12/16/2009 07:32 PM:
The errata 1.153 workaround is busy waiting on XUDF bit in interrupt
context, which may lead to kernel hangs. The problem can be reproduced
by running the bus with wrong (too high) speed.
Signed-off-by: Alexander Shishkin virtu...@slind.org
CC: linux-...@vger.kernel.org
CC: linux-omap@vger.kernel.org
---
drivers/i2c/busses/i2c-omap.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index ad8242a..b474c20 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -678,7 +678,9 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
*/
static int omap3430_workaround(struct omap_i2c_dev *dev, u16 *stat, int
*err)
{
-while (!(*stat OMAP_I2C_STAT_XUDF)) {
+unsigned long timeout = 1;
+
+while (!(*stat OMAP_I2C_STAT_XUDF --timeout)) {
a) timeout without using an actual delay is not a good idea -
consider each OPP - we can go upto 1ghz on 3630,
the actual time for 1 iterations will depend on the MPU speed.
Well, I could calculate the timeout value based on current operating speed,
I guess. Or a delay. Perhaps OMAP_I2C_TIMEOUT can be used here?
b) how did you arrive at the 10k iteration limit?
It was random, but then it seemed ok considering the l4 latency.
if (*stat (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
omap_i2c_ack_stat(dev, *stat (OMAP_I2C_STAT_XRDY |
OMAP_I2C_STAT_XDR));
@@ -689,6 +691,9 @@ static int omap3430_workaround(struct omap_i2c_dev *dev,
u16 *stat, int *err)
*stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
}
+if (!timeout)
+dev_err(dev-dev, timeout waiting on XUDF bit\n);
+
return 0;
}
Regards,
Nishanth Menon
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[PATCH 0/2] omap i2c interrupt handler fixes
Hi, This is the second version of the patch that I've sent to linux-omap to address this issue. This time I've moved the whole errata workaround bit to a separate function to get rid of too long lines and a couple of extra levels of indentation. The actual fix is the same as the first time, it adds a timeout to a busy loop which happens to take place in an interrupt handler and is capable of hanging the kernel. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] omap i2c: make errata 1.153 workaround a separate function
This is to avoid insanely long lines and levels of indentation.
Signed-off-by: Alexander Shishkin virtu...@slind.org
CC: linux-...@vger.kernel.org
CC: linux-omap@vger.kernel.org
---
drivers/i2c/busses/i2c-omap.c | 43 ++--
1 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 75bf3ad..ad8242a 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -671,6 +671,27 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
#define omap_i2c_rev1_isr NULL
#endif
+/*
+ * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
+ * data to DATA_REG. Otherwise some data bytes can be lost while transferring
+ * them from the memory to the I2C interface.
+ */
+static int omap3430_workaround(struct omap_i2c_dev *dev, u16 *stat, int *err)
+{
+ while (!(*stat OMAP_I2C_STAT_XUDF)) {
+ if (*stat (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
+ omap_i2c_ack_stat(dev, *stat (OMAP_I2C_STAT_XRDY |
+ OMAP_I2C_STAT_XDR));
+ *err |= OMAP_I2C_STAT_XUDF;
+ return -1;
+ }
+ cpu_relax();
+ *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+ }
+
+ return 0;
+}
+
static irqreturn_t
omap_i2c_isr(int this_irq, void *dev_id)
{
@@ -794,25 +815,9 @@ complete:
break;
}
- /*
-* OMAP3430 Errata 1.153: When an XRDY/XDR
-* is hit, wait for XUDF before writing data
-* to DATA_REG. Otherwise some data bytes can
-* be lost while transferring them from the
-* memory to the I2C interface.
-*/
-
- if (dev-rev = OMAP_I2C_REV_ON_3430) {
- while (!(stat
OMAP_I2C_STAT_XUDF)) {
- if (stat
(OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
-
omap_i2c_ack_stat(dev, stat (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
- err |=
OMAP_I2C_STAT_XUDF;
- goto complete;
- }
- cpu_relax();
- stat =
omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
- }
- }
+ if (dev-rev = OMAP_I2C_REV_ON_3430
+ omap3430_workaround(dev, stat, err))
+ goto complete;
omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
}
--
1.6.3.3
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Re: [PATCH 1/2] omap i2c: make errata 1.153 workaround a separate function
On Wed, Dec 16, 2009 at 03:43:04 +0200, Alexander Shishkin wrote: From: Alexander Shishkin ext-alexander.shish...@nokia.com Please disregard this, I've got the emails wrong here. I'll resend shortly. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] omap i2c: make errata 1.153 workaround a separate function
This is to avoid insanely long lines and levels of indentation.
Signed-off-by: Alexander Shishkin virtu...@slind.org
CC: linux-...@vger.kernel.org
CC: linux-omap@vger.kernel.org
---
drivers/i2c/busses/i2c-omap.c | 43 ++--
1 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 75bf3ad..ad8242a 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -671,6 +671,27 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
#define omap_i2c_rev1_isr NULL
#endif
+/*
+ * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
+ * data to DATA_REG. Otherwise some data bytes can be lost while transferring
+ * them from the memory to the I2C interface.
+ */
+static int omap3430_workaround(struct omap_i2c_dev *dev, u16 *stat, int *err)
+{
+ while (!(*stat OMAP_I2C_STAT_XUDF)) {
+ if (*stat (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
+ omap_i2c_ack_stat(dev, *stat (OMAP_I2C_STAT_XRDY |
+ OMAP_I2C_STAT_XDR));
+ *err |= OMAP_I2C_STAT_XUDF;
+ return -1;
+ }
+ cpu_relax();
+ *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+ }
+
+ return 0;
+}
+
static irqreturn_t
omap_i2c_isr(int this_irq, void *dev_id)
{
@@ -794,25 +815,9 @@ complete:
break;
}
- /*
-* OMAP3430 Errata 1.153: When an XRDY/XDR
-* is hit, wait for XUDF before writing data
-* to DATA_REG. Otherwise some data bytes can
-* be lost while transferring them from the
-* memory to the I2C interface.
-*/
-
- if (dev-rev = OMAP_I2C_REV_ON_3430) {
- while (!(stat
OMAP_I2C_STAT_XUDF)) {
- if (stat
(OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
-
omap_i2c_ack_stat(dev, stat (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
- err |=
OMAP_I2C_STAT_XUDF;
- goto complete;
- }
- cpu_relax();
- stat =
omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
- }
- }
+ if (dev-rev = OMAP_I2C_REV_ON_3430
+ omap3430_workaround(dev, stat, err))
+ goto complete;
omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
}
--
1.6.3.3
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[PATCH 2/2] omap i2c: add a timeout to the busy waiting
The errata 1.153 workaround is busy waiting on XUDF bit in interrupt
context, which may lead to kernel hangs. The problem can be reproduced
by running the bus with wrong (too high) speed.
Signed-off-by: Alexander Shishkin virtu...@slind.org
CC: linux-...@vger.kernel.org
CC: linux-omap@vger.kernel.org
---
drivers/i2c/busses/i2c-omap.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index ad8242a..b474c20 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -678,7 +678,9 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
*/
static int omap3430_workaround(struct omap_i2c_dev *dev, u16 *stat, int *err)
{
- while (!(*stat OMAP_I2C_STAT_XUDF)) {
+ unsigned long timeout = 1;
+
+ while (!(*stat OMAP_I2C_STAT_XUDF --timeout)) {
if (*stat (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
omap_i2c_ack_stat(dev, *stat (OMAP_I2C_STAT_XRDY |
OMAP_I2C_STAT_XDR));
@@ -689,6 +691,9 @@ static int omap3430_workaround(struct omap_i2c_dev *dev,
u16 *stat, int *err)
*stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
}
+ if (!timeout)
+ dev_err(dev-dev, timeout waiting on XUDF bit\n);
+
return 0;
}
--
1.6.3.3
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[PATCH 0/2][RESEND] omap i2c interrupt handler fixes
Hi, This is the second version of the patch that I've sent to linux-omap to address this issue. This time I've moved the whole errata workaround bit to a separate function to get rid of too long lines and a couple of extra levels of indentation. The actual fix is the same as the first time, it adds a timeout to a busy loop which happens to take place in an interrupt handler and is capable of hanging the kernel. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: FEATURES - is it good enough
On Wed, Dec 02, 2009 at 08:06:16 +0200, Menon, Nishanth wrote: Alexander Shishkin said the following on 12/01/2009 05:42 PM: On Fri, Nov 20, 2009 at 02:09:01 -0600, Nishanth Menon wrote: Aguirre, Sergio had written, on 11/20/2009 01:43 PM, the following: -Original Message- From: Menon, Nishanth Sent: Friday, November 20, 2009 1:24 PM To: Kevin Hilman Cc: Shilimkar, Santosh; Aguirre, Sergio; Pandita, Vikram; linux-omap@vger.kernel.org Subject: Re: FEATURES - is it good enough Kevin Hilman had written, on 11/20/2009 12:35 PM, the following: Shilimkar, Santosh santosh.shilim...@ti.com writes: [...] Probably not something ot be attached in this patch, but... I'm a bit curious about something: Why touching omap3_features in OMAP4? Isn't there a omap4_features? Or even better, an omap_features? This is_feature suppose to take care of Errata's also, is it? It's not a bug it's a feature. :) Bug. Santosh pointed out internally to h/w discussion which clearly shows this as a h/w limitation. (thanks santosh) This is errata more than a feature. We better differentiate in this regard I agree, I have a hard time calling this empty fifo read fault a feature. We need a similar thing for errata. Agreed. This is a classic example why we need a common errata handling mechanism scalable across silicon variants on an IP basis. two problems in front of us: a) what do we want to do with 8250 workaround needed for omap3630 and omap4? can we go ahead with features marking it clearly as a misuse of features for the time being IMHO, That for the time being will stay forever if we don't do something now. Most of the big problems are raised because someone says ok, lets have this for the time being. But that time never comes. See that crazy CaMeL-Casing hanging around in /drivers/dsp/bridge/ for a while as an example. When that will ever be fixed? I bet someone said some time: ok, lets fix it later :-) On the other hand. What's the big motivation to have this as a feature? Who else than the serial driver cares about the feature awareness? please see [1] and [2]. this wont be the first time I published something previously that got ignored and got re-discussed. note: The [1] proposal sounds interesting to me, but it's not a very trivial matter. BTW, to be fair, DSPBridge already has plans to get fixed anyways.. Options I can think which were discussed: a) introduce omap3_features omap3_errata: negative: wont read like if I use omap3_has_errata() for OMAP4 code. b) introduce omap_features and omap_errata: negative: how do you link this to IP based usage across silicon (e.g. I2C). How about omap_has_errata(module, errata)? Or even something more generic? hmm.. just throwing more ideas up in the air: Call method: omap_ip_has_errata(u32 ip, u32 rev, u8 check_type, u8 erratum) where, ip = I2C, GPMC, MMC, etc.. rev = revision number check_type = GT, LT, NE, EQ erratum = erratum type omap_cpu_has_errata(u32 cpu_id, u32 rev, u8 check_type, u16 erratum) where, cpu_id = 15xx, 16xx etc ( can this be a function pointer to cpu_is..() functions? if so, how do we register this) rev = chip revision number Is there a use case when a caller would be interested in an erratum of a cpu other than the one it is currently running on? Otherwise it could be omap_this_cpu_has_errata(). And the same for IPs. check_type = GT, LT, NE, EQ Is this meant to compare cpu ids or revision numbers? I'm not sure I follow the idea here. erratum = erratum type Registration/Initialization: ?? Perhaps, statically compiled in tables of per-cpu/rev erratas/features. This has to be better than runtime detection and at least as good as making assumptions based on cpu_is_omap(). maybe this could be extended to features also.. Aren't features and erratas semantically the same thing? Maybe, the same interface could be used. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/2] arm: a driver for on-chip ETM and ETB
On Mon, Nov 09, 2009 at 01:48:10 +0200, Artem Bityutskiy wrote: On Fri, 2009-10-30 at 14:10 +0200, Alexander Shishkin wrote: On Thu, Oct 22, 2009 at 07:51:54PM +0300, Alexander Shishkin wrote: Changes: v3 -- major update: * switched from platform device to AMBA device * started using clk API in a more proper way * changed omap3 Kconfig part to select the driver instead of depending on it Russell, I believe this one addresses your concerns about my previous patches. Shall I wait for more comments from you or do you want me to upload them to your patch tracker? Alex, I suggest you to: 1. Double check that you really addressed _everything_ Russel and others pointed - may be this is the reason why your patch is stuck. 2. If you have addressed everything, upload the patch to the patch system. My (very limited) experience was that I re-sent a patch several times, got no response for long time, but then Russel simply asked me to upload it, and it was merged. Thus, the silence may simply mean upload to the patch system. Thanks for the hint. I've double checked the patches and I'm fairly sure I have addressed all of the concerns expressed to the best of my ability. So I did as you said: uploaded the patches to the patch tracker. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: FEATURES - is it good enough
On Fri, Nov 20, 2009 at 02:09:01 -0600, Nishanth Menon wrote: Aguirre, Sergio had written, on 11/20/2009 01:43 PM, the following: -Original Message- From: Menon, Nishanth Sent: Friday, November 20, 2009 1:24 PM To: Kevin Hilman Cc: Shilimkar, Santosh; Aguirre, Sergio; Pandita, Vikram; linux-omap@vger.kernel.org Subject: Re: FEATURES - is it good enough Kevin Hilman had written, on 11/20/2009 12:35 PM, the following: Shilimkar, Santosh santosh.shilim...@ti.com writes: [...] Probably not something ot be attached in this patch, but... I'm a bit curious about something: Why touching omap3_features in OMAP4? Isn't there a omap4_features? Or even better, an omap_features? This is_feature suppose to take care of Errata's also, is it? It's not a bug it's a feature. :) Bug. Santosh pointed out internally to h/w discussion which clearly shows this as a h/w limitation. (thanks santosh) This is errata more than a feature. We better differentiate in this regard I agree, I have a hard time calling this empty fifo read fault a feature. We need a similar thing for errata. Agreed. This is a classic example why we need a common errata handling mechanism scalable across silicon variants on an IP basis. two problems in front of us: a) what do we want to do with 8250 workaround needed for omap3630 and omap4? can we go ahead with features marking it clearly as a misuse of features for the time being IMHO, That for the time being will stay forever if we don't do something now. Most of the big problems are raised because someone says ok, lets have this for the time being. But that time never comes. See that crazy CaMeL-Casing hanging around in /drivers/dsp/bridge/ for a while as an example. When that will ever be fixed? I bet someone said some time: ok, lets fix it later :-) On the other hand. What's the big motivation to have this as a feature? Who else than the serial driver cares about the feature awareness? please see [1] and [2]. this wont be the first time I published something previously that got ignored and got re-discussed. note: The [1] proposal sounds interesting to me, but it's not a very trivial matter. BTW, to be fair, DSPBridge already has plans to get fixed anyways.. Options I can think which were discussed: a) introduce omap3_features omap3_errata: negative: wont read like if I use omap3_has_errata() for OMAP4 code. b) introduce omap_features and omap_errata: negative: how do you link this to IP based usage across silicon (e.g. I2C). How about omap_has_errata(module, errata)? Or even something more generic? Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 0/2] omap: serial: handle abort on empty rx fifo read
On Tue, Dec 01, 2009 at 06:50:31 +0530, Gadiyar, Anand wrote: Pandita, Vikram wrote: introduce OMAP3_HAS_UART_NO_EMPTY_FIFO_READ feature this feature is set for omap3630 and omap4 currently as empty uart rx fifo read causes an abort check on this feature on omap3630 and omap4 for now and extend for future vairants in future Patch history: V1: initial implementation http://patchwork.kernel.org/patch/60785/ http://patchwork.kernel.org/patch/60786/ V2: incorporate review comments from Alan Cox http://patchwork.kernel.org/patch/60785/ to remove 8250.c file changes by override serial_in No 8250 driver change required now V3: incorporate review comments khilman: make function override only for affected silicons nishant m: interoduce has_feature check, rather than cpu_is anand g: minor commit message change Vikram Pandita (2): omap: introduce uart_no_empty_fifo_read feature omap: serial: fix non-empty uart fifo read abort arch/arm/mach-omap2/id.c |7 +++ arch/arm/mach-omap2/serial.c | 21 + arch/arm/plat-omap/include/plat/cpu.h |2 ++ 3 files changed, 30 insertions(+), 0 deletions(-) Ping? Tony, These two patches are the only ones pending to make 3630 platforms boot up nicely. Would you consider taking them? Tested. ---cut--- [0.00] OMAP3630 ES1.0 (l2cache iva sgx neon isp uart_no_empty_fifo_read ) ---cut--- Acked-by: Alexander Shishkin virtu...@slind.org Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC] [PATCH] OMAP3630 PM: Correct width for CLKSEL Fields
On Wed, Nov 04, 2009 at 04:58:40 +0530, Sripathy, Vishwanath wrote:
@@ -134,13 +135,13 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL, omap_12m_fck, omap_12m_fck, CK_343X),
CLK(NULL, dpll4_m2_ck, dpll4_m2_ck, CK_343X),
CLK(NULL, dpll4_m2x2_ck, dpll4_m2x2_ck, CK_343X),
- CLK(NULL, dpll4_m3_ck, dpll4_m3_ck, CK_343X),
+ CLK(NULL, dpll4_m3_ck, dpll4_m3_ck, CK_343X | CK_363X),
CLK(NULL, dpll4_m3x2_ck, dpll4_m3x2_ck, CK_343X),
- CLK(NULL, dpll4_m4_ck, dpll4_m4_ck, CK_343X),
+ CLK(NULL, dpll4_m4_ck, dpll4_m4_ck, CK_343X | CK_363X),
CLK(NULL, dpll4_m4x2_ck, dpll4_m4x2_ck, CK_343X),
- CLK(NULL, dpll4_m5_ck, dpll4_m5_ck, CK_343X),
+ CLK(NULL, dpll4_m5_ck, dpll4_m5_ck, CK_343X | CK_363X),
CLK(NULL, dpll4_m5x2_ck, dpll4_m5x2_ck, CK_343X),
- CLK(NULL, dpll4_m6_ck, dpll4_m6_ck, CK_343X),
+ CLK(NULL, dpll4_m6_ck, dpll4_m6_ck, CK_343X | CK_363X),
CLK(NULL, dpll4_m6x2_ck, dpll4_m6x2_ck, CK_343X),
CLK(NULL, emu_per_alwon_ck, emu_per_alwon_ck, CK_343X),
CLK(NULL, dpll5_ck, dpll5_ck, CK_3430ES2),
Doesn't it make more sense to have separate dpll4_*_ck's for 363X so as to
avoid the clksel_mask_3630?
@@ -1216,6 +1217,10 @@ int __init omap2_clk_init(void)
cpu_mask |= RATE_IN_3430ES2;
cpu_clkflg |= CK_3430ES2;
}
+ if (cpu_is_omap36xx()) {
+ dpll4_dd.mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK;
+ cpu_mask |= RATE_IN_363X;
Extra space before '|'.
+ }
}
I think there's an indentation problem.
clk_init(omap2_clk_functions);
@@ -1225,6 +1230,11 @@ int __init omap2_clk_init(void)
for (c = omap34xx_clks; c omap34xx_clks + ARRAY_SIZE(omap34xx_clks);
c++)
if (c-cpu cpu_clkflg) {
+ /* for 3630, change the mask value for clocks which are
+ marked as CK_363X*/
+ if (cpu_is_omap36xx())
+ if (c-cpu CK_363X)
Extra space before ''.
+ c-lk.clk-clksel_mask =
c-lk.clk-clksel_mask_3630;
This looks longer than normally allowed.
Regards,
--
Alex
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Re: [PATCH v2 1/2] omap: add bits for future 3430/3630 ES revisions
2009/10/21 Nishanth Menon n...@ti.com:
Paul Walmsley had written, on 10/20/2009 06:14 PM, the following:
Hi Vikram, Nishanth, Richard,
a few comments on this:
On Tue, 20 Oct 2009, Vikram Pandita wrote:
Add bits for future expansion of omap_chip_id type field.
This is needed to accomodate 3630ES1 chip id which is bit10
...
diff --git a/arch/arm/plat-omap/include/plat/cpu.h
b/arch/arm/plat-omap/include/plat/cpu.h
index 7cb0556..922bf1c 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -45,7 +45,7 @@ int omap_type(void);
struct omap_chip_id {
u8 oc;
- u8 type;
+ u32 type;
};
Just wanted to understand the motivation for using the u32.
Earlier in the life of these patches, two comments were mentioned: the
desire to 'futureproof' and the desire to reserve space for other
34xx-family parts.
Regarding 'futureproofing:' that's part of the reason that a separate
struct was defined for this: to prevent code that uses it from depending on
the size of the type. (Originally it was a typedef, but Linus hates
typedefs...) So it shouldn't matter how big or small the type is here, as
long as it can handle all of the bits allocated for it.
Also mentioned was the idea of reserving space for other 34xx-family
chips. I'd suggest simply renumbering the bits when and if those versions
appear. Code that uses the omap_chip_id system should always use the macros
(e.g. CHIP_IS_OMAP3430) and not encode separate bit shift values, so
renumbering should be completely safe and transparent for core code. Module
code shouldn't be using the omap_chip code, it's for core usage only.
So, since only one bit is being added, why not continue the use of the u8?
Then when the next bits need to be added, the type can be expanded at that
point, and the bits renumbered if necessary. This should be a completely
transparent operation for code that uses it. Vikram's original patch:
http://patchwork.kernel.org/patch/54847/
should be fine.
Assumptions:
a) omap_chip_id is supposedly constant for all devices within the same
family. 3630, 3430 rev x will belong to the same family.
If my understanding of the matter is correct, that's only possible if
you can foretell the total number of upcoming 34xx revisions worth
mentioning in the code. Also, can you please elaborate on why is it
supposed to be constant?
Issues with the strategy of restricting to the current 8 bits:
a) Why extrabits now:
we have 8 bits now and we would have used all 8 bits with 3630 with the
mentioned patch. What do we do with the next revision of 3430? Do we want to
increase the size once it comes along? OR Do we want to do it right now? Why
wait till we get additional silicons to go figure how to add those bits as
Richard pointed out, when there could be one more in the pipeline?
But this code will have to be revisited for each additional silicon
revision anyway, right? Why reserve now?
Regards,
--
Alex
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Re: [PATCH] omap: 3630: update is_chip variable
2009/10/20 Vikram Pandita vikram.pand...@ti.com: 3630 is getting treated like next rev of 3430 omap_chip.oc variable has to be updated for 3630 version Otherwise the Core power domain is not getting registered. This gets used in the registration of power domains in: arch/arm/mach-omap2/powerdomains34xx.h core_34xx_es3_1_pwrdm OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1) Core power doman will get registered for 3630 only when .oc is pouplated correctly. Tested on Zoom3(3630) board Signed-off-by: Vikram Pandita vikram.pand...@ti.com FWIW, Signed-off-by: Alexander Shishkin virtu...@slind.org This version seems to be the common consensus (per discussion in v2 thread). Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] omap: 3630: update is_chip variable
On Mon, Nov 02, 2009 at 07:05:49PM +0200, Alexander Shishkin wrote: 2009/10/20 Vikram Pandita vikram.pand...@ti.com: 3630 is getting treated like next rev of 3430 omap_chip.oc variable has to be updated for 3630 version Otherwise the Core power domain is not getting registered. This gets used in the registration of power domains in: arch/arm/mach-omap2/powerdomains34xx.h core_34xx_es3_1_pwrdm OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1) Core power doman will get registered for 3630 only when .oc is pouplated correctly. Tested on Zoom3(3630) board Signed-off-by: Vikram Pandita vikram.pand...@ti.com FWIW, Signed-off-by: Alexander Shishkin virtu...@slind.org Please excuse me, I obviously wanted to say Acked-by: Alexander Shishkin virtu...@slind.org Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/2] arm: a driver for on-chip ETM and ETB
On Thu, Oct 22, 2009 at 07:51:54PM +0300, Alexander Shishkin wrote: Changes: v3 -- major update: * switched from platform device to AMBA device * started using clk API in a more proper way * changed omap3 Kconfig part to select the driver instead of depending on it Russell, I believe this one addresses your concerns about my previous patches. Shall I wait for more comments from you or do you want me to upload them to your patch tracker? Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/2] OMAP3: add AMBA devices for ETM and ETB
This enables on-chip tracing components found in omap3xxx.
Signed-off-by: Alexander Shishkin virtu...@slind.org
---
arch/arm/mach-omap2/Kconfig |8 +
arch/arm/mach-omap2/Makefile|3 ++
arch/arm/mach-omap2/clock34xx.c |8 ++--
arch/arm/mach-omap2/emu.c | 66 +++
4 files changed, 81 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mach-omap2/emu.c
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 15cb529..f50d5bc 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -96,3 +96,11 @@ config MACH_OMAP_ZOOM2
config MACH_OMAP_4430SDP
bool OMAP 4430 SDP board
depends on ARCH_OMAP4
+
+config OMAP3_EMU
+ bool OMAP3 tracing peripherals
+ depends on ARCH_OMAP3
+ select OC_ETM
+ help
+ Say Y here to enable tracing hardware of omap3
+
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 954693c..c0ceb8c 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -46,6 +46,9 @@ obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
obj-$(CONFIG_OMAP_PM_SRF) += resource34xx.o
+# EMU peripherals
+obj-$(CONFIG_OMAP3_EMU)+= emu.o
+
iommu-y+= iommu2.o
iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index da5bc1f..59d4320 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -123,7 +123,7 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL, dpll3_m2x2_ck, dpll3_m2x2_ck, CK_343X),
CLK(NULL, dpll3_m3_ck, dpll3_m3_ck, CK_343X),
CLK(NULL, dpll3_m3x2_ck, dpll3_m3x2_ck, CK_343X),
- CLK(NULL, emu_core_alwon_ck, emu_core_alwon_ck, CK_343X),
+ CLK(etb, emu_core_alwon_ck, emu_core_alwon_ck, CK_343X),
CLK(NULL, dpll4_ck, dpll4_ck, CK_343X),
CLK(NULL, dpll4_x2_ck, dpll4_x2_ck, CK_343X),
CLK(NULL, omap_96m_alwon_fck, omap_96m_alwon_fck, CK_343X),
@@ -142,7 +142,7 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL, dpll4_m5x2_ck, dpll4_m5x2_ck, CK_343X),
CLK(NULL, dpll4_m6_ck, dpll4_m6_ck, CK_343X),
CLK(NULL, dpll4_m6x2_ck, dpll4_m6x2_ck, CK_343X),
- CLK(NULL, emu_per_alwon_ck, emu_per_alwon_ck, CK_343X),
+ CLK(etb, emu_per_alwon_ck, emu_per_alwon_ck, CK_343X),
CLK(NULL, dpll5_ck, dpll5_ck, CK_3430ES2),
CLK(NULL, dpll5_m2_ck, dpll5_m2_ck, CK_3430ES2),
CLK(NULL, clkout2_src_ck, clkout2_src_ck, CK_343X),
@@ -151,7 +151,7 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL, dpll1_fck,dpll1_fck, CK_343X),
CLK(NULL, mpu_ck, mpu_ck,CK_343X),
CLK(NULL, arm_fck, arm_fck, CK_343X),
- CLK(NULL, emu_mpu_alwon_ck, emu_mpu_alwon_ck, CK_343X),
+ CLK(etb, emu_mpu_alwon_ck, emu_mpu_alwon_ck, CK_343X),
CLK(NULL, dpll2_fck,dpll2_fck, CK_343X),
CLK(NULL, iva2_ck, iva2_ck, CK_343X),
CLK(NULL, l3_ick, l3_ick,CK_343X),
@@ -306,7 +306,7 @@ static struct omap_clk omap34xx_clks[] = {
CLK(omap-mcbsp.2, fck, mcbsp2_fck,CK_343X),
CLK(omap-mcbsp.3, fck, mcbsp3_fck,CK_343X),
CLK(omap-mcbsp.4, fck, mcbsp4_fck,CK_343X),
- CLK(NULL, emu_src_ck, emu_src_ck,CK_343X),
+ CLK(etb, emu_src_ck, emu_src_ck,CK_343X),
CLK(NULL, pclk_fck, pclk_fck, CK_343X),
CLK(NULL, pclkx2_fck, pclkx2_fck,CK_343X),
CLK(NULL, atclk_fck,atclk_fck, CK_343X),
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
new file mode 100644
index 000..ec0d984
--- /dev/null
+++ b/arch/arm/mach-omap2/emu.c
@@ -0,0 +1,66 @@
+/*
+ * emu.c
+ *
+ * ETM and ETB CoreSight components' resources as found in OMAP3xxx.
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/types.h
+#include linux/module.h
+#include linux/device.h
+#include linux/amba/bus.h
+#include linux/io.h
+#include linux/clk.h
+#include linux/err.h
+
+MODULE_LICENSE(GPL);
+MODULE_AUTHOR(Alexander Shishkin);
+
+/* Cortex CoreSight components within omap3xxx EMU */
+#define ETM_BASE (L4_EMU_34XX_PHYS + 0x1)
+#define DBG_BASE (L4_EMU_34XX_PHYS + 0x11000)
+#define ETB_BASE (L4_EMU_34XX_PHYS + 0x1b000
[PATCH v3 1/2] arm: a driver for on-chip ETM and ETB
This driver implements support for on-chip Embedded Tracing Macrocell and
Embedded Trace Buffer. It allows to trigger tracing of kernel execution flow
and exporting trace output to userspace via character device and a sysrq
combo.
Trace output can then be decoded by a fairly simple open source tool [1]
which is already sufficient to get the idea of what the kernel is doing.
[1]: http://github.com/virtuoso/etm2human
Signed-off-by: Alexander Shishkin virtu...@slind.org
---
Changes:
v3 -- major update:
* switched from platform device to AMBA device
* started using clk API in a more proper way
* changed omap3 Kconfig part to select the driver instead of depending
on it
v2 -- major update:
* fixes according to comments from Linus Walleij and Anand Gadiyar
* omap3 clock-related stuff moved to platform device
v1 -- fixed comments from Juha Leppanen
v0 -- initial implementation, has been sent to linux-omap only
arch/arm/Kconfig.debug|8 +
arch/arm/include/asm/hardware/coresight.h | 165
arch/arm/kernel/Makefile |2 +
arch/arm/kernel/etm.c | 641 +
4 files changed, 816 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/hardware/coresight.h
create mode 100644 arch/arm/kernel/etm.c
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1a6f70e..ff54c23 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -83,6 +83,14 @@ config DEBUG_ICEDCC
It does include a timeout to ensure that the system does not
totally freeze when there is nothing connected to read.
+config OC_ETM
+ bool On-chip ETM and ETB
+ select ARM_AMBA
+ help
+ Enables the on-chip embedded trace macrocell and embedded trace
+ buffer driver that will allow you to collect traces of the
+ kernel code.
+
config DEBUG_DC21285_PORT
bool Kernel low-level debugging messages via footbridge serial port
depends on DEBUG_LL FOOTBRIDGE
diff --git a/arch/arm/include/asm/hardware/coresight.h
b/arch/arm/include/asm/hardware/coresight.h
new file mode 100644
index 000..f82b25d
--- /dev/null
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -0,0 +1,165 @@
+/*
+ * linux/arch/arm/include/asm/hardware/coresight.h
+ *
+ * CoreSight components' registers
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_HARDWARE_CORESIGHT_H
+#define __ASM_HARDWARE_CORESIGHT_H
+
+#define TRACER_ACCESSED_BIT0
+#define TRACER_RUNNING_BIT 1
+#define TRACER_CYCLE_ACC_BIT 2
+#define TRACER_ACCESSEDBIT(TRACER_ACCESSED_BIT)
+#define TRACER_RUNNING BIT(TRACER_RUNNING_BIT)
+#define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT)
+
+struct tracectx {
+ unsigned intetb_bufsz;
+ void __iomem*etb_regs;
+ void __iomem*etm_regs;
+ unsigned long flags;
+ int ncmppairs;
+ int etm_portsz;
+ struct device *dev;
+ struct clk *emu_clk;
+ struct mutexmutex;
+};
+
+#define TRACER_TIMEOUT 1
+
+#define etm_writel(t, v, x) \
+ (__raw_writel((v), (t)-etm_regs + (x)))
+#define etm_readl(t, x) (__raw_readl((t)-etm_regs + (x)))
+
+/* CoreSight Management Registers */
+#define CSMR_LOCKACCESS 0xfb0
+#define CSMR_LOCKSTATUS 0xfb4
+#define CSMR_AUTHSTATUS 0xfb8
+#define CSMR_DEVID 0xfc8
+#define CSMR_DEVTYPE 0xfcc
+/* CoreSight Component Registers */
+#define CSCR_CLASS 0xff4
+
+#define CSCR_PRSR 0x314
+
+#define UNLOCK_MAGIC 0xc5acce55
+
+/* ETM control register, ETM Architecture, 3.3.1 */
+#define ETMR_CTRL 0
+#define ETMCTRL_POWERDOWN 1
+#define ETMCTRL_PROGRAM(1 10)
+#define ETMCTRL_PORTSEL(1 11)
+#define ETMCTRL_DO_CONTEXTID (3 14)
+#define ETMCTRL_PORTMASK1 (7 4)
+#define ETMCTRL_PORTMASK2 (1 21)
+#define ETMCTRL_PORTMASK (ETMCTRL_PORTMASK1 | ETMCTRL_PORTMASK2)
+#define ETMCTRL_PORTSIZE(x) x) 7) 4) | (!!((x) 8)) 21)
+#define ETMCTRL_DO_CPRT(1 1)
+#define ETMCTRL_DATAMASK (3 2)
+#define ETMCTRL_DATA_DO_DATA (1 2)
+#define ETMCTRL_DATA_DO_ADDR (1 3)
+#define ETMCTRL_DATA_DO_BOTH (ETMCTRL_DATA_DO_DATA | ETMCTRL_DATA_DO_ADDR)
+#define ETMCTRL_BRANCH_OUTPUT (1 8)
+#define ETMCTRL_CYCLEACCURATE (1 12)
+
+/* ETM configuration code register */
+#define ETMR_CONFCODE (0x04)
+
+/* ETM trace start/stop resource control register */
+#define ETMR_TRACESSCTRL (0x18)
+
+/* ETM trigger event register */
+#define ETMR_TRIGEVT (0x08)
+
+/* address access type register bits, ETM architecture,
+ * table 3-27 */
+/* - access type
Re: [PATCH v2 1/2] arm: a driver for on-chip ETM and ETB
2009/10/13 Russell King - ARM Linux li...@arm.linux.org.uk: On Tue, Oct 13, 2009 at 08:06:50PM +0300, Alexander Shishkin wrote: Changes: v2 -- major update: * fixes according to comments from Linus Walleij and Anand Gadiyar * omap3 clock-related stuff moved to platform device And so what about my comments? Ah, sorry about that. It was just that the same comments were given by Linus, so my reply regarding those was to him. Generally, my concern was that to make not all of the ETM versions even have a memory-mapped registers (earlier versions use cp14 instead; I don't support those at the moment, but it might be a nice thing to do that in future) and some of the registers which the AMBA framework seems to rely (peripheral id and component id) on are only available since ETMv3.2. And the most recent version mentioned in ETM architecture document is 3.4. That said, I'm personally not overly concerned about the support for earlier versions of those macrocells and if you maintain that those are better off implemented as AMBA drivers, I've not problem doing that. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/2] OMAP3: add platform devices for ETM and ETB
This enables on-chip tracing components found in omap3xxx.
Signed-off-by: Alexander Shishkin virtu...@slind.org
---
Changes:
v2 -- use emu_src clock for etb; feed it from sys_ck
arch/arm/mach-omap2/Kconfig |7 +++
arch/arm/mach-omap2/Makefile |3 +
arch/arm/mach-omap2/emu.c| 95 ++
3 files changed, 105 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/emu.c
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 15cb529..4fbbb39 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -96,3 +96,10 @@ config MACH_OMAP_ZOOM2
config MACH_OMAP_4430SDP
bool OMAP 4430 SDP board
depends on ARCH_OMAP4
+
+config OMAP3_EMU
+ bool OMAP3 debugging peripherals
+ depends on ARCH_OMAP3 OC_ETM
+ help
+ Say Y here to enable debugging hardware of omap3
+
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 9e63562..d1e172b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -44,6 +44,9 @@ obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o
obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
+# EMU periferals
+obj-$(CONFIG_OMAP3_EMU)+= emu.o
+
iommu-y+= iommu2.o
iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
new file mode 100644
index 000..d2f03a9
--- /dev/null
+++ b/arch/arm/mach-omap2/emu.c
@@ -0,0 +1,95 @@
+/*
+ * emu.c
+ *
+ * ETM and ETB CoreSight components' resources as found in OMAP3xxx.
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/types.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/io.h
+#include linux/clk.h
+#include linux/err.h
+
+MODULE_LICENSE(GPL);
+MODULE_AUTHOR(Alexander Shishkin);
+
+/* Cortex CoreSight components within omap3xxx EMU */
+#define ETM_BASE (L4_EMU_34XX_PHYS + 0x1)
+#define DBG_BASE (L4_EMU_34XX_PHYS + 0x11000)
+#define ETB_BASE (L4_EMU_34XX_PHYS + 0x1b000)
+#define DAPCTL (L4_EMU_34XX_PHYS + 0x1d000)
+
+static struct resource omap3_etb_resource = {
+ .start = ETB_BASE,
+ .end = ETB_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device omap3_etb_device = {
+ .name = etb,
+ .id = -1,
+ .num_resources = 1,
+ .resource = omap3_etb_resource,
+};
+
+static struct resource omap3_etm_resource = {
+ .start = ETM_BASE,
+ .end = ETM_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device omap3_etm_device = {
+ .name = etm,
+ .id = -1,
+ .num_resources = 1,
+ .resource = omap3_etm_resource,
+};
+
+static struct platform_device *omap3_trace_devices[] = {
+ omap3_etm_device,
+ omap3_etb_device,
+};
+
+static int __init emu_init(void)
+{
+ struct clk *emu_clk, *sys_clk;
+
+ platform_add_devices(omap3_trace_devices,
+ ARRAY_SIZE(omap3_trace_devices));
+
+ sys_clk = clk_get(omap3_etb_device.dev, sys_ck);
+ if (IS_ERR(sys_clk)) {
+ dev_dbg(omap3_etb_device.dev, Failed to obtain sys_ck.\n);
+ return -EFAULT;
+ }
+
+ emu_clk = clk_get(omap3_etb_device.dev, emu_src_ck);
+ if (IS_ERR(emu_clk)) {
+ dev_dbg(omap3_etb_device.dev,
+ Failed to obtain emu_src_ck.\n);
+ return -EFAULT;
+ }
+
+ if (clk_set_parent(emu_clk, sys_clk)) {
+ dev_dbg(omap3_etb_device.dev, clk_set_parent failed.\n);
+ return -EFAULT;
+ }
+
+ /* looks like we could use IORESOURCE_CLOCK */
+ platform_device_add_data(omap3_etb_device, emu_clk, sizeof(emu_clk));
+
+ return 0;
+}
+
+subsys_initcall(emu_init);
+
--
1.6.3.3
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/2] arm: a driver for on-chip ETM and ETB
This driver implements support for on-chip Embedded Tracing Macrocell and
Embedded Trace Buffer. It allows to trigger tracing of kernel execution flow
and exporting trace output to userspace via character device and a sysrq
combo.
Trace output can then be decoded by a fairly simple open source tool [1]
which is already sufficient to get the idea of what the kernel is doing.
[1]: http://github.com/virtuoso/etm2human
Signed-off-by: Alexander Shishkin virtu...@slind.org
---
Changes:
v2 -- major update:
* fixes according to comments from Linus Walleij and Anand Gadiyar
* omap3 clock-related stuff moved to platform device
v1 -- fixed comments from Juha Leppanen
v0 -- initial implementation, has been sent to linux-omap only
arch/arm/Kconfig.debug|8 +
arch/arm/include/asm/hardware/coresight.h | 164
arch/arm/kernel/Makefile |2 +
arch/arm/kernel/etm.c | 593 +
4 files changed, 767 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/hardware/coresight.h
create mode 100644 arch/arm/kernel/etm.c
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1a6f70e..3c20e7f 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -83,6 +83,14 @@ config DEBUG_ICEDCC
It does include a timeout to ensure that the system does not
totally freeze when there is nothing connected to read.
+config OC_ETM
+ bool On-chip ETM and ETB
+ depends on ARCH_OMAP3
+ help
+ Enables the on-chip embedded trace macrocell and embedded trace
+ buffer driver that will allow you to collect traces of the
+ kernel code.
+
config DEBUG_DC21285_PORT
bool Kernel low-level debugging messages via footbridge serial port
depends on DEBUG_LL FOOTBRIDGE
diff --git a/arch/arm/include/asm/hardware/coresight.h
b/arch/arm/include/asm/hardware/coresight.h
new file mode 100644
index 000..3ba99c1
--- /dev/null
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -0,0 +1,164 @@
+/*
+ * linux/arch/arm/include/asm/hardware/coresight.h
+ *
+ * CoreSight components' registers
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_HARDWARE_CORESIGHT_H
+#define __ASM_HARDWARE_CORESIGHT_H
+
+#define TRACER_ACCESSED_BIT0
+#define TRACER_RUNNING_BIT 1
+#define TRACER_CYCLE_ACC_BIT 2
+#define TRACER_ACCESSEDBIT(TRACER_ACCESSED_BIT)
+#define TRACER_RUNNING BIT(TRACER_RUNNING_BIT)
+#define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT)
+
+struct tracectx {
+ unsigned intetb_bufsz;
+ void __iomem*etb_regs;
+ void __iomem*etm_regs;
+ unsigned long flags;
+ int ncmppairs;
+ int etm_portsz;
+ struct device *dev;
+ struct mutexmutex;
+};
+
+#define TRACER_TIMEOUT 1
+
+#define etm_writel(t, v, x) \
+ (__raw_writel((v), (t)-etm_regs + (x)))
+#define etm_readl(t, x) (__raw_readl((t)-etm_regs + (x)))
+
+/* CoreSight Management Registers */
+#define CSMR_LOCKACCESS 0xfb0
+#define CSMR_LOCKSTATUS 0xfb4
+#define CSMR_AUTHSTATUS 0xfb8
+#define CSMR_DEVID 0xfc8
+#define CSMR_DEVTYPE 0xfcc
+/* CoreSight Component Registers */
+#define CSCR_CLASS 0xff4
+
+#define CSCR_PRSR 0x314
+
+#define UNLOCK_MAGIC 0xc5acce55
+
+/* ETM control register, ETM Architecture, 3.3.1 */
+#define ETMR_CTRL 0
+#define ETMCTRL_POWERDOWN 1
+#define ETMCTRL_PROGRAM(1 10)
+#define ETMCTRL_PORTSEL(1 11)
+#define ETMCTRL_DO_CONTEXTID (3 14)
+#define ETMCTRL_PORTMASK1 (7 4)
+#define ETMCTRL_PORTMASK2 (1 21)
+#define ETMCTRL_PORTMASK (ETMCTRL_PORTMASK1 | ETMCTRL_PORTMASK2)
+#define ETMCTRL_PORTSIZE(x) x) 7) 4) | (!!((x) 8)) 21)
+#define ETMCTRL_DO_CPRT(1 1)
+#define ETMCTRL_DATAMASK (3 2)
+#define ETMCTRL_DATA_DO_DATA (1 2)
+#define ETMCTRL_DATA_DO_ADDR (1 3)
+#define ETMCTRL_DATA_DO_BOTH (ETMCTRL_DATA_DO_DATA | ETMCTRL_DATA_DO_ADDR)
+#define ETMCTRL_BRANCH_OUTPUT (1 8)
+#define ETMCTRL_CYCLEACCURATE (1 12)
+
+/* ETM configuration code register */
+#define ETMR_CONFCODE (0x04)
+
+/* ETM trace start/stop resource control register */
+#define ETMR_TRACESSCTRL (0x18)
+
+/* ETM trigger event register */
+#define ETMR_TRIGEVT (0x08)
+
+/* address access type register bits, ETM architecture,
+ * table 3-27 */
+/* - access type */
+#define ETMAAT_IFETCH 0
+#define ETMAAT_IEXEC 1
+#define ETMAAT_IEXECPASS 2
+#define ETMAAT_IEXECFAIL 3
+#define ETMAAT_DLOADSTORE 4
+#define ETMAAT_DLOAD 5
+#define ETMAAT_DSTORE 6
Re: [PATCH v1 1/2] arm: a driver for on-chip ETM and ETB
2009/10/12 Linus Walleij linus.ml.wall...@gmail.com:
2009/10/11 Alexander Shishkin virtu...@slind.org:
This driver implements support for on-chip Embedded Tracing Macrocell and
Embedded Trace Buffer. It allows to trigger tracing of kernel execution flow
and exporting trace output to userspace via character device and a sysrq
combo.
Cool, can it at all be interfaced to kernel tracing mechanisms like
ftrace, LTTng...? Or is this entirely orthogonal?
I'll have to check on that.
First, these are registered as platform devices, should they not be AMBA
devices (i.e. PrimeCells?) I think that's what they are, and they probably
have device ID:s to be matched in the last words of their 4K pages
do they not?
Only ETMv3.2 and are said to comply with AMBA with regards to
peripheral id and component id registers and I'm not quite sure how
useful those are. Whereas having those as platform devices provides
the possibility to have them defined per platform for most of ETM
versions.
(...)
diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c
new file mode 100644
index 000..3e7b431
--- /dev/null
+++ b/arch/arm/kernel/etm.c
@@ -0,0 +1,588 @@
+/*
+ * linux/arch/arm/kernel/etm.c
+ *
+ * Driver for ARM's Embedded Trace Macrocell and Embedded Trace Buffer.
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/types.h
+#include linux/io.h
+#include linux/clk.h
+#include linux/sysrq.h
+#include linux/platform_device.h
+#include linux/fs.h
+#include linux/uaccess.h
+#include linux/miscdevice.h
+#include linux/vmalloc.h
+#include linux/mutex.h
+#include asm/hardware/coresight.h
+#include asm/sections.h
+
+MODULE_LICENSE(GPL);
+MODULE_AUTHOR(Alexander Shishkin);
+
+static struct tracectx tracer;
+
+static inline bool trace_isrunning(struct tracectx *t)
+{
+ return !!(t-flags TRACER_RUNNING);
+}
+
+static int etm_setup_address_range(struct tracectx *t, int n,
+ unsigned long start, unsigned long end, int exclude, int
data)
+{
+ u32 flags = ETMAAT_ARM | ETMAAT_IGNCONTEXTID | ETMAAT_NSONLY | \
+ ETMAAT_NOVALCMP;
+
+ if (n 1 || n t-ncmppairs)
+ return -EINVAL;
+
+ /* comparators and ranges are numbered starting with 1 as opposed
+ * to bits in a word */
+ n--;
+
+ if (data)
+ flags |= ETMAAT_DLOADSTORE;
+ else
+ flags |= ETMAAT_IEXEC;
+
+ /* first comparator for the range */
+ etm_writel(t, flags, ETMR_COMP_ACC_TYPE(n * 2));
+ etm_writel(t, start, ETMR_COMP_VAL(n * 2));
+
+ /* second comparator is right next to it */
+ etm_writel(t, flags, ETMR_COMP_ACC_TYPE(n * 2 + 1));
+ etm_writel(t, end, ETMR_COMP_VAL(n * 2 + 1));
+
+ flags = exclude ? ETMTE_INCLEXCL : 0;
+ etm_writel(t, flags | (1 n), ETMR_TRACEENCTRL);
+
+ return 0;
+}
+
+static int trace_start(struct tracectx *t)
+{
+ u32 v;
+ unsigned long timeout = TRACER_TIMEOUT;
+
+ etb_unlock(t);
+
+ etb_writel(t, 0, ETBR_FORMATTERCTRL);
+ etb_writel(t, 1, ETBR_CTRL);
+
+ etb_lock(t);
+
+ /* configure etm */
+ v = ETMCTRL_OPTS | ETMCTRL_PROGRAM | ETMCTRL_PORTSIZE(t-etm_portsz);
+
+ if (t-flags TRACER_CYCLE_ACC)
+ v |= ETMCTRL_CYCLEACCURATE;
+
+ etm_unlock(t);
+
+ etm_writel(t, v, ETMR_CTRL);
+
+ while (!(etm_readl(t, ETMR_CTRL) ETMCTRL_PROGRAM) --timeout)
+ ;
+ if (!timeout) {
+ dev_dbg(t-dev, Waiting for progbit to assert timed out\n);
+ etm_lock(t);
+ return -EFAULT;
+ }
+
+ etm_setup_address_range(t, 1, (unsigned long)_stext,
+ (unsigned long)_etext, 0, 0);
+ etm_writel(t, 0, ETMR_TRACEENCTRL2);
+ etm_writel(t, 0, ETMR_TRACESSCTRL);
+ etm_writel(t, 0x6f, ETMR_TRACEENEVT);
+
+ v = ~ETMCTRL_PROGRAM;
+ v |= ETMCTRL_PORTSEL;
+
+ etm_writel(t, v, ETMR_CTRL);
+
+ timeout = TRACER_TIMEOUT;
+ while (etm_readl(t, ETMR_CTRL) ETMCTRL_PROGRAM --timeout)
+ ;
+ if (!timeout) {
+ dev_dbg(t-dev, Waiting for progbit to deassert timed
out\n);
+ etm_lock(t);
+ return -EFAULT;
+ }
+
+ etm_lock(t);
+
+ t-flags |= TRACER_RUNNING;
+
+ return 0;
+}
+
+static int trace_stop(struct tracectx *t)
+{
+ unsigned long timeout = TRACER_TIMEOUT;
+
+ etm_unlock(t);
+
+ etm_writel(t, 0x440, ETMR_CTRL);
+ while (!(etm_readl(t, ETMR_CTRL) ETMCTRL_PROGRAM) --timeout
[PATCH v1 1/2] arm: a driver for on-chip ETM and ETB
This driver implements support for on-chip Embedded Tracing Macrocell and
Embedded Trace Buffer. It allows to trigger tracing of kernel execution flow
and exporting trace output to userspace via character device and a sysrq
combo.
Trace output can then be decoded by a fairly simple open source tool [1]
which is already sufficient to get the idea of what the kernel is doing.
[1]: http://github.com/virtuoso/etm2human
Signed-off-by: Alexander Shishkin virtu...@slind.org
Signed-off-by: Juha Leppanen juha_motorsport...@luukku.com
---
Changes:
v1 -- fixed comments from Juha Leppanen
v0 -- initial implementation, has been sent to linux-omap only
arch/arm/Kconfig.debug|8 +
arch/arm/include/asm/hardware/coresight.h | 164
arch/arm/kernel/Makefile |2 +
arch/arm/kernel/etm.c | 588 +
4 files changed, 762 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/hardware/coresight.h
create mode 100644 arch/arm/kernel/etm.c
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1a6f70e..ac83c03 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -83,6 +83,14 @@ config DEBUG_ICEDCC
It does include a timeout to ensure that the system does not
totally freeze when there is nothing connected to read.
+config OC_ETM
+ tristate On-chip ETM and ETB
+ depends on ARCH_OMAP3
+ help
+ Enables the on-chip embedded trace macrocell and embedded trace
+ buffer driver that will allow you to collect traces of the
+ kernel code.
+
config DEBUG_DC21285_PORT
bool Kernel low-level debugging messages via footbridge serial port
depends on DEBUG_LL FOOTBRIDGE
diff --git a/arch/arm/include/asm/hardware/coresight.h
b/arch/arm/include/asm/hardware/coresight.h
new file mode 100644
index 000..ba22df9
--- /dev/null
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -0,0 +1,164 @@
+/*
+ * linux/arch/arm/include/asm/hardware/coresight.h
+ *
+ * CoreSight components' registers
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_HARDWARE_CORESIGHT_H
+#define __ASM_HARDWARE_CORESIGHT_H
+
+#define TRACER_ACCESSED_BIT0
+#define TRACER_RUNNING_BIT 1
+#define TRACER_CYCLE_ACC_BIT 2
+#define TRACER_ACCESSEDBIT(TRACER_ACCESSED_BIT)
+#define TRACER_RUNNING BIT(TRACER_RUNNING_BIT)
+#define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT)
+
+struct tracectx {
+ unsigned int etb_bufsz;
+ void __iomem *etb_regs;
+ void __iomem *etm_regs;
+ unsigned long flags;
+ int ncmppairs;
+ int etm_portsz;
+ struct device *dev;
+ struct mutex mutex;
+};
+
+#define TRACER_TIMEOUT 1
+
+#define etm_writel(t, v, x) \
+ (__raw_writel((v), (t)-etm_regs + (x)))
+#define etm_readl(t, x) (__raw_readl((t)-etm_regs + (x)))
+
+/* CoreSight Management Registers */
+#define CSMR_LOCKACCESS 0xfb0
+#define CSMR_LOCKSTATUS 0xfb4
+#define CSMR_AUTHSTATUS 0xfb8
+#define CSMR_DEVID 0xfc8
+#define CSMR_DEVTYPE 0xfcc
+/* CoreSight Component Registers */
+#define CSCR_CLASS 0xff4
+
+#define CSCR_PRSR 0x314
+
+#define UNLOCK_MAGIC 0xc5acce55
+
+/* ETM control register, ETM Architecture, 3.3.1 */
+#define ETMR_CTRL 0
+#define ETMCTRL_POWERDOWN 1
+#define ETMCTRL_PROGRAM(1 10)
+#define ETMCTRL_PORTSEL(1 11)
+#define ETMCTRL_DO_CONTEXTID (3 14)
+#define ETMCTRL_PORTMASK1 (7 4)
+#define ETMCTRL_PORTMASK2 (1 21)
+#define ETMCTRL_PORTMASK (ETMCTRL_PORTMASK1 | ETMCTRL_PORTMASK2)
+#define ETMCTRL_PORTSIZE(x) x) 7) 4) | (!!((x) 8)) 21)
+#define ETMCTRL_DO_CPRT(1 1)
+#define ETMCTRL_DATAMASK (3 2)
+#define ETMCTRL_DATA_DO_DATA (1 2)
+#define ETMCTRL_DATA_DO_ADDR (1 3)
+#define ETMCTRL_DATA_DO_BOTH (ETMCTRL_DATA_DO_DATA | ETMCTRL_DATA_DO_ADDR)
+#define ETMCTRL_BRANCH_OUTPUT (1 8)
+#define ETMCTRL_CYCLEACCURATE (1 12)
+
+/* ETM configuration code register */
+#define ETMR_CONFCODE (0x04)
+
+/* ETM trace start/stop resource control register */
+#define ETMR_TRACESSCTRL (0x18)
+
+/* ETM trigger event register */
+#define ETMR_TRIGEVT (0x08)
+
+/* address access type register bits, ETM architecture,
+ * table 3-27 */
+/* - access type */
+#define ETMAAT_IFETCH 0
+#define ETMAAT_IEXEC 1
+#define ETMAAT_IEXECPASS 2
+#define ETMAAT_IEXECFAIL 3
+#define ETMAAT_DLOADSTORE 4
+#define ETMAAT_DLOAD 5
+#define ETMAAT_DSTORE 6
+/* - comparison access size */
+#define ETMAAT_JAVA(0 3)
+#define ETMAAT_THUMB (1 3)
+#define ETMAAT_ARM
[PATCH v1 2/2] OMAP3: add platform devices for ETM and ETB
This enables debug components found in omap3xxx.
Signed-off-by: Alexander Shishkin virtu...@slind.org
---
arch/arm/mach-omap2/Kconfig |7
arch/arm/mach-omap2/Makefile |3 ++
arch/arm/mach-omap2/emu.c| 70 ++
3 files changed, 80 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/emu.c
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 75b1c7e..87bcc2a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -88,3 +88,10 @@ config MACH_OMAP_ZOOM2
config MACH_OMAP_4430SDP
bool OMAP 4430 SDP board
depends on ARCH_OMAP4
+
+config OMAP3_EMU
+ tristate OMAP3 debugging peripherals
+ depends on ARCH_OMAP3 OC_ETM
+ help
+ Say Y here to enable debugging hardware of omap3
+
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 6b7702f..572dd27 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -44,6 +44,9 @@ obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o
obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
+# EMU periferals
+obj-$(CONFIG_OMAP3_EMU)+= emu.o
+
iommu-y+= iommu2.o
iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
new file mode 100644
index 000..f98874e
--- /dev/null
+++ b/arch/arm/mach-omap2/emu.c
@@ -0,0 +1,70 @@
+/*
+ * linux/arch/arm/mach-omap2/emu.c
+ *
+ * ETM and ETB CoreSight components' resources as found in OMAP3xxx.
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/types.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/io.h
+
+MODULE_LICENSE(GPL);
+MODULE_AUTHOR(Alexander Shishkin);
+
+/* Cortex CoreSight components within omap3xxx EMU */
+#define ETM_BASE (L4_EMU_34XX_PHYS + 0x1)
+#define DBG_BASE (L4_EMU_34XX_PHYS + 0x11000)
+#define ETB_BASE (L4_EMU_34XX_PHYS + 0x1b000)
+#define DAPCTL (L4_EMU_34XX_PHYS + 0x1d000)
+
+static struct resource rx51_etb_resource = {
+ .start = ETB_BASE,
+ .end = ETB_BASE + SZ_4K,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device rx51_etb_device = {
+ .name = etb,
+ .id = -1,
+ .num_resources = 1,
+ .resource = rx51_etb_resource,
+};
+
+static struct resource rx51_etm_resource = {
+ .start = ETM_BASE,
+ .end = ETM_BASE + SZ_4K,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device rx51_etm_device = {
+ .name = etm,
+ .id = -1,
+ .num_resources = 1,
+ .resource = rx51_etm_resource,
+};
+
+static struct platform_device *rx51_trace_devices[] = {
+ rx51_etm_device,
+ rx51_etb_device,
+};
+
+static int __init emu_init(void)
+{
+ platform_add_devices(rx51_trace_devices,
+ ARRAY_SIZE(rx51_trace_devices));
+
+ return 0;
+}
+
+module_init(emu_init);
+
--
1.6.3.3
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Re: [PATCH 1/2] arm/omap3: a driver for on-chip ETM and ETB
2009/10/10 Shilimkar, Santosh santosh.shilim...@ti.com: -Original Message- From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap- ow...@vger.kernel.org] On Behalf Of virtu...@slind.org Sent: Thursday, October 08, 2009 3:06 AM To: linux-omap@vger.kernel.org Cc: Alexander Shishkin Subject: [PATCH 1/2] arm/omap3: a driver for on-chip ETM and ETB From: Alexander Shishkin virtu...@slind.org This driver implements /dev/tracebuf and some control files for ETM and ETB in sysfs. Looks like a very useful driver for tracing/debug. Do you have some README link on the usage of this driver ? Well, here's a brief intro into how to collect traces and decode them: http://wiki.github.com/virtuoso/etm2human/quickstart That's not much, but if you have any questions, just email them to me and I'll try to update the page. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] OMAP3: add platform devices for ETM and ETB
This enables debug components found in omap3xxx.
Signed-off-by: Alexander Shishkin virtu...@slind.org
---
arch/arm/mach-omap2/Kconfig |7
arch/arm/mach-omap2/Makefile |3 ++
arch/arm/mach-omap2/emu.c| 70 ++
3 files changed, 80 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/emu.c
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 75b1c7e..87bcc2a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -88,3 +88,10 @@ config MACH_OMAP_ZOOM2
config MACH_OMAP_4430SDP
bool OMAP 4430 SDP board
depends on ARCH_OMAP4
+
+config OMAP3_EMU
+ tristate OMAP3 debugging peripherals
+ depends on ARCH_OMAP3 OC_ETM
+ help
+ Say Y here to enable debugging hardware of omap3
+
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 6b7702f..572dd27 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -44,6 +44,9 @@ obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o
obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
+# EMU periferals
+obj-$(CONFIG_OMAP3_EMU)+= emu.o
+
iommu-y+= iommu2.o
iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
new file mode 100644
index 000..f98874e
--- /dev/null
+++ b/arch/arm/mach-omap2/emu.c
@@ -0,0 +1,70 @@
+/*
+ * linux/arch/arm/mach-omap2/emu.c
+ *
+ * ETM and ETB CoreSight components' resources as found in OMAP3xxx.
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/types.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/io.h
+
+MODULE_LICENSE(GPL);
+MODULE_AUTHOR(Alexander Shishkin);
+
+/* Cortex CoreSight components within omap3xxx EMU */
+#define ETM_BASE (L4_EMU_34XX_PHYS + 0x1)
+#define DBG_BASE (L4_EMU_34XX_PHYS + 0x11000)
+#define ETB_BASE (L4_EMU_34XX_PHYS + 0x1b000)
+#define DAPCTL (L4_EMU_34XX_PHYS + 0x1d000)
+
+static struct resource rx51_etb_resource = {
+ .start = ETB_BASE,
+ .end = ETB_BASE + SZ_4K,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device rx51_etb_device = {
+ .name = etb,
+ .id = -1,
+ .num_resources = 1,
+ .resource = rx51_etb_resource,
+};
+
+static struct resource rx51_etm_resource = {
+ .start = ETM_BASE,
+ .end = ETM_BASE + SZ_4K,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device rx51_etm_device = {
+ .name = etm,
+ .id = -1,
+ .num_resources = 1,
+ .resource = rx51_etm_resource,
+};
+
+static struct platform_device *rx51_trace_devices[] = {
+ rx51_etm_device,
+ rx51_etb_device,
+};
+
+static int __init emu_init(void)
+{
+ platform_add_devices(rx51_trace_devices,
+ ARRAY_SIZE(rx51_trace_devices));
+
+ return 0;
+}
+
+module_init(emu_init);
+
--
1.6.3.3
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[PATCH 1/2] arm: a driver for on-chip ETM and ETB
This driver implements support for on-chip Embedded Tracing Macrocell and
Embedded Trace Buffer. It allows to trigger tracing of kernel execution flow
and exporting trace output to userspace via character device and a sysrq
combo.
Trace output can then be decoded by a fairly simple open source tool [1]
which is already sufficient to get the idea of what the kernel is doing.
[1]: http://github.com/virtuoso/etm2human
Signed-off-by: Alexander Shishkin virtu...@slind.org
---
arch/arm/Kconfig.debug|8 +
arch/arm/include/asm/hardware/coresight.h | 164
arch/arm/kernel/Makefile |2 +
arch/arm/kernel/etm.c | 584 +
4 files changed, 758 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/hardware/coresight.h
create mode 100644 arch/arm/kernel/etm.c
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1a6f70e..ac83c03 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -83,6 +83,14 @@ config DEBUG_ICEDCC
It does include a timeout to ensure that the system does not
totally freeze when there is nothing connected to read.
+config OC_ETM
+ tristate On-chip ETM and ETB
+ depends on ARCH_OMAP3
+ help
+ Enables the on-chip embedded trace macrocell and embedded trace
+ buffer driver that will allow you to collect traces of the
+ kernel code.
+
config DEBUG_DC21285_PORT
bool Kernel low-level debugging messages via footbridge serial port
depends on DEBUG_LL FOOTBRIDGE
diff --git a/arch/arm/include/asm/hardware/coresight.h
b/arch/arm/include/asm/hardware/coresight.h
new file mode 100644
index 000..ba22df9
--- /dev/null
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -0,0 +1,164 @@
+/*
+ * linux/arch/arm/include/asm/hardware/coresight.h
+ *
+ * CoreSight components' registers
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_HARDWARE_CORESIGHT_H
+#define __ASM_HARDWARE_CORESIGHT_H
+
+#define TRACER_ACCESSED_BIT0
+#define TRACER_RUNNING_BIT 1
+#define TRACER_CYCLE_ACC_BIT 2
+#define TRACER_ACCESSEDBIT(TRACER_ACCESSED_BIT)
+#define TRACER_RUNNING BIT(TRACER_RUNNING_BIT)
+#define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT)
+
+struct tracectx {
+ unsigned int etb_bufsz;
+ void __iomem *etb_regs;
+ void __iomem *etm_regs;
+ unsigned long flags;
+ int ncmppairs;
+ int etm_portsz;
+ struct device *dev;
+ struct mutex mutex;
+};
+
+#define TRACER_TIMEOUT 1
+
+#define etm_writel(t, v, x) \
+ (__raw_writel((v), (t)-etm_regs + (x)))
+#define etm_readl(t, x) (__raw_readl((t)-etm_regs + (x)))
+
+/* CoreSight Management Registers */
+#define CSMR_LOCKACCESS 0xfb0
+#define CSMR_LOCKSTATUS 0xfb4
+#define CSMR_AUTHSTATUS 0xfb8
+#define CSMR_DEVID 0xfc8
+#define CSMR_DEVTYPE 0xfcc
+/* CoreSight Component Registers */
+#define CSCR_CLASS 0xff4
+
+#define CSCR_PRSR 0x314
+
+#define UNLOCK_MAGIC 0xc5acce55
+
+/* ETM control register, ETM Architecture, 3.3.1 */
+#define ETMR_CTRL 0
+#define ETMCTRL_POWERDOWN 1
+#define ETMCTRL_PROGRAM(1 10)
+#define ETMCTRL_PORTSEL(1 11)
+#define ETMCTRL_DO_CONTEXTID (3 14)
+#define ETMCTRL_PORTMASK1 (7 4)
+#define ETMCTRL_PORTMASK2 (1 21)
+#define ETMCTRL_PORTMASK (ETMCTRL_PORTMASK1 | ETMCTRL_PORTMASK2)
+#define ETMCTRL_PORTSIZE(x) x) 7) 4) | (!!((x) 8)) 21)
+#define ETMCTRL_DO_CPRT(1 1)
+#define ETMCTRL_DATAMASK (3 2)
+#define ETMCTRL_DATA_DO_DATA (1 2)
+#define ETMCTRL_DATA_DO_ADDR (1 3)
+#define ETMCTRL_DATA_DO_BOTH (ETMCTRL_DATA_DO_DATA | ETMCTRL_DATA_DO_ADDR)
+#define ETMCTRL_BRANCH_OUTPUT (1 8)
+#define ETMCTRL_CYCLEACCURATE (1 12)
+
+/* ETM configuration code register */
+#define ETMR_CONFCODE (0x04)
+
+/* ETM trace start/stop resource control register */
+#define ETMR_TRACESSCTRL (0x18)
+
+/* ETM trigger event register */
+#define ETMR_TRIGEVT (0x08)
+
+/* address access type register bits, ETM architecture,
+ * table 3-27 */
+/* - access type */
+#define ETMAAT_IFETCH 0
+#define ETMAAT_IEXEC 1
+#define ETMAAT_IEXECPASS 2
+#define ETMAAT_IEXECFAIL 3
+#define ETMAAT_DLOADSTORE 4
+#define ETMAAT_DLOAD 5
+#define ETMAAT_DSTORE 6
+/* - comparison access size */
+#define ETMAAT_JAVA(0 3)
+#define ETMAAT_THUMB (1 3)
+#define ETMAAT_ARM (3 3)
+/* - data value comparison control */
+#define ETMAAT_NOVALCMP(0 5)
+#define ETMAAT_VALMATCH(1 5)
+#define
Re: linux-omap git tree updated to v2.6.32-rc1, important changes, please read
2009/10/1 Roger Quadros ext-roger.quad...@nokia.com: ext Tony Lindgren wrote: * Gadiyar, Anand gadi...@ti.com [090930 10:05]: Anyway, I haven't been able to make 2.6.31 boot on beagleboard, and other people report similar issues: http://www.spinics.net/lists/linux-omap/msg17968.html Have you got 2.6.32-rc1 (+fixes) to boot? Hmm, looks like it's musb again. This is what I get on my overo after applying the DEBUG_LL hack from omap-debug branch: i've just sent a fix for this musb problem. patch is labelled twl4030: Fix boot with twl4030 usb transceiver enabled I can't quite locate it in linux-usb archives (or anywhere within google's reach). Could you sand it here or provide a link? Here you go. Patchwork rocks! http://patchwork.kernel.org/patch/50721/ Great, thanks. Roger, please send your fix to Samuel for merging. Meanwhile, I'll apply it into fixes-testing while waiting for it to get to mainline via Samuel. Regards, Tony OK Tony, I'll do that. It doesn't crash any more, but I fail to get it to work either: /sys/devices/platform/musb_hdrc/mode always says b_idle no matter what I do and the host never attempts to enumerate it (I have a g_ether statically compiled in for a gadget). Hints greatly appreciated. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: linux-omap git tree updated to v2.6.32-rc1, important changes, please read
2009/9/30 Roger Quadros ext-roger.quad...@nokia.com: ext Tony Lindgren wrote: * Felipe Contreras felipe.contre...@gmail.com [090929 10:24]: On Mon, Sep 28, 2009 at 10:04 PM, Tony Lindgren t...@atomide.com wrote: Hi all, I've updated our linux-omap tree to v2.6.32-rc1. I've also added a branch omap-2.6.31 for the old code. This time I also nuked the remaining omap legacy code we still had lurking around :) The commits at the end of this mail describe what I did first as commits, then I merged everything to be the same as the mainline v2.6.32-rc1. So currently the linux-omap master branch is: v2.6.32-rc1 + omap-fixes + ehci + cbus The new model is that I'll be resetting the linux-omap master branch to mainline at each -rc, then merge in our various upstream queues back in again. Excellent! I was wondering why this wasn't being done. I certainly hope linus' 2.6.32 will work on omap right away. Yeah, let's hope Tomi gets in the DSS2 code too. Anyway, I haven't been able to make 2.6.31 boot on beagleboard, and other people report similar issues: http://www.spinics.net/lists/linux-omap/msg17968.html Have you got 2.6.32-rc1 (+fixes) to boot? Hmm, looks like it's musb again. This is what I get on my overo after applying the DEBUG_LL hack from omap-debug branch: i've just sent a fix for this musb problem. patch is labelled twl4030: Fix boot with twl4030 usb transceiver enabled I can't quite locate it in linux-usb archives (or anywhere within google's reach). Could you sand it here or provide a link? Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: linux-omap git tree updated to v2.6.32-rc1, important changes, please read
2009/9/29 Tony Lindgren t...@atomide.com: * Alexander Shishkin virtu...@slind.org [090929 12:20]: 2009/9/29 Tony Lindgren t...@atomide.com: * Felipe Contreras felipe.contre...@gmail.com [090929 10:24]: On Mon, Sep 28, 2009 at 10:04 PM, Tony Lindgren t...@atomide.com wrote: Hi all, I've updated our linux-omap tree to v2.6.32-rc1. I've also added a branch omap-2.6.31 for the old code. This time I also nuked the remaining omap legacy code we still had lurking around :) The commits at the end of this mail describe what I did first as commits, then I merged everything to be the same as the mainline v2.6.32-rc1. So currently the linux-omap master branch is: v2.6.32-rc1 + omap-fixes + ehci + cbus The new model is that I'll be resetting the linux-omap master branch to mainline at each -rc, then merge in our various upstream queues back in again. Excellent! I was wondering why this wasn't being done. I certainly hope linus' 2.6.32 will work on omap right away. Yeah, let's hope Tomi gets in the DSS2 code too. Anyway, I haven't been able to make 2.6.31 boot on beagleboard, and other people report similar issues: http://www.spinics.net/lists/linux-omap/msg17968.html Have you got 2.6.32-rc1 (+fixes) to boot? Hmm, looks like it's musb again. This is what I get on my overo after applying the DEBUG_LL hack from omap-debug branch: 3musb_hdrc musb_hdrc: musb_init_controller failed with status -19 1Unable to handle kernel NULL pointer dereference at virtual address 1pgd = c0004000 1[] *pgd= Internal error: Oops: 5 [#1] dModules linked in: CPU: 0 Not tainted (2.6.32-rc2-05967-gd350540-dirty #892) PC is at musb_free+0x68/0xb8 LR is at musb_free+0x34/0xb8 pc : [c028a160] lr : [c028a12c] psr: a013 sp : c781fe50 ip : 0064 fp : r10: r9 : r8 : c0557bc0 r7 : c7811000 r6 : c78110e8 r5 : c78110e8 r4 : r3 : r2 : 0001 r1 : c04c95b6 r0 : ffed Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c5387d Table: 80004019 DAC: 0017 Process swapper (pid: 1, stack limit = 0xc781e2f0) Stack: (0xc781fe50 to 0xc782) fe40: ffed c78110e8 c001e8f8 fe60: c781fea4 c7804180 c7804184 c0533dc8 c0533dd0 005c d80ab000 fe80: c0533dac c7811190 c781fedc c0114ad8 c7806850 c0546248 c06d74e0 fea0: c03cd5c8 c781ff00 c78b8de0 c0114cbc c78b8d80 c781ff00 fec0: c78b8de0 c0114864 c78b8d80 c781ff00 c78b8de0 c011493c c781ff00 c78b8de0 fee0: c78b8d80 c781ff00 c78b8de0 c787a210 0001 c01157b4 ff00: c787a210 c0533dd0 c0533dd0 c055df04 c7873600 c0557bc0 ff20: c0210b7c c0533dd0 c020fbd4 c0533dd0 c0533e04 ff40: c055df04 c7873600 c0557bc0 c020fce0 c020fc80 c055df04 c020f420 ff60: c7802d08 c787b240 c0026dd4 0080 c055df04 c020ed38 c03f14f4 c03f14f4 ff80: c782 c0026dd4 c055def0 c055df04 c020ffb0 ffa0: c0026dd4 c055def0 c001dca0 c0210f70 c0026dd4 ffc0: c001dca0 c002d2b4 0031 0192 c0026dd4 ffe0: c0008578 c002ee10 817fdf10 00bbff00 [c028a160] (musb_free+0x68/0xb8) from [c001e8f8] (musb_probe+0xab8/0xbb4) [c001e8f8] (musb_probe+0xab8/0xbb4) from [c0210b7c] (platform_drv_probe+0x1) [c0210b7c] (platform_drv_probe+0x18/0x1c) from [c020fbd4] (driver_probe_dev) [c020fbd4] (driver_probe_device+0xa0/0x14c) from [c020fce0] (__driver_attac) [c020fce0] (__driver_attach+0x60/0x84) from [c020f420] (bus_for_each_dev+0x) [c020f420] (bus_for_each_dev+0x44/0x74) from [c020ed38] (bus_add_driver+0xf) [c020ed38] (bus_add_driver+0xf4/0x278) from [c020ffb0] (driver_register+0xa) [c020ffb0] (driver_register+0xa8/0x130) from [c0210f70] (platform_driver_pr) [c0210f70] (platform_driver_probe+0x10/0x88) from [c002d2b4] (do_one_initca) [c002d2b4] (do_one_initcall+0x5c/0x1b4) from [c0008578] (kernel_init+0x90/0) [c0008578] (kernel_init+0x90/0x10c) from [c002ee10] (kernel_thread_exit+0x0) Code: e1a01005 ebf80722 e595309c e3a04000 (e593) 4---[ end trace 1b75b31a2719ed1c ]--- 0Kernel panic - not syncing: Attempted to kill init! After disabling musb, it boots further but can't mount root on the MMC: ... 4regulator_init_complete: incomplete constraints, leaving VUSB1V8 on regulator_init_complete: incomplete constraints, leaving VUSB1V8 on 4regulator_init_complete: incomplete constraints, leaving VUSB1V5 on regulator_init_complete: incomplete constraints, leaving VUSB1V5 on 4regulator_init_complete: incomplete constraints, leaving VMMC1 on regulator_init_complete: incomplete constraints, leaving VMMC1
Re: linux-omap git tree updated to v2.6.32-rc1, important changes, please read
2009/9/29 Aguirre Rodriguez, Sergio Alberto saagui...@ti.com: From: linux-omap-ow...@vger.kernel.org [linux-omap-ow...@vger.kernel.org] On Behalf Of Alexander Shishkin [virtu...@slind.org] Sent: Tuesday, September 29, 2009 2:20 PM 2009/9/29 Tony Lindgren t...@atomide.com: * Felipe Contreras felipe.contre...@gmail.com [090929 10:24]: On Mon, Sep 28, 2009 at 10:04 PM, Tony Lindgren t...@atomide.com wrote: Hi all, I've updated our linux-omap tree to v2.6.32-rc1. I've also added a branch omap-2.6.31 for the old code. This time I also nuked the remaining omap legacy code we still had lurking around :) The commits at the end of this mail describe what I did first as commits, then I merged everything to be the same as the mainline v2.6.32-rc1. So currently the linux-omap master branch is: v2.6.32-rc1 + omap-fixes + ehci + cbus The new model is that I'll be resetting the linux-omap master branch to mainline at each -rc, then merge in our various upstream queues back in again. Excellent! I was wondering why this wasn't being done. I certainly hope linus' 2.6.32 will work on omap right away. Yeah, let's hope Tomi gets in the DSS2 code too. Anyway, I haven't been able to make 2.6.31 boot on beagleboard, and other people report similar issues: http://www.spinics.net/lists/linux-omap/msg17968.html Have you got 2.6.32-rc1 (+fixes) to boot? Hmm, looks like it's musb again. This is what I get on my overo after applying the DEBUG_LL hack from omap-debug branch: 3musb_hdrc musb_hdrc: musb_init_controller failed with status -19 1Unable to handle kernel NULL pointer dereference at virtual address 1pgd = c0004000 1[] *pgd= Internal error: Oops: 5 [#1] dModules linked in: CPU: 0 Not tainted (2.6.32-rc2-05967-gd350540-dirty #892) PC is at musb_free+0x68/0xb8 LR is at musb_free+0x34/0xb8 snip After disabling musb, it boots further but can't mount root on the MMC: ... 4regulator_init_complete: incomplete constraints, leaving VUSB1V8 on regulator_init_complete: incomplete constraints, leaving VUSB1V8 on 4regulator_init_complete: incomplete constraints, leaving VUSB1V5 on regulator_init_complete: incomplete constraints, leaving VUSB1V5 on 4regulator_init_complete: incomplete constraints, leaving VMMC1 on regulator_init_complete: incomplete constraints, leaving VMMC1 on 6twl4030_rtc twl4030_rtc: setting system clock to 2000-01-01 00:00:00 UTC (94) twl4030_rtc twl4030_rtc: setting system clock to 2000-01-01 00:00:00 UTC (94668) 6Waiting for root device /dev/mmcblk0p2... Waiting for root device /dev/mmcblk0p2... What are you getting with DEBUG_LL enabled and the associated patch applied from omap-debug branch? MUSB enabled gives me the same backtrace. When I disable it, I get (this is beagle B6): 1Unable to handle kernel NULL pointer dereference at virtual address 1pgd = c0004000 1[] *pgd= snip Hi, Can you please try attached patch? Yep, thanks! (provided it's actually the same patch that Toni referred to). -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
