Hi
On Wed, 23 May 2012, Hiremath, Vaibhav wrote:
I believe register read/write to IP block is depends on only interface
Clocks? Atleast in case of OMAP3, it was like that, right??
No, on OMAP3, most modules need both the interface clock enabled, and at
least one of their functional clocks.
On Thu, May 24, 2012 at 13:01:11, Paul Walmsley wrote:
Hi
On Wed, 23 May 2012, Hiremath, Vaibhav wrote:
I believe register read/write to IP block is depends on only interface
Clocks? Atleast in case of OMAP3, it was like that, right??
No, on OMAP3, most modules need both the
On Thu, 24 May 2012, Hiremath, Vaibhav wrote:
On Thu, May 24, 2012 at 13:01:11, Paul Walmsley wrote:
On Wed, 23 May 2012, Hiremath, Vaibhav wrote:
I came across situation where, two modules fall into different clock
domains but their functional clock is happened to be coming from
On Wed, Apr 25, 2012 at 21:06:43, Paul Walmsley wrote:
On Wed, 25 Apr 2012, Cousson, Benoit wrote:
Please take care of changing the hwmod main_clk as well. But maybe
that's not part of that series.
It's not part of the series yet.
Vaibhav, could you take care of changing the main_clk
Hi Vaibhav
On Wed, 23 May 2012, Hiremath, Vaibhav wrote:
I used your cleaned version of clocktree data, where you have removed all
leaf-nodes and merged multiple clocks nodes into one; but it did not work. I
attempted to review the cleanup and tried to debug, but found it bit hard to
come
On Wed, May 23, 2012 at 20:38:27, Paul Walmsley wrote:
Hi Vaibhav
On Wed, 23 May 2012, Hiremath, Vaibhav wrote:
I used your cleaned version of clocktree data, where you have removed all
leaf-nodes and merged multiple clocks nodes into one; but it did not work.
I
attempted to
On Sat, Apr 28, 2012 at 05:34:53, Paul Walmsley wrote:
On Fri, 27 Apr 2012, Hiremath, Vaibhav wrote:
On Thu, Apr 26, 2012 at 14:19:28, Paul Walmsley wrote:
looking at Table 1-1 Device Features of SPRUH73D, it seems that some
AM33xx family chips come with some features disabled, such as
On Thu, Apr 26, 2012 at 14:19:28, Paul Walmsley wrote:
Hello Vaibhav,
looking at Table 1-1 Device Features of SPRUH73D, it seems that some
AM33xx family chips come with some features disabled, such as the
PRU-ICSS, the SGX, Ethernet, or USB. How will this affect the clock tree?
For
On Fri, 27 Apr 2012, Hiremath, Vaibhav wrote:
On Thu, Apr 26, 2012 at 14:19:28, Paul Walmsley wrote:
looking at Table 1-1 Device Features of SPRUH73D, it seems that some
AM33xx family chips come with some features disabled, such as the
PRU-ICSS, the SGX, Ethernet, or USB. How will this
On Thu, Apr 26, 2012 at 11:15:21, Paul Walmsley wrote:
Hi,
+/*
+ * clkdiv32 is generated from fixed division of 732.4219
+ */
+static struct clk clkdiv32k_ick = {
+ .name = clkdiv32k_ick,
+ .clkdm_name = clk_24mhz_clkdm,
+ .rate = 32768,
+ .parent
Hi Vaibhav, Afzal, Vaibhav,
while working on clock33xx_data.c, it became clear that we would not be
able to remove the MODULEMODE leaf clocks for several IP blocks that share
driver code with other DaVinci chips. This is because:
1. the drivers for these IP blocks only use the clock
On Thu, 26 Apr 2012, Hiremath, Vaibhav wrote:
Unfortunately, this is fractional divider, assuming input clock of 24MHz.
24MHz / 732.4219 = 32KHz (Normal OPP100)
24MHz / 366.2109 = 32KHz (OPP50)
Yes, I already saw that in the TRM. The question is, how is the
fractional divider implemented
On Thu, Apr 26, 2012 at 12:06:00, Paul Walmsley wrote:
On Thu, 26 Apr 2012, Hiremath, Vaibhav wrote:
Unfortunately, this is fractional divider, assuming input clock of 24MHz.
24MHz / 732.4219 = 32KHz (Normal OPP100)
24MHz / 366.2109 = 32KHz (OPP50)
Yes, I already saw that in the
On Thu, Apr 26, 2012 at 11:54:51, Paul Walmsley wrote:
Hi Vaibhav, Afzal, Vaibhav,
while working on clock33xx_data.c, it became clear that we would not be
able to remove the MODULEMODE leaf clocks for several IP blocks that share
driver code with other DaVinci chips. This is because:
On Thu, 26 Apr 2012, Hiremath, Vaibhav wrote:
On Thu, Apr 26, 2012 at 12:06:00, Paul Walmsley wrote:
On Thu, 26 Apr 2012, Hiremath, Vaibhav wrote:
Unfortunately, this is fractional divider, assuming input clock of 24MHz.
24MHz / 732.4219 = 32KHz (Normal OPP100)
24MHz / 366.2109
On Wed, 25 Apr 2012, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 19:25:29, Paul Walmsley wrote:
On Wed, 25 Apr 2012, Hiremath, Vaibhav wrote:
Thanks for describing it for me. I will change AM33XX clock tree for this
And submit the next version soon.
Well I can just remove
On Thu, 26 Apr 2012, Paul Walmsley wrote:
I have taken a first pass at this. The updated patch is below. It has
been compile-tested only. Could you please review this and try testing
it? It is also in the branch 'am33xx_support_3.5' of
git://git.pwsan.com/linux-2.6.
Here is the patch.
Hello Vaibhav,
looking at Table 1-1 Device Features of SPRUH73D, it seems that some
AM33xx family chips come with some features disabled, such as the
PRU-ICSS, the SGX, Ethernet, or USB. How will this affect the clock tree?
For example, is it correct for us to include the PRU-ICSS clock
Hi Vaibhav,
On 4/25/2012 7:48 AM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 06:33:26, Paul Walmsley wrote:
Hello Vaibhav, Afzal, Vaibhav,
On Tue, 3 Apr 2012, Vaibhav Hiremath wrote:
AM33XX clock implementation is different than any existing OMAP
family of devices. Although DPLL
On Wed, Apr 25, 2012 at 14:10:49, Cousson, Benoit wrote:
Hi Vaibhav,
On 4/25/2012 7:48 AM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 06:33:26, Paul Walmsley wrote:
Hello Vaibhav, Afzal, Vaibhav,
On Tue, 3 Apr 2012, Vaibhav Hiremath wrote:
AM33XX clock implementation is
On 4/25/2012 12:20 PM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 14:10:49, Cousson, Benoit wrote:
...
That will not change anything, the point is that MODULEMODE_SWCTRL is
uses for module control, not for clock directly, and that's why it is
handled by the hwmod.
That will just
On Wed, Apr 25, 2012 at 17:08:43, Cousson, Benoit wrote:
On 4/25/2012 12:20 PM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 14:10:49, Cousson, Benoit wrote:
...
snip
How would I know the rate of this clock in driver? Say for example, I want
to configure my internal divider based
On 4/25/2012 2:26 PM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 17:08:43, Cousson, Benoit wrote:
On 4/25/2012 12:20 PM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 14:10:49, Cousson, Benoit wrote:
...
snip
How would I know the rate of this clock in driver? Say for example, I
On Wed, Apr 25, 2012 at 18:03:21, Cousson, Benoit wrote:
On 4/25/2012 2:26 PM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 17:08:43, Cousson, Benoit wrote:
On 4/25/2012 12:20 PM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 14:10:49, Cousson, Benoit wrote:
...
snip
How
Hi Vaibhav,
On Wed, 25 Apr 2012, Hiremath, Vaibhav wrote:
Thanks for describing it for me. I will change AM33XX clock tree for this
And submit the next version soon.
Well I can just remove those leaf clock entries from my copy here, if
you're okay with that ?
- Paul
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On Wed, Apr 25, 2012 at 19:25:29, Paul Walmsley wrote:
Hi Vaibhav,
On Wed, 25 Apr 2012, Hiremath, Vaibhav wrote:
Thanks for describing it for me. I will change AM33XX clock tree for this
And submit the next version soon.
Well I can just remove those leaf clock entries from my copy
On 4/25/2012 3:55 PM, Paul Walmsley wrote:
Hi Vaibhav,
On Wed, 25 Apr 2012, Hiremath, Vaibhav wrote:
Thanks for describing it for me. I will change AM33XX clock tree for this
And submit the next version soon.
Well I can just remove those leaf clock entries from my copy here, if
you're okay
On Wed, 25 Apr 2012, Cousson, Benoit wrote:
Please take care of changing the hwmod main_clk as well. But maybe
that's not part of that series.
It's not part of the series yet.
Vaibhav, could you take care of changing the main_clk in your hwmod data
patches, and send those to the list?
-
On Wed, Apr 25, 2012 at 21:06:43, Paul Walmsley wrote:
On Wed, 25 Apr 2012, Cousson, Benoit wrote:
Please take care of changing the hwmod main_clk as well. But maybe
that's not part of that series.
It's not part of the series yet.
Vaibhav, could you take care of changing the main_clk
Hi,
+/*
+ * clkdiv32 is generated from fixed division of 732.4219
+ */
+static struct clk clkdiv32k_ick = {
+ .name = clkdiv32k_ick,
+ .clkdm_name = clk_24mhz_clkdm,
+ .rate = 32768,
+ .parent = clk_24mhz,
+ .enable_reg =
Hello Vaibhav, Afzal, Vaibhav,
On Tue, 3 Apr 2012, Vaibhav Hiremath wrote:
AM33XX clock implementation is different than any existing OMAP
family of devices. Although DPLL module is similar to OMAP4
device, but the usage is very much different than OMAP4.
AM33XX has different peripheral set
On Wed, Apr 25, 2012 at 06:33:26, Paul Walmsley wrote:
Hello Vaibhav, Afzal, Vaibhav,
On Tue, 3 Apr 2012, Vaibhav Hiremath wrote:
AM33XX clock implementation is different than any existing OMAP
family of devices. Although DPLL module is similar to OMAP4
device, but the usage is very
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