Re: [PATCH 0/3] ARM: dts: r8a779[014]: Use R-Car Gen 2 fallback binding for vin nodes

Hi Simon, Thanks for your work. On 2017-07-11 14:56:46 +0200, Simon Horman wrote: > Use R-Car Gen 2 fallback binding for vind nodes in DT for r8a779[014] SoCs. > > This has no run-time effect for the current driver as the initialisation > sequence is the same for the SoC-specific binding for

Re: [PATCH 3/3] ARM: dts: iwg20m: Add MMCIF0 support

Hi Chris, [auto build test ERROR on renesas/next] [also build test ERROR on next-20170712] [cannot apply to v4.12] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Chris-Paterson/Add-MMCIF0

Re: [PATCH V3 8/8] clk: vc5: Add support for IDT VersaClock 5P49V6901

On 07/09, Marek Vasut wrote: > Update IDT VersaClock 5 driver to support IDT VersaClock 6 5P49V6901. > This chip has two clock inputs (external XTAL or external CLKIN), four > fractional dividers (FODs) and five clock outputs (four universal clock > outputs and one reference clock output at

Re: [PATCH V3 3/8] clk: vc5: Do not warn about disabled output buffer input muxes

On 07/09, Marek Vasut wrote: > The output buffer input mux can be configured in either of three > states -- disabled, input from FOD, input from previous output. > If the output buffer input mux is set to disabled, the code in > vc5_clk_out_get_parent() would consider this an invalid setting > and

Re: [PATCH V3 1/8] clk: vc5: Prevent division by zero on unconfigured outputs

On 07/09, Marek Vasut wrote: > In case the initial values of the FOD registers are not configured in > the OTP or by the bootloader, it is possible that the FOD registers > will contain zeroes. The code in vc5_fod_recalc_rate() immediately > feeds the FOD divider value obtained from the FOD

Re: [PATCH V3 2/8] clk: vc5: Fix trivial typo

On 07/09, Marek Vasut wrote: > Fix trivial typo in vc5_clk_out_unprepare() , s/Enable/Disable/ . > > Signed-off-by: Marek Vasut > Cc: Stephen Boyd > Cc: Alexey Firago > Cc: Michael Turquette

[PATCH] drm: rcar-du: Fix comments to comply with the kernel coding style

To avoid mixing comment styles when new comments complying with the kernel coding style are introduced, fix all multiline comments in one go. Signed-off-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c| 24 --

[PATCH 12/14] pinctrl: sh-pfc: r8a7796: Fix to delete MOD_SEL0 bit2 register definitions

From: Takeshi Kihara This patch fixes the macro definitions of MOD_SEL0 bit2 register deleted. This is a correction because MOD_SEL register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: f9aece7344bd ("pinctrl:

[PATCH 13/14] pinctrl: sh-pfc: r8a7796: Fix IPSR and MOD_SEL register pin assignment for FSO pins group

From: Takeshi Kihara This patch fixes IPSR{12,17,18} and MOD_SEL0 pin assignment for FSO pins group. This is a correction because GPSR and IPSR register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E. Signed-off-by:

[PATCH 10/14] pinctrl: sh-pfc: r8a7796: Fix to delete FSCLKST pin and IPSR7 bit[15:12] register definitions

From: Takeshi Kihara This patch fixes the macro definitions of FSCLKST pins function and IPSR7 bit[15:12] register deleted. This is a correction because IPSR register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E or

[PATCH 01/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D

From: Takeshi Kihara This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24] value when STP_ISEN_1_D pin function is selected for IPSR17 bit[27:24]. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7796

[PATCH 08/14] pinctrl: sh-pfc: r8a7796: Fix MSIOF3_{SS1,SS2}_E pins function definitions

From: Takeshi Kihara This patch fixes the implementation incorrect of IPSR register value definitions for MSIOF3_{SS1,SS2}_E pins function. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car

[PATCH 07/14] pinctrl: sh-pfc: r8a7796: Fix NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pin function definitions

From: Takeshi Kihara This patch fixes the implementation incorrect of IPSR register value definitions for NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pins function. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC

[PATCH 06/14] pinctrl: sh-pfc: r8a7796: Fix FMCLK{_C,_D} and FMIN{_C,_D} pin function definitions

From: Takeshi Kihara This patch fixes the implementation incorrect of IPSR register value definitions for FMCLK{_C,_D} and FMIN{_C,_D} pins function. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification

[PATCH 09/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for TCLK{1,2}_{A,B} pins group

From: Takeshi Kihara This patch fixes to set MOD_SEL2 bit19 when using TCLK2_A pin function is selected for IPSR16 bit[23:20] or using TCLK2_B pin function is selected for IPSR17 bit[27:24]. This is a correction to the incorrect implementation of MOD_SEL register

[PATCH 11/14] pinctrl: sh-pfc: r8a7796: Fix to delete SATA_DEVSLP_B pins function definitions

From: Takeshi Kihara This patch fixes the macro definitions of SATA_DEVSLP_B pins function deleted. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or

[PATCH 02/14] pinctrl: sh-pfc: r8a7796: Fix IPSR register setting when MSIOF3_SS1_E pin was selected

From: Takeshi Kihara This patch fixes to set IPSR register when using MSIOF3_SS1_E pin function is selected. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual

[PATCH 04/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for SSI pins group

From: Takeshi Kihara This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment for SSI pins group. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's

[PATCH 05/14] pinctrl: sh-pfc: r8a7796: Fix SCIF_CLK_{A,B} pin's MOD_SEL assignment to MOD_SEL1 bit10

From: Takeshi Kihara This patch fixes SCIF_CLK_{A,B} pin's MOD_SEL assignment from MOD_SEL1 bit11 to MOD_SEL1 bit10. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's

[PATCH 03/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL2 bit26 to 0x0 when using SCK5_A

From: Takeshi Kihara This patch fixes the implementation incorrect of MOD_SEL2 bit26 value when SCK5_A pin function is selected for IPSR16 bit[31:28]. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7796 SoC

[PATCH 00/14] pinctrl: sh-pfc: r8a7796: Fix pin assignment definitions

This series fixes pin assignment definitions for R8A7796 SoC. This series is based on the for-next branch of linux-pinctrl tree. Takeshi Kihara (14): pinctrl: sh-pfc: r8a7796: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D pinctrl: sh-pfc: r8a7796: Fix IPSR register setting when

Re: [PATCH] drm: rcar-du: Setup planes before enabling CRTC to avoid flicker

Hi Laurent, On 28/06/17 19:50, Laurent Pinchart wrote: > Commit 52055bafa1ff ("drm: rcar-du: Move plane commit code from CRTC > start to CRTC resume") changed the order of the plane commit and CRTC > enable operations to accommodate the runtime PM requirements. However, > this introduced

Re: [PATCH v3] mmc: tmio-mmc: fix bad pointer math

On Wed, Jul 12, 2017 at 08:40:01AM -0700, Chris Brandt wrote: > The existing code gives an incorrect pointer value. > The buffer pointer 'buf' was of type unsigned short *, and 'count' was a > number in bytes. A cast of buf should have been used. > > However, instead of casting, just change the

[PATCH v3] mmc: tmio-mmc: fix bad pointer math

The existing code gives an incorrect pointer value. The buffer pointer 'buf' was of type unsigned short *, and 'count' was a number in bytes. A cast of buf should have been used. However, instead of casting, just change the code to use u32 pointers. Reported-by: Dan Carpenter

RE: [PATCH v2] mmc: tmio-mmc: fix bad pointer math

Hi Geert, On Wednesday, July 12, 2017 1, Geert Uytterhoeven wrote: > > Reported-by: Dan Carpenter > > Fixes: 8185e51f358a: ("mmc: tmio-mmc: add support for 32bit data port") > > Signed-off-by: Chris Brandt > > Reviewed-by: Geert Uytterhoeven

Re: Rebasing mmc/next

On 20 June 2017 at 11:06, Geert Uytterhoeven wrote: > Hi Ulf, > > On Tue, Jun 20, 2017 at 10:07 AM, Ulf Hansson wrote: >> On 20 June 2017 at 09:17, Geert Uytterhoeven wrote: >>> It looks like you rebase mmc/next almost daily.

Re: [PATCH v2] mmc: tmio-mmc: fix bad pointer math

On Wed, Jul 12, 2017 at 3:27 PM, Chris Brandt wrote: > The existing code gives an incorrect pointer value. > The buffer pointer 'buf' was of type unsigned short *, and 'count' was a > number in bytes. A cast of buf should have been used. > > However,instead of casting,

[PATCH] ARM: shmobile: rcar-gen2: Fix deadlock in regulator quirk

Simon Horman reported that Koelsch and Lager hang during boot, and bisected this to commit 1c3c5eab171590f8 ("sched/core: Enable might_sleep() and smp_processor_id() checks early"). The da9063/da9210 regulator quirk for R-Car Gen2 boards uses a bus notifier, and unregisters the notifier when it

Re: [PATCH 2/2] drm: rcar-du: Add HDMI outputs to R8A7796 device description

Hi Geert, > Indeed. > > BTW, the M3-W version also has unconnected USB3 and SATA connectors. Thanks for the heads up :) - I've just put a post it note over those, +HDMI1-OUT (or rather the text on the top lid) to prevent any confusion for me down the line. -- Kieran

Re: [PATCH 2/2] drm: rcar-du: Add HDMI outputs to R8A7796 device description

Hi Kieran, On Wed, Jul 12, 2017 at 3:51 PM, Kieran Bingham wrote: > Table 35.1 (in the DU datasheet) certainly shows that there is only an > HDMI-IF0 > on the M3, but it's amusing that (and I was confused by the fact that) my > r8a7796 board (Salvator-X)

Re: [PATCH 2/2] drm: rcar-du: Add HDMI outputs to R8A7796 device description

Hi Laurent, This looks good to me. Table 35.1 (in the DU datasheet) certainly shows that there is only an HDMI-IF0 on the M3, but it's amusing that (and I was confused by the fact that) my r8a7796 board (Salvator-X) still has the HDMI1 populated. Of course I presume this is populated to keep the

[PATCH v2] mmc: tmio-mmc: fix bad pointer math

The existing code gives an incorrect pointer value. The buffer pointer 'buf' was of type unsigned short *, and 'count' was a number in bytes. A cast of buf should have been used. However,instead of casting, just change the code to use u32 pointers. Reported-by: Dan Carpenter

Re: [PATCH v2 2/3] drm: rcar-du: Fix planes to CRTC assignment when using the VSP

Hi Kieran, On Wednesday 12 Jul 2017 11:30:19 Kieran Bingham wrote: > On 11/07/17 23:29, Laurent Pinchart wrote: > > The DU can compose the output of a VSP with other planes on Gen2 > > hardware, and of two VSPs on Gen3 hardware. Neither of these features > > are supported by the driver, and the

[PATCH] pinctrl: sh-pfc: r8a7791: Add missing mmc_data8_b pin group

Pins D6 and D7 of the MMC interface can be muxed to two different sets of pins, but currently only one set is supported. Add a pin group for the alternative set to fix this. Signed-off-by: Geert Uytterhoeven --- To be queued in sh-pfc-for-v4.14.

Re: [PATCH 3/3] ARM: dts: iwg20m: Add MMCIF0 support

Hi Chris, On Wed, Jul 12, 2017 at 12:03 PM, Chris Paterson wrote: > Define the iwg20m board dependent part of the MMCIF0 device node. > > Signed-off-by: Chris Paterson > > diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi >

Re: [PATCH 2/3] ARM: dts: r8a7743: Add MMCIF0 support

On Wed, Jul 12, 2017 at 12:03 PM, Chris Paterson wrote: > Add the MMCIF0 device to the r8a7743 device tree. > > Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s,

Re: [PATCH 1/3] dt-bindings: mmc: sh_mmcif: Document r8a7743 DT bindings

On Wed, Jul 12, 2017 at 12:03 PM, Chris Paterson wrote: > Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots

[PATCH v2 07/16] drm/rcar-du: Use new iterator macros, v2.

Op 12-07-17 om 11:15 schreef Daniel Vetter: > On Wed, Jul 12, 2017 at 10:13:35AM +0200, Maarten Lankhorst wrote: >> for_each_obj_in_state is about to be removed, so use the correct new >> iterator macros. >> >> Signed-off-by: Maarten Lankhorst >> Cc: Laurent

[PATCH v2] ARM: shmobile: rcar-gen2: Add support for CPG/MSSR bindings

When using the new CPG/MSSR bindings, there is no longer a "renesas,rcar-gen2-cpg-clocks" node, and the code to obtain the external clock crystal frequency falls back to a default of 20 MHz. While this is correct for all upstream R-Car Gen2 and RZ/G1 boards, this is not necessarily the case for

[PATCH] arm64: dts: r8a7796: Add missing second pair of DMA names to MSIOF nodes

MSIOF0 and MSIOF1 are tied to two DMA controllers through two pairs of DMA specifiers. However, the second pair of corresponding DMA names was missing. Fixes: 80fab06e258da762 ("arm64: dts: r8a7796: Add all MSIOF nodes") Signed-off-by: Geert Uytterhoeven ---

Re: [PATCH v2 1/3] drm: rcar-du: Use the VBK interrupt for vblank events

Hi Laurent, On 11/07/17 23:29, Laurent Pinchart wrote: > When implementing support for interlaced modes, the driver switched from > reporting vblank events on the vertical blanking (VBK) interrupt to the > frame end interrupt (FRM). This incorrectly divided the reported refresh > rate by two. Fix

[PATCH v3] arm64: dts: r8a7795: Add all MSIOF nodes

Add the device nodes for all MSIOF SPI controllers, incl. clocks, power domain, dma, and reset properties. Due to a hardware erratum on R-Car H3 ES1.x, using MSIOF for SPI is only supported on ES2.0 and later. Signed-off-by: Geert Uytterhoeven --- Tested on

[PATCH 1/5] pinctrl: sh-pfc: r8a7795: Fix MSIOF3_{SS1,SS2}_E pin function definitions

From: Takeshi Kihara This patch fixes the incorrect IPSR register value definitions for MSIOF3_{SS1,SS2}_E pin functions. This is a correction to the incorrect implementation of IPSR register pin assignment of the specifications updated for R8A7795 ES2.0 SoC in

[PATCH 2/5] pinctrl: sh-pfc: r8a7795: Add MSIOF pins, groups and functions

Add pins, groups, and functions for MSIOF on R-Car H3 ES2.0. Extracted from a big patch in the BSP by Takeshi Kihara, with corrections for MSIOF3 SS1_E/SS2_E pins and SS2_E mux. Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 912

[PATCH 3/5] pinctrl: sh-pfc: r8a7796: Fix MSIOF3_{SS1,SS2}_E pin function definitions

From: Takeshi Kihara This patch fixes the incorrect IPSR register value definitions for MSIOF3_{SS1,SS2}_E pin functions. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware

[PATCH 0/5] pinctrl: sh-pfc: r8a7795/r8a7796: MSIOF updates

Hi Linus, Laurent, This patch series fixes MSIOF-related bugs in the R-Car H3 ES2.0 and M3-W pin control drivers, and enables support for MSIOF on R-Car H3 ES2.0. I plan to queue these up in sh-pfc-for-v4.14. Thanks! Geert Uytterhoeven (2): pinctrl: sh-pfc: r8a7795: Add MSIOF pins,

[PATCH 5/5] pinctrl: sh-pfc: r8a7796: Fix MSIOF3 SS2_E mux

Fix a copy-and-paste bug in the MSIOF3 SS2_E mux array. Fixes: 4753231cc9468390 ("pinctrl: sh-pfc: r8a7796: Add MSIOF pins, groups and functions") Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH 4/5] pinctrl: sh-pfc: r8a7796: Fix IPSR setting for MSIOF3_SS1_E pin

From: Takeshi Kihara This patch fixes the IPSR register setting when the MSIOF3_SS1_E pin function is selected. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual

Re: [PATCH v2 2/3] drm: rcar-du: Fix planes to CRTC assignment when using the VSP

Hi Laurent, Thanks for the patch Only a minor nit on one comment, but aside from that, On 11/07/17 23:29, Laurent Pinchart wrote: > The DU can compose the output of a VSP with other planes on Gen2 > hardware, and of two VSPs on Gen3 hardware. Neither of these features > are supported by the

[PATCH] spi: sh-msiof: Limit minimum divider on R-Car Gen3

On R-Car Gen3 SoCs (excluding R-Car H3 ES1.x, which cannot be used for SPI due to a hardware erratum), BRPS x BRDV = 1/1 is an invalid divider setting. Implement this limitation using an SoC/family-specific minimum divider. Signed-off-by: Geert Uytterhoeven ---

[PATCH v2] spi: sh-msiof: Add support for R-Car H3

Add support for MSIOF in r8a7795 (R-Car H3). Due to a hardware erratum on R-Car H3 ES1.x, this is only supported on ES2.0 and later. No driver update is needed. Signed-off-by: Geert Uytterhoeven --- v2: - Drop RFC status, - Rebased, - Drop matching on

Re: [PATCH mmc/next v3 0/4] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

On Tue, Jul 11, 2017 at 04:43:00PM +0200, Ulf Hansson wrote: > On 21 June 2017 at 16:00, Simon Horman wrote: > > Hi, > > > > this series adds support for the internal DMAC used by r8a779[56] SoCs. > > This is achieved by adding a new variant of the SDHI driver for this

[PATCH 3/3] ARM: dts: iwg20m: Add MMCIF0 support

Define the iwg20m board dependent part of the MMCIF0 device node. Signed-off-by: Chris Paterson diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi index 001ca91..ffce1b6 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi +++

[PATCH 2/3] ARM: dts: r8a7743: Add MMCIF0 support

Add the MMCIF0 device to the r8a7743 device tree. Signed-off-by: Chris Paterson diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 0d02191..f62e858 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@

[PATCH 1/3] dt-bindings: mmc: sh_mmcif: Document r8a7743 DT bindings

Signed-off-by: Chris Paterson diff --git a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt index c32dc5a..703e18c 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt +++

[PATCH 0/3] Add MMCIF0 support for r8a7743/iwg20m

This series adds MMCIF0 support for the r8a7743 SoC and the iWave-RZG1M-20M Qseven SOM. This series is based on renesas-devel-20170711-v4.12. Chris Paterson (3): dt-bindings: mmc: sh_mmcif: Document r8a7743 DT bindings ARM: dts: r8a7743: Add MMCIF0 support ARM: dts: iwg20m: Add MMCIF0

Re: [PATCH 07/16] drm/rcar-du: Use new iterator macros

On Wed, Jul 12, 2017 at 10:13:35AM +0200, Maarten Lankhorst wrote: > for_each_obj_in_state is about to be removed, so use the correct new > iterator macros. > > Signed-off-by: Maarten Lankhorst > Cc: Laurent Pinchart > Cc:

Re: [PATCH v2 2/7] arm64: dts: renesas: r8a7796: Add FCPF and FCPV instances

Hi Geert, On Wednesday 12 Jul 2017 09:22:50 Geert Uytterhoeven wrote: > On Wed, Jun 21, 2017 at 11:31 AM, Laurent Pinchart wrote: > > The FCPs handle the interface between various IP cores and memory. Add > > the instances related to the FDPs and VSP2s. > > > > Signed-off-by: Laurent Pinchart >

Re: [PATCH v2 0/2] R-Car H3 ES2.0 Salvator-X: Enable DU support in DT

Hi Simon, On Wednesday 12 Jul 2017 07:56:15 Simon Horman wrote: > On Wed, Jul 12, 2017 at 02:20:43AM +0300, Laurent Pinchart wrote: > > On Tuesday 11 Jul 2017 11:16:17 Simon Horman wrote: > >> On Mon, Jul 10, 2017 at 04:31:38PM +0300, Laurent Pinchart wrote: > >>> On Monday 26 Jun 2017 19:29:28

[RESEND] [PATCH v2.1 1/2] dt-bindings: display: rcar-du: Add a VSP channel index to the vsps DT property

On some R-Car SoCs a single VSP can serve multiple DU channels through multiple LIF instances in the VSP. The current DT bindings don't support specifying that kind of SoC integration scheme. Extend them with a VSP channel index. Backward compatibility can be ensured in drivers by checking the

[PATCH 07/16] drm/rcar-du: Use new iterator macros

for_each_obj_in_state is about to be removed, so use the correct new iterator macros. Signed-off-by: Maarten Lankhorst Cc: Laurent Pinchart Cc: linux-renesas-soc@vger.kernel.org --- drivers/gpu/drm/rcar-du/rcar_du_plane.c |

[PATCH] drm: shmobile: checking for NULL instead if IS_ERR()

We changed from ioremap_nocache() to devm_ioremap_resource() so the check needs to be changed from checking for NULL to checking for error pointers. Fixes: 16ad3b2ce8dd ("drm/shmobile: Use devm_* managed functions") Signed-off-by: Dan Carpenter diff --git

Re: [PATCH v2 3/7] arm64: dts: renesas: r8a7796: Add VSP instances

Hi Laurent, Simon, On Wed, Jun 21, 2017 at 11:31 AM, Laurent Pinchart wrote: > The r8a7796 has 5 VSP instances. > > Signed-off-by: Laurent Pinchart > Reviewed-by: Geert Uytterhoeven

Re: [PATCH v2 2/7] arm64: dts: renesas: r8a7796: Add FCPF and FCPV instances

Hi Laurent, Simon, On Wed, Jun 21, 2017 at 11:31 AM, Laurent Pinchart wrote: > The FCPs handle the interface between various IP cores and memory. Add > the instances related to the FDPs and VSP2s. > > Signed-off-by: Laurent Pinchart

Re: [PATCH] mmc: tmio-mmc: fix bad pointer math

Hi Chris, On Tue, Jul 11, 2017 at 9:37 PM, Chris Brandt wrote: > On Tuesday, July 11, 2017, Geert Uytterhoeven wrote: >> > zeroing out the bottom 2 bits of count for out math. >> >> s/out/our/ > > Thank you! > >> > - buf8 = (u8 *)(buf + (count >> 2)); >> >

Re: [PATCH/RFC] gpio: rcar: add gen[123] fallback compatibility strings

Hi Simon, CC DT On Wed, Jul 12, 2017 at 7:49 AM, Simon Horman wrote: > On Tue, Jul 11, 2017 at 07:59:31PM +0200, Geert Uytterhoeven wrote: >> On Tue, Jul 11, 2017 at 2:38 PM, Simon Horman >> wrote: >> > Add fallback compatibility string for R-Car