Hi
> From: Hiroyuki Yokoyama
>
> Document support for the sound modules in the Renesas M3-N (r8a77965)
> SoC.
>
> No driver update is needed.
>
> Signed-off-by: Hiroyuki Yokoyama
> Signed-off-by: Yoshihiro Kaneko
> ---
Acked-by: Kuninori Morimoto
On 07/23/2018 11:03 AM, Geert Uytterhoeven wrote:
> Hi Marek,
Hi,
> On Sun, Jul 22, 2018 at 2:07 PM Marek Vasut wrote:
>> On 07/20/2018 06:38 PM, Sergei Shtylyov wrote:
>>> On 07/20/2018 03:05 PM, Simon Horman wrote:
From: Marek Vasut
Add PMIC nodes to Porter and connect CPU
On 06/13/2018 07:25 PM, Bjorn Helgaas wrote:
> On Wed, Jun 13, 2018 at 04:52:52PM +0100, Lorenzo Pieralisi wrote:
>> On Wed, Jun 13, 2018 at 08:53:08AM -0500, Bjorn Helgaas wrote:
>>> On Wed, Jun 13, 2018 at 01:54:51AM +0200, Marek Vasut wrote:
On 06/11/2018 03:59 PM, Bjorn Helgaas wrote:
Introduce RZ/A2 (R7S9210) as an SoC that can be selected.
There is no DT mainlined yet, so this is what the entry would look
like for the BSID register:
bsid: chipid@fcfe8004 {
compatible = "renesas,bsid";
reg = <0xfcfe8004 4>;
};
Chris Brandt
Add device tree bindings documentation for Renesas RZ/A2 (r7s9210) SoC.
Also document new option for "renesas,bsid"
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
v2:
* added Reviewed-by
* added renesas,bsid comment
---
Documentation/devicetree/bindings/arm/shmobile.txt | 4
Add support for identifying the RZ/A2M (R7S9210) SoC.
Also add support for reading the BSID register which is a different format
than the PRR.
Signed-off-by: Chris Brandt
---
drivers/soc/renesas/renesas-soc.c | 60 +++
1 file changed, 48 insertions(+), 12
Add the RZ/A2 SoC to the Renesas SoC collection.
Signed-off-by: Chris Brandt
---
arch/arm/mach-shmobile/Kconfig | 6 ++
arch/arm/mach-shmobile/Makefile| 1 +
arch/arm/mach-shmobile/setup-r7s9210.c | 27 +++
3 files changed, 34 insertions(+)
create
Hi Geert,
Thank you for the patch.
On Wednesday, 25 July 2018 16:10:29 EEST Geert Uytterhoeven wrote:
> The Renesas IPMMU-VMSA driver supports not just R-Car H2 and M2 SoCs,
> but also other R-Car Gen2 and R-Car Gen3 SoCs.
>
> Drop a superfluous "Renesas" while at it.
>
> Signed-off-by: Geert
On Mon, Jul 23, 2018 at 10:26 PM Wolfram Sang
wrote:
> And don't reimplement in the driver.
>
> Signed-off-by: Wolfram Sang
Reviewed-by: Linus Walleij
Yours,
Linus Walleij
From: Dien Pham
This patch adds OPPs table for CA57{0,1} cpu devices
Signed-off-by: Dien Pham
Signed-off-by: Takeshi Kihara
Signed-off-by: Yoshihiro Kaneko
---
This patch is based on the devel branch of Simon Horman's renesas tree.
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 44
From: Hiroyuki Yokoyama
Document support for the sound modules in the Renesas M3-N (r8a77965)
SoC.
No driver update is needed.
Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Yoshihiro Kaneko
---
This patch is based on the devel branch of Simon Horman's renesas tree.
From: Takeshi Kihara
Based on a similar patch of the R8A7796 device tree
by Kuninori Morimoto .
Signed-off-by: Takeshi Kihara
Signed-off-by: Yoshihiro Kaneko
---
The following patches were squashed into this patch:
arm64: dts: r8a77965: Add Audio-DMAC device nodes
arm64: dts: r8a77965:
> That all being said, I think this patch is still useful as is.
Linus, do you have time to comment on this?
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On Fri, Jul 20, 2018 at 02:19:40PM +0200, Geert Uytterhoeven wrote:
> Serial aliases are optional since commit 7678f4c20fa7670f ("serial:
> sh-sci: Add support for dynamic instances").
> Update the DT bindings to reflect this.
>
> Signed-off-by: Geert Uytterhoeven
> ---
>
Since Geert also argumented that it is reasonable to have this in the board DTS
files [1], I converted the RFC into proper patches. So, SATA will be available
out of the box for H3 and M3-N if MD12 is switched off properly.
Patches are bases on current renesas-drivers/master. M3-N has been tested
Add the nodes to enable SATA. Note that MD12 (SW12-7) must be switched
off for that to work.
Signed-off-by: Wolfram Sang
---
arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git
Add the nodes to enable SATA. Note that MD12 (SW12-7) must be switched
off for that to work.
Signed-off-by: Wolfram Sang
Tested-by: Geert Uytterhoeven
---
arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git
From: Takeshi Kihara
This patch adds SATA controller node for the R8A77965 SoC.
Signed-off-by: Takeshi Kihara
[wsa: rebased to upstream base]
Signed-off-by: Wolfram Sang
---
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git
Update the binding docs for Renesas R-Car M3-N. No driver changes are
needed.
Signed-off-by: Wolfram Sang
---
Documentation/devicetree/bindings/ata/sata_rcar.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/ata/sata_rcar.txt
From: Takeshi Kihara
This patch adds SATA0 pin, group and function to the R8A77965 SoC.
Signed-off-by: Takeshi Kihara
[wsa: rebased to upstream base]
Signed-off-by: Wolfram Sang
---
drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 27 +++
1 file changed, 27 insertions(+)
diff
From: Takeshi Kihara
This patch adds SATA clock to the R8A77965 SoC.
Signed-off-by: Takeshi Kihara
[wsa: rebased to upstream base]
Signed-off-by: Wolfram Sang
---
drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git
On Fri, Jul 20, 2018 at 02:27:39PM +0200, Geert Uytterhoeven wrote:
> Replace the explicit clock handling to enable/disable the SATA module by
> calls to Runtime PM.
>
> This makes the driver independent of actual SoC clock/power hierarchies,
> and is needed to support virtualization, where the
On Fri, Jul 20, 2018 at 02:27:38PM +0200, Geert Uytterhoeven wrote:
> No functional changes.
>
> Signed-off-by: Geert Uytterhoeven
For the record, works fine with the newly added SATA support for M3-N:
Reviewed-by: Wolfram Sang
Tested-by: Wolfram Sang
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On Tue, Jul 17, 2018 at 10:23:17PM +0300, Sergei Shtylyov wrote:
> Document R-Car V3H (AKA R8A77980) SoC bindings.
>
> Signed-off-by: Sergei Shtylyov
>
> ---
> Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt |
> 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob
On Wed, Jul 25, 2018 at 6:44 PM Sergei Shtylyov
wrote:
> Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
> the R8A77970 SoC's device tree.
8?
Can you hack up a check in checkpatch.pl to catch such mistakes? ;-)
Gr{oetje,eeting}s,
Geert
--
Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
the R8A77970 SoC's device tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov
Signed-off-by: Sergei Shtylyov
---
The patch is against the 'renesas-devel-20180724-v4.18-rc6'
On Wed, Jul 25, 2018 at 06:08:21PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 07/24/2018 02:45 PM, Simon Horman wrote:
>
> [...]
> > On Tue, Jul 24, 2018 at 09:01:59AM +0200, Geert Uytterhoeven wrote:
> >> On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov
> >> wrote:
> >>> Describe RWDT in the
Hello!
On 07/24/2018 02:45 PM, Simon Horman wrote:
[...]
> On Tue, Jul 24, 2018 at 09:01:59AM +0200, Geert Uytterhoeven wrote:
>> On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov
>> wrote:
>>> Describe RWDT in the R8A77980 SoC device tree.
>>>
>>> Enable RWDT on the Condor and V3H Starter Kit
The RZ/A2 uses a modified SCIF that until recently was only used in
Renesas MCU devices (not MPU devices).
So, while it functions mostly the same as a normal SCIF, some things
needed to be shifted around.
In the end, a standard compatible = "renesas,scif" is all that is really
needed (not a SoC
Add R7S9210 (RZ/A2) support.
Also describe interrupts property in more detail.
Signed-off-by: Chris Brandt
---
v2:
* Add more details to interrupts property
* Geert gave a Reviewed-by for V1, but then later said that was a
mistake because it was missing the interrupts description, so
I
Some SCIF versions mux error and break interrupts together and then provide
a separate interrupt ID for just TEI/DRI.
Allow all 6 types of interrupts to be specified via platform data (or DT)
and for any signals that are muxed together (have the same interrupt
number) simply register one handler.
Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers.
Use the register area size to determine the spacing between register.
Signed-off-by: Chris Brandt
---
drivers/tty/serial/sh-sci.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git
From: Auger Eric
Up to now we have relied on the device type to identify a device tree
node creation function. Since we would like the vfio-platform device to
be instantiatable with different compatible strings we introduce the
capability to specialize the node creation depending on actual
Hi all,
This patch series allows to export generic devices in DT using
vfio-platform, providing direct access from a QEMU+KVM guest to the
exported devices.
- Patches 1-2 (submitted before by Eric Auger) make the vfio-platform
device non-abstract, incl. matching using a compatible
From: Auger Eric
Up to now the vfio-platform device has been abstract and could not be
instantiated. The integration of a new vfio platform device required
creating a dummy derived device which only set the compatible string.
Following the few vfio-platform device integrations we have seen the
Allow the instantation of generic dynamic sysbus devices again, without
the need to create a new device-specific vfio type.
This is more or less a partial revert of commit 6f2062b9758ebc64
("hw/arm/virt: Allow only supported dynamic sysbus devices").
Signed-off-by: Geert Uytterhoeven
---
v3:
Add a fallback for instantiating generic devices without a type-specific
or compatible-specific instantation method. This will be used when no
other match is found.
The generic instantation method creates a device node with "reg" and
(optional) "interrupts" properties, and copies the
SATA on R-Car H3 ES2.0 works fine with the IOMMU.
This is also needed for virtualization.
Signed-off-by: Geert Uytterhoeven
---
For testing virtualization, this patch and all prerequisites are
available in the topic/rcar3-virt-gpio-passthrough-v3 branch of my git
repository at
Hi Geert,
On 25/07/18 14:34, Geert Uytterhoeven wrote:
The Renesas IPMMU-VMSA driver is compatible with the notion of a type-1
IOMMU in VFIO.
This patch allows guests to use the VFIO_IOMMU_TYPE1 API on hosts
equipped with a Renesas VMSA-compatible IPMMU.
Signed-off-by: Geert Uytterhoeven
---
From: Jacopo Mondi
Add V4L2 sensor driver for Aptina MT9V111 CMOS image sensor.
The MT9V111 is a 1/4-Inch CMOS image sensor based on MT9V011 with an
integrated Image Flow Processor.
Reviewed-by: Kieran Bingham
Signed-off-by: Jacopo Mondi
---
drivers/media/i2c/Kconfig | 11 +
From: Jacopo Mondi
Add documentation for Aptina MT9V111 image sensor.
Reviewed-by: Rob Herring
Signed-off-by: Jacopo Mondi
---
.../bindings/media/i2c/aptina,mt9v111.txt | 46 ++
MAINTAINERS| 8
2 files changed, 54
Hello,
this is a sensor level driver for Aptina MT9V111.
Compared to v1 the biggest difference is that now auto-exposure and
auto-white-balancing are exposed through the v4l2-ctrl framework, and can be
activated/deactivated by the user.
For this reason, while auto-exposure algorithm still
Hi Wolfram,
On 2018-07-25 14:21:07 +0200, Wolfram Sang wrote:
> Hi Niklas,
>
> > * Changes since v3
> > - Add check for 4TAP for HS400.
>
> Is it the same in the BSP or where does this info come from?
It comes from the BSP but I had to modify it to fit with the upstream
implementation of 4 vs
The Renesas IPMMU-VMSA driver is compatible with the notion of a type-1
IOMMU in VFIO.
This patch allows guests to use the VFIO_IOMMU_TYPE1 API on hosts
equipped with a Renesas VMSA-compatible IPMMU.
Signed-off-by: Geert Uytterhoeven
---
Lightly tested with sata_rcar on Renesas R-Car H3 ES2.0.
When attaching a device to an IOMMU group with
CONFIG_DEBUG_ATOMIC_SLEEP=y:
BUG: sleeping function called from invalid context at mm/slab.h:421
in_atomic(): 1, irqs_disabled(): 128, pid: 61, name: kworker/1:1
...
Call trace:
...
arm_lpae_alloc_pgtable+0x114/0x184
The Renesas IPMMU-VMSA driver supports not just R-Car H2 and M2 SoCs,
but also other R-Car Gen2 and R-Car Gen3 SoCs.
Drop a superfluous "Renesas" while at it.
Signed-off-by: Geert Uytterhoeven
---
drivers/iommu/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Hi Chris,
On Wed, Jul 25, 2018 at 2:05 PM Chris Brandt wrote:
> On Wednesday, July 25, 2018, Geert Uytterhoeven wrote:
> > > However, if "interrupt-names" is specified in DT, then the driver
> > > determines what the interrupt are based on their names, not the order in
> > which
> > > they are
Hi Niklas,
> * Changes since v3
> - Add check for 4TAP for HS400.
Is it the same in the BSP or where does this info come from?
> + if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
> + !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
> + !(host->mmc->ios.timing ==
From: Masaharu Hayakawa
SDR104 and HS200 need to check for SCC error. If SCC error is detected,
retuning is necessary.
Signed-off-by: Masaharu Hayakawa
[Niklas: update commit message]
Signed-off-by: Niklas Söderlund
---
drivers/mmc/host/tmio_mmc_core.c | 4 ++--
1 file changed, 2
Hi,
These patches triggers a retune if a SCC error is detected. They where
ported from the renesas BSP. Masaharu-san did all the real work I just
ported them to upstream and did small fixups.
These patches where broken out of my retuning series as more work where
needed to adapt them to the
From: Masaharu Hayakawa
Checking for SCC error during retuning is unnecessary.
Signed-off-by: Masaharu Hayakawa
[Niklas: fix small style issue]
Signed-off-by: Niklas Söderlund
---
* Changes since v3
- Add check for 4TAP for HS400.
* Changes since v2
- Added check for HS400 as it's now
Hi Geert,
On Wednesday, July 25, 2018, Geert Uytterhoeven wrote:
> > However, if "interrupt-names" is specified in DT, then the driver
> > determines what the interrupt are based on their names, not the order in
> which
> > they are listed.
> >
> > Correct?
>
> Correct.
One final note on this
When copy_properties_from_host() ignores the error for an optional
property, it frees the error, but fails to reset it.
Hence if two or more optional properties are missing, an assertion is
triggered:
util/error.c:57: error_setv: Assertion `*errp == NULL' failed.
Fis this by resetting err
Commit 7f9545aa1a91 ("arm64: smp: remove cpu and numa topology
information when hotplugging out CPU") updates the cpu topology when
the CPU is hotplugged out. However the PSCI checker code uses the
topology_core_cpumask pointers for some of the cpu hotplug testing.
Since the pointer to the
rcar_dmac_chan_get_residue() should not stop the DMAC, because
the commit 538603c6026c ("dmaengine: sh: rcar-dmac: avoid to write
CHCR.TE to 1 if TCR is set to 0") had fixed unexpected re-transferring
issue. But it had caused the next issue which might stop the cyclic
mode transferring. Thus, for
Hi Chris,
On Wed, Jul 25, 2018 at 3:38 AM Chris Brandt wrote:
> I have one last clarification about your idea regarding documenting the
> interrupts separately for RZ/A2.
>
> On Thursday, July 19, 2018, Geert Uytterhoeven wrote:
> > For DT backwards compatibility, we have to keep support for the
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