I have pushed renesas-drivers-2018-12-04-v4.20-rc5 to
https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git
This tree is meant to ease development of platform support and drivers
for Renesas ARM SoCs. It is created by merging (a) the for-next branches
of various subsystem trees
Dear Geert-san, Wolfram-san
I'm sorry for the delay at the comments of this patch.
And I think it's not hurry!
+ /* Enable hwmon thermal sysfs */
+ tsc->zone->tzp->no_hwmon = false;
+ ret = thermal_add_hwmon_sysfs(tsc->zone);
+ if (ret)
On Tue, Dec 4, 2018 at 1:02 PM Wolfram Sang
wrote:
> After discussing this mail thread [1] again, we concluded that giving
> userspace enough time to prepare is our favourite option. So, do not
> keep the time value when suspended but reset it when resuming.
>
> [1]
On Mon, Dec 03, 2018 at 04:04:47PM +0100, Geert Uytterhoeven wrote:
> The thermal hardware description for the RZ/G1M SoC was added to its DTS
> after the introduction of support for thermal zones, and included a
> thermal-zones node from the beginning.
>
> Hence there is no need to claim
On Fri, Nov 30, 2018 at 03:08:26PM -0800, Olof Johansson wrote:
> On Wed, Nov 28, 2018 at 02:02:12PM +0100, Simon Horman wrote:
> > Hi Olof, Hi Kevin, Hi Arnd,
> >
> > Please consider these Renesas ARM based SoC DT updates for v4.21.
> >
> > I am sending out this pull-request at this time as
On Fri, Nov 30, 2018 at 03:54:11PM +, Biju Das wrote:
> This patch series aims to add support for iWave G20D-Q7 board based on RZ/G1N.
>
> This patch series is tested against renesas-dev
>
> V1-->V2
> * r8a7744: Initial SoC device tree: Fixed pfc register size,
> GIC_CPU_MASK_SIMPLE in
On Fri, Nov 30, 2018 at 10:02:16AM +0100, Geert Uytterhoeven wrote:
> On Tue, Nov 27, 2018 at 1:05 PM Biju Das wrote:
> > Add the DT node for the QSPI interface to the SoC dtsi.
> >
> > Signed-off-by: Biju Das
>
> Reviewed-by: Geert Uytterhoeven
Thanks, applied for v4.21.
On Fri, Nov 30, 2018 at 11:04:02AM +0100, Geert Uytterhoeven wrote:
> On Tue, Nov 27, 2018 at 1:05 PM Biju Das wrote:
> > This patch adds support for the camera daughter board which is
> > connected to iWave's RZ/G1N Qseven carrier board.
> >
> > Signed-off-by: Biju Das
>
> Reviewed-by: Geert
On Fri, Nov 30, 2018 at 10:03:28AM +0100, Geert Uytterhoeven wrote:
> On Tue, Nov 27, 2018 at 1:05 PM Biju Das wrote:
> > Add a device node for the xhci controller on the Renesas
> > RZ/G1N (r8a7744) SoC.
> >
> > Signed-off-by: Biju Das
>
> Reviewed-by: Geert Uytterhoeven
Thanks, applied for
On Fri, Nov 30, 2018 at 10:02:49AM +0100, Geert Uytterhoeven wrote:
> On Tue, Nov 27, 2018 at 1:05 PM Biju Das wrote:
> > Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi.
> >
> > Signed-off-by: Biju Das
>
> Reviewed-by: Geert Uytterhoeven
Thanks, applied for v4.21.
On Wed, Nov 28, 2018 at 04:38:26PM +, Biju Das wrote:
> This patch series aims to add support for some more interfaces
> to RZ/G1N SoC (IPMMU, VSP, VIN, PWM and TPU).
>
> This patch series tested against renesas-dev.
> it depends on the the below patch series.
>
>
On Fri, Nov 30, 2018 at 11:02:08AM +, Biju Das wrote:
> Hi Geert,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH 19/22] ARM: dts: r8a7744-iwg20m: Add SPI NOR support
> >
> > Hi Biju,
> >
> > On Fri, Nov 30, 2018 at 11:34 AM Biju Das wrote:
> > > > Subject: Re: [PATCH 19/22] ARM:
On Tue, Nov 27, 2018 at 11:56:35AM +, Biju Das wrote:
> Add a device node for the PCIe controller on the Renesas
> RZ/G1N (r8a7744) SoC.
>
> Signed-off-by: Biju Das
Thanks, applied for v4.21.
After discussing this mail thread [1] again, we concluded that giving
userspace enough time to prepare is our favourite option. So, do not
keep the time value when suspended but reset it when resuming.
[1] https://patchwork.kernel.org/patch/10252209/
Signed-off-by: Wolfram Sang
---
Fabrizio:
Hello Wolfram,
> From: Wolfram Sang
> Sent: 04 December 2018 12:02
> Subject: [RFC] watchdog: renesas_wdt: don't keep timer value during
> suspend/resume
>
> After discussing this mail thread [1] again, we concluded that giving
> userspace enough time to prepare is our favourite option. So, do
On Tue, Nov 27, 2018 at 11:56:30AM +, Biju Das wrote:
> The iWave RZ/G1N board is almost identical to RZ/G1M. cmt and rwdt modules
> are SoC specific and should be part of board dts rather than SoM dtsi. By
> moving these nodes to the common dtsi it allows cmt and rwdt to be enabled
> on both
On Tue, Nov 27, 2018 at 1:05 PM Biju Das wrote:
> The iWave RZ/G1N board is almost identical to RZ/G1M. cmt and rwdt modules
> are SoC specific and should be part of board dts rather than SoM dtsi. By
> moving these nodes to the common dtsi it allows cmt and rwdt to be enabled
> on both of these
Hi Niklas,
On Thu, Nov 29, 2018 at 1:16 AM Niklas Söderlund
wrote:
> The driver tries to figure out which state a SD clock is in when the
> clock is register instead of setting a known state. This can be
> problematic for two reasons.
>
> 1. If the clock driver can't figure out the state of the
On Thu, Nov 29, 2018 at 1:41 AM Niklas Söderlund
wrote:
> On H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1) the clock setting for HS400
> needs a quirk to function properly. The reason for the quirk is that
> there are two settings which produces same divider value for the SDn
> clock. On the effected
Hi Chris,
On Tue, Dec 4, 2018 at 5:25 PM Chris Brandt wrote:
> Besides, this board will only boot as XIP_KERNEL which is an impossible
> configuration in the mainline kernel, so this .dts file is mostly for
> checking the .dtsi file.
Let's hope we can fix that anytime soon.
Gr{oetje,eeting}s,
Add simple suspend/resume handlers to the driver to restore the chip
configuration after resume. It is possible that the chip was configured
with non-default values before suspend-resume cycle and that the chip
is powered down during this cycle, so the configuration could get lost.
Signed-off-by:
Provide the pass-through option of --queue-late to vsp-runner, to request
that yavta will queue frames after the stream has started.
Signed-off-by: Kieran Bingham
---
scripts/vsp-lib.sh | 4
1 file changed, 4 insertions(+)
diff --git a/scripts/vsp-lib.sh b/scripts/vsp-lib.sh
index
On 12/4/18 4:01 AM, Wolfram Sang wrote:
After discussing this mail thread [1] again, we concluded that giving
userspace enough time to prepare is our favourite option. So, do not
keep the time value when suspended but reset it when resuming.
[1] https://patchwork.kernel.org/patch/10252209/
Hi Geert,
Thanks for your review.
On Tuesday, December 04, 2018 1, Geert Uytterhoeven wrote:
> > + * This file is dual-licensed: you can use it either under the terms
> > + * of the GPL or the X11 license, at your option. Note that this dual
> > + * licensing only applies to this file, and not
Signed-off-by: Kieran Bingham
---
scripts/vsp-lib.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/vsp-lib.sh b/scripts/vsp-lib.sh
index 56969606382f..cf15a045ea8c 100755
--- a/scripts/vsp-lib.sh
+++ b/scripts/vsp-lib.sh
@@ -95,7 +95,7 @@ vsp1_set_control() {
}
Validate that a 1xN stream can be read through the RPF and written
through the WPF.
The test framework does not currently support processing images where
the stride does not match the output width - so the testing is currently
limited to testing only the vertical direction in this aspect.
Provide a means for the tester to request pixel perfect matches on tests.
This can be either through setting the environment variable VSP_PIXEL_PERFECT,
or
by passing either '-p' or '--pixel-perfect' on the test command line.
Signed-off-by: Kieran Bingham
---
scripts/vsp-lib.sh | 11
Extend the vsp-lib to support command line parsing for all tests. The
arguments parsed here should be common to all tests, and initially
provide shell level verbose debug output, and the option to easily keep
frames output by the VSP1.
Signed-off-by: Kieran Bingham
---
scripts/vsp-lib.sh | 34
Some of our tests set flipping and rotation controls, and the VSP cell
can be used again by later tests. If these controls are not reset, then
that operation is applied to later tests incorrectly causing that test
to fail.
In an ideal world, tests should clean up after themselves, and leave the
Provide an initial test which can run as part of the test suite.
This test will report the platform and kernel version, along with
the identified paths of required utilities.
This will aid in ensuring that required tools are available on a
running platform - and report the kernel and platform
Update the VSP-Test suite library to use yavta's (new) --reset-controls
feature to ensure each test starts with a clean environment.
This prevents tests being affected by previous settings to controls such
as rotate or flip.
Also, the series reposts other unloved patches which have gone either
Hi Chris,
On Thu, Nov 29, 2018 at 2:07 PM Chris Brandt wrote:
> Add support for Renesas RZ/A2M evaluation board.
>
> Signed-off-by: Chris Brandt
Thanks for your patch!
> index ..9570aeb8f1ce
> --- /dev/null
> +++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
> @@ -0,0 +1,133 @@
> +/*
>
Hi Chris,
On Thu, Nov 29, 2018 at 2:07 PM Chris Brandt wrote:
> Basic support for the RZ/A2 (R7S9210) SoC.
>
> Signed-off-by: Chris Brandt
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm/boot/dts/r7s9210.dtsi
> @@ -0,0 +1,211 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + *
There's quite often repeated sequence of a CPG register read-modify-write,
so it seems worth factoring it out into a function -- this saves 68 bytes
of the object code (AArch64 gcc 4.8.5) and simplifies protecting all such
sequences with a spinlock in the next patch...
Signed-off-by: Sergei
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the R-Car V3H (R8A77980) CPG/MSSR
driver.
Signed-off-by: Sergei Shtylyov
---
Changes in version 2:
- moved the RPCSRC clock support to the R-Car gen3 CPG patch adding the RPC
Hello!
Here's the set of 4 patches against the 'clk-renesas' branch of Geert
Uytterhoeven's
'renesas-drivers.git' repo. We're adding support for the R8A77980 CPG/MSSR RPC
clocks...
[1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify()
[2/4] clk: renesas: rcar-gen3-cpg: add spinlock
The RPCSRC internal clock is controlled by the RPCCKCR.DIV[4:3] on all
the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field
is different between SoCs; it makes sense to support the most common case
of this encoding in the R-Car gen3 CPG driver...
After adding the RPCSRC clock,
On Sun, 18 Nov 2018 18:30:56 +0100, Marek Vasut wrote:
> Document the support for rcar_can on R8A77990 SoC devices.
> Add R8A77990 to the list of SoCs which require the "assigned-clocks"
> and "assigned-clock-rates" properties.
>
> Signed-off-by: Marek Vasut
> Cc: Eugeniu Rosca
> Cc: Geert
On Sun, Nov 18, 2018 at 06:32:00PM +0100, Marek Vasut wrote:
> Document the support for rcar_canfd on R8A77965 SoC devices.
>
> Signed-off-by: Marek Vasut
> Cc: Eugeniu Rosca
> Cc: Geert Uytterhoeven
> Cc: Marc Kleine-Budde
> Cc: Rob Herring
> Cc: Simon Horman
> Cc: Wolfram Sang
> Cc:
On 12/04/2018 11:56 PM, Rob Herring wrote:
> On Sun, Nov 18, 2018 at 06:32:00PM +0100, Marek Vasut wrote:
>> Document the support for rcar_canfd on R8A77965 SoC devices.
>>
>> Signed-off-by: Marek Vasut
>> Cc: Eugeniu Rosca
>> Cc: Geert Uytterhoeven
>> Cc: Marc Kleine-Budde
>> Cc: Rob Herring
From: Ulrich Hecht
Adds compatible strings for the R-Car CAN FD controller in the D3 SoC.
Signed-off-by: Ulrich Hecht
Acked-by: Rob Herring
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
---
Documentation/devicetree/bindings/net/can/rcar_canfd.txt | 8
1 file changed, 4
From: Ulrich Hecht
Adds compatible strings for the R-Car CAN controller in the D3 SoC.
Signed-off-by: Ulrich Hecht
Acked-by: Rob Herring
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
---
Documentation/devicetree/bindings/net/can/rcar_can.txt | 3 ++-
1 file changed, 2
Hi!
These are the bindings for CAN and CAN FD controllers on R-Car D3
(R8A77995).
Changes since v2:
- rebased
- made wording less redundant in rcar_canfd.txt
- added dt-bindings prefix to subjects
CU
Uli
Ulrich Hecht (2):
dt-bindings: can: rcar_can: add r8a77995 (R-Car D3) compatibility
Protect the CPG register read-modify-write sequence with a spinlock.
Signed-off-by: Sergei Shtylyov
---
Changes in version 2:
- new patch.
drivers/clk/renesas/rcar-gen3-cpg.c |8
1 file changed, 8 insertions(+)
Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c
Quoting Marek Vasut (2018-12-04 10:27:21)
> diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
> index decffb3826ec..ac90fb36af1a 100644
> --- a/drivers/clk/clk-versaclock5.c
> +++ b/drivers/clk/clk-versaclock5.c
> @@ -906,6 +906,39 @@ static int vc5_remove(struct
Hi Marek,
On Wednesday, 5 December 2018 01:48:01 EET Marek Vasut wrote:
> On 12/04/2018 09:52 PM, Stephen Boyd wrote:
> > Quoting Marek Vasut (2018-12-04 10:27:21)
> >
> >> diff --git a/drivers/clk/clk-versaclock5.c
> >> b/drivers/clk/clk-versaclock5.c
> >> index decffb3826ec..ac90fb36af1a
Hi Marek,
On Wednesday, 5 December 2018 03:10:18 EET Marek Vasut wrote:
> On 12/03/2018 11:48 PM, Laurent Pinchart wrote:
> > On Tuesday, 4 December 2018 00:24:32 EET Marek Vasut wrote:
> >> On 12/03/2018 10:48 PM, Laurent Pinchart wrote:
> >>> On Monday, 3 December 2018 17:12:41 EET Geert
Hello Yoshihiro,
On Mon, Oct 15, 2018 at 11:11:57PM +0900, Yoshihiro Kaneko wrote:
> This series adds thermal support for R-Car E3 (R8A77990).
>
> This series is based on the next branch of Eduardo Valentin's
> linux-soc-thermal
> tree.
Sorry for the late response, but would you be able to
On 12/04/2018 09:52 PM, Stephen Boyd wrote:
> Quoting Marek Vasut (2018-12-04 10:27:21)
>> diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
>> index decffb3826ec..ac90fb36af1a 100644
>> --- a/drivers/clk/clk-versaclock5.c
>> +++ b/drivers/clk/clk-versaclock5.c
>> @@
On 12/03/2018 11:48 PM, Laurent Pinchart wrote:
> Hi Marek,
>
> On Tuesday, 4 December 2018 00:24:32 EET Marek Vasut wrote:
>> On 12/03/2018 10:48 PM, Laurent Pinchart wrote:
>>> On Monday, 3 December 2018 17:12:41 EET Geert Uytterhoeven wrote:
As of commit 6d2ca85279becdff ("dt-bindings:
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