Hi Shawn,
On Friday, 18 May 2018 04:21:48 EEST Shawn Lin wrote:
> Hi,
>
> linux-next-20180517 fail to build for arm64 defconfig due to this
> drivers.
This is a known issue due to two bugs, fixed by commits 315852b42297 ("drm:
rcar-du: Fix build failure") and dd856d924b
On 16-05-18, 15:06, Ulrich Hecht wrote:
> From: Hiroyuki Yokoyama
>
> Renesas R-Car E3 (R8A77990) SoC also has the R-Car gen2/3 compatible DMA
> controllers, so document the SoC specific binding.
This fails to apply for me, please rebase and send
--
~Vinod
On 16-05-18, 15:06, Ulrich Hecht wrote:
> From: Hiroyuki Yokoyama
>
> Renesas R-Car D3 (R8A77995) and E3 (R8A77990) SoCs also have the R-Car
> gen2/3 compatible DMA controllers, so document the SoC specific binding.
Applied, thanks
--
~Vinod
Hi,
linux-next-20180517 fail to build for arm64 defconfig due to this
drivers.
CC [M] drivers/gpu/drm/rcar-du/rcar_du_drv.o
CC [M] drivers/gpu/drm/rcar-du/rcar_du_vsp.o
CC [M] drivers/gpu/drm/rcar-du/rcar_du_of.o
drivers/gpu/drm/rcar-du/rcar_du_of.c:320:13: error: redefinition of
Hi Sergei,
On Thu, May 17, 2018 at 10:19 PM, Sergei Shtylyov
wrote:
> Add the device nodes for 3 more Cortex-A53 CPU cores; adjust the interrupt
> delivery masks for the ARM GIC and Architectured Timer.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir B
Add the device nodes for 3 more Cortex-A53 CPU cores; adjust the interrupt
delivery masks for the ARM GIC and Architectured Timer.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov
Signed-off-by: Sergei Shtylyov
---
The patch is against the 'renesas-d
Hi Kieran,
On Thursday, 17 May 2018 20:06:46 EEST Kieran Bingham wrote:
> On 17/05/18 15:35, Laurent Pinchart wrote:
> > On Monday, 30 April 2018 20:48:03 EEST Kieran Bingham wrote:
> >> On 07/04/18 01:23, Laurent Pinchart wrote:
> >>> On Thursday, 8 March 2018 02:05:31 EEST Kieran Bingham wrote:
Hi Kieran,
Thank you for the patch.
On Thursday, 17 May 2018 20:24:01 EEST Kieran Bingham wrote:
> We are now able to configure a pipeline directly into a local display
> list body. Take advantage of this fact, and create a cacheable body to
> store the configuration of the pipeline in the video
From: Sergei Shtylyov
Date: Wed, 16 May 2018 22:52:40 +0300
> Here's a set of 3 patches against DaveM's 'net-next.git' repo. They
> (gradually)
> add R8A77980 GEther support to the 'sh_eth' driver, starting with couple new
> register bits/values introduced with this chip, and ending with adding
The body write function relies on the code never asking it to write more
than the entries available in the list.
Currently with each list body containing 256 entries, this is fine, but
we can reduce this number greatly saving memory. In preparation of this
add a level of protection to catch any bu
Extend the display list body with a reference count, allowing bodies to
be kept as long as a reference is maintained. This provides the ability
to keep a cached copy of bodies which will not change, so that they can
be re-applied to multiple display lists.
Signed-off-by: Kieran Bingham
Reviewed-b
Currently the entities store their configurations into a display list.
Adapt this such that the code can be configured into a body directly,
allowing greater flexibility and control of the content.
All users of vsp1_dl_list_write() are removed in this process, thus it
too is removed.
A helper, vs
Each display list allocates a body to store register values in a dma
accessible buffer from a dma_alloc_wc() allocation. Each of these
results in an entry in the IOMMU TLB, and a large number of display list
allocations adds pressure to this resource.
Reduce TLB pressure on the IPMMUs by allocatin
Each display list currently allocates an area of DMA memory to store register
settings for the VSP1 to process. Each of these allocations adds pressure to
the IPMMU TLB entries.
We can reduce the pressure by pre-allocating larger areas and dividing the area
across multiple bodies represented as a
We are now able to configure a pipeline directly into a local display
list body. Take advantage of this fact, and create a cacheable body to
store the configuration of the pipeline in the video object.
vsp1_video_pipeline_run() is now the last user of the pipe->dl object.
Convert this function to
Adapt the dl->body0 object to use an object from the body pool. This
greatly reduces the pressure on the TLB for IPMMU use cases, as all of
the lists use a single allocation for the main body.
The CLU and LUT objects pre-allocate a pool containing three bodies,
allowing a userspace update before t
The entities provide a single .configure operation which configures the
object into the target display list, based on the vsp1_entity_params
selection.
Split the configure function into three parts, '.configure_stream()',
'.configure_frame()', and '.configure_partition()' to facilitate
splitting t
Throughout the codebase, the term 'fragment' is used to represent a
display list body. This term duplicates the 'body' which is already in
use.
The datasheet references these objects as a body, therefore replace all
mentions of a fragment with a body, along with the corresponding
pluralised terms.
Hi Laurent,
On 17/05/18 15:35, Laurent Pinchart wrote:
> Hi Kieran,
>
> On Monday, 30 April 2018 20:48:03 EEST Kieran Bingham wrote:
>> On 07/04/18 01:23, Laurent Pinchart wrote:
>>> On Thursday, 8 March 2018 02:05:31 EEST Kieran Bingham wrote:
We are now able to configure a pipeline directl
Hi Lee,
On 5/16/18, 11:25 PM, "Lee Jones" wrote:
On Wed, 16 May 2018, Hoan Tran wrote:
> Hi Phil,
>
> On 5/11/18, 1:31 AM, "Phil Edworthy" wrote:
>
> The DesignWare GPIO IP can be configured for either 1 interrupt or 1
> per GPIO in port A, but the dr
Hi Geert,
Thanks for your patch.
On 2018-05-17 12:21:02 +0200, Geert Uytterhoeven wrote:
> Add the CR core clock, which is used by the Secure Engine (SCEG).
>
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Niklas Söderlund
> ---
> Pending successfull use of the SCEG.
>
> drivers/clk/rene
Hi Kieran,
On Monday, 30 April 2018 20:48:03 EEST Kieran Bingham wrote:
> On 07/04/18 01:23, Laurent Pinchart wrote:
> > On Thursday, 8 March 2018 02:05:31 EEST Kieran Bingham wrote:
> >> We are now able to configure a pipeline directly into a local display
> >> list body. Take advantage of this f
Prepare for adding a new IOCTL VIDIOC_SUBDEV_ENUMSTD which would
enumerate the standards for a subdevice by breaking out the code which
could be shared between the video and subdevice versions of this IOCTL.
Signed-off-by: Niklas Söderlund
---
drivers/media/v4l2-core/v4l2-ioctl.c | 66 ++
Hi Hans,
This series enables the video standards to be controlled directly on the
subdev device node. This is needed as there is no way to control the
standard of a subdevice if it's part of a media controller centric setup
as oppose to a video centric one.
I have tested this on Renesas Gen3 S
There is no way to control the standard of subdevices which are part of
a media device. The ioctls which exists all target video devices
explicitly and the idea is that the video device should talk to the
subdevice. For subdevices part of a media graph this is not possible and
the standard must be
On Mon, Apr 30, 2018 at 01:55:42PM +0200, Wolfram Sang wrote:
> While researching some PM behaviour within I2C, I found out that the i2c-demux
> driver does not play well with that due to broken relationship with other
> devices. Patch 1 ensures the right parent-child relationship. Patch 2 makes
>
Hi Gilad,
On Thu, May 17, 2018 at 3:41 PM, Gilad Ben-Yossef wrote:
> On Thu, May 17, 2018 at 4:35 PM, Geert Uytterhoeven
> wrote:
>> On Thu, May 17, 2018 at 3:09 PM, Gilad Ben-Yossef
>> wrote:
>>> On Thu, May 17, 2018 at 1:16 PM, Geert Uytterhoeven
>>> wrote:
However, even with your cloc
On Thu, May 17, 2018 at 4:35 PM, Geert Uytterhoeven
wrote:
> Hi Gilad,
>
> On Thu, May 17, 2018 at 3:09 PM, Gilad Ben-Yossef wrote:
>> On Thu, May 17, 2018 at 1:16 PM, Geert Uytterhoeven
>> wrote:
>>> However, even with your clock patch, the signature checking fails for me,
>>> on both R-Car H3
Hi Gilad,
On Thu, May 17, 2018 at 3:09 PM, Gilad Ben-Yossef wrote:
> On Thu, May 17, 2018 at 1:16 PM, Geert Uytterhoeven
> wrote:
>> However, even with your clock patch, the signature checking fails for me,
>> on both R-Car H3 ES1.0 and ES2.0.
>> Does this need changes to the ARM Trusted Firmwar
On Thu, May 17, 2018 at 12:16 PM, Geert Uytterhoeven
wrote:
> On Thu, May 17, 2018 at 10:01 AM, Gilad Ben-Yossef
> wrote:
>> On Wed, May 16, 2018 at 10:43 AM, Simon Horman wrote:
>>> On Tue, May 15, 2018 at 04:50:44PM +0200, Geert Uytterhoeven wrote:
On Tue, May 15, 2018 at 2:29 PM, Gilad
On Thu, May 17, 2018 at 12:04 PM, Simon Horman wrote:
> On Thu, May 17, 2018 at 11:01:57AM +0300, Gilad Ben-Yossef wrote:
>> On Wed, May 16, 2018 at 10:43 AM, Simon Horman wrote:
>> > On Tue, May 15, 2018 at 04:50:44PM +0200, Geert Uytterhoeven wrote:
>> >> Hi Gilad,
>> >>
>> >> On Tue, May 15, 2
On Thu, May 17, 2018 at 1:16 PM, Geert Uytterhoeven
wrote:
> Hi Gilad,
>
> On Thu, May 17, 2018 at 10:01 AM, Gilad Ben-Yossef
> wrote:
>> On Wed, May 16, 2018 at 10:43 AM, Simon Horman wrote:
>>> On Tue, May 15, 2018 at 04:50:44PM +0200, Geert Uytterhoeven wrote:
On Tue, May 15, 2018 at 2:
Hi Laurent,
Thanks for the review,
On 17/05/18 10:41, Laurent Pinchart wrote:
> Hi Kieran,
>
> Thank you for the patch.
>
> On Thursday, 3 May 2018 16:35:45 EEST Kieran Bingham wrote:
>> The entities provide a single .configure operation which configures the
>> object into the target display li
Herbert,
On Tue, May 15, 2018 at 3:29 PM, Gilad Ben-Yossef wrote:
> We were using the content of the signature register as a sanity
> check for the hardware functioning but it turns out not all
> implementers use the same values so the check is giving false
> negative on certain SoCs and so we dr
Hi Hans,
Thanks for your feedback.
On 2018-05-17 10:04:35 +0200, Hans Verkuil wrote:
> On 17/05/18 04:00, Niklas Söderlund wrote:
>
> Missing commit log.
I checked other commits doing the same thing, they had no commit log and
that was enough reason for me to be lazy. Will fix in v2. And thank
Hi Jacopo,
On 2018-05-17 12:13:06 +0200, Jacopo Mondi wrote:
> Hi Niklas,
>thanks for review.
>
> On Wed, May 16, 2018 at 10:32:49PM +0200, Niklas Söderlund wrote:
> > Hi Jacopo,
> >
> > Thanks for your work!
> >
> > First let me apologies for the use of the keyword 'digital' in the
> > drive
Add the CR core clock, which is used by the Secure Engine (SCEG).
Signed-off-by: Geert Uytterhoeven
---
Pending successfull use of the SCEG.
drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c
b/drivers/clk/renesas/r
Hi Gilad,
On Thu, May 17, 2018 at 10:01 AM, Gilad Ben-Yossef wrote:
> On Wed, May 16, 2018 at 10:43 AM, Simon Horman wrote:
>> On Tue, May 15, 2018 at 04:50:44PM +0200, Geert Uytterhoeven wrote:
>>> On Tue, May 15, 2018 at 2:29 PM, Gilad Ben-Yossef
>>> wrote:
>>> > Add bindings for CryptoCell
Hi Niklas,
thanks for review.
On Wed, May 16, 2018 at 10:32:49PM +0200, Niklas Söderlund wrote:
> Hi Jacopo,
>
> Thanks for your work!
>
> First let me apologies for the use of the keyword 'digital' in the
> driver it should have been parallel... Someday we should remedy this.
>
> If you touch
Hi Kieran,
Thank you for the patch.
On Thursday, 3 May 2018 16:35:46 EEST Kieran Bingham wrote:
> Currently the entities store their configurations into a display list.
> Adapt this such that the code can be configured into a body directly,
> allowing greater flexibility and control of the conten
Hi Kieran,
Thank you for the patch.
On Thursday, 3 May 2018 16:35:45 EEST Kieran Bingham wrote:
> The entities provide a single .configure operation which configures the
> object into the target display list, based on the vsp1_entity_params
> selection.
>
> Split the configure function into thre
Hi Niklas,
On Thu, May 17, 2018 at 12:13:07AM +0200, Niklas Söderlund wrote:
> Hi Jacopo,
>
> Thanks for your work.
>
> On 2018-05-16 18:32:31 +0200, Jacopo Mondi wrote:
> > The 'bus-width' and 'pclk-sample' properties are not parsed by the VIN
> > driver and only confuse users. Remove them in all
On Wed, May 16, 2018 at 11:00:29PM +0300, Sergei Shtylyov wrote:
> Finally, add support for the DT probing of the R-Car V3H (AKA R8A77980) --
> it's the only R-Car gen3 SoC having the GEther controller -- others have
> only EtherAVB...
>
> Based on the original (and large) patch by Vladimir Barino
On Thu, May 17, 2018 at 11:01:57AM +0300, Gilad Ben-Yossef wrote:
> On Wed, May 16, 2018 at 10:43 AM, Simon Horman wrote:
> > On Tue, May 15, 2018 at 04:50:44PM +0200, Geert Uytterhoeven wrote:
> >> Hi Gilad,
> >>
> >> On Tue, May 15, 2018 at 2:29 PM, Gilad Ben-Yossef
> >> wrote:
> >> > Add bind
On Thu, May 17, 2018 at 09:14:56AM +0200, jacopo mondi wrote:
> Hi Niklas,
>
> On Thu, May 17, 2018 at 12:23:18AM +0200, Niklas Söderlund wrote:
> > Hi Jacopo,
> >
> > Thanks for your patch.
> >
> > On 2018-05-16 15:42:09 +0200, Jacopo Mondi wrote:
> > > Describe HDMI input connector and ADV7612 H
On 5/17/2018 2:32 AM, Niklas Söderlund wrote:
The style for referring to ports and endpoint are wrong. Refer to them
using lowercase and a unit address, port@x and endpoint@x.
Signed-off-by: Niklas Söderlund
Reported-by: Geert Uytterhoeven
More typos, yay! :-)
---
.../devicetree/bind
On Wed, May 16, 2018 at 11:59:32AM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 5/16/2018 10:54 AM, Simon Horman wrote:
>
> > > Add support for the R-Car D3 (R8A77995) SoC to the LVDS encoder driver.
> > >
> > > Signed-off-by: Ulrich Hecht
> > > ---
> > > drivers/gpu/drm/rcar-du/rcar_lvds.c
Hello!
On 5/17/2018 2:22 AM, Niklas Söderlund wrote:
When starting the VIN capture procedure we are not guaranteed that the
first buffer writing to is VnMB1 to which we assigned the first buffer
Written, perhaps?
queued. This is problematic for two reasons. Buffers might not be
dequeued
Hello!
On 5/16/2018 7:32 PM, Jacopo Mondi wrote:
The data-active property has to be specified when running with embedded
Prop names are typically enclosed in "".
synchronization. The VIN peripheral can use HSYNC in place of CLOCKENB
CLKENB, maybe?
when the CLOCKENB pin is not conn
Hi Niklas,
On Thu, May 17, 2018 at 12:11:03AM +0200, Niklas Söderlund wrote:
> Hi Jacopo,
>
> Thanks for your patch.
>
> I'm happy that you dig into this as it clearly needs doing!
>
> On 2018-05-16 18:32:30 +0200, Jacopo Mondi wrote:
> > Handle CLOCKENB pin polarity, or use HSYNC in its place if
Hi Gilad,
On Thu, May 17, 2018 at 10:00 AM, Gilad Ben-Yossef wrote:
> On Tue, May 15, 2018 at 5:47 PM, Geert Uytterhoeven
> wrote:
>> On Tue, May 15, 2018 at 2:29 PM, Gilad Ben-Yossef
>> wrote:
>>> This patch adds the clock used by the CryptoCell 630p instance in the SoC.
>>>
>>> Signed-off-by
Hi Niklas,
On Wed, May 16, 2018 at 11:58:47PM +0200, Niklas Söderlund wrote:
> Hi Jacopo,
>
> Thanks for your work.
>
> On 2018-05-16 18:32:29 +0200, Jacopo Mondi wrote:
> > The data-active property has to be specified when running with embedded
> > synchronization. The VIN peripheral can use HSYN
Hi Niklas,
On Wed, May 16, 2018 at 11:55:38PM +0200, Niklas Söderlund wrote:
> Hi Jacopo,
>
> Thanks for your work.
>
> On 2018-05-16 18:32:28 +0200, Jacopo Mondi wrote:
> > Document 'data-active' property in R-Car VIN device tree bindings.
> > The property is optional when running with explicit s
On 5/16/2018 11:37 PM, Andrew Lunn wrote:
What about
PHY_INTERFACE_MODE_RGMII_ID,
PHY_INTERFACE_MODE_RGMII_RXID,
PHY_INTERFACE_MODE_RGMII_TXID,
Oops, totally forgot about those... :-/
Everybody does. I keep intending to write a email template for
this, and phy_int
On Wed, May 16, 2018 at 10:58:26PM +0300, Sergei Shtylyov wrote:
> The R-Car V3H (AKA R8A77980) GEther controller adds the DMA burst mode bit
> (NBST) in EDMR and the manual tells to always set it before doing any DMA.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-of
On 17/05/18 04:00, Niklas Söderlund wrote:
Missing commit log.
> Signed-off-by: Niklas Söderlund
> ---
> Documentation/media/uapi/v4l/vidioc-g-std.rst| 14 ++
> Documentation/media/uapi/v4l/vidioc-querystd.rst | 11 +++
What about ENUMSTD?
Regards,
Hans
> dri
On Wed, May 16, 2018 at 10:43 AM, Simon Horman wrote:
> On Tue, May 15, 2018 at 04:50:44PM +0200, Geert Uytterhoeven wrote:
>> Hi Gilad,
>>
>> On Tue, May 15, 2018 at 2:29 PM, Gilad Ben-Yossef
>> wrote:
>> > Add bindings for CryptoCell instance in the SoC.
>> >
>> > Signed-off-by: Gilad Ben-Yoss
On Tue, May 15, 2018 at 5:47 PM, Geert Uytterhoeven
wrote:
> Hi Gilad,
>
> On Tue, May 15, 2018 at 2:29 PM, Gilad Ben-Yossef wrote:
>> This patch adds the clock used by the CryptoCell 630p instance in the SoC.
>>
>> Signed-off-by: Gilad Ben-Yossef
>
> Thanks for your patch!
>
>> --- a/drivers/cl
On Wed, May 16, 2018 at 03:05:15PM +0200, Ulrich Hecht wrote:
> From: Hiromitsu Yamasaki
>
> This patch adds MSIOF device nodes for the R8A77995 SoC.
>
> Signed-off-by: Hiromitsu Yamasaki
> Signed-off-by: Takeshi Kihara
> [uli: remove unimplemented ref clock]
> Signed-off-by: Ulrich Hecht
Th
On Wed, May 16, 2018 at 09:08:06PM +0200, Niklas Söderlund wrote:
> Hi Ulrich,
>
> On 2018-05-16 15:07:01 +0200, Ulrich Hecht wrote:
> > On Wed, Apr 11, 2018 at 11:01 AM, jacopo mondi wrote:
> > > Hello Kaneko-san,
> > >
> > > On Tue, Apr 03, 2018 at 09:43:02PM +0900, Yoshihiro Kaneko wrote:
> >
On Wed, May 16, 2018 at 07:43:29PM +0200, Geert Uytterhoeven wrote:
> Hi Uli,
>
> On Wed, May 16, 2018 at 3:05 PM, Ulrich Hecht
> wrote:
> > From: Hiromitsu Yamasaki
> >
> > This patch adds MSIOF device nodes for the R8A77995 SoC.
> >
> > Signed-off-by: Hiromitsu Yamasaki
> > Signed-off-by: Tak
On Wed, May 16, 2018 at 03:05:16PM +0200, Ulrich Hecht wrote:
> Document support for the MSIOF module in the Renesas D3 (r8a77995) SoC.
>
> No driver update is needed.
>
> Signed-off-by: Ulrich Hecht
Reviewed-by: Simon Horman
> ---
> Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 +
>
On Wed, May 16, 2018 at 03:06:19PM +0200, Ulrich Hecht wrote:
> From: Hiroyuki Yokoyama
>
> Renesas R-Car E3 (R8A77990) SoC also has the R-Car gen2/3 compatible DMA
> controllers, so document the SoC specific binding.
>
> Signed-off-by: Hiroyuki Yokoyama
> Signed-off-by: Ulrich Hecht
Reviewed
On Wed, May 16, 2018 at 03:06:18PM +0200, Ulrich Hecht wrote:
> From: Hiroyuki Yokoyama
>
> Renesas R-Car D3 (R8A77995) and E3 (R8A77990) SoCs also have the R-Car
> gen2/3 compatible DMA controllers, so document the SoC specific binding.
>
> Signed-off-by: Hiroyuki Yokoyama
> [uli: squashed]
>
On Wed, May 16, 2018 at 03:04:51PM +0200, Ulrich Hecht wrote:
> From: Takeshi Kihara
>
> This patch adds the device nodes for SCIF-{0,1,3,4,5} serial ports,
> incl. clocks and power domain.
>
> Signed-off-by: Takeshi Kihara
> Signed-off-by: Ulrich Hecht
> ---
> arch/arm64/boot/dts/renesas/r8a
On Wed, May 16, 2018 at 03:04:50PM +0200, Ulrich Hecht wrote:
> From: Takeshi Kihara
>
> This patch adds the device nodes all HSCIF serial ports
> incl. clocks and power domain to the R8A77995 SoC.
>
> Signed-off-by: Takeshi Kihara
> Signed-off-by: Ulrich Hecht
> ---
> arch/arm64/boot/dts/ren
Hi Niklas,
On Thu, May 17, 2018 at 12:23:18AM +0200, Niklas Söderlund wrote:
> Hi Jacopo,
>
> Thanks for your patch.
>
> On 2018-05-16 15:42:09 +0200, Jacopo Mondi wrote:
> > Describe HDMI input connector and ADV7612 HDMI decoder installed on
> > R-Car Gen3 Draak board.
> >
> > The video signal ro
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