[PATCH v4 4/5] ARM: shmobile: Enable NXP pcf85363 rtc in shmobile_defconfig
The iWave RZ/G1C SBC supports RTC (NXP pcf85263). To increase hardware support enable the driver in the shmobile_defconfig multiplatform configuration. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- V1-->V2 * No change. V2-->V3 * No change. V3-->V4 * No Change. --- arch/arm/configs/shmobile_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 9e5a5ad..fdac4e4 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -177,6 +177,7 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_RS5C372=y +CONFIG_RTC_DRV_PCF85363=y CONFIG_RTC_DRV_BQ32K=y CONFIG_RTC_DRV_S35390A=y CONFIG_RTC_DRV_RX8581=y -- 2.7.4
[PATCH v4 5/5] ARM: dts: iwg23s-sbc: Enable RTC
Enable NXP pcf85263 real time clock for the iWave SBC based on RZ/G1C.
Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No change
V2-->V3
* No change
V3-->V4
* No change
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 40b7f98..77d1824 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -84,12 +84,30 @@
clock-frequency = <2000>;
};
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <40>;
+
+ rtc@51 {
+ compatible = "nxp,pcf85263";
+ reg = <0x51>;
+ };
+};
+
{
avb_pins: avb {
groups = "avb_mdio", "avb_gmii_tx_rx";
function = "avb";
};
+ i2c3_pins: i2c3 {
+ groups = "i2c3_c";
+ function = "i2c3";
+ };
+
mmc_pins_uhs: mmc_uhs {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
--
2.7.4
[PATCH v4 3/5] rtc: pcf85363: Add support for NXP pcf85263 rtc
Add support for NXP pcf85263 real-time clock. pcf85263 rtc is compatible
with pcf85363,except that pcf85363 has additional 64 bytes of RAM.
1 byte of nvmem is supported and exposed in sysfs (# is the instance
number,starting with 0): /sys/bus/nvmem/devices/pcf85x63-#/nvmem
Signed-off-by: Biju Das
---
V1-->V2
* Incorporated Alexandre and Geert's review comment.
V2-->V3
* Incorporated Geert's review comment.
V3-->V4
* Incorporated Geert's and Alexandre's review comment.
---
drivers/rtc/rtc-pcf85363.c | 94 +-
1 file changed, 76 insertions(+), 18 deletions(-)
diff --git a/drivers/rtc/rtc-pcf85363.c b/drivers/rtc/rtc-pcf85363.c
index c04a1ed..a398807 100644
--- a/drivers/rtc/rtc-pcf85363.c
+++ b/drivers/rtc/rtc-pcf85363.c
@@ -120,6 +120,11 @@ struct pcf85363 {
struct regmap *regmap;
};
+struct pcf85x63_config {
+ struct regmap_config regmap;
+ unsigned int num_nvram;
+};
+
static int pcf85363_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
@@ -311,25 +316,75 @@ static int pcf85363_nvram_write(void *priv, unsigned int
offset, void *val,
val, bytes);
}
-static const struct regmap_config regmap_config = {
- .reg_bits = 8,
- .val_bits = 8,
- .max_register = 0x7f,
+static int pcf85x63_nvram_read(void *priv, unsigned int offset, void *val,
+ size_t bytes)
+{
+ struct pcf85363 *pcf85363 = priv;
+ unsigned int tmp_val;
+ int ret;
+
+ ret = regmap_read(pcf85363->regmap, CTRL_RAMBYTE, _val);
+ (*(unsigned char *) val) = (unsigned char) tmp_val;
+
+ return ret;
+}
+
+static int pcf85x63_nvram_write(void *priv, unsigned int offset, void *val,
+ size_t bytes)
+{
+ struct pcf85363 *pcf85363 = priv;
+ unsigned char tmp_val;
+
+ tmp_val = *((unsigned char *)val);
+ return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
+ (unsigned int)tmp_val);
+}
+
+static const struct pcf85x63_config pcf_85263_config = {
+ .regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0x2f,
+ },
+ .num_nvram = 1
+};
+
+static const struct pcf85x63_config pcf_85363_config = {
+ .regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0x7f,
+ },
+ .num_nvram = 2
};
static int pcf85363_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct pcf85363 *pcf85363;
- struct nvmem_config nvmem_cfg = {
- .name = "pcf85363-",
- .word_size = 1,
- .stride = 1,
- .size = NVRAM_SIZE,
- .reg_read = pcf85363_nvram_read,
- .reg_write = pcf85363_nvram_write,
+ const struct pcf85x63_config *config = _85363_config;
+ const void *data = of_device_get_match_data(>dev);
+ static struct nvmem_config nvmem_cfg[] = {
+ {
+ .name = "pcf85x63-",
+ .word_size = 1,
+ .stride = 1,
+ .size = 1,
+ .reg_read = pcf85x63_nvram_read,
+ .reg_write = pcf85x63_nvram_write,
+ }, {
+ .name = "pcf85363-",
+ .word_size = 1,
+ .stride = 1,
+ .size = NVRAM_SIZE,
+ .reg_read = pcf85363_nvram_read,
+ .reg_write = pcf85363_nvram_write,
+ },
};
- int ret;
+ int ret, i;
+
+ if (data)
+ config = data;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -ENODEV;
@@ -339,7 +394,7 @@ static int pcf85363_probe(struct i2c_client *client,
if (!pcf85363)
return -ENOMEM;
- pcf85363->regmap = devm_regmap_init_i2c(client, _config);
+ pcf85363->regmap = devm_regmap_init_i2c(client, >regmap);
if (IS_ERR(pcf85363->regmap)) {
dev_err(>dev, "regmap allocation failed\n");
return PTR_ERR(pcf85363->regmap);
@@ -370,15 +425,18 @@ static int pcf85363_probe(struct i2c_client *client,
ret = rtc_register_device(pcf85363->rtc);
- nvmem_cfg.priv = pcf85363;
- rtc_nvmem_register(pcf85363->rtc, _cfg);
+ for (i = 0; i < config->num_nvram; i++) {
+ nvmem_cfg[i].priv = pcf85363;
+ rtc_nvmem_register(pcf85363->rtc, _cfg[i]);
+ }
return ret;
}
static const struct of_device_id dev_ids[] = {
- { .compatible = "nxp,pcf85363" },
[PATCH v4 2/5] dt-bindings: rtc: pcf85363: Document pcf85263 real-time clock
The pcf85263 RTC is compatible with the pcf85363 RTC. The difference between the pcf85263 and pcf85363 RTC is that the latter has 64 bytes more RAM. This renders them incompatible from a DT point of view. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- V1-->V2 * Incorporated Simon's review comment. V2-->V3 * No Change. V3-->V4 * No Change. --- Documentation/devicetree/bindings/rtc/pcf85363.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/rtc/pcf85363.txt b/Documentation/devicetree/bindings/rtc/pcf85363.txt index 76fdabc..94adc1c 100644 --- a/Documentation/devicetree/bindings/rtc/pcf85363.txt +++ b/Documentation/devicetree/bindings/rtc/pcf85363.txt @@ -1,8 +1,8 @@ -NXP PCF85363 Real Time Clock +NXP PCF85263/PCF85363 Real Time Clock Required properties: -- compatible: Should contain "nxp,pcf85363". +- compatible: Should contain "nxp,pcf85263" or "nxp,pcf85363". - reg: I2C address for chip. Optional properties: -- 2.7.4
[PATCH v4 0/5] Add NXP pcf85263 real-time clock support
This patch set aims to add support for NXP pcf85263 real-time clock.
pcf85263 rtc is compatible with pcf85363 rtc except that pcf85363 has
64 bytes additional RAM.
1 byte of nvmem is supported in pcf85263 and is exposed through sysfs.
The details of pcf85363 and pcf85263 can be found in the below data sheets.
https://www.nxp.com/docs/en/data-sheet/PCF85363A.pdf
https://www.nxp.com/docs/en/data-sheet/PCF85263A.pdf
This patch is tested against linux-next.
V1-->V2
* Incorporated simon's review comment for binding patch.
* Incorporated Geert and Alexandre's review comments.
V2-->V3
* Incorporated Geert's review comments.
V3-->V4
* Incorporated Geert and Alexandre's review comments.
Biju Das (5):
nvmem: check invalid number of bytes in nvmem_device_{read,write}
dt-bindings: rtc: pcf85363: Document pcf85263 real-time clock
rtc: pcf85363: Add support for NXP pcf85263 rtc
ARM: shmobile: Enable NXP pcf85363 rtc in shmobile_defconfig
ARM: dts: iwg23s-sbc: Enable RTC
Documentation/devicetree/bindings/rtc/pcf85363.txt | 4 +-
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 18 +
arch/arm/configs/shmobile_defconfig| 1 +
drivers/nvmem/core.c | 26 +-
drivers/rtc/rtc-pcf85363.c | 94 +-
5 files changed, 122 insertions(+), 21 deletions(-)
--
2.7.4
[PATCH v4 1/5] nvmem: check invalid number of bytes in nvmem_device_{read,write}
Add check in nvmem_device_{read,write}()to ensure that nvmem core never
passes an invalid number of bytes.
Signed-off-by: Biju Das
---
V3-->V4
* New patch.
---
drivers/nvmem/core.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c
index d9fd110..db7de33 100644
--- a/drivers/nvmem/core.c
+++ b/drivers/nvmem/core.c
@@ -1433,10 +1433,21 @@ int nvmem_device_read(struct nvmem_device *nvmem,
size_t bytes, void *buf)
{
int rc;
+ size_t new_bytes;
if (!nvmem)
return -EINVAL;
+ /* Stop the user from reading */
+ if ((offset >= nvmem->size) || (bytes == 0))
+ return 0;
+
+ if (unlikely(check_add_overflow(bytes, offset, _bytes)))
+ return -EOVERFLOW;
+
+ if (new_bytes > nvmem->size)
+ bytes = nvmem->size - offset;
+
rc = nvmem_reg_read(nvmem, offset, buf, bytes);
if (rc)
@@ -1461,16 +1472,29 @@ int nvmem_device_write(struct nvmem_device *nvmem,
size_t bytes, void *buf)
{
int rc;
+ size_t new_bytes;
if (!nvmem)
return -EINVAL;
+ /* Stop the user from writing */
+ if (offset >= nvmem->size)
+ return -ENOSPC;
+
+ if (bytes == 0)
+ return 0;
+
+ if (unlikely(check_add_overflow(bytes, offset, _bytes)))
+ return -EOVERFLOW;
+
+ if (new_bytes > nvmem->size)
+ bytes = nvmem->size - offset;
+
rc = nvmem_reg_write(nvmem, offset, buf, bytes);
if (rc)
return rc;
-
return bytes;
}
EXPORT_SYMBOL_GPL(nvmem_device_write);
--
2.7.4
RE: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
>
> Hi Biju,
>
> On Fri, Dec 7, 2018 at 10:34 AM Biju Das wrote:
> > > Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP
> > > pcf85263 rtc
> > >
> > > On 06/12/2018 15:49:57+, Biju Das wrote:
>
> > > > > Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP
> > > > > pcf85263 rtc
>
> > > > > On Thu, Dec 6, 2018 at 4:24 PM Biju Das
> > > > >
> > > wrote:
> > > > > > > Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for
> > > > > > > NXP
> > > > > > > pcf85263 rtc CC nvmem maintainer Given bytes should be 1,
> > > > > > > val should be a pointer to a single byte...
> > > > > > > What if bytes == 0?
> > > > > >
> > > > > > I doubt we get "bytes==0" because of the checks in "
> > > > > drivers/nvmem/core.c"
> > > > > > Function " bin_attr_nvmem_read/ bin_attr_nvmem_write".
> > > > >
> > > > > Depends. There are other functions calling
> > > > > nvmem_reg_{read,write}(),
> > > e.g.
> > > > > nvmem_device_{read,write}().
> > > >
> > > > OK. In that case, I will return (-EINVAL) for "bytes !=1"
> > >
> > > I think it is probably better to ensure the nvmem core never passes
> > > an invalid number of bytes. All the ther RTC drivers make that
> assumption.
> >
> > In that case, I will do following checks in
> > nvmem_device_{read,write}() before calling nvmem_reg_{read,write}(),
> >
> > nvmem_device_read
> >
> > /* Stop the user from reading */
> > if (offset >= nvmem->size)
> > return 0;
> >
> > if (bytes == 0)
> > return -EINVAL;
>
> Why not 0?
Ok. Will merge with above check.
if ((offset >= nvmem->size) && (bytes == 0))
return 0;
> >
> > if (offset + bytes > nvmem->size)
>
> This might overflow, please use check_add_overflow().
Will use check_add_overflow() and then the result is compared with
nvmem->size, if the check operation is successful.
> > bytes = nvmem->size - offset;
> >
> > nvmem_device_write
> >
> > /* Stop the user from writing */
> > if (offset >= nvmem->size)
> > return -EFBIG;
>
> ENOSPC?
OK, Will change it to ENOSPC.
> + same comments as for read.
>
> Oh, and offset is unsigned int instead of loff_t.
> Nobody's envisioning nvmem devices larger than 4 GiB?
Regards,
Biju
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RE: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
Hi Alexandre,
Thanks for the feedback.
> Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
>
> On 06/12/2018 15:49:57+0000, Biju Das wrote:
> > Hi Geert,
> >
> > Thanks for the feedback.
> >
> > > Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP
> > > pcf85263 rtc
> > >
> > > Hi Biju,
> > >
> > > On Thu, Dec 6, 2018 at 4:24 PM Biju Das
> wrote:
> > > > > Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP
> > > > > pcf85263 rtc CC nvmem maintainer
> > > > >
> > > > > On Thu, Dec 6, 2018 at 10:04 AM Biju Das
> > > > >
> > > wrote:
> > > > > > Add support for NXP pcf85263 real-time clock. pcf85263 rtc is
> > > > > > compatible with pcf85363,except that pcf85363 has additional
> > > > > > 64 bytes of
> > > > > RAM.
> > >
> > > > > > --- a/drivers/rtc/rtc-pcf85363.c
> > > > > > +++ b/drivers/rtc/rtc-pcf85363.c
> > > > > > @@ -120,6 +120,11 @@ struct pcf85363 {
> > > > > > struct regmap *regmap;
> > > > > > };
> > > > > >
> > > > > > +struct pcf85x63_config {
> > > > > > + struct regmap_config regmap;
> > > > > > + unsigned int num_nvram; };
> > > > > > +
> > > > > > static int pcf85363_rtc_read_time(struct device *dev, struct
> > > > > > rtc_time
> > > > > > *tm) {
> > > > > > struct pcf85363 *pcf85363 = dev_get_drvdata(dev); @@
> > > > > > -311,25
> > > > > > +316,68 @@ static int pcf85363_nvram_write(void *priv,
> > > > > > +unsigned int
> > > > > offset, void *val,
> > > > > > val, bytes); }
> > > > > >
> > > > > > -static const struct regmap_config regmap_config = {
> > > > > > - .reg_bits = 8,
> > > > > > - .val_bits = 8,
> > > > > > - .max_register = 0x7f,
> > > > > > +static int pcf85x63_nvram_read(void *priv, unsigned int
> > > > > > +offset, void
> > > *val,
> > > > > > + size_t bytes)
> > > > >
> > > > > Given bytes should be 1, val should be a pointer to a single byte...
> > > > > What if bytes == 0?
> > > >
> > > > I doubt we get "bytes==0" because of the checks in "
> > > drivers/nvmem/core.c"
> > > > Function " bin_attr_nvmem_read/ bin_attr_nvmem_write".
> > >
> > > Depends. There are other functions calling nvmem_reg_{read,write}(),
> e.g.
> > > nvmem_device_{read,write}().
> >
> > OK. In that case, I will return (-EINVAL) for "bytes !=1"
> >
>
> I think it is probably better to ensure the nvmem core never passes an invalid
> number of bytes. All the ther RTC drivers make that assumption.
In that case, I will do following checks in nvmem_device_{read,write}() before
calling nvmem_reg_{read,write}(),
nvmem_device_read
/* Stop the user from reading */
if (offset >= nvmem->size)
return 0;
if (bytes == 0)
return -EINVAL;
if (offset + bytes > nvmem->size)
bytes = nvmem->size - offset;
nvmem_device_write
/* Stop the user from writing */
if (offset >= nvmem->size)
return -EFBIG;
if (bytes == 0)
return -EINVAL;
if (offset + bytes > nvmem->size)
bytes = nvmem->size - offset;
regards,
Biju
[https://www2.renesas.eu/media/email/unicef.jpg]
This Christmas, instead of sending out cards, Renesas Electronics Europe have
decided to support Unicef with a donation. For further details click
here<https://www.unicef.org/> to find out about the valuable work they do,
helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a
prosperous New Year.
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
RE: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
>
> Hi Biju,
>
> On Thu, Dec 6, 2018 at 4:24 PM Biju Das wrote:
> > > Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP
> > > pcf85263 rtc CC nvmem maintainer
> > >
> > > On Thu, Dec 6, 2018 at 10:04 AM Biju Das
> wrote:
> > > > Add support for NXP pcf85263 real-time clock. pcf85263 rtc is
> > > > compatible with pcf85363,except that pcf85363 has additional 64
> > > > bytes of
> > > RAM.
>
> > > > --- a/drivers/rtc/rtc-pcf85363.c
> > > > +++ b/drivers/rtc/rtc-pcf85363.c
> > > > @@ -120,6 +120,11 @@ struct pcf85363 {
> > > > struct regmap *regmap;
> > > > };
> > > >
> > > > +struct pcf85x63_config {
> > > > + struct regmap_config regmap;
> > > > + unsigned int num_nvram;
> > > > +};
> > > > +
> > > > static int pcf85363_rtc_read_time(struct device *dev, struct
> > > > rtc_time
> > > > *tm) {
> > > > struct pcf85363 *pcf85363 = dev_get_drvdata(dev); @@
> > > > -311,25
> > > > +316,68 @@ static int pcf85363_nvram_write(void *priv, unsigned
> > > > +int
> > > offset, void *val,
> > > > val, bytes); }
> > > >
> > > > -static const struct regmap_config regmap_config = {
> > > > - .reg_bits = 8,
> > > > - .val_bits = 8,
> > > > - .max_register = 0x7f,
> > > > +static int pcf85x63_nvram_read(void *priv, unsigned int offset, void
> *val,
> > > > + size_t bytes)
> > >
> > > Given bytes should be 1, val should be a pointer to a single byte...
> > > What if bytes == 0?
> >
> > I doubt we get "bytes==0" because of the checks in "
> drivers/nvmem/core.c"
> > Function " bin_attr_nvmem_read/ bin_attr_nvmem_write".
>
> Depends. There are other functions calling nvmem_reg_{read,write}(), e.g.
> nvmem_device_{read,write}().
OK. In that case, I will return (-EINVAL) for "bytes !=1"
> >
> > > > +{> + struct pcf85363 *pcf85363 = priv;
> > > > +
> > > > + return regmap_read(pcf85363->regmap, CTRL_RAMBYTE, val);
> > >
> > > However, regmap_read() has an unsigned int output parameter!
> > > So it's writing too many bytes, and only writing the actual data
> > > byte to the correct address on little-endian systems.
> > > Hence you need to use an intermediate variable to convert from
> > > unsigned int to byte.
> >
> > OK. Will use an intermediate integer variable.
> >
> > > > +}
> > > > +
> > > > +static int pcf85x63_nvram_write(void *priv, unsigned int offset, void
> *val,
> > > > + size_t bytes) {
> > > > + struct pcf85363 *pcf85363 = priv;
> > > > +
> > > > + return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
> > > > + *((unsigned int *)val));
> > >
> > > Likewise for writing.
> > >
> > > > +}
> > >
> > > BTW, while the nvmem_device_{read,write}() public API is documented,
> > > the
> > > nvmem_device.reg_{read,write}() driver API isn't.
> > > And the behavior might be confusing.
> > >
> > > E.g.
> > > * Return: length of successful bytes read on success and negative
> > > * error code on error.
> > >
> > > The public API seems to assume the driver API returns zero on
> > > success, and replaces the zero by the number of bytes requested.
> > > If the requested number of bytes is too large, a zero success would
> > > be converted to a value that's larger than the actual number of
> > > bytes transferred!
> > > However, the driver API can return a smaller (positive) number,
> > > which matches "standard" read/write() APIs.
Regards,
Biju
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No. 04586709.
RE: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
Hi Geert,
Thanks for feedback.
> Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
>
> Hi Biju,
>
> CC nvmem maintainer
>
> On Thu, Dec 6, 2018 at 10:04 AM Biju Das wrote:
> > Add support for NXP pcf85263 real-time clock. pcf85263 rtc is
> > compatible with pcf85363,except that pcf85363 has additional 64 bytes of
> RAM.
> >
> > 1 byte of nvmem is supported and exposed in sysfs (# is the instance
> > number,starting with 0): /sys/bus/nvmem/devices/pcf85x63-#/nvmem
> >
> > Signed-off-by: Biju Das
> > ---
> > V1-->V2
> > * Incorporated Alexandre and Geert's review comment.
> > V2-->V3
> > * Incorporated Geert's review comment.
>
> Thanks for the update!
>
> > --- a/drivers/rtc/rtc-pcf85363.c
> > +++ b/drivers/rtc/rtc-pcf85363.c
> > @@ -120,6 +120,11 @@ struct pcf85363 {
> > struct regmap *regmap;
> > };
> >
> > +struct pcf85x63_config {
> > + struct regmap_config regmap;
> > + unsigned int num_nvram;
> > +};
> > +
> > static int pcf85363_rtc_read_time(struct device *dev, struct rtc_time
> > *tm) {
> > struct pcf85363 *pcf85363 = dev_get_drvdata(dev); @@ -311,25
> > +316,68 @@ static int pcf85363_nvram_write(void *priv, unsigned int
> offset, void *val,
> > val, bytes); }
> >
> > -static const struct regmap_config regmap_config = {
> > - .reg_bits = 8,
> > - .val_bits = 8,
> > - .max_register = 0x7f,
> > +static int pcf85x63_nvram_read(void *priv, unsigned int offset, void *val,
> > + size_t bytes)
>
> Given bytes should be 1, val should be a pointer to a single byte...
> What if bytes == 0?
I doubt we get "bytes==0" because of the checks in " drivers/nvmem/core.c"
Function " bin_attr_nvmem_read/ bin_attr_nvmem_write".
> > +{> + struct pcf85363 *pcf85363 = priv;
> > +
> > + return regmap_read(pcf85363->regmap, CTRL_RAMBYTE, val);
>
> However, regmap_read() has an unsigned int output parameter!
> So it's writing too many bytes, and only writing the actual data byte to the
> correct address on little-endian systems.
> Hence you need to use an intermediate variable to convert from unsigned int
> to byte.
OK. Will use an intermediate integer variable.
> > +}
> > +
> > +static int pcf85x63_nvram_write(void *priv, unsigned int offset, void *val,
> > + size_t bytes) {
> > + struct pcf85363 *pcf85363 = priv;
> > +
> > + return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
> > + *((unsigned int *)val));
>
> Likewise for writing.
>
> > +}
>
> BTW, while the nvmem_device_{read,write}() public API is documented, the
> nvmem_device.reg_{read,write}() driver API isn't.
> And the behavior might be confusing.
>
> E.g.
> * Return: length of successful bytes read on success and negative
> * error code on error.
>
> The public API seems to assume the driver API returns zero on success, and
> replaces the zero by the number of bytes requested.
> If the requested number of bytes is too large, a zero success would be
> converted to a value that's larger than the actual number of bytes
> transferred!
> However, the driver API can return a smaller (positive) number, which
> matches "standard" read/write() APIs.
>
> > +static const struct pcf85x63_config pcf_85263_config = {
> > + {
> > + .reg_bits = 8,
> > + .val_bits = 8,
> > + .max_register = 0x2f,
> > + },
> > + 1
>
> The "1" looks funny. Please use C99 initializers for all struct members.
OK will fix this.
> > +};
> > +
> > +static const struct pcf85x63_config pcf_85363_config = {
> > + {
> > + .reg_bits = 8,
> > + .val_bits = 8,
> > + .max_register = 0x7f,
> > + },
> > + 2
>
> Likewise.
OK will fix this.
Regards,
Biju
> The rest looks good to me, so
> Reviewed-by: Geert Uytterhoeven
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
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RE: [PATCH v3 4/4] ARM: dts: iwg23s-sbc: Enable RTC
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v3 4/4] ARM: dts: iwg23s-sbc: Enable RTC
>
> Hi Biju,
>
> On Thu, Dec 6, 2018 at 10:04 AM Biju Das wrote:
> > Enable NXP pcf85263 real time clock for the iWave SBC based on RZ/G1C.
> >
> > Signed-off-by: Biju Das
>
> Reviewed-by: Geert Uytterhoeven
>
> > --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
> > +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
> > @@ -84,12 +84,30 @@
> > clock-frequency = <2000>;
> > };
> >
> > + {
> > + pinctrl-0 = <_pins>;
> > + pinctrl-names = "default";
> > +
> > + status = "okay";
> > + clock-frequency = <40>;
> > +
> > + rtc@51 {
> > + compatible = "nxp,pcf85263";
> > + reg = <0x51>;
>
> You might want to enable the optional interrupt:
I have enabled this but unfortunately it is generating 10 of gpio
interrupts during boot.
The reason is, by default this pin is configured as function(Power on reset/at
u-boot).
Currently there is no function available in kernel to convert a pin from
function to gpio (Similar to the issue Fab is facing for display hot plug
interrupt)
May be we can add optional interrupt at a later stage, once we have a solution
for converting pin from function to gpio.
Please share your opinion on this.
Regards,
Biju
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This Christmas, instead of sending out cards, Renesas Electronics Europe have
decided to support Unicef with a donation. For further details click
here<https://www.unicef.org/> to find out about the valuable work they do,
helping children all over the world.
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[PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
Add support for NXP pcf85263 real-time clock. pcf85263 rtc is compatible
with pcf85363,except that pcf85363 has additional 64 bytes of RAM.
1 byte of nvmem is supported and exposed in sysfs (# is the instance
number,starting with 0): /sys/bus/nvmem/devices/pcf85x63-#/nvmem
Signed-off-by: Biju Das
---
V1-->V2
* Incorporated Alexandre and Geert's review comment.
V2-->V3
* Incorporated Geert's review comment.
---
drivers/rtc/rtc-pcf85363.c | 87 --
1 file changed, 69 insertions(+), 18 deletions(-)
diff --git a/drivers/rtc/rtc-pcf85363.c b/drivers/rtc/rtc-pcf85363.c
index c04a1ed..6a0a994 100644
--- a/drivers/rtc/rtc-pcf85363.c
+++ b/drivers/rtc/rtc-pcf85363.c
@@ -120,6 +120,11 @@ struct pcf85363 {
struct regmap *regmap;
};
+struct pcf85x63_config {
+ struct regmap_config regmap;
+ unsigned int num_nvram;
+};
+
static int pcf85363_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
@@ -311,25 +316,68 @@ static int pcf85363_nvram_write(void *priv, unsigned int
offset, void *val,
val, bytes);
}
-static const struct regmap_config regmap_config = {
- .reg_bits = 8,
- .val_bits = 8,
- .max_register = 0x7f,
+static int pcf85x63_nvram_read(void *priv, unsigned int offset, void *val,
+ size_t bytes)
+{
+ struct pcf85363 *pcf85363 = priv;
+
+ return regmap_read(pcf85363->regmap, CTRL_RAMBYTE, val);
+}
+
+static int pcf85x63_nvram_write(void *priv, unsigned int offset, void *val,
+ size_t bytes)
+{
+ struct pcf85363 *pcf85363 = priv;
+
+ return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
+ *((unsigned int *)val));
+}
+
+static const struct pcf85x63_config pcf_85263_config = {
+ {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0x2f,
+ },
+ 1
+};
+
+static const struct pcf85x63_config pcf_85363_config = {
+ {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0x7f,
+ },
+ 2
};
static int pcf85363_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct pcf85363 *pcf85363;
- struct nvmem_config nvmem_cfg = {
- .name = "pcf85363-",
- .word_size = 1,
- .stride = 1,
- .size = NVRAM_SIZE,
- .reg_read = pcf85363_nvram_read,
- .reg_write = pcf85363_nvram_write,
+ const struct pcf85x63_config *config = _85363_config;
+ const void *data = of_device_get_match_data(>dev);
+ static struct nvmem_config nvmem_cfg[] = {
+ {
+ .name = "pcf85x63-",
+ .word_size = 1,
+ .stride = 1,
+ .size = 1,
+ .reg_read = pcf85x63_nvram_read,
+ .reg_write = pcf85x63_nvram_write,
+ }, {
+ .name = "pcf85363-",
+ .word_size = 1,
+ .stride = 1,
+ .size = NVRAM_SIZE,
+ .reg_read = pcf85363_nvram_read,
+ .reg_write = pcf85363_nvram_write,
+ },
};
- int ret;
+ int ret, i;
+
+ if (data)
+ config = data;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -ENODEV;
@@ -339,7 +387,7 @@ static int pcf85363_probe(struct i2c_client *client,
if (!pcf85363)
return -ENOMEM;
- pcf85363->regmap = devm_regmap_init_i2c(client, _config);
+ pcf85363->regmap = devm_regmap_init_i2c(client, >regmap);
if (IS_ERR(pcf85363->regmap)) {
dev_err(>dev, "regmap allocation failed\n");
return PTR_ERR(pcf85363->regmap);
@@ -370,15 +418,18 @@ static int pcf85363_probe(struct i2c_client *client,
ret = rtc_register_device(pcf85363->rtc);
- nvmem_cfg.priv = pcf85363;
- rtc_nvmem_register(pcf85363->rtc, _cfg);
+ for (i = 0; i < config->num_nvram; i++) {
+ nvmem_cfg[i].priv = pcf85363;
+ rtc_nvmem_register(pcf85363->rtc, _cfg[i]);
+ }
return ret;
}
static const struct of_device_id dev_ids[] = {
- { .compatible = "nxp,pcf85363" },
- {}
+ { .compatible = "nxp,pcf85263", .data = _85263_config },
+ { .compatible = "nxp,pcf85363", .data = _85363_config },
+ { /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, dev_ids);
@@ -393,5 +444,5 @@ static struct i2c_driver pcf85363_driver = {
module_i2c_driver(pcf8536
[PATCH v3 4/4] ARM: dts: iwg23s-sbc: Enable RTC
Enable NXP pcf85263 real time clock for the iWave SBC based on RZ/G1C.
Signed-off-by: Biju Das
---
V1-->V2
* No change
V2-->V3
* No change
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 40b7f98..77d1824 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -84,12 +84,30 @@
clock-frequency = <2000>;
};
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <40>;
+
+ rtc@51 {
+ compatible = "nxp,pcf85263";
+ reg = <0x51>;
+ };
+};
+
{
avb_pins: avb {
groups = "avb_mdio", "avb_gmii_tx_rx";
function = "avb";
};
+ i2c3_pins: i2c3 {
+ groups = "i2c3_c";
+ function = "i2c3";
+ };
+
mmc_pins_uhs: mmc_uhs {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
--
2.7.4
[PATCH v3 1/4] dt-bindings: rtc: pcf85363: Document pcf85263 real-time clock
The pcf85263 RTC is compatible with the pcf85363 RTC. The difference between the pcf85263 and pcf85363 RTC is that the latter has 64 bytes more RAM. This renders them incompatible from a DT point of view. Signed-off-by: Biju Das --- V1-->V2 * Incorporated Simon's review comment. V2-->V3 * No Change --- Documentation/devicetree/bindings/rtc/pcf85363.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/rtc/pcf85363.txt b/Documentation/devicetree/bindings/rtc/pcf85363.txt index 76fdabc..94adc1c 100644 --- a/Documentation/devicetree/bindings/rtc/pcf85363.txt +++ b/Documentation/devicetree/bindings/rtc/pcf85363.txt @@ -1,8 +1,8 @@ -NXP PCF85363 Real Time Clock +NXP PCF85263/PCF85363 Real Time Clock Required properties: -- compatible: Should contain "nxp,pcf85363". +- compatible: Should contain "nxp,pcf85263" or "nxp,pcf85363". - reg: I2C address for chip. Optional properties: -- 2.7.4
[PATCH v3 3/4] ARM: shmobile: Enable NXP pcf85363 rtc in shmobile_defconfig
The iWave RZ/G1C SBC supports RTC (NXP pcf85263). To increase hardware support enable the driver in the shmobile_defconfig multiplatform configuration. Signed-off-by: Biju Das --- V1-->V2 * No change. V2-->V3 * No change. --- arch/arm/configs/shmobile_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 9e5a5ad..fdac4e4 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -177,6 +177,7 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_RS5C372=y +CONFIG_RTC_DRV_PCF85363=y CONFIG_RTC_DRV_BQ32K=y CONFIG_RTC_DRV_S35390A=y CONFIG_RTC_DRV_RX8581=y -- 2.7.4
[PATCH v3 0/4] Add NXP pcf85263 real-time clock support
This patch set aims to add support for NXP pcf85263 real-time clock. pcf85263 rtc is compatible with pcf85363 rtc except that pcf85363 has 64 bytes additional RAM. 1 byte of nvmem is supported in pcf85263 and is exposed through sysfs. The details of pcf85363 and pcf85263 can be found in the below data sheets. https://www.nxp.com/docs/en/data-sheet/PCF85363A.pdf https://www.nxp.com/docs/en/data-sheet/PCF85263A.pdf This patch is tested against linux-next. V1-->V2 * Incorporated simon's review comment for binding patch. * Incorporated Geert and Alexandre's review comments. V2-->V3 * Incorporated Geert's review comments. Biju Das (4): dt-bindings: rtc: pcf85363: Document pcf85263 real-time clock rtc: pcf85363: Add support for NXP pcf85263 rtc ARM: shmobile: Enable NXP pcf85363 rtc in shmobile_defconfig ARM: dts: iwg23s-sbc: Enable RTC Documentation/devicetree/bindings/rtc/pcf85363.txt | 4 +- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 18 + arch/arm/configs/shmobile_defconfig| 1 + drivers/rtc/rtc-pcf85363.c | 87 +- 4 files changed, 90 insertions(+), 20 deletions(-) -- 2.7.4
RE: [PATCH v2 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v2 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
>
> Hi Biju,
>
> On Thu, Nov 29, 2018 at 6:03 PM Biju Das wrote:
> > Add support for NXP pcf85263 real-time clock. pcf85263 rtc is
> > compatible with pcf85363,except that pcf85363 has additional 64 bytes of
> RAM.
> >
> > 1 byte of nvmem is supported and exposed in sysfs (# is the instance
> > number,starting with 0): /sys/bus/nvmem/devices/pcf85x63-#/nvmem
> >
> > Signed-off-by: Biju Das
> > ---
> > V1-->V2 Incorporated Alexandre and Geert's review comment.
>
> Thanks for the update!
>
> > --- a/drivers/rtc/rtc-pcf85363.c
> > +++ b/drivers/rtc/rtc-pcf85363.c
>
> > @@ -321,15 +344,25 @@ static int pcf85363_probe(struct i2c_client *client,
> > const struct i2c_device_id *id) {
> > struct pcf85363 *pcf85363;
> > - struct nvmem_config nvmem_cfg = {
> > - .name = "pcf85363-",
> > - .word_size = 1,
> > - .stride = 1,
> > - .size = NVRAM_SIZE,
> > - .reg_read = pcf85363_nvram_read,
> > - .reg_write = pcf85363_nvram_write,
> > + const struct regmap_config *regmap_config =
> _85363_regmap_config;
> > + struct nvmem_config nvmem_cfg[] = {
>
> static?
>
> Although the nvmem_config is copied, and thus static is not needed, I guess
> using static will decrease kernel size.
>
> > + {
> > + .name = "pcf85x63-",
> > + .word_size = 1,
> > + .stride = 1,
> > + .size = 1,
> > + .reg_read = pcf85x63_nvram_read,
> > + .reg_write = pcf85x63_nvram_write,
> > + }, {
> > + .name = "pcf85363-",
> > + .word_size = 1,
> > + .stride = 1,
> > + .size = NVRAM_SIZE,
> > + .reg_read = pcf85363_nvram_read,
> > + .reg_write = pcf85363_nvram_write,
> > + },
> > };
> > - int ret;
> > + int ret, i, num_nvmem = 2;
> >
> > if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
> > return -ENODEV;
> > @@ -339,7 +372,13 @@ static int pcf85363_probe(struct i2c_client *client,
> > if (!pcf85363)
> > return -ENOMEM;
> >
> > - pcf85363->regmap = devm_regmap_init_i2c(client, _config);
> > + if (of_device_get_match_data(>dev) ==
> > + _85263_regmap_config) {
> > + regmap_config = _85263_regmap_config;
> > + num_nvmem = 1;
>
> I think it's cleaner if you store the full config (regmap_config + num_nvmem)
> in of_device_id.data, instead of just the regmap_config, using
>
> struct pcf85x63_config {
> struct regmap_config regmap;
> unsigned int num_nvram;
> };
>
> static const struct pcf85x63_config pcf85263_config = { ... };
> static const struct pcf85x63_config pcf85363_config = { ... };
>
> static const struct of_device_id dev_ids[] = {
> { .compatible = "nxp,pcf85263", .data = _85263_config },
> { .compatible = "nxp,pcf85363", .data = _85363_config },
> { /* sentinel */ }
> };
>
> Then you can just do
>
> struct pcf85x63_config *config = _config; /* default for
> non-DT
> */
> void *data = of_device_get_match_data(>dev);
> if (data)
> config = data;
>
> > + }
Will send V3 with above changes.
Regards,
Biju
[https://www2.renesas.eu/media/email/unicef.jpg]
This Christmas, instead of sending out cards, Renesas Electronics Europe have
decided to support Unicef with a donation. For further details click
here<https://www.unicef.org/> to find out about the valuable work they do,
helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a
prosperous New Year.
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
RE: [PATCH v2 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
Hi Geert and Alexandre,
Thanks for the feedback.
> Subject: Re: [PATCH v2 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
>
> Hi Alexandre,
>
> On Fri, Nov 30, 2018 at 1:32 PM Alexandre Belloni
> wrote:
> > On 30/11/2018 12:05:16+0100, Geert Uytterhoeven wrote:
> > > On Thu, Nov 29, 2018 at 6:03 PM Biju Das
> wrote:
> > > > Add support for NXP pcf85263 real-time clock. pcf85263 rtc is
> > > > compatible with pcf85363,except that pcf85363 has additional 64 bytes
> of RAM.
> > > >
> > > > 1 byte of nvmem is supported and exposed in sysfs (# is the
> > > > instance number,starting with 0):
> > > > /sys/bus/nvmem/devices/pcf85x63-#/nvmem
> > > >
> > > > Signed-off-by: Biju Das
> > > > ---
> > > > V1-->V2 Incorporated Alexandre and Geert's review comment.
> > >
> > > Thanks for the update!
> > >
> > > > --- a/drivers/rtc/rtc-pcf85363.c
> > > > +++ b/drivers/rtc/rtc-pcf85363.c
> > >
> > > > @@ -321,15 +344,25 @@ static int pcf85363_probe(struct i2c_client
> *client,
> > > > const struct i2c_device_id *id) {
> > > > struct pcf85363 *pcf85363;
> > > > - struct nvmem_config nvmem_cfg = {
> > > > - .name = "pcf85363-",
> > > > - .word_size = 1,
> > > > - .stride = 1,
> > > > - .size = NVRAM_SIZE,
> > > > - .reg_read = pcf85363_nvram_read,
> > > > - .reg_write = pcf85363_nvram_write,
> > > > + const struct regmap_config *regmap_config =
> _85363_regmap_config;
> > > > + struct nvmem_config nvmem_cfg[] = {
> > >
> > > static?
> > >
> > > Although the nvmem_config is copied, and thus static is not needed,
> > > I guess using static will decrease kernel size.
> > >
> >
> > Hum, I don't think, this is on the stack anyway.
>
> If you make it static, it's no longer allocated on the stack, and gcc has no
> longer to emit code to initialize all members.
>
I have used "size" command to check the size of vmlinux with and without
static. Please find the results.
Without static
===
$ size vmlinux
text databssdechexfilename
71473602625982 29260810065950 99981evmlinux
With static variable
==
$ size vmlinux
text databssdechexfilename
71472002626110 29260810065918 9997fevmlinux
So overall with static, there is a reduction in kernel size. I will send V3
with declaring it as static.
Regards,
Biju
[https://www2.renesas.eu/media/email/unicef.jpg]
This Christmas, instead of sending out cards, Renesas Electronics Europe have
decided to support Unicef with a donation. For further details click
here<https://www.unicef.org/> to find out about the valuable work they do,
helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a
prosperous New Year.
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
[PATCH v2 0/5] Add more support to RZ/G1N
This patch series aims to add support for some more interfaces to RZ/G1N SoC/iwg20d based board (Display and QSPI). This patch series tested against renesas-dev. V1--> V2 * Add SPI NOR support : Incorporated Geert's review comment. * Add DU support : Removed LVDS definition from DU node. Biju Das (5): ARM: dts: iwg20d-q7-common: Move cmt/rwdt node out of RZ/G1M SOM ARM: dts: r8a7744-iwg20m: Add SPI NOR support ARM: dts: r8a7744: Add DU support ARM: dts: r8a7743: Remove LVDS encoder from du node ARM: dts: r8a7744: Fix sorting of vsp and msiof nodes arch/arm/boot/dts/iwg20d-q7-common.dtsi | 9 ++ arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 9 -- arch/arm/boot/dts/r8a7743.dtsi | 9 +- arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 26 ++ arch/arm/boot/dts/r8a7744.dtsi | 161 5 files changed, 121 insertions(+), 93 deletions(-) -- 2.7.4
[PATCH v2 4/5] ARM: dts: r8a7743: Remove LVDS encoder from du node
The internal LVDS encoder now has DT bindings separate from the DU.
So remove it from du node.
Fixes: c6a27fa41fab ("drm: rcar-du: Convert LVDS encoder code to bridge driver")
Signed-off-by: Biju Das
---
V1-->V2
* Removed LVDS encoder definition from DU node.
---
arch/arm/boot/dts/r8a7743.dtsi | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 3cc33f7..3ad1efc 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -1681,15 +1681,12 @@
du: display@feb0 {
compatible = "renesas,du-r8a7743";
- reg = <0 0xfeb0 0 0x4>,
- <0 0xfeb9 0 0x1c>;
- reg-names = "du", "lvds.0";
+ reg = <0 0xfeb0 0 0x4>;
interrupts = ,
;
clocks = < CPG_MOD 724>,
-< CPG_MOD 723>,
-< CPG_MOD 726>;
- clock-names = "du.0", "du.1", "lvds.0";
+< CPG_MOD 723>;
+ clock-names = "du.0", "du.1";
status = "disabled";
ports {
--
2.7.4
[PATCH v2 3/5] ARM: dts: r8a7744: Add DU support
Add du node to r8a7744 SoC DT. Boards that want to enable the DU
need to specify the output topology.
Signed-off-by: Biju Das
---
V1-->V2
* Removed LVDS encoder definition from DU node.
---
arch/arm/boot/dts/r8a7744.dtsi | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 04148d6..6a51b16 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1645,8 +1645,14 @@
};
du: display@feb0 {
- reg = <0 0xfeb0 0 0x4>,
- <0 0xfeb9 0 0x1c>;
+ compatible = "renesas,du-r8a7744";
+ reg = <0 0xfeb0 0 0x4>;
+ interrupts = ,
+;
+ clocks = < CPG_MOD 724>,
+< CPG_MOD 723>;
+ clock-names = "du.0", "du.1";
+ status = "disabled";
ports {
#address-cells = <1>;
@@ -1663,7 +1669,6 @@
};
};
};
- /* placeholder */
};
prr: chipid@ff44 {
--
2.7.4
[PATCH v2 5/5] ARM: dts: r8a7744: Fix sorting of vsp and msiof nodes
This patch fixes sorting of vsp and msiof nodes.
Signed-off-by: Biju Das
---
V1-->V2
* No change. It is a new patch.
---
arch/arm/boot/dts/r8a7744.dtsi | 150 -
1 file changed, 75 insertions(+), 75 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 6a51b16..83804aa 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -998,6 +998,54 @@
status = "disabled";
};
+ msiof0: spi@e6e2 {
+ compatible = "renesas,msiof-r8a7744",
+"renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e2 0 0x0064>;
+ interrupts = ;
+ clocks = < CPG_MOD 000>;
+ dmas = < 0x51>, < 0x52>,
+ < 0x51>, < 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = < 000>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6e1 {
+ compatible = "renesas,msiof-r8a7744",
+"renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e1 0 0x0064>;
+ interrupts = ;
+ clocks = < CPG_MOD 208>;
+ dmas = < 0x55>, < 0x56>,
+ < 0x55>, < 0x56>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = < 208>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6e0 {
+ compatible = "renesas,msiof-r8a7744",
+"renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e0 0 0x0064>;
+ interrupts = ;
+ clocks = < CPG_MOD 205>;
+ dmas = < 0x41>, < 0x42>,
+ < 0x41>, < 0x42>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = < 205>;
+ status = "disabled";
+ };
+
pwm0: pwm@e6e3 {
compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
reg = <0 0xe6e3 0 0x8>;
@@ -1068,54 +1116,6 @@
status = "disabled";
};
- msiof0: spi@e6e2 {
- compatible = "renesas,msiof-r8a7744",
-"renesas,rcar-gen2-msiof";
- reg = <0 0xe6e2 0 0x0064>;
- interrupts = ;
- clocks = < CPG_MOD 000>;
- dmas = < 0x51>, < 0x52>,
- < 0x51>, < 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = < R8A7744_PD_ALWAYS_ON>;
- #address-cells = <1>;
- #size-cells = <0>;
- resets = < 000>;
- status = "disabled";
- };
-
- msiof1: spi@e6e1 {
- compatible = "renesas,msiof-r8a7744",
-"renesas,rcar-gen2-msiof";
- reg = <0 0xe6e1 0 0x0064>;
- interrupts = ;
- clocks = < CPG_MOD 208>;
- dmas = < 0x55>, < 0x56>,
- < 0x55>, < 0x56>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = < R8A7744_PD_ALWAYS_ON>;
- #address-cells = <1>;
- #size-cells = <0>
[PATCH v2 2/5] ARM: dts: r8a7744-iwg20m: Add SPI NOR support
Add support for the SPI NOR device used to boot up the system
to the iWave RZ/G1N Qseven System On Module DT.
Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* Removed compatible string "sst,sst25vf016b".
---
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
index 503583e..82ee3c1 100644
--- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
@@ -36,6 +36,11 @@
function = "mmc";
};
+ qspi_pins: qspi {
+ groups = "qspi_ctrl", "qspi_data2";
+ function = "qspi";
+ };
+
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
@@ -53,6 +58,27 @@
status = "okay";
};
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ /* WARNING - This device contains the bootloader. Handle with care. */
+ flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <5000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+ };
+};
+
{
pinctrl-0 = <_pins>;
pinctrl-names = "default";
--
2.7.4
[PATCH v2 00/21] Add support for iWave G20D-Q7 board based on RZ/G1N
This patch series aims to add support for iWave G20D-Q7 board based on RZ/G1N.
This patch series is tested against renesas-dev
V1-->V2
* r8a7744: Initial SoC device tree: Fixed pfc register size,
GIC_CPU_MASK_SIMPLE in gic/timer nodes
* r8a7744: Add SMP support: Fixed GIC_CPU_MASK_SIMPLE in gic/timer nodes
* r8a7744: Add I2C and IIC support: Dropped i2c aliases, removed generic
compatible from iic3.
* r8a7744-iwg20m: Enable SDHI0 controller: Fixed subject line
* r8a7744: Add RWDT node: Moved rwdt node just before gpio.
Biju Das (21):
ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM
ARM: dts: r8a7744: Initial SoC device tree
ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based
on RZ/G1N
ARM: dts: r8a7744: Add SYS-DMAC support
ARM: dts: r8a7744: Add GPIO support
ARM: dts: r8a7744: Add Ethernet AVB support
ARM: dts: r8a7744: Add SMP support
ARM: dts: r8a7744: Add [H]SCIF{A|B} support
ARM: dts: r8a7744: Add I2C and IIC support
ARM: dts: r8a7744: Add SDHI nodes
ARM: dts: r8a7744: Add MMC node
ARM: dts: r8a7744-iwg20m: Add eMMC support
ARM: dts: r8a7744-iwg20m: Enable SDHI0 controller
ARM: dts: r8a7744: USB 2.0 host support
ARM: dts: r8a7744: Add USB-DMAC and HSUSB device nodes
ARM: dts: r8a7744: Add RWDT node
ARM: dts: r8a7744: Add audio support
ARM: dts: r8a7744: Add CAN support
ARM: dts: r8a7744: Add IRQC support
ARM: dts: r8a7744: Add thermal device to DT
ARM: dts: r8a7744: Add CMT SoC specific support
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/r8a7744-iwg20d-q7.dts | 15 +
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 64 ++
arch/arm/boot/dts/r8a7744.dtsi | 1431 +++
4 files changed, 1511 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20m.dtsi
create mode 100644 arch/arm/boot/dts/r8a7744.dtsi
--
2.7.4
[PATCH v2 19/21] ARM: dts: r8a7744: Add IRQC support
Describe the IRQC interrupt controller in the r8a7744 device tree.
Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No Change
---
arch/arm/boot/dts/r8a7744.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 87187f2..91096c3 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -297,6 +297,26 @@
#power-domain-cells = <1>;
};
+ irqc: interrupt-controller@e61c {
+ compatible = "renesas,irqc-r8a7744", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c 0 0x200>;
+ interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+ clocks = < CPG_MOD 407>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 407>;
+ };
+
icram0: sram@e63a {
compatible = "mmio-sram";
reg = <0 0xe63a 0 0x12000>;
--
2.7.4
[PATCH v2 20/21] ARM: dts: r8a7744: Add thermal device to DT
This patch instantiates the thermal sensor module with thermal-zone
support.
Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No Change
---
arch/arm/boot/dts/r8a7744.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 91096c3..937c800 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -317,6 +317,17 @@
resets = < 407>;
};
+ thermal: thermal@e61f {
+ compatible = "renesas,thermal-r8a7744",
+"renesas,rcar-gen2-thermal";
+ reg = <0 0xe61f 0 0x10>, <0 0xe61f0100 0 0x38>;
+ interrupts = ;
+ clocks = < CPG_MOD 522>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 522>;
+ #thermal-sensor-cells = <0>;
+ };
+
icram0: sram@e63a {
compatible = "mmio-sram";
reg = <0 0xe63a 0 0x12000>;
@@ -1351,6 +1362,26 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <>;
+
+ trips {
+ cpu-crit {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
--
2.7.4
[PATCH v2 21/21] ARM: dts: r8a7744: Add CMT SoC specific support
Add CMT[01] support to SoC DT.
Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No Change
---
arch/arm/boot/dts/r8a7744.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 937c800..8f43fb4 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1360,6 +1360,38 @@
compatible = "renesas,prr";
reg = <0 0xff44 0 4>;
};
+
+ cmt0: timer@ffca {
+ compatible = "renesas,r8a7744-cmt0",
+"renesas,rcar-gen2-cmt0";
+ reg = <0 0xffca 0 0x1004>;
+ interrupts = ,
+;
+ clocks = < CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 124>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e613 {
+ compatible = "renesas,r8a7744-cmt1",
+"renesas,rcar-gen2-cmt1";
+ reg = <0 0xe613 0 0x1004>;
+ interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+ clocks = < CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 329>;
+ status = "disabled";
+ };
};
thermal-zones {
--
2.7.4
[PATCH v2 15/21] ARM: dts: r8a7744: Add USB-DMAC and HSUSB device nodes
Add usb dmac and hsusb device nodes on RZ/G1N SoC dtsi.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No Change
---
arch/arm/boot/dts/r8a7744.dtsi | 42 +-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 1d4cb5e..cf05ce0 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -449,8 +449,20 @@
};
hsusb: usb@e659 {
+ compatible = "renesas,usbhs-r8a7744",
+"renesas,rcar-gen2-usbhs";
reg = <0 0xe659 0 0x100>;
- /* placeholder */
+ interrupts = ;
+ clocks = < CPG_MOD 704>;
+ dmas = <_dmac0 0>, <_dmac0 1>,
+ <_dmac1 0>, <_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 704>;
+ renesas,buswait = <4>;
+ phys = < 1>;
+ phy-names = "usb";
+ status = "disabled";
};
usbphy: usb-phy@e6590100 {
@@ -475,6 +487,34 @@
};
};
+ usb_dmac0: dma-controller@e65a {
+ compatible = "renesas,r8a7744-usb-dmac",
+"renesas,usb-dmac";
+ reg = <0 0xe65a 0 0x100>;
+ interrupts = ;
+ interrupt-names = "ch0", "ch1";
+ clocks = < CPG_MOD 330>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac1: dma-controller@e65b {
+ compatible = "renesas,r8a7744-usb-dmac",
+"renesas,usb-dmac";
+ reg = <0 0xe65b 0 0x100>;
+ interrupts = ;
+ interrupt-names = "ch0", "ch1";
+ clocks = < CPG_MOD 331>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
dmac0: dma-controller@e670 {
compatible = "renesas,dmac-r8a7744",
"renesas,rcar-dmac";
--
2.7.4
[PATCH v2 14/21] ARM: dts: r8a7744: USB 2.0 host support
Describe internal PCI bridge devices, USB phy device and
link PCI USB devices to USB phy.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No Change
---
arch/arm/boot/dts/r8a7744.dtsi | 77 +++---
1 file changed, 72 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 3f7674b..1d4cb5e 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -454,8 +454,25 @@
};
usbphy: usb-phy@e6590100 {
+ compatible = "renesas,usb-phy-r8a7744",
+"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
- /* placeholder */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < CPG_MOD 704>;
+ clock-names = "usbhs";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 704>;
+ status = "disabled";
+
+ usb0: usb-channel@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+ usb2: usb-channel@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
};
dmac0: dma-controller@e670 {
@@ -847,23 +864,73 @@
};
pci0: pci@ee09 {
- reg = <0 0xee09 0 0xc00>;
+ compatible = "renesas,pci-r8a7744",
+"renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee09 0 0xc00>,
+ <0 0xee08 0 0x1100>;
+ interrupts = ;
+ clocks = < CPG_MOD 703>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 703>;
+ status = "disabled";
bus-range = <0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
- /* placeholder */
+ ranges = <0x0200 0 0xee08 0 0xee08 0
0x0001>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x 0 0 1 GIC_SPI 108
IRQ_TYPE_LEVEL_HIGH
+0x0800 0 0 1 GIC_SPI 108
IRQ_TYPE_LEVEL_HIGH
+0x1000 0 0 2 GIC_SPI 108
IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = < 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = < 0>;
+ phy-names = "usb";
+ };
};
pci1: pci@ee0d {
- reg = <0 0xee0d 0 0xc00>;
+ compatible = "renesas,pci-r8a7744",
+"renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee0d 0 0xc00>,
+ <0 0xee0c 0 0x1100>;
+ interrupts = ;
+ clocks = < CPG_MOD 703>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 703>;
+ status = "disabled";
bus-range = <1 1>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
- /* placeholder */
+ ranges = <0x0200 0 0xee0c 0 0xee0c 0
0x0001>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x 0 0 1 GIC_SPI 113
IRQ_TYPE_LEVEL_HIGH
+0x0800 0 0 1 GIC_SPI 113
IRQ_TYPE_LEVEL_HIGH
+0x1000 0 0 2 GIC_SPI 113
IRQ_TYPE_LEVEL_HIGH>;
+
+
[PATCH v2 16/21] ARM: dts: r8a7744: Add RWDT node
Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
RZ/G1N (r8a7744) SoC.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* Moved rwdt node before gpio.
---
arch/arm/boot/dts/r8a7744.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index cf05ce0..fabc7f9 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -135,6 +135,16 @@
#size-cells = <2>;
ranges;
+ rwdt: watchdog@e602 {
+ compatible = "renesas,r8a7744-wdt",
+"renesas,rcar-gen2-wdt";
+ reg = <0 0xe602 0 0x0c>;
+ clocks = < CPG_MOD 402>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 402>;
+ status = "disabled";
+ };
+
gpio0: gpio@e605 {
compatible = "renesas,gpio-r8a7744",
"renesas,rcar-gen2-gpio";
--
2.7.4
[PATCH v2 17/21] ARM: dts: r8a7744: Add audio support
Add sound support for the RZ/G1N SoC (a.k.a. R8A7744).
This work is based on similar work done on the R8A7743 SoC.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No Change
---
arch/arm/boot/dts/r8a7744.dtsi | 243 +++--
1 file changed, 235 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index fabc7f9..cb6dfb5 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -894,23 +894,250 @@
};
rcar_sound: sound@ec50 {
- reg = <0 0xec50 0 0x1000>;
+ /*
+* #sound-dai-cells is required
+*
+* Single DAI : #sound-dai-cells = <0>;
<_sound>;
+* Multi DAI : #sound-dai-cells = <1>;
<_sound N>;
+*/
+ compatible = "renesas,rcar_sound-r8a7744",
+"renesas,rcar_sound-gen2";
+ reg = <0 0xec50 0 0x1000>, /* SCU */
+ <0 0xec5a 0 0x100>, /* ADG */
+ <0 0xec54 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec74 0 0x200>; /* Audio DMAC peri peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = < CPG_MOD 1005>,
+< CPG_MOD 1006>, < CPG_MOD 1007>,
+< CPG_MOD 1008>, < CPG_MOD 1009>,
+< CPG_MOD 1010>, < CPG_MOD 1011>,
+< CPG_MOD 1012>, < CPG_MOD 1013>,
+< CPG_MOD 1014>, < CPG_MOD 1015>,
+< CPG_MOD 1022>, < CPG_MOD 1023>,
+< CPG_MOD 1024>, < CPG_MOD 1025>,
+< CPG_MOD 1026>, < CPG_MOD 1027>,
+< CPG_MOD 1028>, < CPG_MOD 1029>,
+< CPG_MOD 1030>, < CPG_MOD 1031>,
+< CPG_MOD 1021>, < CPG_MOD 1020>,
+< CPG_MOD 1021>, < CPG_MOD 1020>,
+< CPG_MOD 1019>, < CPG_MOD 1018>,
+<_clk_a>, <_clk_b>, <_clk_c>,
+< CPG_CORE R8A7744_CLK_M2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1",
"ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
"src.5",
+ "src.4", "src.3", "src.2", "src.1",
"src.0",
+ "ctu.0", "ctu.1",
+ "mix.0", "mix.1",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 1005>,
+< 1006>, < 1007>, < 1008>, <
1009>,
+< 1010>, < 1011>, < 1012>, <
1013>,
+< 1014>, < 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1",
"ssi.0";
+ status = "disabled";
rcar_sound,dvc {
- dvc0: dvc-0 {};
- dvc1: dvc-1 {};
+ dvc0: dvc-0 {
+ dmas = < 0xbc>;
+ dma-names = "tx";
+
[PATCH v2 18/21] ARM: dts: r8a7744: Add CAN support
Add the definitions for can0 and can1 to the r8a7744 SoC dtsi.
Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No Change
---
arch/arm/boot/dts/r8a7744.dtsi | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index cb6dfb5..87187f2 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -884,13 +884,31 @@
};
can0: can@e6e8 {
+ compatible = "renesas,can-r8a7744",
+"renesas,rcar-gen2-can";
reg = <0 0xe6e8 0 0x1000>;
- /* placeholder */
+ interrupts = ;
+ clocks = < CPG_MOD 916>,
+< CPG_CORE R8A7744_CLK_RCAN>,
+<_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 916>;
+ status = "disabled";
};
can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7744",
+"renesas,rcar-gen2-can";
reg = <0 0xe6e88000 0 0x1000>;
- /* placeholder */
+ interrupts = ;
+ clocks = < CPG_MOD 915>,
+< CPG_CORE R8A7744_CLK_RCAN>,
+<_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 915>;
+ status = "disabled";
};
rcar_sound: sound@ec50 {
--
2.7.4
[PATCH v2 11/21] ARM: dts: r8a7744: Add MMC node
Add MMC node to the DT of the r8a7744 SoC.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No Change
---
arch/arm/boot/dts/r8a7744.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 97b417c..3f7674b 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -911,6 +911,22 @@
status = "disabled";
};
+ mmcif0: mmc@ee20 {
+ compatible = "renesas,mmcif-r8a7744",
+"renesas,sh-mmcif";
+ reg = <0 0xee20 0 0x80>;
+ interrupts = ;
+ clocks = < CPG_MOD 315>;
+ dmas = < 0xd1>, < 0xd2>,
+ < 0xd1>, < 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 315>;
+ reg-io-width = <4>;
+ max-frequency = <9750>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.4
[PATCH v2 09/21] ARM: dts: r8a7744: Add I2C and IIC support
Add the I2C[0-5] and IIC[0,1,3] devices nodes to the R8A7744 device tree.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* Dropped i2c aliases, removed generic compatible from iic3.
---
arch/arm/boot/dts/r8a7744.dtsi | 127 -
1 file changed, 125 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 1fe694d..57e0be3 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -310,19 +310,142 @@
reg = <0 0xe630 0 0x4>;
};
+ /* The memory map in the User's Manual maps the cores to
+* bus numbers
+*/
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 931>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 931>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 930>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 930>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
i2c2: i2c@e653 {
#address-cells = <1>;
#size-cells = <0>;
+ compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
reg = <0 0xe653 0 0x40>;
- /* placeholder */
+ interrupts = ;
+ clocks = < CPG_MOD 929>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e654 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
+ reg = <0 0xe654 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 928>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 928>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e652 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
+ reg = <0 0xe652 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 927>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 927>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
};
i2c5: i2c@e6528000 {
/* doesn't need pinmux */
#address-cells = <1>;
#size-cells = <0>;
+ compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
reg = <0 0xe6528000 0 0x40>;
- /* placeholder */
+ interrupts = ;
+ clocks = < CPG_MOD 925>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 925>;
+ i2c-scl-internal-delay-ns = <110
[PATCH v2 08/21] ARM: dts: r8a7744: Add [H]SCIF{A|B} support
Describe [H]SCIF{|A|B} ports in the R8A7744 device tree.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No Change
---
arch/arm/boot/dts/r8a7744.dtsi | 257 -
1 file changed, 254 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 2cb6d8f..1fe694d 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -414,9 +414,139 @@
status = "disabled";
};
+ scifa0: serial@e6c4 {
+ compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c4 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = < 0x21>, < 0x22>,
+ < 0x21>, < 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 204>;
+ status = "disabled";
+ };
+
+ scifa1: serial@e6c5 {
+ compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c5 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = < 0x25>, < 0x26>,
+ < 0x25>, < 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 203>;
+ status = "disabled";
+ };
+
+ scifa2: serial@e6c6 {
+ compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c6 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = < 0x27>, < 0x28>,
+ < 0x27>, < 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 202>;
+ status = "disabled";
+ };
+
+ scifa3: serial@e6c7 {
+ compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c7 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 1106>;
+ clock-names = "fck";
+ dmas = < 0x1b>, < 0x1c>,
+ < 0x1b>, < 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 1106>;
+ status = "disabled";
+ };
+
+ scifa4: serial@e6c78000 {
+ compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c78000 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 1107>;
+ clock-names = "fck";
+ dmas = < 0x1f>, < 0x20>,
+ < 0x1f>, < 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 1107>;
+ status = "disabled";
+ };
+
+ scifa5: serial@e6c8 {
+ compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa&q
[PATCH v2 10/21] ARM: dts: r8a7744: Add SDHI nodes
Add SDHI nodes to the DT of the r8a7744 SoC.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No Change
---
arch/arm/boot/dts/r8a7744.dtsi | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 57e0be3..97b417c 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -866,14 +866,49 @@
/* placeholder */
};
+ sdhi0: sd@ee10 {
+ compatible = "renesas,sdhi-r8a7744",
+"renesas,rcar-gen2-sdhi";
+ reg = <0 0xee10 0 0x328>;
+ interrupts = ;
+ clocks = < CPG_MOD 314>;
+ dmas = < 0xcd>, < 0xce>,
+ < 0xcd>, < 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <19500>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 314>;
+ status = "disabled";
+ };
+
sdhi1: sd@ee14 {
+ compatible = "renesas,sdhi-r8a7744",
+"renesas,rcar-gen2-sdhi";
reg = <0 0xee14 0 0x100>;
- /* placeholder */
+ interrupts = ;
+ clocks = < CPG_MOD 312>;
+ dmas = < 0xc1>, < 0xc2>,
+ < 0xc1>, < 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <9750>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 312>;
+ status = "disabled";
};
sdhi2: sd@ee16 {
+ compatible = "renesas,sdhi-r8a7744",
+"renesas,rcar-gen2-sdhi";
reg = <0 0xee16 0 0x100>;
- /* placeholder */
+ interrupts = ;
+ clocks = < CPG_MOD 311>;
+ dmas = < 0xd3>, < 0xd4>,
+ < 0xd3>, < 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <9750>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 311>;
+ status = "disabled";
};
gic: interrupt-controller@f1001000 {
--
2.7.4
[PATCH v2 13/21] ARM: dts: r8a7744-iwg20m: Enable SDHI0 controller
Enable the SDHI0 controller on iWave RZ/G1N Qseven System On Module.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* Fixed subject line SDHI10 to SDHI0
---
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
index 1e57b1f..503583e 100644
--- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
@@ -35,6 +35,12 @@
groups = "mmc_data8_b", "mmc_ctrl";
function = "mmc";
};
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
};
{
@@ -46,3 +52,13 @@
non-removable;
status = "okay";
};
+
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <_3p3v>;
+ vqmmc-supply = <_3p3v>;
+ cd-gpios = < 11 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
--
2.7.4
[PATCH v2 07/21] ARM: dts: r8a7744: Add SMP support
Add DT node for the Advanced Power Management Unit (APMU), add the
second CPU core, and use "renesas,apmu" as "enable-method".
Also add cpu1 phandle node to the PMU interrupt-affinity property.
Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* Fixed GIC_CPU_MASK_SIMPLE in gic/timer nodes
---
arch/arm/boot/dts/r8a7744.dtsi | 38 --
1 file changed, 32 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 4d4ddba..2cb6d8f 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -49,6 +49,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -69,6 +70,25 @@
< 375000 100>;
};
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <15>;
+ clocks = < CPG_CORE R8A7744_CLK_Z>;
+ clock-latency = <30>; /* 300 us */
+ power-domains = < R8A7744_PD_CA15_CPU1>;
+ next-level-cache = <_CA15>;
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <150 100>,
+ <1312500 100>,
+ <1125000 100>,
+ < 937500 100>,
+ < 75 100>,
+ < 375000 100>;
+ };
+
L2_CA15: cache-controller-0 {
compatible = "cache";
cache-unified;
@@ -96,7 +116,7 @@
compatible = "arm,cortex-a15-pmu";
interrupts-extended = < GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
< GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <>;
+ interrupt-affinity = <>, <>;
};
/* External SCIF clock */
@@ -250,6 +270,12 @@
#reset-cells = <1>;
};
+ apmu@e6152000 {
+ compatible = "renesas,r8a7744-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = < >;
+ };
+
rst: reset-controller@e616 {
compatible = "renesas,r8a7744-rst";
reg = <0 0xe616 0 0x100>;
@@ -483,7 +509,7 @@
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
- interrupts = ;
+ interrupts = ;
clocks = < CPG_MOD 408>;
clock-names = "clk";
power-domains = < R8A7744_PD_ALWAYS_ON>;
@@ -520,10 +546,10 @@
timer {
compatible = "arm,armv7-timer";
- interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1)
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1)
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1)
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1)
| IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clock - can be overridden by the board */
--
2.7.4
[PATCH v2 06/21] ARM: dts: r8a7744: Add Ethernet AVB support
Add Ethernet AVB support for R8A7744 SoC.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No Change
---
arch/arm/boot/dts/r8a7744.dtsi | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index ea1a782..4d4ddba 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -376,10 +376,16 @@
};
avb: ethernet@e680 {
+ compatible = "renesas,etheravb-r8a7744",
+"renesas,etheravb-rcar-gen2";
reg = <0 0xe680 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = ;
+ clocks = < CPG_MOD 812>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 812>;
#address-cells = <1>;
#size-cells = <0>;
- /* placeholder */
+ status = "disabled";
};
scifb1: serial@e6c3 {
--
2.7.4
[PATCH v2 04/21] ARM: dts: r8a7744: Add SYS-DMAC support
Describe SYS-DMAC0/1 in the R8A7744 device tree.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No change
---
arch/arm/boot/dts/r8a7744.dtsi | 66 ++
1 file changed, 66 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index f4d0abd..732c5d7 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -215,6 +215,72 @@
/* placeholder */
};
+ dmac0: dma-controller@e670 {
+ compatible = "renesas,dmac-r8a7744",
+"renesas,rcar-dmac";
+ reg = <0 0xe670 0 0x2>;
+ interrupts = ;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = < CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e672 {
+ compatible = "renesas,dmac-r8a7744",
+"renesas,rcar-dmac";
+ reg = <0 0xe672 0 0x2>;
+ interrupts = ;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = < CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
avb: ethernet@e680 {
reg = <0 0xe680 0 0x800>, <0 0xee0e8000 0 0x4000>;
#address-cells = <1>;
--
2.7.4
[PATCH v2 05/21] ARM: dts: r8a7744: Add GPIO support
Describe GPIO blocks in the R8A7744 device tree.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No Change
---
arch/arm/boot/dts/r8a7744.dtsi | 102 +++--
1 file changed, 98 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 732c5d7..ea1a782 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -116,29 +116,123 @@
ranges;
gpio0: gpio@e605 {
+ compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
reg = <0 0xe605 0 0x50>;
+ interrupts = ;
#gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 0 32>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = < CPG_MOD 912>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 912>;
};
gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
reg = <0 0xe6051000 0 0x50>;
+ interrupts = ;
#gpio-cells = <2>;
- /* placeholder */
+ gpio-controller;
+ gpio-ranges = < 0 32 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 911>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 911>;
};
gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
reg = <0 0xe6052000 0 0x50>;
+ interrupts = ;
#gpio-cells = <2>;
- /* placeholder */
+ gpio-controller;
+ gpio-ranges = < 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 910>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 909>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 908>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 160 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 907>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 907>;
};
[PATCH v2 12/21] ARM: dts: r8a7744-iwg20m: Add eMMC support
Add eMMC support for iWave RZ/G1N Qseven System On Module.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No Change
---
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
index 6166ae0..1e57b1f 100644
--- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
@@ -29,3 +29,20 @@
_clk {
clock-frequency = <2000>;
};
+
+ {
+ mmcif0_pins: mmc {
+ groups = "mmc_data8_b", "mmc_ctrl";
+ function = "mmc";
+ };
+};
+
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <_3p3v>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
--
2.7.4
[PATCH v2 02/21] ARM: dts: r8a7744: Initial SoC device tree
Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders
to avoid compilation error with the common platform code.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* Fixed pfc register size, GIC_CPU_MASK_SIMPLE in gic/timer nodes
---
arch/arm/boot/dts/r8a7744.dtsi | 369 +
1 file changed, 369 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7744.dtsi
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
new file mode 100644
index 000..f4d0abd
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a7744 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "renesas,r8a7744";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /*
+* The external audio clocks are configured as 0 Hz fixed frequency
+* clocks by default.
+* Boards that provide audio clocks should override them.
+*/
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <15>;
+ clocks = < CPG_CORE R8A7744_CLK_Z>;
+ clock-latency = <30>; /* 300 us */
+ power-domains = < R8A7744_PD_CA15_CPU0>;
+ next-level-cache = <_CA15>;
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <150 100>,
+ <1312500 100>,
+ <1125000 100>,
+ < 937500 100>,
+ < 75 100>,
+ < 375000 100>;
+ };
+
+ L2_CA15: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ power-domains = < R8A7744_PD_CA15_SCU>;
+ };
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts-extended = < GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@e605 {
+ reg = <0 0xe605 0 0x50>;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
[PATCH v2 01/21] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM
Add support for iWave RZ/G1N Qseven System On Module.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No change
---
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 31 +++
1 file changed, 31 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20m.dtsi
diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
new file mode 100644
index 000..6166ae0
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave RZ/G1N Qseven SOM
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include "r8a7744.dtsi"
+#include
+
+/ {
+ compatible = "iwave,g20m", "renesas,r8a7744";
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x4000>;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+_clk {
+ clock-frequency = <2000>;
+};
--
2.7.4
[PATCH v2 03/21] ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1N
Add support for iWave RainboW-G20D-Qseven board based on RZ/G1N.
Signed-off-by: Biju Das
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No change
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r8a7744-iwg20d-q7.dts | 15 +++
2 files changed, 16 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b0e966d..aba5a25 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -829,6 +829,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7743-iwg20d-q7.dtb \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \
+ r8a7744-iwg20d-q7.dtb \
r8a7745-iwg22d-sodimm.dtb \
r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
r8a7745-sk-rzg1e.dtb \
diff --git a/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
b/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
new file mode 100644
index 000..1fdac52
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave-RZ/G1N Qseven board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a7744-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"
+
+/ {
+ model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1N";
+ compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744";
+};
--
2.7.4
RE: [PATCH 19/22] ARM: dts: r8a7744-iwg20m: Add SPI NOR support
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 19/22] ARM: dts: r8a7744-iwg20m: Add SPI NOR support
>
> Hi Biju,
>
> On Fri, Nov 30, 2018 at 11:34 AM Biju Das wrote:
> > > Subject: Re: [PATCH 19/22] ARM: dts: r8a7744-iwg20m: Add SPI NOR
> > > support On Tue, Nov 27, 2018 at 1:05 PM Biju Das
> wrote:
> > > > Add support for the SPI NOR device used to boot up the system to
> > > > the iWave RZ/G1N Qseven System On Module DT.
> > > >
> > > > Signed-off-by: Biju Das
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
> > > > +++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
> > >
> > > > @@ -53,6 +58,27 @@
> > > > status = "okay";
> > > > };
> > > >
> > > > + {
> > > > + pinctrl-0 = <_pins>;
> > > > + pinctrl-names = "default";
> > > > +
> > > > + status = "okay";
> > > > +
> > > > + /* WARNING - This device contains the bootloader. Handle with
> care.
> > > */
> > > > + flash: flash@0 {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + compatible = "sst,sst25vf016b", "jedec,spi-nor";
> > >
> > > According to the schematics, this is an ISSI IS25LP016D?
> > > ISSI was acquired by GigaDevice, according to Wikipedia.
> > > While SST is now MicroChip.
> >
> > As per the schematic and BoM, it is.
> > IC FLASH 16MBIT 50MHZ 8SOIC SST25VF016B-50-4I-S2AF Microchip
> > Technology 1 U1
>
> Oh, this seems to differ for different revisions of the schematics.
> R5.1 has the ISSI part, R3.4 has the SST part.
>
> Due to "jedec,spi-nor", it will auto-detect, but IIRC, the driver will warn
> if the
> compatible doesn't match the detected part, which thus may happen for
> some boards.
OK. Will remove "sst" part for the compatible string.
> > > > + reg = <0>;
> > > > + spi-max-frequency = <5000>;
> > > > + spi-tx-bus-width = <1>;
> > > > + spi-rx-bus-width = <1>;
> > >
> > > <1> is the default, but it's indeed good to make this explicit, as
> > > this is a QSPI device with 2 unwired data pins.
> > > However, as the device seems to support dual transfers, and dual
> > > mode uses the standard MOSI/MISO pins, you should use <2> for both.
> > > The RSPI driver supports this.
> > >
> > > The same applies to the RZ/G1M version.
> >
> > SST25VF016B this doesn't support dual mode.
>
> OK.
>
> So some boards have a dual-capable part, others don't.
>
> I'm not 100% sure, but I think writing <2> will still work, as the driver
> won't
> use dual mode on the SST25VF016B part, due to lack of
> SPI_NOR_DUAL_READ in the entry in the spi-nor driver.
OK. Will check this.
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
RE: [PATCH 05/22] ARM: dts: r8a7744-iwg20m: Add eMMC support
Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH 05/22] ARM: dts: r8a7744-iwg20m: Add eMMC support > > On Tue, Nov 27, 2018 at 1:05 PM Biju Das wrote: > > Add eMMC support for iWave RZ/G1N Qseven System On Module. > > > > Signed-off-by: Biju Das > > Reviewed-by: Geert Uytterhoeven > > I assume the PCB is the same for RZ/G1M and RZ/G1N, so perhaps this can > be factored out in a common .dtsi file, like we did for Salvator-X(S)? SoM is different between RZ/G1M and RZ/G1N in terms of memory and PCie/SATA. The only common part in SoM is eMMC,SDHI0 and QSPI flash. So it doesn't make sense to factored it out. What do you think? Regards, Biju Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
RE: [PATCH 19/22] ARM: dts: r8a7744-iwg20m: Add SPI NOR support
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 19/22] ARM: dts: r8a7744-iwg20m: Add SPI NOR support
>
> Hi Biju,
>
> On Tue, Nov 27, 2018 at 1:05 PM Biju Das wrote:
> > Add support for the SPI NOR device used to boot up the system to the
> > iWave RZ/G1N Qseven System On Module DT.
> >
> > Signed-off-by: Biju Das
>
> Thanks for your patch!
>
> > --- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
> > +++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
>
> > @@ -53,6 +58,27 @@
> > status = "okay";
> > };
> >
> > + {
> > + pinctrl-0 = <_pins>;
> > + pinctrl-names = "default";
> > +
> > + status = "okay";
> > +
> > + /* WARNING - This device contains the bootloader. Handle with care.
> */
> > + flash: flash@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "sst,sst25vf016b", "jedec,spi-nor";
>
> According to the schematics, this is an ISSI IS25LP016D?
> ISSI was acquired by GigaDevice, according to Wikipedia.
> While SST is now MicroChip.
As per the schematic and BoM, it is.
IC FLASH 16MBIT 50MHZ 8SOIC SST25VF016B-50-4I-S2AF Microchip Technology 1 U1
I agree for RZ/G1C, it is ISSI IS25LP016D.
>
> > + reg = <0>;
> > + spi-max-frequency = <5000>;
> > + spi-tx-bus-width = <1>;
> > + spi-rx-bus-width = <1>;
>
> <1> is the default, but it's indeed good to make this explicit, as this is a
> QSPI
> device with 2 unwired data pins.
> However, as the device seems to support dual transfers, and dual mode uses
> the standard MOSI/MISO pins, you should use <2> for both.
> The RSPI driver supports this.
>
> The same applies to the RZ/G1M version.
SST25VF016B this doesn't support dual mode.
Please let me know are you ok with this findings.
> > + m25p,fast-read;
> > + spi-cpol;
> > + spi-cpha;
> > + };
> > +};
>
> Apart from that:
> Reviewed-by: Geert Uytterhoeven
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
RE: [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM
Hello Geert,
Thanks for the feedback.
> -Original Message-
> From: Geert Uytterhoeven
> Sent: 30 November 2018 09:45
> To: Biju Das
> Cc: Rob Herring ; Mark Rutland
> ; Simon Horman ; Magnus
> Damm ; Linux-Renesas s...@vger.kernel.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS ; Geert Uytterhoeven
> ; Chris Paterson
> ; Fabrizio Castro
>
> Subject: Re: [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N
> Qseven SOM
>
> Hi Biju,
>
> On Thu, Nov 22, 2018 at 10:22 AM Biju Das
> wrote:
> > Add support for iWave RZ/G1N Qseven System On Module.
> >
> > Signed-off-by: Biju Das
>
> Reviewed-by: Geert Uytterhoeven
>
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
> > @@ -0,0 +1,31 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree Source for the iWave RZ/G1N Qseven SOM
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > + */
> > +
> > +#include "r8a7744.dtsi"
> > +#include
> > +
> > +/ {
> > + compatible = "iwave,g20m", "renesas,r8a7744";
> > +
> > + memory@4000 {
> > + device_type = "memory";
> > + reg = <0 0x4000 0 0x4000>;
> > + };
>
> I could not verify the memory configuration, but I assume it's correct ;-)
Yes it is correct, 1GB memory populated on this board.
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
RE: [PATCH 11/22] ARM: dts: r8a7744: Add DU support
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 11/22] ARM: dts: r8a7744: Add DU support
>
> Hi Biju,
>
> On Tue, Nov 27, 2018 at 1:05 PM Biju Das wrote:
> > Add du node to r8a7744 SoC DT. Boards that want to enable the DU need
> > to specify the output topology.
> >
> > Signed-off-by: Biju Das
>
> Thanks for your patch!
>
> > --- a/arch/arm/boot/dts/r8a7744.dtsi
> > +++ b/arch/arm/boot/dts/r8a7744.dtsi
> > @@ -1300,8 +1300,17 @@
> > };
> >
> > du: display@feb0 {
> > + compatible = "renesas,du-r8a7744";
> > reg = <0 0xfeb0 0 0x4>,
> > <0 0xfeb9 0 0x1c>;
> > + reg-names = "du", "lvds.0";
>
> Please use the new DU/LVDS bindings, using a separate node for LVDS.
>
> BTW, I believe the display won't work with a recent tree, unless you've
> added a DT live patch drivers/gpu/drm/rcar-
> du/rcar_du_of_lvds_r8a7744.dts?
>
> The same is true for RZ/G1M.
So far we haven't enabled LVDS panel on board specific dtsi.
I have tested du with below renesas-dev kernel version
Linux version 4.20.0-rc4-00127-g5ad8ac8 (biju@be1yocto) (gcc version 7.2.1
20171011 (Linaro GCC 7.2-2017.11)) #56 SMP Fri Nov 30 08:03:21 GMT 2018
[1.942603] [drm] Device feb0.display probed
root@iwg20m:~# modetest -M rcar-du
Encoders:
id crtctypepossible crtcs possible clones
54 52 none0x0003 0x0001
Connectors:
id encoder status namesize (mm) modes encoders
55 54 connected HDMI-A-1520x320 27 54
modes:
name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot)
1920x1080 60 1920 1968 2000 2080 1080 1082 1087 138000 flags: phsync,
nvsync; type: preferred, driver
1920x1080 60 1920 2008 2052 2200 1080 1084 1089 1125 148500 flags: phsync,
pvsync; type: driver
1920x1080 60 1920 2008 2052 2200 1080 1084 1089 1125 148352 flags: phsync,
pvsync; type: driver
1280x1024 75 1280 1296 1440 1688 1024 1025 1028 1066 135000 flags: phsync,
pvsync; type: driver
1280x1024 60 1280 1328 1440 1688 1024 1025 1028 1066 108000 flags: phsync,
pvsync; type: driver
1152x864 75 1152 1216 1344 1600 864 865 868 900 108000 flags: phsync, pvsync;
type: driver
1280x720 60 1280 1390 1430 1650 720 725 730 750 74250 flags: phsync, pvsync;
type: driver
1280x720 60 1280 1390 1430 1650 720 725 730 750 74176 flags: phsync, pvsync;
type: driver
1280x720 50 1280 1720 1760 1980 720 725 730 750 74250 flags: phsync, pvsync;
type: driver
1024x768 75 1024 1040 1136 1312 768 769 772 800 78750 flags: phsync, pvsync;
type: driver
1024x768 70 1024 1048 1184 1328 768 771 777 806 75000 flags: nhsync, nvsync;
type: driver
1024x768 60 1024 1048 1184 1344 768 771 777 806 65000 flags: nhsync, nvsync;
type: driver
1080x607 60 1080 1120 1232 1384 607 608 611 629 52210 flags: nhsync, pvsync;
type:
832x624 75 832 864 928 1152 624 625 628 667 57284 flags: nhsync, nvsync;
type: driver
800x600 75 800 816 896 1056 600 601 604 625 49500 flags: phsync, pvsync;
type: driver
800x600 72 800 856 976 1040 600 637 643 666 5 flags: phsync, pvsync;
type: driver
800x600 60 800 840 968 1056 600 601 605 628 4 flags: phsync, pvsync;
type: driver
800x600 56 800 824 896 1024 600 601 603 625 36000 flags: phsync, pvsync;
type: driver
720x576 50 720 732 796 864 576 581 586 625 27000 flags: nhsync, nvsync; type:
driver
720x480 60 720 736 798 858 480 489 495 525 27027 flags: nhsync, nvsync; type:
driver
720x480 60 720 736 798 858 480 489 495 525 27000 flags: nhsync, nvsync; type:
driver
640x480 75 640 656 720 840 480 481 484 500 31500 flags: nhsync, nvsync; type:
driver
640x480 73 640 664 704 832 480 489 492 520 31500 flags: nhsync, nvsync; type:
driver
640x480 67 640 704 768 864 480 483 486 525 30240 flags: nhsync, nvsync; type:
driver
640x480 60 640 656 752 800 480 490 492 525 25200 flags: nhsync, nvsync; type:
driver
640x480 60 640 656 752 800 480 490 492 525 25175 flags: nhsync, nvsync; type:
driver
720x400 70 720 738 846 900 400 412 414 449 28320 flags: nhsync, pvsync; type:
driver
Also tested libdrm/kms tests. It works fine with 4.20.0-rc4 kernel on
renesas-dev branch.
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
RE: [PATCH 7/7] ARM: dts: r8a7744: Add SMP support
Hi Geert,
Thanks for the feedback.
> -Original Message-
> From: linux-renesas-soc-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Geert Uytterhoeven
> Sent: 30 November 2018 08:54
> To: Biju Das
> Cc: Rob Herring ; Mark Rutland
> ; Simon Horman ; Magnus
> Damm ; Linux-Renesas s...@vger.kernel.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS ; Geert Uytterhoeven
> ; Chris Paterson
> ; Fabrizio Castro
>
> Subject: Re: [PATCH 7/7] ARM: dts: r8a7744: Add SMP support
>
> On Thu, Nov 22, 2018 at 10:23 AM Biju Das
> wrote:
> > Add DT node for the Advanced Power Management Unit (APMU), add the
> > second CPU core, and use "renesas,apmu" as "enable-method".
> >
> > Also add cpu1 phandle node to the PMU interrupt-affinity property.
>
> Please change GIC_CPU_MASK_SIMPLE() from 1 to 2 in this patch, too.
OK, Will send V2 for this.
> > Signed-off-by: Biju Das
>
> Reviewed-by: Geert Uytterhoeven
>
> Gr{oetje,eeting}s,
>
> Geert
>
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
RE: [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree
Hi Geert,
Thanks for the feedback.
> -Original Message-
> From: linux-renesas-soc-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Geert Uytterhoeven
> Sent: 30 November 2018 08:49
> To: Biju Das
> Cc: Rob Herring ; Mark Rutland
> ; Simon Horman ; Magnus
> Damm ; Linux-Renesas s...@vger.kernel.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS ; Geert Uytterhoeven
> ; Chris Paterson
> ; Fabrizio Castro
>
> Subject: Re: [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree
>
> Hi Biju,
>
> On Thu, Nov 22, 2018 at 10:23 AM Biju Das
> wrote:
> > Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders to
> > avoid compilation error with the common platform code.
> >
> > Signed-off-by: Biju Das
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/r8a7744.dtsi
>
> > + soc {
>
> > + pfc: pin-controller@e606 {
> > + compatible = "renesas,pfc-r8a7744";
> > + reg = <0 0xe606 0 0x164>;
>
> Given the datasheet mentions (reserved) registers up to offset 0x24c, you
> may want to use 0x250 for the register block length.
>
Ok will send V2 for this.
I was in confusion to set the size as 0x164 or 0x250, since the Data sheet
mention that setting prohibited for 0x240-0x24c and is reserved.
> Reviewed-by: Geert Uytterhoeven
>
> Gr{oetje,eeting}s,
>
> Geert
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
RE: Issue with enabling VSP source on rcar gen2 koelsch board
Hi Laurent, Thanks for the feedback. > Subject: Re: Issue with enabling VSP source on rcar gen2 koelsch board > > Hi Biju, > > On Thursday, 29 November 2018 10:39:00 EET Biju Das wrote: > > > Subject: Re: Issue with enabling VSP source on rcar gen2 koelsch > > > board On Wednesday, 28 November 2018 15:20:58 EET Biju Das wrote: > > >> Hi all, > > >> > > >> On the past, I have tested vsp source on rcar gen2 koelsch board, > > >> using the patches series below(Apart from the below patch series, > > >> I have enabled "CONFIG_DRM_RCAR_VSP=y") > > >> https://git.linuxtv.org/pinchartl/media.git/log/?h=drm/du/panels > > >> > > >> 1) [HACK] ARM: shmobile: r8a7791: Link the VSP1 and DU > > >> 2) [HACK] v4l: vsp1: Disable UAPI for VSP1D > > >> 3) [HACK] drm: rcar-du: Enable VSP source support for R8A7791 > > >> > > >> But on the latest renesas-dev branch looks like it is broken > > > > > > That doesn't surprise me too much as I don't actively maintain that code. > > > > > > For my information, what are your use cases ? Do you think this > > > approach should be pursued and patches merged upstream ? The > amount > > > of work will be quite high though, given that it introduces a new > > > userspace API, we will have to publish an open-source implementation > > > in an X.org or Wayland driver. > > > > Basically as part of RZ-G1/M VSP upstreaming(Linux 4.15 kernel) > > ,previously I have executed the below test cases > > > > 1) vsp test suite:- based on the instruction present on > > "http://git.ideasonboard.com/renesas/vsp-tests.git; > > > > 2) vspd testing:- based on the instruction present on > > "https://git.linuxtv.org/pinchartl/media.git/log/?h=drm/du/panels; > > > > Both the test cases were working fine with 4.15 kernel. > > > > Now as part of RZ/G1N vsp upstreaming, I rebased to latest branch > > from renesas-dev , and executed the same test case > > > > Only test cases in vsp test suite is working. the vspd test case is broken. > > Could you please post the tests output and log ? Sorry for the confusion, Basically I am trying to do vsp -->du rendering based on the below patch 1) [HACK] ARM: shmobile: r8a7791: Link the VSP1 and DU 2) [HACK] v4l: vsp1: Disable UAPI for VSP1D 3) [HACK] drm: rcar-du: Enable VSP source support for R8A7791 You already mentioned that you are not maintaining this patches. It worked for me on Linux 4.15, where as it is broken with latest kernel. > > So I am wondering how do we expose the r-car gen2 SoC feature "VSPD" > > to the end user? > > Isn't the VSPD already exposed to the user as a V4L2 device on Gen2 ? Yes, But I am trying to do vsp-->du rendering on r-car gen2/rz/g1 board with the latest kernel. Regards, Biju Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
[PATCH v2 3/4] ARM: shmobile: Enable NXP pcf85363 rtc in shmobile_defconfig
The iWave RZ/G1C SBC supports RTC (NXP pcf85263). To increase hardware support enable the driver in the shmobile_defconfig multiplatform configuration. Signed-off-by: Biju Das --- V1-->V2 no change. --- arch/arm/configs/shmobile_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 9e5a5ad..fdac4e4 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -177,6 +177,7 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_RS5C372=y +CONFIG_RTC_DRV_PCF85363=y CONFIG_RTC_DRV_BQ32K=y CONFIG_RTC_DRV_S35390A=y CONFIG_RTC_DRV_RX8581=y -- 2.7.4
[PATCH v2 4/4] ARM: dts: iwg23s-sbc: Enable RTC
Enable NXP pcf85263 real time clock for the iWave SBC based on RZ/G1C.
Signed-off-by: Biju Das
---
V1-->V2 no change
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 40b7f98..77d1824 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -84,12 +84,30 @@
clock-frequency = <2000>;
};
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <40>;
+
+ rtc@51 {
+ compatible = "nxp,pcf85263";
+ reg = <0x51>;
+ };
+};
+
{
avb_pins: avb {
groups = "avb_mdio", "avb_gmii_tx_rx";
function = "avb";
};
+ i2c3_pins: i2c3 {
+ groups = "i2c3_c";
+ function = "i2c3";
+ };
+
mmc_pins_uhs: mmc_uhs {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
--
2.7.4
[PATCH v2 1/4] dt-bindings: rtc: pcf85363: Document pcf85263 real-time clock
The pcf85263 RTC is compatible with the pcf85363 RTC. The difference between the pcf85263 and pcf85363 RTC is that the latter has 64 bytes more RAM. This renders them incompatible from a DT point of view. Signed-off-by: Biju Das --- V1-->V2 Incorporated Simon's review comment. --- Documentation/devicetree/bindings/rtc/pcf85363.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/rtc/pcf85363.txt b/Documentation/devicetree/bindings/rtc/pcf85363.txt index 76fdabc..94adc1c 100644 --- a/Documentation/devicetree/bindings/rtc/pcf85363.txt +++ b/Documentation/devicetree/bindings/rtc/pcf85363.txt @@ -1,8 +1,8 @@ -NXP PCF85363 Real Time Clock +NXP PCF85263/PCF85363 Real Time Clock Required properties: -- compatible: Should contain "nxp,pcf85363". +- compatible: Should contain "nxp,pcf85263" or "nxp,pcf85363". - reg: I2C address for chip. Optional properties: -- 2.7.4
[PATCH v2 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
Add support for NXP pcf85263 real-time clock. pcf85263 rtc is compatible
with pcf85363,except that pcf85363 has additional 64 bytes of RAM.
1 byte of nvmem is supported and exposed in sysfs (# is the instance
number,starting with 0): /sys/bus/nvmem/devices/pcf85x63-#/nvmem
Signed-off-by: Biju Das
---
V1-->V2 Incorporated Alexandre and Geert's review comment.
---
drivers/rtc/rtc-pcf85363.c | 72 --
1 file changed, 57 insertions(+), 15 deletions(-)
diff --git a/drivers/rtc/rtc-pcf85363.c b/drivers/rtc/rtc-pcf85363.c
index c04a1ed..9c567c8 100644
--- a/drivers/rtc/rtc-pcf85363.c
+++ b/drivers/rtc/rtc-pcf85363.c
@@ -311,7 +311,30 @@ static int pcf85363_nvram_write(void *priv, unsigned int
offset, void *val,
val, bytes);
}
-static const struct regmap_config regmap_config = {
+static int pcf85x63_nvram_read(void *priv, unsigned int offset, void *val,
+ size_t bytes)
+{
+ struct pcf85363 *pcf85363 = priv;
+
+ return regmap_read(pcf85363->regmap, CTRL_RAMBYTE, val);
+}
+
+static int pcf85x63_nvram_write(void *priv, unsigned int offset, void *val,
+ size_t bytes)
+{
+ struct pcf85363 *pcf85363 = priv;
+
+ return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
+ *((unsigned int *)val));
+}
+
+static const struct regmap_config pcf_85263_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0x2f,
+};
+
+static const struct regmap_config pcf_85363_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x7f,
@@ -321,15 +344,25 @@ static int pcf85363_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct pcf85363 *pcf85363;
- struct nvmem_config nvmem_cfg = {
- .name = "pcf85363-",
- .word_size = 1,
- .stride = 1,
- .size = NVRAM_SIZE,
- .reg_read = pcf85363_nvram_read,
- .reg_write = pcf85363_nvram_write,
+ const struct regmap_config *regmap_config = _85363_regmap_config;
+ struct nvmem_config nvmem_cfg[] = {
+ {
+ .name = "pcf85x63-",
+ .word_size = 1,
+ .stride = 1,
+ .size = 1,
+ .reg_read = pcf85x63_nvram_read,
+ .reg_write = pcf85x63_nvram_write,
+ }, {
+ .name = "pcf85363-",
+ .word_size = 1,
+ .stride = 1,
+ .size = NVRAM_SIZE,
+ .reg_read = pcf85363_nvram_read,
+ .reg_write = pcf85363_nvram_write,
+ },
};
- int ret;
+ int ret, i, num_nvmem = 2;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -ENODEV;
@@ -339,7 +372,13 @@ static int pcf85363_probe(struct i2c_client *client,
if (!pcf85363)
return -ENOMEM;
- pcf85363->regmap = devm_regmap_init_i2c(client, _config);
+ if (of_device_get_match_data(>dev) ==
+ _85263_regmap_config) {
+ regmap_config = _85263_regmap_config;
+ num_nvmem = 1;
+ }
+
+ pcf85363->regmap = devm_regmap_init_i2c(client, regmap_config);
if (IS_ERR(pcf85363->regmap)) {
dev_err(>dev, "regmap allocation failed\n");
return PTR_ERR(pcf85363->regmap);
@@ -370,15 +409,18 @@ static int pcf85363_probe(struct i2c_client *client,
ret = rtc_register_device(pcf85363->rtc);
- nvmem_cfg.priv = pcf85363;
- rtc_nvmem_register(pcf85363->rtc, _cfg);
+ for (i = 0; i < num_nvmem ; i++) {
+ nvmem_cfg[i].priv = pcf85363;
+ rtc_nvmem_register(pcf85363->rtc, _cfg[i]);
+ }
return ret;
}
static const struct of_device_id dev_ids[] = {
- { .compatible = "nxp,pcf85363" },
- {}
+ { .compatible = "nxp,pcf85263", .data = _85263_regmap_config },
+ { .compatible = "nxp,pcf85363", .data = _85363_regmap_config },
+ { /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, dev_ids);
@@ -393,5 +435,5 @@ static struct i2c_driver pcf85363_driver = {
module_i2c_driver(pcf85363_driver);
MODULE_AUTHOR("Eric Nelson");
-MODULE_DESCRIPTION("pcf85363 I2C RTC driver");
+MODULE_DESCRIPTION("pcf85263/pcf85363 I2C RTC driver");
MODULE_LICENSE("GPL");
--
2.7.4
[PATCH v2 0/4] Add NXP pcf85263 real-time clock support
This patch set aims to add support for NXP pcf85263 real-time clock. pcf85263 rtc is compatible with pcf85363 rtc except that pcf85363 has 64 bytes additional RAM. 1 byte of nvmem is supported in pcf85263 and is exposed through sysfs. The details of pcf85363 and pcf85263 can be found in the below data sheets. https://www.nxp.com/docs/en/data-sheet/PCF85363A.pdf https://www.nxp.com/docs/en/data-sheet/PCF85263A.pdf This patch is tested against linux-next. V1-->V2 * Incorporated simon's review comment for binding patch. * Incorporated Geert and Alexandre's review comments. Biju Das (4): dt-bindings: rtc: pcf85363: Document pcf85263 real-time clock rtc: pcf85363: Add support for NXP pcf85263 rtc ARM: shmobile: Enable NXP pcf85363 rtc in shmobile_defconfig ARM: dts: iwg23s-sbc: Enable RTC Documentation/devicetree/bindings/rtc/pcf85363.txt | 4 +- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 18 ++ arch/arm/configs/shmobile_defconfig| 1 + drivers/rtc/rtc-pcf85363.c | 72 +- 4 files changed, 78 insertions(+), 17 deletions(-) -- 2.7.4
RE: [PATCH 02/22] ARM: dts: r8a7744: Add I2C and IIC support
Hi Simon & Geert,
Thanks for the feedback.
> -Original Message-
> From: linux-renesas-soc-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Simon Horman
> Sent: 29 November 2018 13:41
> To: Biju Das
> Cc: Rob Herring ; Mark Rutland
> ; Magnus Damm ;
> linux-renesas-soc@vger.kernel.org; devicet...@vger.kernel.org; Geert
> Uytterhoeven ; Chris Paterson
> ; Fabrizio Castro
>
> Subject: Re: [PATCH 02/22] ARM: dts: r8a7744: Add I2C and IIC support
>
> On Tue, Nov 27, 2018 at 11:56:15AM +, Biju Das wrote:
> > Add the I2C[0-5] and IIC[0,1,3] devices nodes to the R8A7744 device tree.
> >
> > Signed-off-by: Biju Das
> > ---
> > arch/arm/boot/dts/r8a7744.dtsi | 141
> > -
> > 1 file changed, 139 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/r8a7744.dtsi
> > b/arch/arm/boot/dts/r8a7744.dtsi index 165c701..6505ebd 100644
> > --- a/arch/arm/boot/dts/r8a7744.dtsi
> > +++ b/arch/arm/boot/dts/r8a7744.dtsi
> > @@ -15,6 +15,18 @@
> > #address-cells = <2>;
> > #size-cells = <2>;
> >
> > +aliases {
> > +i2c0 =
> > +i2c1 =
> > +i2c2 =
> > +i2c3 =
> > +i2c4 =
> > +i2c5 =
> > +i2c6 =
> > +i2c7 =
> > +i2c8 =
> > +};
> > +
>
> I believe we are moving away from adding aliases such as those above.
> Geert, can you comment on this?
I thought of removing this for the first instance. But for tools like
i2cdetect, it works on index.
Basically we need to work out index from device name, if we don't have aliases.
Regards,
Biju
> Other than that this patch looks good to me.
> Reviewed-by: Simon Horman
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
RE: [PATCH 7/7] ARM: dts: r8a7744: Add SMP support
Hi Simon,
Thanks for the feedback.
> -Original Message-
> From: linux-renesas-soc-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Simon Horman
> Sent: 29 November 2018 12:49
> To: Biju Das
> Cc: Rob Herring ; Mark Rutland
> ; Magnus Damm ;
> linux-renesas-soc@vger.kernel.org; devicet...@vger.kernel.org; Geert
> Uytterhoeven ; Chris Paterson
> ; Fabrizio Castro
>
> Subject: Re: [PATCH 7/7] ARM: dts: r8a7744: Add SMP support
>
> On Thu, Nov 22, 2018 at 09:14:35AM +, Biju Das wrote:
> > Add DT node for the Advanced Power Management Unit (APMU), add the
> > second CPU core, and use "renesas,apmu" as "enable-method".
> >
> > Also add cpu1 phandle node to the PMU interrupt-affinity property.
>
> Hi Biju,
>
> Could you comment on how well this has been tested with respect to CPU
> hotplug and suspend to RAM?
Please find the snippet from test script. It will details the tests related to
CPU hot plug and STR.
For cpu hotplug
-
SCRIPTS_DIRECTORY="$(cd "$(dirname "$0")"; pwd)"
source "${SCRIPTS_DIRECTORY}"/identity.sh
PROCESSORS=$(cat /test-data/apmu_t_001-rzg1${RZG1_VARIANT}.txt | grep -c
^processor)
for CURRENT_PROCESSOR in $(seq ${PROCESSORS}); do
echo "*** Testing CPU hotplug for processor ${CURRENT_PROCESSOR} ***"
echo 0 > /sys/devices/system/cpu/cpu$((CURRENT_PROCESSOR - 1))/online
CURRENT_PROCESSORS=$(cat /proc/cpuinfo | grep -c ^processor)
if [ ${CURRENT_PROCESSORS} -eq ${PROCESSORS} ]; then
echo "FAILED: Can't take processor ${CURRENT_PROCESSOR} offline"
exit 1
fi
echo 1 > /sys/devices/system/cpu/cpu$((CURRENT_PROCESSOR - 1))/online
CURRENT_PROCESSORS=$(cat /proc/cpuinfo | grep -c ^processor)
if [ ${CURRENT_PROCESSORS} -ne ${PROCESSORS} ]; then
echo "FAILED: Can't take processor ${CURRENT_PROCESSOR} online"
exit 1
fi
done
For STR
-
PROCESSORS=$(cat /test-data/apmu_t_001-rzg1${RZG1_VARIANT}.txt | grep -c
^processor)
PROCESSORS_COMBINATIONS=$(power_of_two ${PROCESSORS})
PROCESSORS_COMBINATIONS=$((PROCESSORS_COMBINATIONS - 1))
for CURRENT_PROCESSORS in $(seq ${PROCESSORS_COMBINATIONS}); do
echo "***"
echo "* Testing suspend-to-RAM with the following configuration *"
echo "***"
enable_all_cpus
disable_cpus ${CURRENT_PROCESSORS}
sleep 1
print_cpus_status
echo
echo
dmesg -c > /dev/null
echo enabled > /sys/class/tty/${DEBUG_CONSOLE}/power/wakeup
echo N > /sys/module/printk/parameters/console_suspend
echo mem > /sys/power/state
dmesg | grep -F "Restarting tasks ... done." > /dev/null
if [ $? -ne 0 ]; then
echo "FAILED: Something went wrong either when going to sleep or when waking up"
exit 1
fi
done
regards,
Biju
> > Signed-off-by: Biju Das
> > ---
> > arch/arm/boot/dts/r8a7744.dtsi | 28 +++-
> > 1 file changed, 27 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/boot/dts/r8a7744.dtsi
> > b/arch/arm/boot/dts/r8a7744.dtsi index 046ed94..79e75e7 100644
> > --- a/arch/arm/boot/dts/r8a7744.dtsi
> > +++ b/arch/arm/boot/dts/r8a7744.dtsi
> > @@ -49,6 +49,7 @@
> > cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > +enable-method = "renesas,apmu";
> >
> > cpu0: cpu@0 {
> > device_type = "cpu";
> > @@ -69,6 +70,25 @@
> > < 375000 100>;
> > };
> >
> > +cpu1: cpu@1 {
> > +device_type = "cpu";
> > +compatible = "arm,cortex-a15";
> > +reg = <1>;
> > +clock-frequency = <15>;
> > +clocks = < CPG_CORE R8A7744_CLK_Z>;
> > +clock-latency = <30>; /* 300 us */
> > +power-domains = < R8A7744_PD_CA15_CPU1>;
> > +next-level-cache = <_CA15>;
> > +
> > +/* kHz - uV - OPPs unknown yet */
> > +operating-points = <150 100>,
> > + <1312500 100>,
> > + <1125000 100>,
> > + < 937500 100>,
> > + < 75 100>,
> > + < 375000 100>;
> > +};
> > +
> > L2_CA15: cache-controller-0 {
> > compatible = "cache";
> > cache-unified;
> > @@ -96,7 +116,7 @@
> > compatible = "arm,cortex-a15-pmu";
> > interrupts-extended = < GIC_SPI 72
> IRQ_TYPE_LEVEL_HIGH>,
> >< GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> > -interrupt-affinity = <>;
> > +interrupt-affinity = <>, <>;
> > };
> >
> > /* External SCIF clock */
> > @@ -250,6 +270,12 @@
> > #reset-cells = <1>;
> > };
> >
> > +apmu@e6152000 {
> > +compatible = "renesas,r8a7744-apmu",
> "renesas,apmu";
> > +reg = <0 0xe6152000 0 0x188>;
> > +cpus = < >;
> > +};
> > +
> > rst: reset-controller@e616 {
> > compatible = "renesas,r8a7744-rst";
> > reg = <0 0xe616 0 0x100>;
> > --
> > 2.7.4
> >
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
RE: Issue with enabling VSP source on rcar gen2 koelsch board
Hi Laurent, Thanks for the feedback. > Subject: Re: Issue with enabling VSP source on rcar gen2 koelsch board > > Hi Biju, > > On Wednesday, 28 November 2018 15:20:58 EET Biju Das wrote: > > Hi all, > > > > On the past, I have tested vsp source on rcar gen2 koelsch board, > > using the patches series below(Apart from the below patch series, I > > have enabled > > "CONFIG_DRM_RCAR_VSP=y") > > https://git.linuxtv.org/pinchartl/media.git/log/?h=drm/du/panels > > > > 1) [HACK] ARM: shmobile: r8a7791: Link the VSP1 and DU > > 2) [HACK] v4l: vsp1: Disable UAPI for VSP1D > > 3) [HACK] drm: rcar-du: Enable VSP source support for R8A7791 > > > > But on the latest renesas-dev branch looks like it is broken > > That doesn't surprise me too much as I don't actively maintain that code. > > For my information, what are your use cases ? Do you think this approach > should be pursued and patches merged upstream ? The amount of work will > be quite high though, given that it introduces a new userspace API, we will > have to publish an open-source implementation in an X.org or Wayland > driver. Basically as part of RZ-G1/M VSP upstreaming(Linux 4.15 kernel) ,previously I have executed the below test cases 1) vsp test suite:- based on the instruction present on "http://git.ideasonboard.com/renesas/vsp-tests.git; 2) vspd testing:- based on the instruction present on "https://git.linuxtv.org/pinchartl/media.git/log/?h=drm/du/panels; Both the test cases were working fine with 4.15 kernel. Now as part of RZ/G1N vsp upstreaming, I rebased to latest branch from renesas-dev , and executed the same test case Only test cases in vsp test suite is working. the vspd test case is broken. So I am wondering how do we expose the r-car gen2 SoC feature "VSPD" to the end user? Regards, Biju Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
[PATCH 2/5] ARM: dts: r8a7744: Add VSP support
Add VSP support to SoC DT.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 3b8aa3b..0937349 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1493,6 +1493,33 @@
status = "disabled";
};
+ vsp@fe928000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe928000 0 0x8000>;
+ interrupts = ;
+ clocks = < CPG_MOD 131>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 131>;
+ };
+
+ vsp@fe93 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe93 0 0x8000>;
+ interrupts = ;
+ clocks = < CPG_MOD 128>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 128>;
+ };
+
+ vsp@fe938000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe938000 0 0x8000>;
+ interrupts = ;
+ clocks = < CPG_MOD 127>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 127>;
+ };
+
du: display@feb0 {
compatible = "renesas,du-r8a7744";
reg = <0 0xfeb0 0 0x4>,
--
2.7.4
[PATCH 5/5] ARM: dts: r8a7744: Add TPU support
Add TPU support to SoC DT.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 43da6a0..40de227 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -272,6 +272,16 @@
reg = <0 0xe606 0 0x164>;
};
+ tpu: pwm@e60f {
+ compatible = "renesas,tpu-r8a7744", "renesas,tpu";
+ reg = <0 0xe60f 0 0x148>;
+ clocks = < CPG_MOD 304>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 304>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e615 {
compatible = "renesas,r8a7744-cpg-mssr";
reg = <0 0xe615 0 0x1000>;
--
2.7.4
[PATCH 4/5] ARM: dts: r8a7744: Add PWM SoC support
Add the definitions for pwm[0123456] to the SoC dtsi.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 70 ++
1 file changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 152431c..43da6a0 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1050,6 +1050,76 @@
status = "disabled";
};
+ pwm0: pwm@e6e3 {
+ compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+ reg = <0 0xe6e3 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@e6e35000 {
+ compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+ reg = <0 0xe6e35000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@e6e36000 {
+ compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+ reg = <0 0xe6e36000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
can0: can@e6e8 {
compatible = "renesas,can-r8a7744",
"renesas,rcar-gen2-can";
--
2.7.4
[PATCH 3/5] ARM: dts: r8a7744: Add IPMMU DT nodes
Add the six IPMMU instances found in the r8a7744 to DT with a disabled
status.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 58 ++
1 file changed, 58 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 0937349..152431c 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -340,6 +340,64 @@
#thermal-sensor-cells = <0>;
};
+ ipmmu_sy0: mmu@e628 {
+ compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+ reg = <0 0xe628 0 0x1000>;
+ interrupts = ,
+;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_sy1: mmu@e629 {
+ compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+ reg = <0 0xe629 0 0x1000>;
+ interrupts = ;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_ds: mmu@e674 {
+ compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+ reg = <0 0xe674 0 0x1000>;
+ interrupts = ,
+;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mp: mmu@ec68 {
+ compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+ reg = <0 0xec68 0 0x1000>;
+ interrupts = ;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mx: mmu@fe951000 {
+ compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+ reg = <0 0xfe951000 0 0x1000>;
+ interrupts = ,
+;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_gp: mmu@e62a {
+ compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+ reg = <0 0xe62a 0 0x1000>;
+ interrupts = ,
+;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
icram0: sram@e63a {
compatible = "mmio-sram";
reg = <0 0xe63a 0 0x12000>;
--
2.7.4
[PATCH 1/5] ARM: dts: r8a7744: add VIN dt support
Add VIN[012] support to SoC dt.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 33 +
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 2eae905..3b8aa3b 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1020,6 +1020,39 @@
status = "disabled";
};
+ vin0: video@e6ef {
+ compatible = "renesas,vin-r8a7744",
+"renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef 0 0x1000>;
+ interrupts = ;
+ clocks = < CPG_MOD 811>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 811>;
+ status = "disabled";
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a7744",
+"renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = ;
+ clocks = < CPG_MOD 810>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 810>;
+ status = "disabled";
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a7744",
+"renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = ;
+ clocks = < CPG_MOD 809>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 809>;
+ status = "disabled";
+ };
+
rcar_sound: sound@ec50 {
/*
* #sound-dai-cells is required
--
2.7.4
[PATCH 0/5] Add more support to RZ/G1N
This patch series aims to add support for some more interfaces to RZ/G1N SoC (IPMMU, VSP, VIN, PWM and TPU). This patch series tested against renesas-dev. it depends on the the below patch series. https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=48065 Biju Das (5): ARM: dts: r8a7744: add VIN dt support ARM: dts: r8a7744: Add VSP support ARM: dts: r8a7744: Add IPMMU DT nodes ARM: dts: r8a7744: Add PWM SoC support ARM: dts: r8a7744: Add TPU support arch/arm/boot/dts/r8a7744.dtsi | 198 + 1 file changed, 198 insertions(+) -- 2.7.4
RE: [PATCH 06/22] ARM: dts: r8a7744-iwg20m: Enable SDHI10 controller
> -Original Message- > From: linux-renesas-soc-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Simon Horman > Sent: 28 November 2018 13:24 > To: Biju Das > Cc: Sergei Shtylyov ; Rob Herring > ; Mark Rutland ; Magnus > Damm ; linux-renesas-soc@vger.kernel.org; > devicet...@vger.kernel.org; Geert Uytterhoeven > ; Chris Paterson > ; Fabrizio Castro > > Subject: Re: [PATCH 06/22] ARM: dts: r8a7744-iwg20m: Enable SDHI10 > > > > > > On 11/27/2018 02:56 PM, Biju Das wrote: > > > > > > > Enable the SDHI0 controller on iWave RZ/G1N Qseven System On > Module. > > > > > >Why your subject has SDHI10? > > > > It is a typo. > > > > Simon, Will you fix this while applying or do you want me to send V2? > > Please let me know. > > No need to repost for this. Thanks Simon. Regards, Biju Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
Issue with enabling VSP source on rcar gen2 koelsch board
Hi all, On the past, I have tested vsp source on rcar gen2 koelsch board, using the patches series below(Apart from the below patch series, I have enabled "CONFIG_DRM_RCAR_VSP=y") https://git.linuxtv.org/pinchartl/media.git/log/?h=drm/du/panels 1) [HACK] ARM: shmobile: r8a7791: Link the VSP1 and DU 2) [HACK] v4l: vsp1: Disable UAPI for VSP1D 3) [HACK] drm: rcar-du: Enable VSP source support for R8A7791 But on the latest renesas-dev branch looks like it is broken The issue is kernel doesn't boot, if I connect display panel. Looks like it is hanging in register_framebuffer. [5.344412] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [5.364250] [drm] No driver support for vblank timestamp query. Have any one noticed this issue? Regards, Biju Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
RE: [PATCH 06/22] ARM: dts: r8a7744-iwg20m: Enable SDHI10 controller
Hello Sergei, Thanks for the feedback. > -Original Message- > From: Sergei Shtylyov > Sent: 27 November 2018 14:17 > To: Biju Das ; Rob Herring > ; Mark Rutland > Cc: Simon Horman ; Magnus Damm > ; linux-renesas-soc@vger.kernel.org; > devicet...@vger.kernel.org; Geert Uytterhoeven > ; Chris Paterson > ; Fabrizio Castro > > Subject: Re: [PATCH 06/22] ARM: dts: r8a7744-iwg20m: Enable SDHI10 > controller > > Hello! > > On 11/27/2018 02:56 PM, Biju Das wrote: > > > Enable the SDHI0 controller on iWave RZ/G1N Qseven System On Module. > >Why your subject has SDHI10? It is a typo. Simon, Will you fix this while applying or do you want me to send V2? Please let me know. > > Signed-off-by: Biju Das > [...] > > MBR, Sergei Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
[PATCH 22/22] ARM: dts: r8a7744: Add PCIe Controller device node
Add a device node for the PCIe controller on the Renesas
RZ/G1N (r8a7744) SoC.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 9c9508e..2eae905 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1432,6 +1432,34 @@
resets = < 408>;
};
+ pciec: pcie@fe00 {
+ compatible = "renesas,pcie-r8a7744",
+"renesas,pcie-rcar-gen2";
+ reg = <0 0xfe00 0 0x8>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x0100 0 0x 0 0xfe10 0
0x0010
+ 0x0200 0 0xfe20 0 0xfe20 0
0x0020
+ 0x0200 0 0x3000 0 0x3000 0
0x0800
+ 0x4200 0 0x3800 0 0x3800 0
0x0800>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x8000
+ 0x4300 2 0x 2 0x 1
0x>;
+ interrupts = ,
+,
+;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 116
IRQ_TYPE_LEVEL_HIGH>;
+ clocks = < CPG_MOD 319>, <_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 319>;
+ status = "disabled";
+ };
+
du: display@feb0 {
compatible = "renesas,du-r8a7744";
reg = <0 0xfeb0 0 0x4>,
--
2.7.4
[PATCH 09/22] ARM: dts: r8a7744: Add RWDT node
Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
RZ/G1N (r8a7744) SoC.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 118a596..4613a54 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -293,6 +293,16 @@
reg = <0 0xe616 0 0x100>;
};
+ rwdt: watchdog@e602 {
+ compatible = "renesas,r8a7744-wdt",
+"renesas,rcar-gen2-wdt";
+ reg = <0 0xe602 0 0x0c>;
+ clocks = < CPG_MOD 402>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 402>;
+ status = "disabled";
+ };
+
sysc: system-controller@e618 {
compatible = "renesas,r8a7744-sysc";
reg = <0 0xe618 0 0x200>;
--
2.7.4
[PATCH 21/22] ARM: dts: r8a7744: Add xhci support
Add a device node for the xhci controller on the Renesas
RZ/G1N (r8a7744) SoC.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index c9e9678..9c9508e 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1267,6 +1267,26 @@
dma-channels = <13>;
};
+ /*
+* pci1 and xhci share the same phy, therefore only one of them
+* can be active at any one time. If both of them are enabled,
+* a race condition will determine who'll control the phy.
+* A firmware file is needed by the xhci driver in order for
+* USB 3.0 to work properly.
+*/
+ xhci: usb@ee00 {
+ compatible = "renesas,xhci-r8a7744",
+"renesas,rcar-gen2-xhci";
+ reg = <0 0xee00 0 0xc00>;
+ interrupts = ;
+ clocks = < CPG_MOD 328>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 328>;
+ phys = < 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
pci0: pci@ee09 {
compatible = "renesas,pci-r8a7744",
"renesas,pci-rcar-gen2";
--
2.7.4
[PATCH 14/22] ARM: dts: r8a7744: Add IRQC support
Describe the IRQC interrupt controller in the r8a7744 device tree.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index e6662d9..b26315d 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -309,6 +309,26 @@
#power-domain-cells = <1>;
};
+ irqc: interrupt-controller@e61c {
+ compatible = "renesas,irqc-r8a7744", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c 0 0x200>;
+ interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+ clocks = < CPG_MOD 407>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 407>;
+ };
+
icram0: sram@e63a {
compatible = "mmio-sram";
reg = <0 0xe63a 0 0x12000>;
--
2.7.4
[PATCH 20/22] ARM: dts: r8a7744: Add MSIOF[012] support
Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 48 ++
1 file changed, 48 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index abe0ee3..c9e9678 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -944,6 +944,54 @@
status = "disabled";
};
+ msiof0: spi@e6e2 {
+ compatible = "renesas,msiof-r8a7744",
+"renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e2 0 0x0064>;
+ interrupts = ;
+ clocks = < CPG_MOD 000>;
+ dmas = < 0x51>, < 0x52>,
+ < 0x51>, < 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = < 000>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6e1 {
+ compatible = "renesas,msiof-r8a7744",
+"renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e1 0 0x0064>;
+ interrupts = ;
+ clocks = < CPG_MOD 208>;
+ dmas = < 0x55>, < 0x56>,
+ < 0x55>, < 0x56>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = < 208>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6e0 {
+ compatible = "renesas,msiof-r8a7744",
+"renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e0 0 0x0064>;
+ interrupts = ;
+ clocks = < CPG_MOD 205>;
+ dmas = < 0x41>, < 0x42>,
+ < 0x41>, < 0x42>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = < 205>;
+ status = "disabled";
+ };
+
can0: can@e6e8 {
compatible = "renesas,can-r8a7744",
"renesas,rcar-gen2-can";
--
2.7.4
[PATCH 15/22] ARM: dts: r8a7744: Add thermal device to DT
This patch instantiates the thermal sensor module with thermal-zone
support.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index b26315d..0eaf8a1 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -329,6 +329,17 @@
resets = < 407>;
};
+ thermal: thermal@e61f {
+ compatible = "renesas,thermal-r8a7744",
+"renesas,rcar-gen2-thermal";
+ reg = <0 0xe61f 0 0x10>, <0 0xe61f0100 0 0x38>;
+ interrupts = ;
+ clocks = < CPG_MOD 522>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 522>;
+ #thermal-sensor-cells = <0>;
+ };
+
icram0: sram@e63a {
compatible = "mmio-sram";
reg = <0 0xe63a 0 0x12000>;
@@ -1373,6 +1384,26 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <>;
+
+ trips {
+ cpu-crit {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
--
2.7.4
[PATCH 19/22] ARM: dts: r8a7744-iwg20m: Add SPI NOR support
Add support for the SPI NOR device used to boot up the system
to the iWave RZ/G1N Qseven System On Module DT.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
index 503583e..664a827 100644
--- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
@@ -36,6 +36,11 @@
function = "mmc";
};
+ qspi_pins: qspi {
+ groups = "qspi_ctrl", "qspi_data2";
+ function = "qspi";
+ };
+
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
@@ -53,6 +58,27 @@
status = "okay";
};
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ /* WARNING - This device contains the bootloader. Handle with care. */
+ flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sst,sst25vf016b", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <5000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+ };
+};
+
{
pinctrl-0 = <_pins>;
pinctrl-names = "default";
--
2.7.4
[PATCH 18/22] ARM: dts: r8a7744: Add QSPI support
Add the DT node for the QSPI interface to the SoC dtsi.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 39f309c..abe0ee3 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -649,6 +649,22 @@
status = "disabled";
};
+ qspi: spi@e6b1 {
+ compatible = "renesas,qspi-r8a7744", "renesas,qspi";
+ reg = <0 0xe6b1 0 0x2c>;
+ interrupts = ;
+ clocks = < CPG_MOD 917>;
+ dmas = < 0x17>, < 0x18>,
+ < 0x17>, < 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = < 917>;
+ status = "disabled";
+ };
+
scifa0: serial@e6c4 {
compatible = "renesas,scifa-r8a7744",
"renesas,rcar-gen2-scifa", "renesas,scifa";
--
2.7.4
[PATCH 16/22] ARM: dts: r8a7744: Add CMT SoC specific support
Add CMT[01] support to SoC DT.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 0eaf8a1..39f309c 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1382,6 +1382,38 @@
compatible = "renesas,prr";
reg = <0 0xff44 0 4>;
};
+
+ cmt0: timer@ffca {
+ compatible = "renesas,r8a7744-cmt0",
+"renesas,rcar-gen2-cmt0";
+ reg = <0 0xffca 0 0x1004>;
+ interrupts = ,
+;
+ clocks = < CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 124>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e613 {
+ compatible = "renesas,r8a7744-cmt1",
+"renesas,rcar-gen2-cmt1";
+ reg = <0 0xe613 0 0x1004>;
+ interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+ clocks = < CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 329>;
+ status = "disabled";
+ };
};
thermal-zones {
--
2.7.4
[PATCH 17/22] ARM: dts: iwg20d-q7-common: Move cmt/rwdt node out of RZ/G1M SOM
The iWave RZ/G1N board is almost identical to RZ/G1M. cmt and rwdt modules
are SoC specific and should be part of board dts rather than SoM dtsi. By
moving these nodes to the common dtsi it allows cmt and rwdt to be enabled
on both of these boards with less lines of code.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 9 +
arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 9 -
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index ca9154dd..e2b1ab9 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -116,6 +116,10 @@
status = "okay";
};
+ {
+ status = "okay";
+};
+
{
status = "okay";
pinctrl-0 = <_pins>;
@@ -230,6 +234,11 @@
};
};
+ {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
{
pinctrl-0 = <_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
index 0e2e033..b3fee1d 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
@@ -31,10 +31,6 @@
};
};
- {
- status = "okay";
-};
-
_clk {
clock-frequency = <2000>;
};
@@ -88,11 +84,6 @@
};
};
- {
- timeout-sec = <60>;
- status = "okay";
-};
-
{
pinctrl-0 = <_pins>;
pinctrl-names = "default";
--
2.7.4
[PATCH 13/22] ARM: dts: r8a7744: Add CAN support
Add the definitions for can0 and can1 to the r8a7744 SoC dtsi.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 9c2e8ea..e6662d9 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -898,13 +898,31 @@
};
can0: can@e6e8 {
+ compatible = "renesas,can-r8a7744",
+"renesas,rcar-gen2-can";
reg = <0 0xe6e8 0 0x1000>;
- /* placeholder */
+ interrupts = ;
+ clocks = < CPG_MOD 916>,
+< CPG_CORE R8A7744_CLK_RCAN>,
+<_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 916>;
+ status = "disabled";
};
can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7744",
+"renesas,rcar-gen2-can";
reg = <0 0xe6e88000 0 0x1000>;
- /* placeholder */
+ interrupts = ;
+ clocks = < CPG_MOD 915>,
+< CPG_CORE R8A7744_CLK_RCAN>,
+<_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 915>;
+ status = "disabled";
};
rcar_sound: sound@ec50 {
--
2.7.4
[PATCH 03/22] ARM: dts: r8a7744: Add SDHI nodes
Add SDHI nodes to the DT of the r8a7744 SoC.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 6505ebd..660747d 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -880,14 +880,49 @@
/* placeholder */
};
+ sdhi0: sd@ee10 {
+ compatible = "renesas,sdhi-r8a7744",
+"renesas,rcar-gen2-sdhi";
+ reg = <0 0xee10 0 0x328>;
+ interrupts = ;
+ clocks = < CPG_MOD 314>;
+ dmas = < 0xcd>, < 0xce>,
+ < 0xcd>, < 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <19500>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 314>;
+ status = "disabled";
+ };
+
sdhi1: sd@ee14 {
+ compatible = "renesas,sdhi-r8a7744",
+"renesas,rcar-gen2-sdhi";
reg = <0 0xee14 0 0x100>;
- /* placeholder */
+ interrupts = ;
+ clocks = < CPG_MOD 312>;
+ dmas = < 0xc1>, < 0xc2>,
+ < 0xc1>, < 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <9750>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 312>;
+ status = "disabled";
};
sdhi2: sd@ee16 {
+ compatible = "renesas,sdhi-r8a7744",
+"renesas,rcar-gen2-sdhi";
reg = <0 0xee16 0 0x100>;
- /* placeholder */
+ interrupts = ;
+ clocks = < CPG_MOD 311>;
+ dmas = < 0xd3>, < 0xd4>,
+ < 0xd3>, < 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <9750>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 311>;
+ status = "disabled";
};
gic: interrupt-controller@f1001000 {
--
2.7.4
[PATCH 06/22] ARM: dts: r8a7744-iwg20m: Enable SDHI10 controller
Enable the SDHI0 controller on iWave RZ/G1N Qseven System On Module.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
index 1e57b1f..503583e 100644
--- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
@@ -35,6 +35,12 @@
groups = "mmc_data8_b", "mmc_ctrl";
function = "mmc";
};
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
};
{
@@ -46,3 +52,13 @@
non-removable;
status = "okay";
};
+
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <_3p3v>;
+ vqmmc-supply = <_3p3v>;
+ cd-gpios = < 11 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
--
2.7.4
[PATCH 00/22] Add more support to RZ/G1N
This patch series aims to add support for some more interfaces to
RZ/G1N SoC (SCIF/HSCIF, I2C, IIC, SDHI, MMC, USBHost, USB Function,
rwdt, Audio, Display, CAN and CMT ).
This patch series tested against renesas-dev.
it depends on the the below patch series.
https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=46273
Biju Das (22):
ARM: dts: r8a7744: Add [H]SCIF{A|B} support
ARM: dts: r8a7744: Add I2C and IIC support
ARM: dts: r8a7744: Add SDHI nodes
ARM: dts: r8a7744: Add MMC node
ARM: dts: r8a7744-iwg20m: Add eMMC support
ARM: dts: r8a7744-iwg20m: Enable SDHI10 controller
ARM: dts: r8a7744: USB 2.0 host support
ARM: dts: r8a7744: Add USB-DMAC and HSUSB device nodes
ARM: dts: r8a7744: Add RWDT node
ARM: dts: r8a7744: Add audio support
ARM: dts: r8a7744: Add DU support
ARM: dts: r8a7744-iwg20d-q7-dbcm-ca: Add device tree for camera DB
ARM: dts: r8a7744: Add CAN support
ARM: dts: r8a7744: Add IRQC support
ARM: dts: r8a7744: Add thermal device to DT
ARM: dts: r8a7744: Add CMT SoC specific support
ARM: dts: iwg20d-q7-common: Move cmt/rwdt node out of RZ/G1M SOM
ARM: dts: r8a7744: Add QSPI support
ARM: dts: r8a7744-iwg20m: Add SPI NOR support
ARM: dts: r8a7744: Add MSIOF[012] support
ARM: dts: r8a7744: Add xhci support
ARM: dts: r8a7744: Add PCIe Controller device node
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/iwg20d-q7-common.dtsi |9 +
arch/arm/boot/dts/r8a7743-iwg20m.dtsi |9 -
arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts | 17 +
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 59 ++
arch/arm/boot/dts/r8a7744.dtsi | 1052 ++-
6 files changed, 1114 insertions(+), 33 deletions(-)
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts
--
2.7.4
[PATCH 02/22] ARM: dts: r8a7744: Add I2C and IIC support
Add the I2C[0-5] and IIC[0,1,3] devices nodes to the R8A7744 device tree.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 141 -
1 file changed, 139 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 165c701..6505ebd 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -15,6 +15,18 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ i2c4 =
+ i2c5 =
+ i2c6 =
+ i2c7 =
+ i2c8 =
+ };
+
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
@@ -310,19 +322,144 @@
reg = <0 0xe630 0 0x4>;
};
+ /* The memory map in the User's Manual maps the cores to
+* bus numbers
+*/
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 931>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 931>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 930>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 930>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
i2c2: i2c@e653 {
#address-cells = <1>;
#size-cells = <0>;
+ compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
reg = <0 0xe653 0 0x40>;
- /* placeholder */
+ interrupts = ;
+ clocks = < CPG_MOD 929>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e654 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
+ reg = <0 0xe654 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 928>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 928>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e652 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
+ reg = <0 0xe652 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 927>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 927>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
};
i2c5: i2c@e6528000 {
/* doesn't need pinmux */
#address-cells = <1>;
#size-cells = <0>;
+ compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
reg = <0 0xe6528000 0 0x40>;
-
[PATCH 01/22] ARM: dts: r8a7744: Add [H]SCIF{A|B} support
Describe [H]SCIF{|A|B} ports in the R8A7744 device tree.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 257 -
1 file changed, 254 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 79e75e7..165c701 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -414,9 +414,139 @@
status = "disabled";
};
+ scifa0: serial@e6c4 {
+ compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c4 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = < 0x21>, < 0x22>,
+ < 0x21>, < 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 204>;
+ status = "disabled";
+ };
+
+ scifa1: serial@e6c5 {
+ compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c5 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = < 0x25>, < 0x26>,
+ < 0x25>, < 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 203>;
+ status = "disabled";
+ };
+
+ scifa2: serial@e6c6 {
+ compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c6 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = < 0x27>, < 0x28>,
+ < 0x27>, < 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 202>;
+ status = "disabled";
+ };
+
+ scifa3: serial@e6c7 {
+ compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c7 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 1106>;
+ clock-names = "fck";
+ dmas = < 0x1b>, < 0x1c>,
+ < 0x1b>, < 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 1106>;
+ status = "disabled";
+ };
+
+ scifa4: serial@e6c78000 {
+ compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c78000 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 1107>;
+ clock-names = "fck";
+ dmas = < 0x1f>, < 0x20>,
+ < 0x1f>, < 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 1107>;
+ status = "disabled";
+ };
+
+ scifa5: serial@e6c8 {
+ compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c8 0 0x40>;
+
[PATCH 11/22] ARM: dts: r8a7744: Add DU support
Add du node to r8a7744 SoC DT. Boards that want to enable the DU
need to specify the output topology.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index d902f76..9c2e8ea 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1300,8 +1300,17 @@
};
du: display@feb0 {
+ compatible = "renesas,du-r8a7744";
reg = <0 0xfeb0 0 0x4>,
<0 0xfeb9 0 0x1c>;
+ reg-names = "du", "lvds.0";
+ interrupts = ,
+;
+ clocks = < CPG_MOD 724>,
+< CPG_MOD 723>,
+< CPG_MOD 726>;
+ clock-names = "du.0", "du.1", "lvds.0";
+ status = "disabled";
ports {
#address-cells = <1>;
@@ -1318,7 +1327,6 @@
};
};
};
- /* placeholder */
};
prr: chipid@ff44 {
--
2.7.4
[PATCH 10/22] ARM: dts: r8a7744: Add audio support
Add sound support for the RZ/G1N SoC (a.k.a. R8A7744).
This work is based on similar work done on the R8A7743 SoC.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 243 +++--
1 file changed, 235 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 4613a54..d902f76 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -908,23 +908,250 @@
};
rcar_sound: sound@ec50 {
- reg = <0 0xec50 0 0x1000>;
+ /*
+* #sound-dai-cells is required
+*
+* Single DAI : #sound-dai-cells = <0>;
<_sound>;
+* Multi DAI : #sound-dai-cells = <1>;
<_sound N>;
+*/
+ compatible = "renesas,rcar_sound-r8a7744",
+"renesas,rcar_sound-gen2";
+ reg = <0 0xec50 0 0x1000>, /* SCU */
+ <0 0xec5a 0 0x100>, /* ADG */
+ <0 0xec54 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec74 0 0x200>; /* Audio DMAC peri peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = < CPG_MOD 1005>,
+< CPG_MOD 1006>, < CPG_MOD 1007>,
+< CPG_MOD 1008>, < CPG_MOD 1009>,
+< CPG_MOD 1010>, < CPG_MOD 1011>,
+< CPG_MOD 1012>, < CPG_MOD 1013>,
+< CPG_MOD 1014>, < CPG_MOD 1015>,
+< CPG_MOD 1022>, < CPG_MOD 1023>,
+< CPG_MOD 1024>, < CPG_MOD 1025>,
+< CPG_MOD 1026>, < CPG_MOD 1027>,
+< CPG_MOD 1028>, < CPG_MOD 1029>,
+< CPG_MOD 1030>, < CPG_MOD 1031>,
+< CPG_MOD 1021>, < CPG_MOD 1020>,
+< CPG_MOD 1021>, < CPG_MOD 1020>,
+< CPG_MOD 1019>, < CPG_MOD 1018>,
+<_clk_a>, <_clk_b>, <_clk_c>,
+< CPG_CORE R8A7744_CLK_M2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1",
"ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
"src.5",
+ "src.4", "src.3", "src.2", "src.1",
"src.0",
+ "ctu.0", "ctu.1",
+ "mix.0", "mix.1",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 1005>,
+< 1006>, < 1007>, < 1008>, <
1009>,
+< 1010>, < 1011>, < 1012>, <
1013>,
+< 1014>, < 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1",
"ssi.0";
+ status = "disabled";
rcar_sound,dvc {
- dvc0: dvc-0 {};
- dvc1: dvc-1 {};
+ dvc0: dvc-0 {
+ dmas = < 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = < 0xbe>;
+
[PATCH 07/22] ARM: dts: r8a7744: USB 2.0 host support
Describe internal PCI bridge devices, USB phy device and
link PCI USB devices to USB phy.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 77 +++---
1 file changed, 72 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 7a0ccae..3549ee1 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -468,8 +468,25 @@
};
usbphy: usb-phy@e6590100 {
+ compatible = "renesas,usb-phy-r8a7744",
+"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
- /* placeholder */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < CPG_MOD 704>;
+ clock-names = "usbhs";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 704>;
+ status = "disabled";
+
+ usb0: usb-channel@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+ usb2: usb-channel@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
};
dmac0: dma-controller@e670 {
@@ -861,23 +878,73 @@
};
pci0: pci@ee09 {
- reg = <0 0xee09 0 0xc00>;
+ compatible = "renesas,pci-r8a7744",
+"renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee09 0 0xc00>,
+ <0 0xee08 0 0x1100>;
+ interrupts = ;
+ clocks = < CPG_MOD 703>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 703>;
+ status = "disabled";
bus-range = <0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
- /* placeholder */
+ ranges = <0x0200 0 0xee08 0 0xee08 0
0x0001>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x 0 0 1 GIC_SPI 108
IRQ_TYPE_LEVEL_HIGH
+0x0800 0 0 1 GIC_SPI 108
IRQ_TYPE_LEVEL_HIGH
+0x1000 0 0 2 GIC_SPI 108
IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = < 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = < 0>;
+ phy-names = "usb";
+ };
};
pci1: pci@ee0d {
- reg = <0 0xee0d 0 0xc00>;
+ compatible = "renesas,pci-r8a7744",
+"renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee0d 0 0xc00>,
+ <0 0xee0c 0 0x1100>;
+ interrupts = ;
+ clocks = < CPG_MOD 703>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 703>;
+ status = "disabled";
bus-range = <1 1>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
- /* placeholder */
+ ranges = <0x0200 0 0xee0c 0 0xee0c 0
0x0001>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x 0 0 1 GIC_SPI 113
IRQ_TYPE_LEVEL_HIGH
+0x0800 0 0 1 GIC_SPI 113
IRQ_TYPE_LEVEL_HIGH
+0x1000 0 0 2 GIC_SPI 113
IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x10800 0 0 0 0>;
+ phys = < 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x11000 0 0 0 0>;
+ phys = < 0>;
+ phy-names = "usb";
+ };
};
sdhi0: sd@ee10 {
--
2.7.4
[PATCH 12/22] ARM: dts: r8a7744-iwg20d-q7-dbcm-ca: Add device tree for camera DB
This patch adds support for the camera daughter board which is
connected to iWave's RZ/G1N Qseven carrier board.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts | 17 +
2 files changed, 18 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index aba5a25..9cf6fdf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -830,6 +830,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \
r8a7744-iwg20d-q7.dtb \
+ r8a7744-iwg20d-q7-dbcm-ca.dtb \
r8a7745-iwg22d-sodimm.dtb \
r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
r8a7745-sk-rzg1e.dtb \
diff --git a/arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts
b/arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts
new file mode 100644
index 000..3e58c2e9
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave Systems RZ/G1N Qseven board development
+ * platform with camera daughter board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a7744-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"
+#include "iwg20d-q7-dbcm-ca.dtsi"
+
+/ {
+ model = "iWave Systems RZ/G1N Qseven development platform with camera
add-on";
+ compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744";
+};
--
2.7.4
[PATCH 04/22] ARM: dts: r8a7744: Add MMC node
Add MMC node to the DT of the r8a7744 SoC.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 660747d..7a0ccae 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -925,6 +925,22 @@
status = "disabled";
};
+ mmcif0: mmc@ee20 {
+ compatible = "renesas,mmcif-r8a7744",
+"renesas,sh-mmcif";
+ reg = <0 0xee20 0 0x80>;
+ interrupts = ;
+ clocks = < CPG_MOD 315>;
+ dmas = < 0xd1>, < 0xd2>,
+ < 0xd1>, < 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 315>;
+ reg-io-width = <4>;
+ max-frequency = <9750>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.4
[PATCH 05/22] ARM: dts: r8a7744-iwg20m: Add eMMC support
Add eMMC support for iWave RZ/G1N Qseven System On Module.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
index 6166ae0..1e57b1f 100644
--- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
@@ -29,3 +29,20 @@
_clk {
clock-frequency = <2000>;
};
+
+ {
+ mmcif0_pins: mmc {
+ groups = "mmc_data8_b", "mmc_ctrl";
+ function = "mmc";
+ };
+};
+
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <_3p3v>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
--
2.7.4
[PATCH 08/22] ARM: dts: r8a7744: Add USB-DMAC and HSUSB device nodes
Add usb dmac and hsusb device nodes on RZ/G1N SoC dtsi.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 42 +-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 3549ee1..118a596 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -463,8 +463,20 @@
};
hsusb: usb@e659 {
+ compatible = "renesas,usbhs-r8a7744",
+"renesas,rcar-gen2-usbhs";
reg = <0 0xe659 0 0x100>;
- /* placeholder */
+ interrupts = ;
+ clocks = < CPG_MOD 704>;
+ dmas = <_dmac0 0>, <_dmac0 1>,
+ <_dmac1 0>, <_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 704>;
+ renesas,buswait = <4>;
+ phys = < 1>;
+ phy-names = "usb";
+ status = "disabled";
};
usbphy: usb-phy@e6590100 {
@@ -489,6 +501,34 @@
};
};
+ usb_dmac0: dma-controller@e65a {
+ compatible = "renesas,r8a7744-usb-dmac",
+"renesas,usb-dmac";
+ reg = <0 0xe65a 0 0x100>;
+ interrupts = ;
+ interrupt-names = "ch0", "ch1";
+ clocks = < CPG_MOD 330>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac1: dma-controller@e65b {
+ compatible = "renesas,r8a7744-usb-dmac",
+"renesas,usb-dmac";
+ reg = <0 0xe65b 0 0x100>;
+ interrupts = ;
+ interrupt-names = "ch0", "ch1";
+ clocks = < CPG_MOD 331>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
dmac0: dma-controller@e670 {
compatible = "renesas,dmac-r8a7744",
"renesas,rcar-dmac";
--
2.7.4
RE: [PATCH] arm64: dts: renesas: r8a7796: Add CMT device nodes
Hello Daniel,
Thanks for the feedback.
> -Original Message-
> From: Daniel Lezcano
> Sent: 19 November 2018 17:15
> To: Biju Das ; Rob Herring
> ; Mark Rutland
> Cc: Simon Horman ; Magnus Damm
> ; linux-renesas-soc@vger.kernel.org;
> devicet...@vger.kernel.org; Geert Uytterhoeven
> ; Chris Paterson
> ; Thomas Gleixner ;
> John Stultz ; Fabrizio Castro
>
> Subject: Re: [PATCH] arm64: dts: renesas: r8a7796: Add CMT device nodes
>
> On 19/11/2018 16:50, Biju Das wrote:
> > Hi Daniel,
> >
> > Thanks for the feedback.
> >
> >>>> Subject: Re: [PATCH] arm64: dts: renesas: r8a7796: Add CMT device
> >>>> nodes
> >>>>
> >>>> On 26/10/2018 10:25, Biju Das wrote:
> >>>>> This patch adds CMT{0|1|2|3} device nodes for r8a7796 SoC.
> >>>>>
> >>>>> Signed-off-by: Biju Das
> >>>>> ---
> >>>>> This patch is tested against renesas-dev
> >>>>>
> >>>>> I have executed on inconsistency-check, nanosleep and
> >>>>> clocksource_switch selftests on this arm64 SoC. The
> >>>>> inconsistency-check and nanosleep tests are working fine.The
> >>>>> clocksource_switch asynchronous test is failing due to
> >>>>> inconsistency-check
> >>>> failure on "arch_sys_counter".
> >>>>>
> >>>>> But if i skip the clocksource_switching of "arch_sys_counter", the
> >>>>> asynchronous test is passing for CMT0/1/2/3 timer.
> >>>>>
> >>>>> Has any one noticed this issue?
> >>>>
> >>>> So now that you mention that, I've been through the
> >>>> clocksource_switch on another ARM64 platform (hikey960) and
> >>>> disabled the
> >>>> ARM64_ERRATUM_858921 config option. I can see the same issue.
> >>>>
> >>>> Is this option set on your config ?
> >>>
> >>> No. As per " config ARM64_ERRATUM_858921", it is "Workaround for
> >> Cortex-A73 erratum 858921"
> >>>
> >>> Our SoC is 2xCA-57 + 4 x CA-53. Does it impact CA-57 + CA_53?
> >>
> >> Dunno :/
> >>
> >>> Any way I will enable this config option and will provide you the results.
> >>
> >> Ok, thanks!
> >
> > The following config is enabled by default on upstream
> > kernel(4.20-rc3) CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
> > CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
> > CONFIG_FSL_ERRATUM_A008585=y
> > CONFIG_HISILICON_ERRATUM_161010101=y
> > CONFIG_ARM64_ERRATUM_858921=y
> >
> > For a quick testing, I have activated the erratum using the property
> "fsl,erratum-a008585" on device tree.
> > With this I confirm the issue is fixed.
> >
> > I have some questions on this.
> > 1) Based on the test result ,do you think renesas soc also impacted by the
> ARM64_ERRATUM_858921?
> > 2) Is there any way to find, is this Erratum actually causing the
> asynchronous test to fail?
>
> I guess, you can hack the __fsl_a008585_read_reg macro and check if the
> invalid condition is reached.
>
> This thread https://lkml.org/lkml/2018/5/10/773 will give you all the answers
> you are looking for (well very likely).
>
> Let me know if it helped.
In our case , Delta: 174760 ns
1530553351:205762284
1530553351:205762404
1530553351:205951226
1530553351:205776466
I have tried the workaround for ARM64_ERRATUM_858921, that also fixes the issue.
But all the workaround disables ARM64 VDSO. How do we conclude that is it VDSO
issue or ARM64_ERRATUM issue?
Please share your ideas.
Regards,
Biju
> > timer {
> > compatible = "arm,armv8-timer";
> > interrupts-extended = < GIC_PPI 13
> (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > < GIC_PPI 14
> > (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>,
> > < GIC_PPI 11
> > (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>,
> > < GIC_PPI 10
> > (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> > +fsl,erratum-a008585;
> > }
>
>
>
>
> --
> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-
> blog/> Blog
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
RE: [PATCH 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
Hi Geert and Alexandre,
Thanks for the feedback.
> -Original Message-
> From: Alexandre Belloni
> Sent: 21 November 2018 10:35
> To: Geert Uytterhoeven
> Cc: Biju Das ; Alessandro Zummo
> ; linux-...@vger.kernel.org; Simon Horman
> ; Geert Uytterhoeven ;
> Chris Paterson ; Fabrizio Castro
> ; Linux-Renesas s...@vger.kernel.org>
> Subject: Re: [PATCH 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
>
> On 21/11/2018 11:23:08+0100, Geert Uytterhoeven wrote:
> > Hi Biju,
> >
> > On Mon, Nov 19, 2018 at 12:23 PM Biju Das
> wrote:
> > > Add support for NXP pcf85263 real-time clock. pcf85263 rtc is
> > > compatible with pcf85363,except that pcf85363 has additional 64 bytes of
> RAM.
> > >
> > > 1 byte of nvmem is supported and exposed in sysfs (# is the instance
> > > number,starting with 0): /sys/bus/nvmem/devices/pcf85263-#/nvmem
> > >
> > > Signed-off-by: Biju Das
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/rtc/rtc-pcf85363.c
> > > +++ b/drivers/rtc/rtc-pcf85363.c
> > > @@ -311,7 +311,30 @@ static int pcf85363_nvram_write(void *priv,
> unsigned int offset, void *val,
> > > val, bytes); }
> > >
> > > -static const struct regmap_config regmap_config = {
> > > +static int pcf85263_nvram_read(void *priv, unsigned int offset, void
> *val,
> > > + size_t bytes) {
> > > + struct pcf85363 *pcf85363 = priv;
> > > +
> > > + return regmap_read(pcf85363->regmap, CTRL_RAMBYTE, val); }
> >
> > AFAIU without reading the datasheet, the pcf85363 also has this
> > RAMBYTE register. Would it make sense to expose the contents on both
> parts?
>
> Yes it has. This series allows calling rtc_nvmem_register() multiple times
> from
> the same driver:
>
> http://patchwork.ozlabs.org/project/rtc-linux/list/?series=75212
Will check and send v2,
1) For pcf85363, calling rtc_nvmem_register twice (1 with 64 bytes and another
with 1 byte)
2) For pcf85263, calling rtc_nvmem_register ( with 1 byte)
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
RE: [PATCH 1/4] dt-bindings: rtc: pcf85363: Document pcf85263 real-time clock
Hello Simon, Thanks for the feedback. > -Original Message- > From: Simon Horman > Sent: 21 November 2018 10:10 > To: Biju Das > Cc: Alessandro Zummo ; Alexandre Belloni > ; Rob Herring ; > Mark Rutland ; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; Geert Uytterhoeven > ; Chris Paterson > ; Fabrizio Castro > ; linux-renesas-soc@vger.kernel.org > Subject: Re: [PATCH 1/4] dt-bindings: rtc: pcf85363: Document pcf85263 real- > time clock > > On Wed, Nov 21, 2018 at 11:04:52AM +0100, Simon Horman wrote: > > On Mon, Nov 19, 2018 at 11:15:05AM +, Biju Das wrote: > > > This patch adds binding for NXP pcf85263 real-time clock. pcf85263 > > > rtc is compatible with pcf85363 rtc except that pcf85363 has 64 > > > bytes additional RAM. > > > > How about this: > > > > This patch adds binding for the NXP pcf85263 real-time clock. > > > > The pcf85263 RTC is compatible with the pcf85363 RTC. The difference > > between the parts is except that the pcf85363 has 64 bytes more RAM. > > The pcf85263 anRTC is compatible with the pcf85363 RTC. > > The difference between the pcf85263 and pcf85363 RTS is that the latter has > 64 bytes more RAM. This renders them incompatible from a DT point of view. Will send V2 with the below changes. This patch adds binding for the NXP pcf85263 real-time clock. The pcf85263 RTC is compatible with the pcf85363 RTC. The difference between the parts is except that the pcf85363 has 64 bytes more RAM. The pcf85263 RTC is compatible with the pcf85363 RTC. The difference between the pcf85263 and pcf85363 RTC is that the latter has 64 bytes more RAM. This renders them incompatible from a DT point of view. Regards, Biju > > > > > Signed-off-by: Biju Das > > > --- > > > Documentation/devicetree/bindings/rtc/pcf85363.txt | 4 ++-- > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/rtc/pcf85363.txt > > > b/Documentation/devicetree/bindings/rtc/pcf85363.txt > > > index 76fdabc..94adc1c 100644 > > > --- a/Documentation/devicetree/bindings/rtc/pcf85363.txt > > > +++ b/Documentation/devicetree/bindings/rtc/pcf85363.txt > > > @@ -1,8 +1,8 @@ > > > -NXP PCF85363 Real Time Clock > > > +NXP PCF85263/PCF85363 Real Time Clock > > > > > > > > > Required properties: > > > -- compatible: Should contain "nxp,pcf85363". > > > +- compatible: Should contain "nxp,pcf85263" or "nxp,pcf85363". > > > - reg: I2C address for chip. > > > > > > Optional properties: > > > -- > > > 2.7.4 > > > > > Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
[PATCH 7/7] ARM: dts: r8a7744: Add SMP support
Add DT node for the Advanced Power Management Unit (APMU), add the
second CPU core, and use "renesas,apmu" as "enable-method".
Also add cpu1 phandle node to the PMU interrupt-affinity property.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 046ed94..79e75e7 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -49,6 +49,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -69,6 +70,25 @@
< 375000 100>;
};
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <15>;
+ clocks = < CPG_CORE R8A7744_CLK_Z>;
+ clock-latency = <30>; /* 300 us */
+ power-domains = < R8A7744_PD_CA15_CPU1>;
+ next-level-cache = <_CA15>;
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <150 100>,
+ <1312500 100>,
+ <1125000 100>,
+ < 937500 100>,
+ < 75 100>,
+ < 375000 100>;
+ };
+
L2_CA15: cache-controller-0 {
compatible = "cache";
cache-unified;
@@ -96,7 +116,7 @@
compatible = "arm,cortex-a15-pmu";
interrupts-extended = < GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
< GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <>;
+ interrupt-affinity = <>, <>;
};
/* External SCIF clock */
@@ -250,6 +270,12 @@
#reset-cells = <1>;
};
+ apmu@e6152000 {
+ compatible = "renesas,r8a7744-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = < >;
+ };
+
rst: reset-controller@e616 {
compatible = "renesas,r8a7744-rst";
reg = <0 0xe616 0 0x100>;
--
2.7.4
[PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM
Add support for iWave RZ/G1N Qseven System On Module.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 31 +++
1 file changed, 31 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20m.dtsi
diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
new file mode 100644
index 000..6166ae0
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave RZ/G1N Qseven SOM
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include "r8a7744.dtsi"
+#include
+
+/ {
+ compatible = "iwave,g20m", "renesas,r8a7744";
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x4000>;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+_clk {
+ clock-frequency = <2000>;
+};
--
2.7.4
[PATCH 5/7] ARM: dts: r8a7744: Add GPIO support
Describe GPIO blocks in the R8A7744 device tree.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 102 +++--
1 file changed, 98 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index a9ebd09..114642a 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -116,29 +116,123 @@
ranges;
gpio0: gpio@e605 {
+ compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
reg = <0 0xe605 0 0x50>;
+ interrupts = ;
#gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 0 32>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = < CPG_MOD 912>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 912>;
};
gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
reg = <0 0xe6051000 0 0x50>;
+ interrupts = ;
#gpio-cells = <2>;
- /* placeholder */
+ gpio-controller;
+ gpio-ranges = < 0 32 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 911>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 911>;
};
gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
reg = <0 0xe6052000 0 0x50>;
+ interrupts = ;
#gpio-cells = <2>;
- /* placeholder */
+ gpio-controller;
+ gpio-ranges = < 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 910>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 909>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 908>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 160 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 907>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 907>;
};
gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a7744&qu
[PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree
Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders
to avoid compilation error with the common platform code.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 369 +
1 file changed, 369 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7744.dtsi
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
new file mode 100644
index 000..cf02bf7
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a7744 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "renesas,r8a7744";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /*
+* The external audio clocks are configured as 0 Hz fixed frequency
+* clocks by default.
+* Boards that provide audio clocks should override them.
+*/
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <15>;
+ clocks = < CPG_CORE R8A7744_CLK_Z>;
+ clock-latency = <30>; /* 300 us */
+ power-domains = < R8A7744_PD_CA15_CPU0>;
+ next-level-cache = <_CA15>;
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <150 100>,
+ <1312500 100>,
+ <1125000 100>,
+ < 937500 100>,
+ < 75 100>,
+ < 375000 100>;
+ };
+
+ L2_CA15: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ power-domains = < R8A7744_PD_CA15_SCU>;
+ };
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts-extended = < GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@e605 {
+ reg = <0 0xe605 0 0x50>;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ /* placeholder */
+ };
+
+ gpio1: gpio@e6051000 {
+ reg = <0 0xe6051000 0 0x5
