Re: [PATCH v3] gpio: dwapb: Add support for 1 interrupt per port A GPIO

Hi Phil, On Fri, Apr 13, 2018 at 1:51 AM, Phil Edworthy wrote: > The DesignWare GPIO IP can be configured for either 1 interrupt or 1 > per GPIO in port A, but the driver currently only supports 1 interrupt. > See the DesignWare DW_apb_gpio Databook description of the

Re: [PATCH V5] PCI: rcar: Use runtime PM to control controller clock

On Fri, Apr 13, 2018 at 02:48:19PM +0200, Simon Horman wrote: > On Tue, Apr 10, 2018 at 06:17:04PM +0200, Marek Vasut wrote: > > On 04/10/2018 05:28 PM, Geert Uytterhoeven wrote: > > ... > > > >>> rcar_pcie_get_resources() is called while the device is > > >>> runtime-enabled/resumed, > > >>>

Re: Potential problem with 31e77c93e432dec7 ("sched/fair: Update blocked load when newly idle")

Hi Vincent, On 2018-04-12 13:15:19 +0200, Niklas Söderlund wrote: > Hi Vincent, > > Thanks for your feedback. > > On 2018-04-12 12:33:27 +0200, Vincent Guittot wrote: > > Hi Niklas, > > > > On 12 April 2018 at 11:18, Niklas Söderlund > > wrote: > > > Hi Vincent,

Re: [PATCH v8 1/2] dt-bindings: display: bridge: Document THC63LVD1024 LVDS decoder

On Tue, Apr 10, 2018 at 12:53:09PM +0200, Jacopo Mondi wrote: > Document Thine THC63LVD1024 LVDS decoder device tree bindings. > > Signed-off-by: Jacopo Mondi > Reviewed-by: Andrzej Hajda > Reviewed-by: Niklas Söderlund

Re: [PATCH] base: dma-mapping: Postpone cpu addr translation on mmap()

Please send a v2.

RE: [PATCH v3] gpio: dwapb: Add support for 1 interrupt per port A GPIO

Hi Hoan, On 13 April 2018 17:37 Hoan Tran wrote: > On Fri, Apr 13, 2018 at 1:51 AM, Phil Edworthy wrote: > > The DesignWare GPIO IP can be configured for either 1 interrupt or 1 > > per GPIO in port A, but the driver currently only supports 1 interrupt. > > See the DesignWare DW_apb_gpio Databook

[PATCH 2/2] serial: sh-sci: Use pm_runtime_get_sync()/put() on resume

From: Hien Dang Since commit '39dd0f234fc37d ("PM / Domains: Allow runtime PM during system PM phases")', runtime PM may be in suspended state during the system suspend phase. It is therefore necessary to call pm_runtime_get_sync()/ pm_runtime_put() when accessing the

[PATCH] spi: sh-msiof: Add spi_master_suspend/spi_master_resume

From: Gaku Inami Add spi_master_suspend(), spi_master_resume() in PM callback since it needs to start/stop the queue during suspend/resume. Signed-off-by: Gaku Inami Signed-off-by: Hiromitsu Yamasaki

Re: [PATCH v2 5/5] DT: pci: rcar-pci: document R8A77980 bindings

On Sun, Apr 08, 2018 at 09:10:43PM +0300, Sergei Shtylyov wrote: > Document the R-Car V3H (R8A77980) SoC in the R-Car PCIe bindings. > > Signed-off-by: Sergei Shtylyov > > --- > Changes in version 2: > - new patch. > >

Re: [PATCH v2 3/5] pcie-rcar: add R-Car gen3 PHY support

On Sun, Apr 08, 2018 at 09:05:10PM +0300, Sergei Shtylyov wrote: > On R-Car gen3 SoCs the PCIe PHY has its own register region -- and I have > written a generic PHY driver for it, thus we need to add the corresponding > code in rcar_pcie_hw_init_gen3() and call devm_phy_optional_get() at the >

[PATCH 0/2] serial: sh-sci: Use pm_runtime_get_sync()/put()

Hi! These patches make sure that the device is up while the suspend/resume code is executed. Up-port from the BSP, tested not to break stuff. CU Uli Hien Dang (2): serial: sh-sci: Use pm_runtime_get_sync()/put() on suspend serial: sh-sci: Use pm_runtime_get_sync()/put() on resume

[PATCH 1/2] serial: sh-sci: Use pm_runtime_get_sync()/put() on suspend

From: Hien Dang Since commit '39dd0f234fc37d ("PM / Domains: Allow runtime PM during system PM phases")', runtime PM may be in suspended state when the module registers are backed up. It is therefore necessary to ensure the device is on during suspend by using

Re: [PATCH 0/2] serial: sh-sci: Use pm_runtime_get_sync()/put()

Hi Ulrich, On Fri, Apr 13, 2018 at 7:00 PM, Ulrich Hecht wrote: > These patches make sure that the device is up while the suspend/resume code > is executed. Up-port from the BSP, tested not to break stuff. > > Hien Dang (2): > serial: sh-sci: Use

Re: [PATCH] spi: sh-msiof: Add spi_master_suspend/spi_master_resume

> + struct platform_device *pdev = to_platform_device(dev); > + struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); struct sh_msiof_spi_priv *p = dev_get_drvdata(dev); signature.asc Description: PGP signature

Re: [PATCH v2] base: dma-mapping: Postpone cpu addr translation on mmap()

On 13/04/18 18:25, Jacopo Mondi wrote: Postpone calling virt_to_page() translation on memory locations not guaranteed to be backed by a struct page. Try first to map memory from device's coherent memory pool, then perform translation if that fails. On some architectures, specifically SH when

Re: [RESEND PATCH] serial: sh-sci: Document r8a77470 bindings

On Mon, Apr 09, 2018 at 01:20:00PM +0100, Biju Das wrote: > RZ/G1C (R8A77470) SoC also has the R-Car gen2 compatible SCIF and HSCIF > ports, so document the SoC specific bindings. > > Signed-off-by: Biju Das > Reviewed-by: Fabrizio Castro

Re: [PATCH v4 3/8] dt-bindings: mfd: renesas,rzn1-sysctrl: document RZ/N1 sysctrl node

On Tue, Apr 10, 2018 at 09:30:03AM +0100, Michel Pollet wrote: > The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function > system controller. This documents the node used to encapsulate > it's sub drivers. > > Signed-off-by: Michel Pollet > --- >

[PATCH] pinctrl: sh-pfc: r8a77970: add pin I/O voltage control

Add the pin I/O voltage level control to the R8A77980 PFC driver. Loosely based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov ---

Re: [PATCH] pinctrl: sh-pfc: r8a77970: add pin I/O voltage control

On 04/13/2018 09:31 PM, Sergei Shtylyov wrote: >> Add the pin I/O voltage level control to the R8A77980 PFC driver. >> >> Loosely based on the original (and large) patch by Vladimir Barinov. >> >> Signed-off-by: Vladimir Barinov >> Signed-off-by: Sergei

Re: [PATCH] watchdog: renesas-wdt: Add support for the R8A77965 WDT

Hi Wolfram, On Fri, Apr 13, 2018 at 5:37 PM, Wolfram Sang wrote: > On Fri, Apr 13, 2018 at 04:54:17PM +0200, Geert Uytterhoeven wrote: >> On Fri, Apr 13, 2018 at 4:25 PM, Wolfram Sang >> wrote: >> > Document support for the Watchdog Timer

[PATCH v2] base: dma-mapping: Postpone cpu addr translation on mmap()

Postpone calling virt_to_page() translation on memory locations not guaranteed to be backed by a struct page. Try first to map memory from device's coherent memory pool, then perform translation if that fails. On some architectures, specifically SH when configured with SPARSEMEM memory model,

Re: [PATCH] pinctrl: sh-pfc: r8a77970: add pin I/O voltage control

On 04/13/2018 09:29 PM, Sergei Shtylyov wrote: > Add the pin I/O voltage level control to the R8A77980 PFC driver. > > Loosely based on the original (and large) patch by Vladimir Barinov. > > Signed-off-by: Vladimir Barinov > Signed-off-by: Sergei Shtylyov

Re: [PATCH v4 5/8] dt-bindings: arm: Document the RZN1D-DB board

On Tue, Apr 10, 2018 at 09:30:05AM +0100, Michel Pollet wrote: > This documents the RZ/N1 bindings for the RZN1D-DB board. > > Signed-off-by: Michel Pollet > --- > Documentation/devicetree/bindings/arm/shmobile.txt | 5 - > 1 file changed, 4 insertions(+), 1

Re: [PATCH v2 1/5] mmc: renesas_sdhi_internal_dmac: limit DMA RX for old SoCs

Hello! On 04/13/2018 05:10 PM, Wolfram Sang wrote: > Early revisions of certain SoCs cannot do multiple DMA RX streams in > parallel. To avoid data corruption, only allow one DMA RX channel and > fall back to PIO, if needed. > > Signed-off-by: Wolfram Sang >

Re: [PATCH v2 1/2] gpio: dwapb: Add support for 1 interrupt per port A GPIO

Hi Phil, Thank you for the patch! Yet something to improve: [auto build test ERROR on gpio/for-next] [also build test ERROR on v4.16 next-20180413] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux

Re: RFC: RZ/N1 clock architecture...

Hi Michel, Cc'ing linux-clk On Tue, Apr 10, 2018 at 6:56 AM, Michel Pollet wrote: > Hi Geert, > > On 10 April 2018 11:08, Geert wrote: >> >> Hi Michel, >> >> On Tue, Apr 10, 2018 at 11:56 AM, Michel Pollet >> wrote: >> > In the

Re: [PATCH v2 1/2] gpio: dwapb: Add support for 1 interrupt per port A GPIO

Hi Phil, Thank you for the patch! Yet something to improve: [auto build test ERROR on gpio/for-next] [also build test ERROR on v4.16 next-20180413] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux

Re: [PATCH 1/5] mmc: renesas_sdhi_internal_dmac: limit DMA RX for old SoCs

> As the implementation stands it is global - only one DMA RX stream may > be in flight for the entire system. I am wondering if that is the right > granularity for the restriction. Perhaps it could be per-SDHI device, > allowing concurrent streams on different SDHI devices. As we have only one

Re: [PATCH 3/4] soc: renesas: rcar-sysc: Add support for R-Car E3 power areas

Hi Shimoda-san, On Thu, Apr 12, 2018 at 10:25 AM, Yoshihiro Shimoda wrote: >> From: Simon Horman , Sent: Thursday, April 12, 2018 4:55 >> PM >> On Wed, Apr 11, 2018 at 05:10:02PM +0200, Geert Uytterhoeven wrote: >> > On Wed, Apr 11, 2018 at

Re: [PATCH 1/5] mmc: renesas_sdhi_internal_dmac: limit DMA RX for old SoCs

On Thu, Apr 12, 2018 at 01:21:42PM +0200, Wolfram Sang wrote: > > > > +static unsigned long global_flags; > > > > Is the restriction on concurrent DMA RX streams global or per-device? > > ? Each device has only one DMA RX channel. Hey Simon, you upstreamed > this driver :) Or did I get the

Re: [PATCH v2 2/2] mfd: intel_quark_i2c_gpio: Update Synopsys GPIO interrupts

Hi Phil, On Fri, Apr 13, 2018 at 10:08 AM, Phil Edworthy wrote: > Since the way the Synopsys GPIO interrupts are stored has changed, this > driver needs to be updated in line with the changes. > > Signed-off-by: Phil Edworthy > --- > v2: >

RE: [PATCH v2 2/2] mfd: intel_quark_i2c_gpio: Update Synopsys GPIO interrupts

Hi Geert, On 13 April 2018 09:20 Geert Uytterhoeven wrote: > On Fri, Apr 13, 2018 at 10:08 AM, Phil Edworthy wrote: > > Since the way the Synopsys GPIO interrupts are stored has changed, > > this driver needs to be updated in line with the changes. > > > > Signed-off-by: Phil Edworthy

[PATCH v2 0/2] gpio: dwapb: Add support for 1 interrupt per port A GPIO

All details about the change is in patch 0001. patch 0002 fixes up other users of 'struct dwapb_port_property'. One point to mention is that I have made it possible for users to have unconncted interrupts by specifying holes in the list of interrupts. This is done by supporting the

[PATCH v2 1/2] gpio: dwapb: Add support for 1 interrupt per port A GPIO

The DesignWare GPIO IP can be configured for either 1 interrupt or 1 per GPIO in port A, but the driver currently only supports 1 interrupt. See the DesignWare DW_apb_gpio Databook description of the 'GPIO_INTR_IO' parameter. This change allows the driver to work with up to 32 interrupts, it will

Re: [PATCH 4/4] soc: renesas: rcar-rst: Add support for R-Car E3

On Thu, Apr 12, 2018 at 08:11:22AM +, Yoshihiro Shimoda wrote: > Hi Simon-san, > > > From: Simon Horman, Sent: Thursday, April 12, 2018 4:55 PM > > > > On Wed, Apr 11, 2018 at 05:18:28PM +0200, Geert Uytterhoeven wrote: > > > Hi Shimoda-san, > > > > > > Thanks for your patch! > > > > > > On

[PATCH v2 2/2] mfd: intel_quark_i2c_gpio: Update Synopsys GPIO interrupts

Since the way the Synopsys GPIO interrupts are stored has changed, this driver needs to be updated in line with the changes. Signed-off-by: Phil Edworthy --- v2: - New patch in v2 to fix the only other user of struct dwapb_port_property. ---

Re: [PATCH v3 2/2] vfio: platform: Add generic DT reset support

Hi Geert, Philipp, On 12/04/18 18:02, Geert Uytterhoeven wrote: > Hi Philipp, > > On Thu, Apr 12, 2018 at 4:10 PM, Philipp Zabel wrote: >> On Thu, 2018-04-12 at 15:12 +0200, Geert Uytterhoeven wrote: >>> On Thu, Apr 12, 2018 at 2:36 PM, Sinan Kaya

[PATCH v3] gpio: dwapb: Add support for 1 interrupt per port A GPIO

The DesignWare GPIO IP can be configured for either 1 interrupt or 1 per GPIO in port A, but the driver currently only supports 1 interrupt. See the DesignWare DW_apb_gpio Databook description of the 'GPIO_INTR_IO' parameter. This change allows the driver to work with up to 32 interrupts, it will

Re: [PATCH v3 2/2] vfio: platform: Add generic DT reset support

Hi Eric, On Fri, Apr 13, 2018 at 10:52 AM, Auger Eric wrote: > On 12/04/18 18:02, Geert Uytterhoeven wrote: >> On Thu, Apr 12, 2018 at 4:10 PM, Philipp Zabel >> wrote: >>> On Thu, 2018-04-12 at 15:12 +0200, Geert Uytterhoeven wrote: On Thu,

Re: [PATCH 1/5] mmc: renesas_sdhi_internal_dmac: limit DMA RX for old SoCs

On Fri, Apr 13, 2018 at 10:35:48AM +0200, Wolfram Sang wrote: > > > As the implementation stands it is global - only one DMA RX stream may > > be in flight for the entire system. I am wondering if that is the right > > granularity for the restriction. Perhaps it could be per-SDHI device, > >

Re: [PATCH] vfio: platform: Fix using devices in PM Domains

Hi Geert, On 13/04/18 11:19, Geert Uytterhoeven wrote: > Hi Eric, > > On Fri, Apr 13, 2018 at 11:14 AM, Auger Eric wrote: >> On 11/04/18 11:24, Geert Uytterhoeven wrote: >>> If a device is part of a PM Domain (e.g. power and/or clock domain), its >>> power state is

Re: [PATCH] vfio: platform: Fix using devices in PM Domains

Hi Geert, On 11/04/18 11:24, Geert Uytterhoeven wrote: > If a device is part of a PM Domain (e.g. power and/or clock domain), its > power state is managed using Runtime PM. Without Runtime PM, the device > may not be powered up, causing subtle failures, crashes, or system > lock-ups when the

Re: [PATCH] vfio: platform: Fix using devices in PM Domains

Hi Eric, On Fri, Apr 13, 2018 at 11:14 AM, Auger Eric wrote: > On 11/04/18 11:24, Geert Uytterhoeven wrote: >> If a device is part of a PM Domain (e.g. power and/or clock domain), its >> power state is managed using Runtime PM. Without Runtime PM, the device >> may not be

Re: [PATCH v3 1/2] vfio: platform: Fix reset module leak in error path

Hi Geert, On 11/04/18 11:15, Geert Uytterhoeven wrote: > If the IOMMU group setup fails, the reset module is not released. > > Fixes: b5add544d677d363 ("vfio, platform: make reset driver a requirement by > default") > Signed-off-by: Geert Uytterhoeven > Reviewed-by:

Re: [PATCH v3 2/2] vfio: platform: Add generic DT reset support

Hi Geert, On Thu, 2018-04-12 at 18:02 +0200, Geert Uytterhoeven wrote: > Hi Philipp, > > On Thu, Apr 12, 2018 at 4:10 PM, Philipp Zabel wrote: > > On Thu, 2018-04-12 at 15:12 +0200, Geert Uytterhoeven wrote: > > > On Thu, Apr 12, 2018 at 2:36 PM, Sinan Kaya

Re: [PATCH v3 2/2] vfio: platform: Add generic DT reset support

Hi Philipp, On 13/04/18 11:22, Philipp Zabel wrote: [..] > That also means it is impossible to use just one of the devices that > share a reset line for vfio individually, while the other ones are still > in use by the host. Currently the reset line is a shared resource > similar to the iommu for

Re: [PATCH 2/2] clk: renesas: cpg-mssr: Add support for R-Car E3

Hi Shimoda-san, On Wed, Apr 11, 2018 at 11:37 AM, Yoshihiro Shimoda wrote: > Initial support for R-Car E3 (r8a77990), including core and module > clocks. > > Based on the Table 8.2g of "R-Car Series, 3rd Generation User's Manual: > Hardware ((Rev. 0.80, Oct 31,

Re: [PATCH] watchdog: renesas-wdt: Add support for the R8A77965 WDT

On Fri, Apr 13, 2018 at 04:54:17PM +0200, Geert Uytterhoeven wrote: > On Fri, Apr 13, 2018 at 4:25 PM, Wolfram Sang > wrote: > > Document support for the Watchdog Timer (WDT) Controller in the Renesas > > R-Car M3N (R8A77965) SoC. No driver update is needed. > >

[PATCH 0/2] spi: sh-msiof: Fix bit field overflow writes to TSCR/RSCR

The changeset fixes a bit field overflow which allows to write to higher bits while calculating SPI transfer clock and setting BRPS and BRDV bit fields, the problem is reproduced if 'parent_rate' to 'spi_hz' ratio is greater than 1024. I attach the second patch to the series, because actually the

[PATCH 2/2] spi: sh-msiof: Simplify calculation of divisors for transfer rate

The change updates sh_msiof_spi_set_clk_regs() function by iterating over BRDV power values. Note that the change is a functional one, namely prescaler output x 1/1 set in BRDV bit field (0b111) for MSO division rate set to 2 is substituted by BRDV = 0b000 and BRPS = 0b0, in terms of written

[PATCH 1/2] spi: sh-msiof: Fix bit field overflow writes to TSCR/RSCR

The change fixes a bit field overflow which allows to write to higher bits while calculating SPI transfer clock and setting BRPS and BRDV bit fields, the problem is reproduced if 'parent_rate' to 'spi_hz' ratio is greater than 1024, for instance p->min_div = 2, MSO rate=

Re: [PATCH V5] PCI: rcar: Use runtime PM to control controller clock

On Tue, Apr 10, 2018 at 06:17:04PM +0200, Marek Vasut wrote: > On 04/10/2018 05:28 PM, Geert Uytterhoeven wrote: ... > >>> rcar_pcie_get_resources() is called while the device is > >>> runtime-enabled/resumed, > >>> pci_free_resource_list() is called while the device is runtime-disabled. > >

Re: [PATCH v3 2/2] vfio: platform: Add generic DT reset support

Hi Philipp, On Fri, Apr 13, 2018 at 11:22 AM, Philipp Zabel wrote: > On Thu, 2018-04-12 at 18:02 +0200, Geert Uytterhoeven wrote: >> On Thu, Apr 12, 2018 at 4:10 PM, Philipp Zabel >> wrote: >> > On Thu, 2018-04-12 at 15:12 +0200, Geert

Re: [PATCH] vfio: platform: Fix using devices in PM Domains

Hi Eric, On Fri, Apr 13, 2018 at 11:44 AM, Auger Eric wrote: > On 13/04/18 11:19, Geert Uytterhoeven wrote: >> On Fri, Apr 13, 2018 at 11:14 AM, Auger Eric wrote: >>> On 11/04/18 11:24, Geert Uytterhoeven wrote: If a device is part of a PM

[PATCH] watchdog: renesas-wdt: Add support for the R8A77965 WDT

Document support for the Watchdog Timer (WDT) Controller in the Renesas R-Car M3N (R8A77965) SoC. No driver update is needed. Signed-off-by: Takeshi Kihara [wsa: rebased to top-of-tree] Signed-off-by: Wolfram Sang ---

Re: [PATCH] watchdog: renesas-wdt: Add support for the R8A77965 WDT

On Fri, Apr 13, 2018 at 4:25 PM, Wolfram Sang wrote: > Document support for the Watchdog Timer (WDT) Controller in the Renesas > R-Car M3N (R8A77965) SoC. No driver update is needed. M3-N > > Signed-off-by: Takeshi Kihara > [wsa:

[PATCH v2 5/5] mmc: renesas_sdhi_internal_dmac: remove superfluous WARN

The WARN can never trigger because we limited the max_seg number in renesas_sdhi_of_data already. Remove it and update the comment. Signed-off-by: Wolfram Sang Reviewed-by: Simon Horman ---

[PATCH v2 0/5] mmc: renesas_sdhi_internal_dmac: DMA handling fixes

I have collected the patches floating around for renesas_sdhi_internal_dmac and grouped them to avoid dependency issues. I think it would be good to give Shimoda-san next week to look at these patches, too. Regarding stable: I think patch 1 is clearly for stable. Patch 3 maybe, but it needs patch

[PATCH v2 1/5] mmc: renesas_sdhi_internal_dmac: limit DMA RX for old SoCs

Early revisions of certain SoCs cannot do multiple DMA RX streams in parallel. To avoid data corruption, only allow one DMA RX channel and fall back to PIO, if needed. Signed-off-by: Wolfram Sang Reviewed-by: Yoshihiro Shimoda

[PATCH v2 3/5] mmc: renesas_sdhi: Fix alignment check of sg buffer

From: Masaharu Hayakawa Sometimes sg->offset is not used for buffer addresses allocated by dma_map_sg(), so alignment checks should be done on the allocated buffer addresses. Delete the alignment check for sg->offset that is done before dma_map_sg(). Instead, it

[PATCH v2 2/5] mmc: renesas_sdhi: use helpers to access struct scatterlist members

From: Niklas Söderlund Instead of directly accessing the members of struct scatterlist use the helpers mmc_get_dma_dir() and sg_dma_address() in renesas_sdhi_internal_dmac_start_dma(). Based on previous work by Masaharu Hayakawa. Signed-off-by: Niklas

[PATCH v2 4/5] mmc: renesas_sdhi_internal_dmac: use more generic whitelisting

Whitelisting every ES version does not scale. So, we whitelist whole SoCs independent of ES version. If we need specific handling for an ES version, we put it to the front, so it will be matched first. Signed-off-by: Wolfram Sang Reviewed-by: Yoshihiro Shimoda

[PATCH v2] watchdog: renesas-wdt: Add support for WDIOF_CARDRESET

From: Veeraiyan Chidambaram This patch adds the WDIOF_CARDRESET support for the Renesas platform watchdog, to know if the board reboot is due to a watchdog reset. This is done via the WOVF bit (bit 4) of the RWTCSRA register, which indicates if RWTCNT

Re: [PATCH] watchdog: renesas-wdt: Add support for WDIOF_CARDRESET

> Reviewed-by: Guenetr Roeck Guenter, how about a keyboard macro to avoid such typos? ;) Fixed it in v2. signature.asc Description: PGP signature

Re: [PATCH v2 4/5] mmc: renesas_sdhi_internal_dmac: use more generic whitelisting

Hello! On 04/13/2018 05:10 PM, Wolfram Sang wrote: > Whitelisting every ES version does not scale. So, we whitelist whole > SoCs independent of ES version. If we need specific handling for an ES > version, we put it to the front, so it will be matched first. > > Signed-off-by: Wolfram Sang

Re: [PATCH RESEND] backlight: pwm_bl: don't use GPIOF_* with gpiod_get_direction

On Wed, Apr 11, 2018 at 09:32:16AM +0200, Simon Horman wrote: > On Tue, Apr 10, 2018 at 02:32:40PM +0200, Wolfram Sang wrote: > > The documentation was wrong, gpiod_get_direction() returns 0/1 instead > > of the GPIOF_* flags. The docs were fixed with commit 94fc73094abe47 > > ("gpio: correct docs

Re: [PATCH v8 2/2] drm: bridge: Add thc63lvd1024 LVDS decoder driver

Hello, small self review, as I've just noticed a trivial error. On Tue, Apr 10, 2018 at 12:53:10PM +0200, Jacopo Mondi wrote: > Add DRM bridge driver for Thine THC63LVD1024 LVDS to digital parallel > output converter. > > Signed-off-by: Jacopo Mondi > Reviewed-by:

Re: [PATCH] base: dma-mapping: Postpone cpu addr translation on mmap()

Hello again, On Tue, Apr 10, 2018 at 09:57:52AM +0200, jacopo mondi wrote: > Hi Christoph, > > On Mon, Apr 09, 2018 at 10:52:51AM -0700, Christoph Hellwig wrote: > > On Mon, Apr 09, 2018 at 06:59:08PM +0200, Jacopo Mondi wrote: > > > I'm still a bit puzzled on what happens if