[PATCH 0/2] mmc: core: Support packed command feature of eMMC4.5
This patch-set adds support of packed command feature for eMMC4.5 devices. Seungwon Jeon (2): mmc: core: Add packed command feature of eMMC4.5 mmc: core: Support packed command for eMMC4.5 device drivers/mmc/card/block.c | 355 -- drivers/mmc/card/queue.c | 48 ++- drivers/mmc/card/queue.h | 12 ++ drivers/mmc/core/mmc.c | 22 ++ include/linux/mmc/core.h |3 + include/linux/mmc/card.h |3 +++ include/linux/mmc/host.h |1 + include/linux/mmc/mmc.h | 15 +++ 8 files changed, 445 insertions(+), 14 deletions(-) -- 1.7.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] mmc: core: Add packed command feature of eMMC4.5
This patch adds packed command feature of eMMC4.5.
The maximum number for packing read(or write) is offered
and exception event relevant to packed command which is
used for error handling is enabled. If host wants to use
this feature, MMC_CAP2_PACKED_CMD should be set.
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
drivers/mmc/core/mmc.c | 22 ++
include/linux/mmc/card.h |3 +++
include/linux/mmc/host.h |1 +
include/linux/mmc/mmc.h | 15 +++
4 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 3627044..bf4fa6e 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -487,6 +487,9 @@ static int mmc_read_ext_csd(struct mmc_card *card, u8
*ext_csd)
ext_csd[EXT_CSD_CACHE_SIZE + 1] 8 |
ext_csd[EXT_CSD_CACHE_SIZE + 2] 16 |
ext_csd[EXT_CSD_CACHE_SIZE + 3] 24;
+
+ card-ext_csd.max_packed_writes =
ext_csd[EXT_CSD_MAX_PACKED_WRITES];
+ card-ext_csd.max_packed_reads =
ext_csd[EXT_CSD_MAX_PACKED_READS];
}
out:
@@ -1072,6 +1075,25 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
card-ext_csd.cache_ctrl = err ? 0 : 1;
}
+ if ((host-caps2 MMC_CAP2_PACKED_CMD)
+ (card-ext_csd.max_packed_writes 0)
+ (card-ext_csd.max_packed_reads 0)) {
+ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_EXP_EVENTS_CTRL,
+ EXT_CSD_PACKED_EVENT_EN,
+ card-ext_csd.generic_cmd6_time);
+ if (err err != -EBADMSG)
+ goto free_card;
+ if (err) {
+ pr_warning(%s: Enabling packed event failed\n,
+ mmc_hostname(card-host));
+ card-ext_csd.packed_event_en = 0;
+ err = 0;
+ } else {
+ card-ext_csd.packed_event_en = 1;
+ }
+ }
+
if (!oldcard)
host-card = card;
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index 415f2db..70ea3d6 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -52,6 +52,9 @@ struct mmc_ext_csd {
u8 part_config;
u8 cache_ctrl;
u8 rst_n_function;
+ u8 max_packed_writes;
+ u8 max_packed_reads;
+ u8 packed_event_en;
unsigned intpart_time; /* Units: ms */
unsigned intsa_timeout; /* Units: 100ns */
unsigned intgeneric_cmd6_time; /* Units: 10ms */
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index a3ac9c4..d2e4210 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -242,6 +242,7 @@ struct mmc_host {
#define MMC_CAP2_CACHE_CTRL(1 1)/* Allow cache control */
#define MMC_CAP2_POWEROFF_NOTIFY (1 2) /* Notify poweroff supported */
#define MMC_CAP2_NO_MULTI_READ (1 3)/* Multiblock reads don't work
*/
+#define MMC_CAP2_PACKED_CMD(1 4)/* Allow packed command */
mmc_pm_flag_t pm_caps;/* supported pm features */
unsigned intpower_notify_type;
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index 0e71356..1b94c4f 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -138,6 +138,7 @@ static inline bool mmc_op_multi(u32 opcode)
#define R1_CURRENT_STATE(x)((x 0x1E00) 9) /* sx, b (4 bits) */
#define R1_READY_FOR_DATA (1 8)/* sx, a */
#define R1_SWITCH_ERROR(1 7)/* sx, c */
+#define R1_EXP_EVENT (1 6)/* sr, a */
#define R1_APP_CMD (1 5)/* sr, c */
#define R1_STATE_IDLE 0
@@ -273,6 +274,10 @@ struct _mmc_csd {
#define EXT_CSD_FLUSH_CACHE32 /* W */
#define EXT_CSD_CACHE_CTRL 33 /* R/W */
#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
+#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
+#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
+#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
+#define EXT_CSD_EXP_EVENTS_CTRL56 /* R/W, 2 bytes */
#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
#define EXT_CSD_PARTITION_ATTRIBUTE156 /* R/W */
#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
@@ -313,6 +318,8 @@ struct _mmc_csd {
#define EXT_CSD_POWER_OFF_LONG_TIME247 /* RO */
#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
+#define EXT_CSD_MAX_PACKED_WRITES
Re: [PATCH 2/2] mmc: core: Support packed command for eMMC4.5 device
On 2 November 2011 04:03, Seungwon Jeon tgih@samsung.com wrote:
This patch supports packed command of eMMC4.5 device.
Several reads(or writes) can be grouped in packed command
and all data of the individual commands can be sent in a
single transfer on the bus.
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
drivers/mmc/card/block.c | 355
--
drivers/mmc/card/queue.c | 48 ++-
drivers/mmc/card/queue.h | 12 ++
include/linux/mmc/core.h | 3 +
4 files changed, 404 insertions(+), 14 deletions(-)
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index a1cb21f..6c49656 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -59,6 +59,13 @@ MODULE_ALIAS(mmc:block);
#define INAND_CMD38_ARG_SECTRIM1 0x81
#define INAND_CMD38_ARG_SECTRIM2 0x88
+#define mmc_req_rel_wr(req) (((req-cmd_flags REQ_FUA) || \
+ (req-cmd_flags REQ_META)) \
+ (rq_data_dir(req) == WRITE))
+#define PACKED_CMD_VER 0x01
+#define PACKED_CMD_RD 0x01
+#define PACKED_CMD_WR 0x02
+
static DEFINE_MUTEX(block_mutex);
/*
@@ -943,7 +950,8 @@ static int mmc_blk_err_check(struct mmc_card *card,
* kind. If it was a write, we may have transitioned to
* program mode, which we have to wait for it to complete.
*/
- if (!mmc_host_is_spi(card-host) rq_data_dir(req) != READ) {
+ if ((!mmc_host_is_spi(card-host) rq_data_dir(req) != READ) ||
+ (mq_mrq-packed_cmd == MMC_PACKED_WR_HDR)) {
u32 status;
do {
int err = get_card_status(card, status, 5);
@@ -980,12 +988,67 @@ static int mmc_blk_err_check(struct mmc_card *card,
if (!brq-data.bytes_xfered)
return MMC_BLK_RETRY;
+ if (mq_mrq-packed_cmd != MMC_PACKED_NONE) {
+ if (unlikely(brq-data.blocks 9 != brq-data.bytes_xfered))
+ return MMC_BLK_PARTIAL;
+ else
+ return MMC_BLK_SUCCESS;
+ }
+
if (blk_rq_bytes(req) != brq-data.bytes_xfered)
return MMC_BLK_PARTIAL;
return MMC_BLK_SUCCESS;
}
+static int mmc_blk_packed_err_check(struct mmc_card *card,
+ struct mmc_async_req *areq)
+{
+ struct mmc_queue_req *mq_mrq = container_of(areq, struct
mmc_queue_req,
+ mmc_active);
+ int err, check, status;
+ u8 ext_csd[512];
+
+ check = mmc_blk_err_check(card, areq);
+
+ if (check == MMC_BLK_SUCCESS)
+ return check;
+
+ if (check == MMC_BLK_PARTIAL) {
+ err = get_card_status(card, status, 0);
+ if (err)
+ return MMC_BLK_ABORT;
+
+ if (status R1_EXP_EVENT) {
+ err = mmc_send_ext_csd(card, ext_csd);
+ if (err)
+ return MMC_BLK_ABORT;
+
+ if ((ext_csd[EXT_CSD_EXP_EVENTS_STATUS + 0]
+ EXT_CSD_PACKED_FAILURE)
+ (ext_csd[EXT_CSD_PACKED_CMD_STATUS]
+ EXT_CSD_PACKED_GENERIC_ERROR)) {
+ if (ext_csd[EXT_CSD_PACKED_CMD_STATUS]
+ EXT_CSD_PACKED_INDEXED_ERROR)
{
+ /* Make be 0-based */
+ mq_mrq-packed_fail_idx =
+
ext_csd[EXT_CSD_PACKED_FAILURE_INDEX] - 1;
+ return MMC_BLK_PARTIAL;
+ } else {
+ return MMC_BLK_RETRY;
+ }
+ }
+ } else {
+ return MMC_BLK_RETRY;
+ }
+ }
+
+ if (check != MMC_BLK_ABORT)
+ return MMC_BLK_RETRY;
+ else
+ return MMC_BLK_ABORT;
+}
+
static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq,
struct mmc_card *card,
int disable_multi,
@@ -1129,6 +1192,211 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req
*mqrq,
mmc_queue_bounce_pre(mqrq);
}
+static u8 mmc_blk_chk_packable(struct mmc_queue *mq, struct request *req)
+{
+ struct request_queue *q = mq-queue;
+ struct mmc_card *card = mq-card;
+ struct request *cur = req, *next = NULL;
+ struct mmc_blk_data *md = mq-data;
+ bool en_rel_wr = card-ext_csd.rel_param EXT_CSD_WR_REL_PARAM_EN;
+ unsigned int req_sectors = 0, phys_segments = 0;
+ unsigned int max_blk_count,
[PATCH V4 1/4] ARM: S3C64XX: Add SPI clkdev support
Registered the SPI bus clocks with clkdev using generic
connection id.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/mach-s3c64xx/clock.c | 80 +
1 files changed, 49 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 415c540..0187cde 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -184,18 +184,6 @@ static struct clk init_clocks_off[] = {
.enable = s3c64xx_pclk_ctrl,
.ctrlbit= S3C_CLKCON_PCLK_SPI1,
}, {
- .name = spi_48m,
- .devname= s3c64xx-spi.0,
- .parent = clk_48m,
- .enable = s3c64xx_sclk_ctrl,
- .ctrlbit= S3C_CLKCON_SCLK_SPI0_48,
- }, {
- .name = spi_48m,
- .devname= s3c64xx-spi.1,
- .parent = clk_48m,
- .enable = s3c64xx_sclk_ctrl,
- .ctrlbit= S3C_CLKCON_SCLK_SPI1_48,
- }, {
.name = 48m,
.devname= s3c-sdhci.0,
.parent = clk_48m,
@@ -226,6 +214,22 @@ static struct clk init_clocks_off[] = {
},
};
+static struct clk clk_48m_spi0 = {
+ .name = spi_48m,
+ .devname= s3c64xx-spi.0,
+ .parent = clk_48m,
+ .enable = s3c64xx_sclk_ctrl,
+ .ctrlbit= S3C_CLKCON_SCLK_SPI0_48,
+};
+
+static struct clk clk_48m_spi1 = {
+ .name = spi_48m,
+ .devname= s3c64xx-spi.1,
+ .parent = clk_48m,
+ .enable = s3c64xx_sclk_ctrl,
+ .ctrlbit= S3C_CLKCON_SCLK_SPI1_48,
+};
+
static struct clk init_clocks[] = {
{
.name = lcd,
@@ -592,25 +596,6 @@ static struct clksrc_clk clksrcs[] = {
.sources= clkset_uhost,
}, {
.clk= {
- .name = spi-bus,
- .devname= s3c64xx-spi.0,
- .ctrlbit= S3C_CLKCON_SCLK_SPI0,
- .enable = s3c64xx_sclk_ctrl,
- },
- .reg_src= { .reg = S3C_CLK_SRC, .shift = 14, .size = 2
},
- .reg_div= { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4
},
- .sources= clkset_spi_mmc,
- }, {
- .clk= {
- .name = spi-bus,
- .devname= s3c64xx-spi.1,
- .enable = s3c64xx_sclk_ctrl,
- },
- .reg_src= { .reg = S3C_CLK_SRC, .shift = 16, .size = 2
},
- .reg_div= { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4
},
- .sources= clkset_spi_mmc,
- }, {
- .clk= {
.name = audio-bus,
.devname= samsung-i2s.0,
.ctrlbit= S3C_CLKCON_SCLK_AUDIO0,
@@ -708,6 +693,30 @@ static struct clksrc_clk clk_sclk_mmc2 = {
.sources= clkset_spi_mmc,
};
+static struct clksrc_clk clk_sclk_spi0 = {
+ .clk= {
+ .name = spi-bus,
+ .devname= s3c64xx-spi.0,
+ .ctrlbit= S3C_CLKCON_SCLK_SPI0,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
+ .sources = clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_spi1 = {
+ .clk= {
+ .name = spi-bus,
+ .devname= s3c64xx-spi.1,
+ .ctrlbit= S3C_CLKCON_SCLK_SPI1,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
+ .sources = clkset_spi_mmc,
+};
+
/* Clock initialisation code */
static struct clksrc_clk *init_parents[] = {
@@ -721,12 +730,16 @@ static struct clksrc_clk *clksrc_cdev[] = {
clk_sclk_mmc0,
clk_sclk_mmc1,
clk_sclk_mmc2,
+ clk_sclk_spi0,
+ clk_sclk_spi1,
};
static struct clk *clk_cdev[] = {
clk_hsmmc0,
clk_hsmmc1,
clk_hsmmc2,
+ clk_48m_spi0,
+ clk_48m_spi1,
};
static struct clk_lookup s3c64xx_clk_lookup[] = {
@@ -738,6 +751,11 @@ static struct clk_lookup s3c64xx_clk_lookup[] = {
CLKDEV_INIT(s3c-sdhci.0, mmc_busclk.2, clk_sclk_mmc0.clk),
CLKDEV_INIT(s3c-sdhci.1, mmc_busclk.2, clk_sclk_mmc1.clk),
CLKDEV_INIT(s3c-sdhci.2, mmc_busclk.2, clk_sclk_mmc2.clk),
+ CLKDEV_INIT(NULL,
[PATCH V4 3/4] ARM: S5P64X0: Add SPI clkdev support
Registered the SPI bus clocks with clkdev using generic
connection id.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/mach-s5p64x0/clock-s5p6440.c | 61 +++-
arch/arm/mach-s5p64x0/clock-s5p6450.c | 49 +++---
2 files changed, 58 insertions(+), 52 deletions(-)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c
b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index bfb1917..73c7cc9 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -268,18 +268,6 @@ static struct clk init_clocks_off[] = {
.enable = s5p64x0_pclk_ctrl,
.ctrlbit= (1 31),
}, {
- .name = sclk_spi_48,
- .devname= s3c64xx-spi.0,
- .parent = clk_48m,
- .enable = s5p64x0_sclk_ctrl,
- .ctrlbit= (1 22),
- }, {
- .name = sclk_spi_48,
- .devname= s3c64xx-spi.1,
- .parent = clk_48m,
- .enable = s5p64x0_sclk_ctrl,
- .ctrlbit= (1 23),
- }, {
.name = mmc_48m,
.devname= s3c-sdhci.0,
.parent = clk_48m,
@@ -421,26 +409,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
}, {
.clk= {
- .name = sclk_spi,
- .devname= s3c64xx-spi.0,
- .ctrlbit= (1 20),
- .enable = s5p64x0_sclk_ctrl,
- },
- .sources = clkset_group1,
- .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
- .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
- }, {
- .clk= {
- .name = sclk_spi,
- .devname= s3c64xx-spi.1,
- .ctrlbit= (1 21),
- .enable = s5p64x0_sclk_ctrl,
- },
- .sources = clkset_group1,
- .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
- .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
- }, {
- .clk= {
.name = sclk_post,
.ctrlbit= (1 10),
.enable = s5p64x0_sclk_ctrl,
@@ -489,6 +457,30 @@ static struct clksrc_clk clk_sclk_uclk = {
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
};
+static struct clksrc_clk clk_sclk_spi0 = {
+ .clk= {
+ .name = sclk_spi,
+ .devname= s3c64xx-spi.0,
+ .ctrlbit= (1 20),
+ .enable = s5p64x0_sclk_ctrl,
+ },
+ .sources = clkset_group1,
+ .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+ .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi1 = {
+ .clk= {
+ .name = sclk_spi,
+ .devname= s3c64xx-spi.1,
+ .ctrlbit= (1 21),
+ .enable = s5p64x0_sclk_ctrl,
+ },
+ .sources = clkset_group1,
+ .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+ .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+};
+
/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
clk_mout_apll,
@@ -509,11 +501,16 @@ static struct clk dummy_apb_pclk = {
static struct clksrc_clk *clksrc_cdev[] = {
clk_sclk_uclk,
+ clk_sclk_spi0,
+ clk_sclk_spi1,
};
static struct clk_lookup s5p6440_clk_lookup[] = {
CLKDEV_INIT(NULL, clk_uart_baud2, clk_pclk_low.clk),
CLKDEV_INIT(NULL, clk_uart_baud3, clk_sclk_uclk.clk),
+ CLKDEV_INIT(NULL, spi_busclk0, clk_p),
+ CLKDEV_INIT(s3c64xx-spi.0, spi_busclk1, clk_sclk_spi0.clk),
+ CLKDEV_INIT(s3c64xx-spi.1, spi_busclk1, clk_sclk_spi1.clk),
};
void __init_or_cpufreq s5p6440_setup_clocks(void)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c
b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index d132638..50f90cb 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -443,26 +443,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
}, {
.clk= {
- .name = sclk_spi,
- .devname= s3c64xx-spi.0,
- .ctrlbit= (1 20),
- .enable = s5p64x0_sclk_ctrl,
-
[PATCH V4 0/4] Add SPI clkdev support
This patchset modifies the existing clkdev to make SPI driver independent of the clock names send from platform data. This patches enables the SPI driver to request SPI bus clocks using generic connection ID. Link to V1: http://www.spinics.net/lists/arm-kernel/msg141671.html V2 Changes: -Add newly introduced CLKDEV_INIT macro for creating clk_lookup structure as suggested by Russell King V2 patches series are: http://www.spinics.net/lists/arm-kernel/msg142733.html V3 Changes: -Reworked the patches as per the following link. Patch series in the following link removed and , from the macro declaration and added in the macro defination. http://www.spinics.net/lists/arm-kernel/msg143663.html V4 Changes: Rebased to next-samsung-dt. Padmavathi Venna (4): ARM: S3C64XX: Add SPI clkdev support ARM: S5PC100: Add SPI clkdev support ARM: S5P64X0: Add SPI clkdev support ARM: S5PV210: Add SPI clkdev support arch/arm/mach-s3c64xx/clock.c | 80 + arch/arm/mach-s5p64x0/clock-s5p6440.c | 61 - arch/arm/mach-s5p64x0/clock-s5p6450.c | 49 - arch/arm/mach-s5pc100/clock.c | 124 +++-- arch/arm/mach-s5pv210/clock.c | 50 - 5 files changed, 210 insertions(+), 154 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 2/4] ARM: S5PC100: Add SPI clkdev support
Registered the SPI bus clocks with clkdev using generic
connection id.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/mach-s5pc100/clock.c | 124 -
1 files changed, 73 insertions(+), 51 deletions(-)
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 69829ba..88110ab 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -655,24 +655,6 @@ static struct clk init_clocks_off[] = {
.enable = s5pc100_d1_5_ctrl,
.ctrlbit= (1 8),
}, {
- .name = spi_48m,
- .devname= s3c64xx-spi.0,
- .parent = clk_mout_48m.clk,
- .enable = s5pc100_sclk0_ctrl,
- .ctrlbit= (1 7),
- }, {
- .name = spi_48m,
- .devname= s3c64xx-spi.1,
- .parent = clk_mout_48m.clk,
- .enable = s5pc100_sclk0_ctrl,
- .ctrlbit= (1 8),
- }, {
- .name = spi_48m,
- .devname= s3c64xx-spi.2,
- .parent = clk_mout_48m.clk,
- .enable = s5pc100_sclk0_ctrl,
- .ctrlbit= (1 9),
- }, {
.name = mmc_48m,
.devname= s3c-sdhci.0,
.parent = clk_mout_48m.clk,
@@ -717,6 +699,30 @@ static struct clk clk_hsmmc0 = {
.ctrlbit= (1 5),
};
+static struct clk clk_48m_spi0 = {
+ .name = spi_48m,
+ .devname= s3c64xx-spi.0,
+ .parent = clk_mout_48m.clk,
+ .enable = s5pc100_sclk0_ctrl,
+ .ctrlbit= (1 7),
+};
+
+static struct clk clk_48m_spi1 = {
+ .name = spi_48m,
+ .devname= s3c64xx-spi.1,
+ .parent = clk_mout_48m.clk,
+ .enable = s5pc100_sclk0_ctrl,
+ .ctrlbit= (1 8),
+};
+
+static struct clk clk_48m_spi2 = {
+ .name = spi_48m,
+ .devname= s3c64xx-spi.2,
+ .parent = clk_mout_48m.clk,
+ .enable = s5pc100_sclk0_ctrl,
+ .ctrlbit= (1 9),
+};
+
static struct clk clk_vclk54m = {
.name = vclk_54m,
.rate = 5400,
@@ -935,39 +941,6 @@ static struct clksrc_clk clk_sclk_spdif = {
static struct clksrc_clk clksrcs[] = {
{
.clk= {
- .name = sclk_spi,
- .devname= s3c64xx-spi.0,
- .ctrlbit= (1 4),
- .enable = s5pc100_sclk0_ctrl,
-
- },
- .sources = clk_src_group1,
- .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
- }, {
- .clk= {
- .name = sclk_spi,
- .devname= s3c64xx-spi.1,
- .ctrlbit= (1 5),
- .enable = s5pc100_sclk0_ctrl,
-
- },
- .sources = clk_src_group1,
- .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
- }, {
- .clk= {
- .name = sclk_spi,
- .devname= s3c64xx-spi.2,
- .ctrlbit= (1 6),
- .enable = s5pc100_sclk0_ctrl,
-
- },
- .sources = clk_src_group1,
- .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
- }, {
- .clk= {
.name = sclk_mixer,
.ctrlbit= (1 6),
.enable = s5pc100_sclk0_ctrl,
@@ -1108,6 +1081,42 @@ static struct clksrc_clk clk_sclk_mmc2 = {
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
};
+static struct clksrc_clk clk_sclk_spi0 = {
+ .clk= {
+ .name = sclk_spi,
+ .devname= s3c64xx-spi.0,
+ .ctrlbit= (1 4),
+ .enable = s5pc100_sclk0_ctrl,
+ },
+ .sources = clk_src_group1,
+ .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
+ .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi1 = {
+ .clk= {
+ .name = sclk_spi,
+ .devname= s3c64xx-spi.1,
+ .ctrlbit= (1 5),
+ .enable =
[PATCH V4 4/4] ARM: S5PV210: Add SPI clkdev support
Registered the SPI bus clocks with clkdev using generic
connection id.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/mach-s5pv210/clock.c | 50
1 files changed, 30 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index dc4586b..cead513 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -911,26 +911,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
}, {
.clk= {
- .name = sclk_spi,
- .devname= s3c64xx-spi.0,
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit= (1 16),
- },
- .sources = clkset_group2,
- .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
- .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
- }, {
- .clk= {
- .name = sclk_spi,
- .devname= s3c64xx-spi.1,
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit= (1 17),
- },
- .sources = clkset_group2,
- .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
- .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
- }, {
- .clk= {
.name = sclk_pwi,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit= (1 29),
@@ -1046,6 +1026,31 @@ static struct clksrc_clk clk_sclk_mmc3 = {
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
};
+static struct clksrc_clk clk_sclk_spi0 = {
+ .clk= {
+ .name = sclk_spi,
+ .devname= s3c64xx-spi.0,
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit= (1 16),
+ },
+ .sources = clkset_group2,
+ .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
+ };
+
+static struct clksrc_clk clk_sclk_spi1 = {
+ .clk= {
+ .name = sclk_spi,
+ .devname= s3c64xx-spi.1,
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit= (1 17),
+ },
+ .sources = clkset_group2,
+ .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
+ .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
+ };
+
+
static struct clksrc_clk *clksrc_cdev[] = {
clk_sclk_uart0,
clk_sclk_uart1,
@@ -1055,6 +1060,8 @@ static struct clksrc_clk *clksrc_cdev[] = {
clk_sclk_mmc1,
clk_sclk_mmc2,
clk_sclk_mmc3,
+ clk_sclk_spi0,
+ clk_sclk_spi1,
};
static struct clk *clk_cdev[] = {
@@ -1317,6 +1324,9 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
CLKDEV_INIT(s3c-sdhci.1, mmc_busclk.2, clk_sclk_mmc1.clk),
CLKDEV_INIT(s3c-sdhci.2, mmc_busclk.2, clk_sclk_mmc2.clk),
CLKDEV_INIT(s3c-sdhci.3, mmc_busclk.2, clk_sclk_mmc3.clk),
+ CLKDEV_INIT(NULL, spi_busclk0, clk_p),
+ CLKDEV_INIT(s3c64xx-spi.0, spi_busclk1, clk_sclk_spi0.clk),
+ CLKDEV_INIT(s3c64xx-spi.1, spi_busclk1, clk_sclk_spi1.clk),
};
void __init s5pv210_register_clocks(void)
--
1.7.0.4
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[RESEND][PATCH 6/6] ARM: SAMSUNG: Remove SPI bus clocks from platform data
SPI bus clocks can be avoided passing through platform
data as spi driver is getting the bus clock using the
generic clock connection id registered via clkdev.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/mach-s3c64xx/dev-spi.c |7 ---
arch/arm/mach-s5p64x0/dev-spi.c |6 --
arch/arm/mach-s5pc100/dev-spi.c |7 ---
arch/arm/mach-s5pv210/dev-spi.c |6 --
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h |2 --
5 files changed, 0 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
index 5e6b420..86fb130 100644
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ b/arch/arm/mach-s3c64xx/dev-spi.c
@@ -23,12 +23,6 @@
#include plat/gpio-cfg.h
#include plat/devs.h
-static char *spi_src_clks[] = {
- [S3C64XX_SPI_SRCCLK_PCLK] = pclk,
- [S3C64XX_SPI_SRCCLK_SPIBUS] = spi-bus,
- [S3C64XX_SPI_SRCCLK_48M] = spi_48m,
-};
-
/* SPI Controller platform_devices */
/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
@@ -175,5 +169,4 @@ void __init s3c64xx_spi_set_info(int cntrlr, int
src_clk_nr, int num_cs)
pd-num_cs = num_cs;
pd-src_clk_nr = src_clk_nr;
- pd-src_clk_name = spi_src_clks[src_clk_nr];
}
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
index 1fd9c79..5b5d3c0 100644
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ b/arch/arm/mach-s5p64x0/dev-spi.c
@@ -25,11 +25,6 @@
#include plat/s3c64xx-spi.h
#include plat/gpio-cfg.h
-static char *s5p64x0_spi_src_clks[] = {
- [S5P64X0_SPI_SRCCLK_PCLK] = pclk,
- [S5P64X0_SPI_SRCCLK_SCLK] = sclk_spi,
-};
-
/* SPI Controller platform_devices */
/* Since we emulate multi-cs capability, we do not touch the CS.
@@ -220,5 +215,4 @@ void __init s5p64x0_spi_set_info(int cntrlr, int
src_clk_nr, int num_cs)
pd-num_cs = num_cs;
pd-src_clk_nr = src_clk_nr;
- pd-src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
}
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
index e5d6c4d..155f50d 100644
--- a/arch/arm/mach-s5pc100/dev-spi.c
+++ b/arch/arm/mach-s5pc100/dev-spi.c
@@ -21,12 +21,6 @@
#include plat/gpio-cfg.h
#include plat/irqs.h
-static char *spi_src_clks[] = {
- [S5PC100_SPI_SRCCLK_PCLK] = pclk,
- [S5PC100_SPI_SRCCLK_48M] = spi_48m,
- [S5PC100_SPI_SRCCLK_SPIBUS] = spi_bus,
-};
-
/* SPI Controller platform_devices */
/* Since we emulate multi-cs capability, we do not touch the CS.
@@ -223,5 +217,4 @@ void __init s5pc100_spi_set_info(int cntrlr, int
src_clk_nr, int num_cs)
pd-num_cs = num_cs;
pd-src_clk_nr = src_clk_nr;
- pd-src_clk_name = spi_src_clks[src_clk_nr];
}
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c
index eaf9a7b..39bef19 100644
--- a/arch/arm/mach-s5pv210/dev-spi.c
+++ b/arch/arm/mach-s5pv210/dev-spi.c
@@ -20,11 +20,6 @@
#include plat/s3c64xx-spi.h
#include plat/gpio-cfg.h
-static char *spi_src_clks[] = {
- [S5PV210_SPI_SRCCLK_PCLK] = pclk,
- [S5PV210_SPI_SRCCLK_SCLK] = sclk_spi,
-};
-
/* SPI Controller platform_devices */
/* Since we emulate multi-cs capability, we do not touch the CS.
@@ -171,5 +166,4 @@ void __init s5pv210_spi_set_info(int cntrlr, int
src_clk_nr, int num_cs)
pd-num_cs = num_cs;
pd-src_clk_nr = src_clk_nr;
- pd-src_clk_name = spi_src_clks[src_clk_nr];
}
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index 4c16fa3..c3d82a5 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -31,7 +31,6 @@ struct s3c64xx_spi_csinfo {
/**
* struct s3c64xx_spi_info - SPI Controller defining structure
* @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
- * @src_clk_name: Platform name of the corresponding clock.
* @clk_from_cmu: If the SPI clock/prescalar control block is present
* by the platform's clock-management-unit and not in SPI controller.
* @num_cs: Number of CS this controller emulates.
@@ -43,7 +42,6 @@ struct s3c64xx_spi_csinfo {
*/
struct s3c64xx_spi_info {
int src_clk_nr;
- char *src_clk_name;
bool clk_from_cmu;
int num_cs;
--
1.7.4.4
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RE: [PATCH 1/7] SPI: S3C64XX: Use bus clocks created using clkdev
padma venkat wrote: Hi All, On Tue, Sep 27, 2011 at 4:52 AM, Kukjin Kim kgene@samsung.com wrote: Grant Likely wrote: On Fri, Sep 23, 2011 at 05:23:41PM +0530, Padmavathi Venna wrote: This patch modifies the driver to stop depending on the clock names being passed from platform and switch over to lookup clocks generic names using clkdev Signed-off-by: Padmavathi Venna padm...@samsung.com Looks okay to me. Acked-by: Grant Likely grant.lik...@secretlab.ca This series I imagine should go in via the arm-soc tree. OK, if others ok to me, I will pick up this series so that it will be sent to upstream via arm-soc. Ping. Any update on this. As I said, you need to re-submit others now. Then I will pick this up with others. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/7] ARM: EXYNOS4: Add support external GIC
On 12/10/11 06:16, Kukjin Kim wrote: Marc Zyngier wrote: Hi Changwan, On 11/10/11 13:22, Changhwan Youn wrote: Kukjin, could you please comment on the presence of a common memory region for the distributor? This seem quite odd... Some registers in Distributor are banked for PPI and SGI support (banked interrupts). The register for pending and enable status of these interrupts are banked. Right, that explains it then. Marc, I think the approach in your patch is much better than mine if it doesn't hurt the performance of other platforms which use the common gic code. It probably doesn't hurt the general case too much (I expect a bit more pressure on the d-cache because of the per-cpu stuff, but nothing to be too worried about). I'll re-work the exynos4 interrupt code based on your patch though I'm not sure that it's possible to be merged in merge window. My main concern at the moment is that mainline is broken as far as EXYNOS4 is concerned (there's a race with the EOI hook), so that should get fixed first. Hi Marc, OK. I agree with Will and your opinions and I think Changhwan can fix it as per your suggestion, but he needs fixed/updated regarding gic codes to avoid re-work and conflicts with others. So it would be better to us if he could fix it after merging your patches even probably at the end of upcoming merge window. I hope he can do it before v3.2-rc1. Right. So this damned thing has made it to mainline in its full glory. Furthermore, the MCT code is also broken, as it uses the old PPI API (doesn't even compile). Can we please fix this as soon as possible? I posted patches for both a while ago, with almost no reaction... M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH V4 0/4] Add SPI clkdev support
Padmavathi Venna wrote: This patchset modifies the existing clkdev to make SPI driver independent of the clock names send from platform data. This patches enables the SPI driver to request SPI bus clocks using generic connection ID. Link to V1: http://www.spinics.net/lists/arm-kernel/msg141671.html V2 Changes: -Add newly introduced CLKDEV_INIT macro for creating clk_lookup structure as suggested by Russell King V2 patches series are: http://www.spinics.net/lists/arm-kernel/msg142733.html V3 Changes: -Reworked the patches as per the following link. Patch series in the following link removed and , from the macro declaration and added in the macro defination. http://www.spinics.net/lists/arm-kernel/msg143663.html V4 Changes: Rebased to next-samsung-dt. Padmavathi Venna (4): ARM: S3C64XX: Add SPI clkdev support ARM: S5PC100: Add SPI clkdev support ARM: S5P64X0: Add SPI clkdev support ARM: S5PV210: Add SPI clkdev support arch/arm/mach-s3c64xx/clock.c | 80 + arch/arm/mach-s5p64x0/clock-s5p6440.c | 61 - arch/arm/mach-s5p64x0/clock-s5p6450.c | 49 - arch/arm/mach-s5pc100/clock.c | 124 +++-- arch/arm/mach-s5pv210/clock.c | 50 - 5 files changed, 210 insertions(+), 154 deletions(-) Applied. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v5 0/2] Add device tree support for Samsung's keypad controller driver
Kukjin Kim wrote: On 10/11/11 14:09, Kukjin Kim wrote: Thomas Abraham wrote: Changes since v4: - Tested with linux 3.1-rc9. No changes in code. Changes since v3: - Addressed comments from Grant Likely. - Set num_rows and num_cols to zero in samsung_keypad_parse_dt function. - Fixed the wierd looking if-else block in samsung_keypad_probe function. Changes since v2: - Addressed comments from Grant Likely. - Renamed 'keypad,key-code' property name to 'linux,code'. - Fixed incorrect data types for all instances of of_property+read_u32. - linux,input-type binding was not added as suggested since the driver supports only EV_KEY event type. Changes since v1: - Addressed comments from Dmitry Torokhov. - Type of controller is cached in driver's private data and the function that determines the type of the controller for each keypad scan is removed. - pdata allocated during probe is explicitly freed after probe completes without any error. In case of exit from probe due a error, no explicit deallocation of pdata memory is performed and it is left to devres to handle that. - The generic code to translate KEY(x,y,code) is retained in the driver itself. I am unsure of a right common place for it. - Driver continues with the probe even if one or more gpio configuration fails. - Patch 1 that adds a new config option is still retained in this patchset. This patchset adds device tree support for samsung's keypad controller driver. First patch adds a new config option to be used by device tree enabled platforms for selecting the samsung's keypad controller driver. The second patch adds device tree support for the keypad driver. Thomas Abraham (2): input: samsung-keypad: Add HAVE_SAMSUNG_KEYPAD config option input: samsung-keypad: Add device tree support .../devicetree/bindings/input/samsung-keypad.txt | 88 ++ drivers/input/keyboard/Kconfig |9 +- drivers/input/keyboard/samsung-keypad.c| 174 ++-- 3 files changed, 258 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/input/samsung- keypad.txt Looks ok to me, Acked-by: Kukjin Kimkgene@samsung.com Hi Dmitry, If you're ok on this, please adding this in your tree for upcoming merge window. Dmitry, Any problem on this? Hi Dmitry, I applied this in Samsung tree, if any problems, please let me know. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 5/7] ARM: EXYNOS4: Add support external GIC
Marc Zyngier wrote: On 12/10/11 06:16, Kukjin Kim wrote: Marc Zyngier wrote: Hi Changwan, On 11/10/11 13:22, Changhwan Youn wrote: Kukjin, could you please comment on the presence of a common memory region for the distributor? This seem quite odd... Some registers in Distributor are banked for PPI and SGI support (banked interrupts). The register for pending and enable status of these interrupts are banked. Right, that explains it then. Marc, I think the approach in your patch is much better than mine if it doesn't hurt the performance of other platforms which use the common gic code. It probably doesn't hurt the general case too much (I expect a bit more pressure on the d-cache because of the per-cpu stuff, but nothing to be too worried about). I'll re-work the exynos4 interrupt code based on your patch though I'm not sure that it's possible to be merged in merge window. My main concern at the moment is that mainline is broken as far as EXYNOS4 is concerned (there's a race with the EOI hook), so that should get fixed first. Hi Marc, OK. I agree with Will and your opinions and I think Changhwan can fix it as per your suggestion, but he needs fixed/updated regarding gic codes to avoid re-work and conflicts with others. So it would be better to us if he could fix it after merging your patches even probably at the end of upcoming merge window. I hope he can do it before v3.2-rc1. Right. So this damned thing has made it to mainline in its full glory. Furthermore, the MCT code is also broken, as it uses the old PPI API (doesn't even compile). Can we please fix this as soon as possible? I posted patches for both a while ago, with almost no reaction... Yeah, should be fixed. Let me check again and if any updates, let you know. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] mmc: core: Support packed command for eMMC4.5 device
On Wed, Nov 2, 2011 at 1:33 PM, Seungwon Jeon tgih@samsung.com wrote:
This patch supports packed command of eMMC4.5 device.
Several reads(or writes) can be grouped in packed command
and all data of the individual commands can be sent in a
single transfer on the bus.
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
drivers/mmc/card/block.c | 355
--
drivers/mmc/card/queue.c | 48 ++-
drivers/mmc/card/queue.h | 12 ++
include/linux/mmc/core.h | 3 +
4 files changed, 404 insertions(+), 14 deletions(-)
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index a1cb21f..6c49656 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -59,6 +59,13 @@ MODULE_ALIAS(mmc:block);
#define INAND_CMD38_ARG_SECTRIM1 0x81
#define INAND_CMD38_ARG_SECTRIM2 0x88
+#define mmc_req_rel_wr(req) (((req-cmd_flags REQ_FUA) || \
+ (req-cmd_flags REQ_META)) \
+ (rq_data_dir(req) == WRITE))
+#define PACKED_CMD_VER 0x01
+#define PACKED_CMD_RD 0x01
+#define PACKED_CMD_WR 0x02
+
static DEFINE_MUTEX(block_mutex);
/*
@@ -943,7 +950,8 @@ static int mmc_blk_err_check(struct mmc_card *card,
* kind. If it was a write, we may have transitioned to
* program mode, which we have to wait for it to complete.
*/
- if (!mmc_host_is_spi(card-host) rq_data_dir(req) != READ) {
+ if ((!mmc_host_is_spi(card-host) rq_data_dir(req) != READ) ||
+ (mq_mrq-packed_cmd == MMC_PACKED_WR_HDR)) {
u32 status;
do {
int err = get_card_status(card, status, 5);
@@ -980,12 +988,67 @@ static int mmc_blk_err_check(struct mmc_card *card,
if (!brq-data.bytes_xfered)
return MMC_BLK_RETRY;
+ if (mq_mrq-packed_cmd != MMC_PACKED_NONE) {
+ if (unlikely(brq-data.blocks 9 != brq-data.bytes_xfered))
+ return MMC_BLK_PARTIAL;
+ else
+ return MMC_BLK_SUCCESS;
+ }
+
if (blk_rq_bytes(req) != brq-data.bytes_xfered)
return MMC_BLK_PARTIAL;
return MMC_BLK_SUCCESS;
}
+static int mmc_blk_packed_err_check(struct mmc_card *card,
+ struct mmc_async_req *areq)
+{
+ struct mmc_queue_req *mq_mrq = container_of(areq, struct
mmc_queue_req,
+ mmc_active);
+ int err, check, status;
+ u8 ext_csd[512];
+
+ check = mmc_blk_err_check(card, areq);
+
+ if (check == MMC_BLK_SUCCESS)
+ return check;
+
+ if (check == MMC_BLK_PARTIAL) {
+ err = get_card_status(card, status, 0);
+ if (err)
+ return MMC_BLK_ABORT;
+
+ if (status R1_EXP_EVENT) {
+ err = mmc_send_ext_csd(card, ext_csd);
+ if (err)
+ return MMC_BLK_ABORT;
+
+ if ((ext_csd[EXT_CSD_EXP_EVENTS_STATUS + 0]
+ EXT_CSD_PACKED_FAILURE)
+ (ext_csd[EXT_CSD_PACKED_CMD_STATUS]
+ EXT_CSD_PACKED_GENERIC_ERROR)) {
+ if (ext_csd[EXT_CSD_PACKED_CMD_STATUS]
+ EXT_CSD_PACKED_INDEXED_ERROR)
{
+ /* Make be 0-based */
+ mq_mrq-packed_fail_idx =
+
ext_csd[EXT_CSD_PACKED_FAILURE_INDEX] - 1;
+ return MMC_BLK_PARTIAL;
+ } else {
+ return MMC_BLK_RETRY;
+ }
+ }
+ } else {
+ return MMC_BLK_RETRY;
+ }
+ }
+
+ if (check != MMC_BLK_ABORT)
+ return MMC_BLK_RETRY;
+ else
+ return MMC_BLK_ABORT;
+}
+
static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq,
struct mmc_card *card,
int disable_multi,
@@ -1129,6 +1192,211 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req
*mqrq,
mmc_queue_bounce_pre(mqrq);
}
+static u8 mmc_blk_chk_packable(struct mmc_queue *mq, struct request *req)
+{
+ struct request_queue *q = mq-queue;
+ struct mmc_card *card = mq-card;
+ struct request *cur = req, *next = NULL;
+ struct mmc_blk_data *md = mq-data;
+ bool en_rel_wr = card-ext_csd.rel_param EXT_CSD_WR_REL_PARAM_EN;
+ unsigned int req_sectors = 0, phys_segments = 0;
+ unsigned int
RE: [PATCH v2] gpio/samsung: Add device tree support for Exynos4
Thomas Abraham wrote:
As gpio chips get registered, a device tree node which represents the
gpio chip is searched and attached to it. A translate function is also
provided to convert the gpio specifier into actual platform settings
for pin function selection, pull up/down and driver strength settings.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Acked-by: Grant Likely grant.lik...@secretlab.ca
---
Changes since v1:
- As suggested by Rob and Grant, the gpio controller node lookup is based
on the base address of the gpio controller instead of the unique
per-controller compatible property value.
This patch is based on the following tree and branch.
git://git.linaro.org/git/people/arnd/arm-soc.git branch: for-next
.../devicetree/bindings/gpio/gpio-samsung.txt | 40
drivers/gpio/gpio-samsung.c| 66
2 files changed, 106 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/gpio/gpio-samsung.txt
diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
new file mode 100644
index 000..c143058
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
@@ -0,0 +1,40 @@
+Samsung Exynos4 GPIO Controller
+
+Required properties:
+- compatible: Compatible property value should be
samsung,exynos4-gpio.
+
+- reg: Physical base address of the controller and length of memory
mapped
+ region.
+
+- #gpio-cells: Should be 4. The syntax of the gpio specifier used by
client nodes
+ should be the following with values derived from the SoC user manual.
+ [phandle of the gpio controller node]
+ [pin number within the gpio controller]
+ [mux function]
+ [pull up/down]
+ [drive strength]
+
+ Values for gpio specifier:
+ - Pin number: is a value between 0 to 7.
+ - Pull Up/Down: 0 - Pull Up/Down Disabled.
+ 1 - Pull Down Enabled.
+ 3 - Pull Up Enabled.
+ - Drive Strength: 0 - 1x,
+1 - 3x,
+2 - 2x,
+3 - 4x
+
+- gpio-controller: Specifies that the node is a gpio controller.
+- #address-cells: should be 1.
+- #size-cells: should be 1.
+
+Example:
+
+ gpa0: gpio-controller@1140 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = samsung,exynos4-gpio;
+ reg = 0x1140 0x20;
+ #gpio-cells = 4;
+ gpio-controller;
+ };
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 8662518..0140756 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -24,6 +24,9 @@
#include linux/interrupt.h
#include linux/sysdev.h
#include linux/ioport.h
+#include linux/of.h
+#include linux/slab.h
+#include linux/of_address.h
#include asm/irq.h
@@ -2374,6 +2377,63 @@ static struct samsung_gpio_chip exynos4_gpios_3[] =
{
#endif
};
+#if defined(CONFIG_ARCH_EXYNOS4) defined(CONFIG_OF)
+int exynos4_gpio_xlate(struct gpio_chip *gc, struct device_node *np,
+ const void *gpio_spec, u32 *flags)
+{
+ const __be32 *gpio = gpio_spec;
+ const u32 n = be32_to_cpup(gpio);
+ unsigned int pin = gc-base + be32_to_cpu(gpio[0]);
+
+ if (gc-of_gpio_n_cells 4) {
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ if (n gc-ngpio)
+ return -EINVAL;
+
+ s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(be32_to_cpu(gpio[1])));
+ s3c_gpio_setpull(pin, be32_to_cpu(gpio[2]));
+ s5p_gpio_set_drvstr(pin, be32_to_cpu(gpio[3]));
+ return n;
+}
+
+static const struct of_device_id exynos4_gpio_dt_match[] __initdata = {
+ { .compatible = samsung,exynos4-gpio, },
+ {}
+};
+
+static __init void exynos4_gpiolib_attach_ofnode(struct samsung_gpio_chip
*chip,
+ u64 base, u64 offset)
+{
+ struct gpio_chip *gc = chip-chip;
+ u64 address;
+
+ if (!of_have_populated_dt())
+ return;
+
+ address = (chip-base) ? (base + ((u32)chip-base 0xfff)) :
+ (base + offset);
+
+ gc-of_node = of_find_matching_node_by_address(NULL,
+ exynos4_gpio_dt_match, address);
+ if (!gc-of_node) {
+ pr_info(gpio: device tree node not found for gpio
controller
+ with base address %08llx\n, address);
+ return;
+ }
+ gc-of_gpio_n_cells = 4;
+ gc-of_xlate = exynos4_gpio_xlate;
+}
+#else
+static __init void exynos4_gpiolib_attach_ofnode(struct samsung_gpio_chip
*chip,
+ u64 base, u64 offset)
+{
+ return;
+}
+#endif /* defined(CONFIG_ARCH_EXYNOS4) defined(CONFIG_OF) */
+
/* TODO: cleanup soc_is_* */
static __init int
RE: [PATCH] ARM: SAMSUNG: Fix compile error due to kfree
jhbird.c...@gmail.com wrote: From: Jonghwan Choi jhbird.c...@gmail.com Fix implicit declaration of function 'kfree' Signed-off-by: Jonghwan Choi jhbird.c...@gmail.com --- arch/arm/plat-samsung/dev-backlight.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-samsung/dev-backlight.c b/arch/arm/plat-samsung/dev- backlight.c index 3cedd4c..2adbeae 100644 --- a/arch/arm/plat-samsung/dev-backlight.c +++ b/arch/arm/plat-samsung/dev-backlight.c @@ -14,6 +14,7 @@ #include linux/platform_device.h #include linux/io.h #include linux/pwm_backlight.h +#include linux/slab.h #include plat/devs.h #include plat/gpio-cfg.h -- 1.7.0.4 Yes, applied. But would be better if you could add description in detail.. Fix following build error. arch/arm/plat-samsung/dev-backlight.c: In function 'samsung_bl_set': arch/arm/plat-samsung/dev-backlight.c:145: error: implicit declaration of function 'kfree' Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH V6] SDHCI: S3C: Use generic clock names for sdhci bus clock options
Rajeshwari Shinde wrote:
This patch modifies the driver to stop depending on the clock names
being passed from the platform and switch over to bus clock lookup
using generic clock names.
V6 Changes:
Changed sprintf to snprintf as suggested by Chris Ball.
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Kukjin Kim kgene@samsung.com
Hi Chirs,
Could you please pick this up in your tree for this merge window?
Thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
---
drivers/mmc/host/sdhci-s3c.c |7 ++-
1 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 82709b6..488223c 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -435,14 +435,11 @@ static int __devinit sdhci_s3c_probe(struct
platform_device *pdev)
for (clks = 0, ptr = 0; ptr MAX_BUS_CLK; ptr++) {
struct clk *clk;
- char *name = pdata-clocks[ptr];
-
- if (name == NULL)
- continue;
+ char name[14];
+ snprintf(name, 14, mmc_busclk.%d, ptr);
clk = clk_get(dev, name);
if (IS_ERR(clk)) {
- dev_err(dev, failed to get clock %s\n, name);
continue;
}
--
1.7.4.4
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[PATCH 1/5] [CPUFREQ] EXYNOS4210: Remove code about bus on cpufreq
From: Jongpill Lee boyko@samsung.com
This patch removes code for bus on cpufreq because the code
for bus frequency changing moves to busfreq driver.
So code about bus on cpufreq is not necessary.
Signed-off-by: Jongpill Lee boyko@samsung.com
Signed-off-by: SangWook Ju sw...@samsung.com
Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
drivers/cpufreq/exynos4210-cpufreq.c | 174
+-
1 files changed, 1 insertions(+), 173 deletions(-)
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
b/drivers/cpufreq/exynos4210-cpufreq.c
index b7c3a84..6ff3993 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -31,16 +31,8 @@ static struct clk *mout_mpll;
static struct clk *mout_apll;
static struct regulator *arm_regulator;
-static struct regulator *int_regulator;
static struct cpufreq_freqs freqs;
-static unsigned int memtype;
-
-enum exynos4_memory_type {
- DDR2 = 4,
- LPDDR2,
- DDR3,
-};
enum cpufreq_level_index {
L0, L1, L2, L3, CPUFREQ_LEVEL_END,
@@ -93,87 +85,24 @@ static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] =
{
{ 3, 0 },
};
-static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
- /*
-* Clock divider value for following
-* { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
-* DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
-*/
-
- /* DMC L0: 400MHz */
- { 3, 1, 1, 1, 1, 1, 3, 1 },
-
- /* DMC L1: 400MHz */
- { 3, 1, 1, 1, 1, 1, 3, 1 },
-
- /* DMC L2: 266.7MHz */
- { 7, 1, 1, 2, 1, 1, 3, 1 },
-
- /* DMC L3: 200MHz */
- { 7, 1, 1, 3, 1, 1, 3, 1 },
-};
-
-static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
- /*
-* Clock divider value for following
-* { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
-*/
-
- /* ACLK200 L0: 200MHz */
- { 3, 7, 4, 5, 1 },
-
- /* ACLK200 L1: 200MHz */
- { 3, 7, 4, 5, 1 },
-
- /* ACLK200 L2: 160MHz */
- { 4, 7, 5, 7, 1 },
-
- /* ACLK200 L3: 133.3MHz */
- { 5, 7, 7, 7, 1 },
-};
-
-static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
- /*
-* Clock divider value for following
-* { DIVGDL/R, DIVGPL/R }
-*/
-
- /* ACLK_GDL/R L0: 200MHz */
- { 3, 1 },
-
- /* ACLK_GDL/R L1: 200MHz */
- { 3, 1 },
-
- /* ACLK_GDL/R L2: 160MHz */
- { 4, 1 },
-
- /* ACLK_GDL/R L3: 133.3MHz */
- { 5, 1 },
-};
-
struct cpufreq_voltage_table {
unsigned intindex; /* any */
unsigned intarm_volt; /* uV */
- unsigned intint_volt;
};
static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] =
{
{
.index = L0,
.arm_volt = 120,
- .int_volt = 110,
}, {
.index = L1,
.arm_volt = 110,
- .int_volt = 110,
}, {
.index = L2,
.arm_volt = 100,
- .int_volt = 100,
}, {
.index = L3,
.arm_volt = 90,
- .int_volt = 100,
},
};
@@ -242,80 +171,6 @@ static void exynos4_set_clkdiv(unsigned int div_index)
do {
tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
} while (tmp 0x11);
-
- /* Change Divider - DMC0 */
-
- tmp = __raw_readl(S5P_CLKDIV_DMC0);
-
- tmp = ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
- S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
- S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
- S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
-
- tmp |= ((clkdiv_dmc0[div_index][0] S5P_CLKDIV_DMC0_ACP_SHIFT) |
- (clkdiv_dmc0[div_index][1] S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
|
- (clkdiv_dmc0[div_index][2] S5P_CLKDIV_DMC0_DPHY_SHIFT) |
- (clkdiv_dmc0[div_index][3] S5P_CLKDIV_DMC0_DMC_SHIFT) |
- (clkdiv_dmc0[div_index][4] S5P_CLKDIV_DMC0_DMCD_SHIFT) |
- (clkdiv_dmc0[div_index][5] S5P_CLKDIV_DMC0_DMCP_SHIFT) |
- (clkdiv_dmc0[div_index][6] S5P_CLKDIV_DMC0_COPY2_SHIFT) |
- (clkdiv_dmc0[div_index][7]
S5P_CLKDIV_DMC0_CORETI_SHIFT));
-
- __raw_writel(tmp, S5P_CLKDIV_DMC0);
-
- do {
- tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
- } while (tmp 0x);
-
- /* Change Divider - TOP */
-
- tmp = __raw_readl(S5P_CLKDIV_TOP);
-
- tmp = ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
- S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
- S5P_CLKDIV_TOP_ONENAND_MASK);
-
-
[PATCH 2/5] [CPUFREQ] EXYNOS4210: Update frequency table for cpu divider
From: Jongpill Lee boyko@samsung.com
This patch is changes frequency table for cpu divider for stable frequency.
Signed-off-by: Jongpill Lee boyko@samsung.com
Signed-off-by: SangWook Ju sw...@samsung.com
Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
drivers/cpufreq/exynos4210-cpufreq.c | 69
--
1 files changed, 41 insertions(+), 28 deletions(-)
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
b/drivers/cpufreq/exynos4210-cpufreq.c
index 6ff3993..5ca9380 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -35,14 +35,15 @@ static struct regulator *arm_regulator;
static struct cpufreq_freqs freqs;
enum cpufreq_level_index {
- L0, L1, L2, L3, CPUFREQ_LEVEL_END,
+ L0, L1, L2, L3, L4, CPUFREQ_LEVEL_END,
};
static struct cpufreq_frequency_table exynos4_freq_table[] = {
- {L0, 1000*1000},
- {L1, 800*1000},
- {L2, 400*1000},
- {L3, 100*1000},
+ {L0, 1200*1000},
+ {L1, 1000*1000},
+ {L2, 800*1000},
+ {L3, 500*1000},
+ {L4, 200*1000},
{0, CPUFREQ_TABLE_END},
};
@@ -53,17 +54,20 @@ static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] =
{
* DIVATB, DIVPCLK_DBG, DIVAPLL }
*/
- /* ARM L0: 1000MHz */
- { 0, 3, 7, 3, 3, 0, 1 },
+ /* ARM L0: 1200MHz */
+ { 0, 3, 7, 3, 4, 1, 7 },
- /* ARM L1: 800MHz */
- { 0, 3, 7, 3, 3, 0, 1 },
+ /* ARM L1: 1000MHz */
+ { 0, 3, 7, 3, 4, 1, 7 },
- /* ARM L2: 400MHz */
- { 0, 1, 3, 1, 3, 0, 1 },
+ /* ARM L2: 800MHz */
+ { 0, 3, 7, 3, 3, 1, 7 },
- /* ARM L3: 100MHz */
- { 0, 0, 1, 0, 3, 1, 1 },
+ /* ARM L3: 500MHz */
+ { 0, 3, 7, 3, 3, 1, 7 },
+
+ /* ARM L4: 200MHz */
+ { 0, 1, 3, 1, 3, 1, 0 },
};
static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
@@ -72,16 +76,19 @@ static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] =
{
* { DIVCOPY, DIVHPM }
*/
-/* ARM L0: 1000MHz */
- { 3, 0 },
+ /* ARM L0: 1200MHz */
+ { 5, 0 },
+
+ /* ARM L1: 1000MHz */
+ { 4, 0 },
- /* ARM L1: 800MHz */
+ /* ARM L2: 800MHz */
{ 3, 0 },
- /* ARM L2: 400MHz */
+ /* ARM L3: 500MHz */
{ 3, 0 },
- /* ARM L3: 100MHz */
+ /* ARM L4: 200MHz */
{ 3, 0 },
};
@@ -93,31 +100,37 @@ struct cpufreq_voltage_table {
static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] =
{
{
.index = L0,
- .arm_volt = 120,
+ .arm_volt = 135,
}, {
.index = L1,
- .arm_volt = 110,
+ .arm_volt = 130,
}, {
.index = L2,
- .arm_volt = 100,
+ .arm_volt = 120,
}, {
.index = L3,
- .arm_volt = 90,
+ .arm_volt = 110,
+ }, {
+ .index = L4,
+ .arm_volt = 105,
},
};
static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
- /* APLL FOUT L0: 1000MHz */
+ /* APLL FOUT L0: 1200MHz */
+ ((150 16) | (3 8) | 1),
+
+ /* APLL FOUT L1: 1000MHz */
((250 16) | (6 8) | 1),
- /* APLL FOUT L1: 800MHz */
+ /* APLL FOUT L2: 800MHz */
((200 16) | (6 8) | 1),
- /* APLL FOUT L2 : 400MHz */
- ((200 16) | (6 8) | 2),
+ /* APLL FOUT L3: 500MHz */
+ ((250 16) | (6 8) | 2),
- /* APLL FOUT L3: 100MHz */
- ((200 16) | (6 8) | 4),
+ /* APLL FOUT L4: 200MHz */
+ ((200 16) | (6 8) | 3),
};
static int exynos4_verify_speed(struct cpufreq_policy *policy)
--
1.7.1
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[PATCH 3/5] [CPUFREQ] EXYNOS4210: cpufreq code is changed for stable working
From: Jongpill Lee boyko@samsung.com
This patch is modify code for stable working
1. Remove unused register access code
2. Change sequence for frequency changing
Signed-off-by: Jongpill Lee boyko@samsung.com
Signed-off-by: SangWook Ju sw...@samsung.com
Signed-off-by: Jonghwan Choi jhbird.c...@samsung.com
Signed-off-by: Jaecheol Lee jc@samsung.com
---
drivers/cpufreq/exynos4210-cpufreq.c | 139
+
1 files changed, 88 insertions(+), 51 deletions(-)
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
b/drivers/cpufreq/exynos4210-cpufreq.c
index 5ca9380..246f9e2 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -34,10 +34,16 @@ static struct regulator *arm_regulator;
static struct cpufreq_freqs freqs;
+struct cpufreq_clkdiv {
+ unsigned int clkdiv;
+};
+
enum cpufreq_level_index {
L0, L1, L2, L3, L4, CPUFREQ_LEVEL_END,
};
+static struct cpufreq_clkdiv exynos4_clkdiv_table[CPUFREQ_LEVEL_END];
+
static struct cpufreq_frequency_table exynos4_freq_table[] = {
{L0, 1200*1000},
{L1, 1000*1000},
@@ -149,20 +155,7 @@ static void exynos4_set_clkdiv(unsigned int div_index)
/* Change Divider - CPU0 */
- tmp = __raw_readl(S5P_CLKDIV_CPU);
-
- tmp = ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
- S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
- S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
- S5P_CLKDIV_CPU0_APLL_MASK);
-
- tmp |= ((clkdiv_cpu0[div_index][0] S5P_CLKDIV_CPU0_CORE_SHIFT) |
- (clkdiv_cpu0[div_index][1] S5P_CLKDIV_CPU0_COREM0_SHIFT)
|
- (clkdiv_cpu0[div_index][2] S5P_CLKDIV_CPU0_COREM1_SHIFT)
|
- (clkdiv_cpu0[div_index][3] S5P_CLKDIV_CPU0_PERIPH_SHIFT)
|
- (clkdiv_cpu0[div_index][4] S5P_CLKDIV_CPU0_ATB_SHIFT) |
- (clkdiv_cpu0[div_index][5] S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
|
- (clkdiv_cpu0[div_index][6] S5P_CLKDIV_CPU0_APLL_SHIFT));
+ tmp = exynos4_clkdiv_table[div_index].clkdiv;
__raw_writel(tmp, S5P_CLKDIV_CPU);
@@ -227,14 +220,12 @@ static void exynos4_set_frequency(unsigned int
old_index, unsigned int new_index
unsigned int tmp;
if (old_index new_index) {
- /* The frequency changing to L0 needs to change apll */
- if (freqs.new == exynos4_freq_table[L0].frequency) {
- /* 1. Change the system clock divider values */
- exynos4_set_clkdiv(new_index);
-
- /* 2. Change the apll m,p,s value */
- exynos4_set_apll(new_index);
- } else {
+ /*
+* L1/L3, L2/L4 Level change require
+* to only change s divider value
+*/
+ if (((old_index == L3) (new_index == L1)) ||
+ ((old_index == L4) (new_index == L2))) {
/* 1. Change the system clock divider values */
exynos4_set_clkdiv(new_index);
@@ -243,18 +234,20 @@ static void exynos4_set_frequency(unsigned int
old_index, unsigned int new_index
tmp = ~(0x7 0);
tmp |= (exynos4_apll_pms_table[new_index] 0x7);
__raw_writel(tmp, S5P_APLL_CON0);
- }
- }
-
- else if (old_index new_index) {
- /* The frequency changing from L0 needs to change apll */
- if (freqs.old == exynos4_freq_table[L0].frequency) {
- /* 1. Change the apll m,p,s value */
- exynos4_set_apll(new_index);
-
- /* 2. Change the system clock divider values */
- exynos4_set_clkdiv(new_index);
} else {
+ /* Clock Configuration Procedure */
+ /* 1. Change the system clock divider values */
+ exynos4_set_clkdiv(new_index);
+ /* 2. Change the apll m,p,s value */
+ exynos4_set_apll(new_index);
+ }
+ } else if (old_index new_index) {
+ /*
+* L1/L3, L2/L4 Level change require
+* to only change s divider value
+*/
+ if (((old_index == L1) (new_index == L3)) ||
+ ((old_index == L2) (new_index == L4))) {
/* 1. Change just s value in apll m,p,s value */
tmp = __raw_readl(S5P_APLL_CON0);
tmp = ~(0x7 0);
@@ -263,6 +256,12 @@ static void exynos4_set_frequency(unsigned int
old_index, unsigned int new_index
/* 2. Change the system clock divider values */
exynos4_set_clkdiv(new_index);
+ } else {
[PATCH 4/5] [CPUFREQ] EXYNOS4210: Add DVS lock feature for other driver
From: Jongpill Lee boyko@samsung.com
This patch adds DVS lock feature for other driver and pm/
reboot notifier to enhance stability.
Signed-off-by: Jongpill Lee boyko@samsung.com
Signed-off-by: SangWook Ju sw...@samsung.com
Signed-off-by: Jonghwan Choi jhbird.c...@samsung.com
Signed-off-by: Jaecheol Lee jc@samsung.com
---
arch/arm/mach-exynos4/include/mach/cpufreq.h | 39 ++
drivers/cpufreq/exynos4210-cpufreq.c | 174
+-
2 files changed, 207 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/mach-exynos4/include/mach/cpufreq.h
diff --git a/arch/arm/mach-exynos4/include/mach/cpufreq.h
b/arch/arm/mach-exynos4/include/mach/cpufreq.h
new file mode 100644
index 000..7e00931
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/cpufreq.h
@@ -0,0 +1,39 @@
+/* linux/arch/arm/mach-exynos4/include/mach/cpufreq.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS4 - CPUFreq support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * CPU frequency level index for using cpufreq lock API
+ * This should be same with cpufreq_frequency_table
+ */
+enum cpufreq_level_request {
+ CPU_L0, /* 1200MHz */
+ CPU_L1, /* 1000MHz */
+ CPU_L2, /* 800MHz */
+ CPU_L3, /* 500MHz */
+ CPU_L4, /* 200MHz */
+ CPU_LEVEL_END,
+};
+
+enum cpufreq_lock_ID {
+ DVFS_LOCK_ID_G2D, /* G2D */
+ DVFS_LOCK_ID_TV,/* TV */
+ DVFS_LOCK_ID_MFC, /* MFC */
+ DVFS_LOCK_ID_USB, /* USB */
+ DVFS_LOCK_ID_CAM, /* CAM */
+ DVFS_LOCK_ID_PM,/* PM */
+ DVFS_LOCK_ID_USER, /* USER */
+ DVFS_LOCK_ID_END,
+};
+
+int exynos4_cpufreq_lock(unsigned int nId,
+ enum cpufreq_level_request cpufreq_level);
+void exynos4_cpufreq_lock_free(unsigned int nId);
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
b/drivers/cpufreq/exynos4210-cpufreq.c
index 246f9e2..30e1949 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -17,14 +17,21 @@
#include linux/slab.h
#include linux/regulator/consumer.h
#include linux/cpufreq.h
+#include linux/suspend.h
+#include linux/reboot.h
#include mach/map.h
#include mach/regs-clock.h
#include mach/regs-mem.h
+#include mach/cpufreq.h
#include plat/clock.h
#include plat/pm.h
+static bool exynos4_cpufreq_init_done;
+static DEFINE_MUTEX(set_freq_lock);
+static DEFINE_MUTEX(set_cpu_freq_lock);
+
static struct clk *cpu_clk;
static struct clk *moutcore;
static struct clk *mout_mpll;
@@ -53,6 +60,12 @@ static struct cpufreq_frequency_table
exynos4_freq_table[] = {
{0, CPUFREQ_TABLE_END},
};
+/* This defines are for cpufreq lock */
+#define CPUFREQ_MIN_LEVEL (CPUFREQ_LEVEL_END - 1)
+unsigned int cpufreq_lock_id;
+unsigned int cpufreq_lock_val[DVFS_LOCK_ID_END];
+unsigned int cpufreq_lock_level = CPUFREQ_MIN_LEVEL;
+
static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
/*
* Clock divider value for following
@@ -272,22 +285,31 @@ static int exynos4_target(struct cpufreq_policy
*policy,
{
unsigned int index, old_index;
unsigned int arm_volt;
+ int ret = 0;
+
+ mutex_lock(set_freq_lock);
freqs.old = exynos4_getspeed(policy-cpu);
if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
- freqs.old, relation, old_index))
- return -EINVAL;
+ freqs.old, relation, old_index))
{
+ ret = -EINVAL;
+ goto out;
+ }
if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
- target_freq, relation, index))
- return -EINVAL;
+ target_freq, relation, index)) {
+ ret = -EINVAL;
+ goto out;
+ }
freqs.new = exynos4_freq_table[index].frequency;
freqs.cpu = policy-cpu;
- if (freqs.new == freqs.old)
- return 0;
+ if (freqs.new == freqs.old) {
+ ret = -EINVAL;
+ goto out;
+ }
/* get the voltage value */
arm_volt = exynos4_volt_table[index].arm_volt;
@@ -311,8 +333,98 @@ static int exynos4_target(struct cpufreq_policy
*policy,
regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
}
+out:
+ mutex_unlock(set_freq_lock);
+
+ return ret;
+}
+
+atomic_t exynos4_cpufreq_lock_count;
+
+int exynos4_cpufreq_lock(unsigned int id,
+ enum cpufreq_level_request cpufreq_level)
+{
+ int i, old_idx = 0;
+ unsigned int freq_old, freq_new, arm_volt;
[PATCH 5/5] [CPUFREQ] EXYNOS4210: Add support ASV feature
From: Jaecheol Lee jc@samsung.com
This patch adds support ASV on Exynos4210. Exynos4 CPUFREQ
driver uses Adaptive Supply Voltage to configure voltage table.
Signed-off-by: Jaecheol Lee jc@samsung.com
---
arch/arm/mach-exynos4/include/mach/cpufreq.h |7 +++
drivers/cpufreq/exynos4210-cpufreq.c | 76
+-
2 files changed, 57 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-exynos4/include/mach/cpufreq.h
b/arch/arm/mach-exynos4/include/mach/cpufreq.h
index 7e00931..16bb3e9 100644
--- a/arch/arm/mach-exynos4/include/mach/cpufreq.h
+++ b/arch/arm/mach-exynos4/include/mach/cpufreq.h
@@ -37,3 +37,10 @@ enum cpufreq_lock_ID {
int exynos4_cpufreq_lock(unsigned int nId,
enum cpufreq_level_request cpufreq_level);
void exynos4_cpufreq_lock_free(unsigned int nId);
+
+#define SUPPORT_1400MHZ(1 31)
+#define SUPPORT_1200MHZ(1 30)
+#define SUPPORT_1000MHZ(1 29)
+
+#define SUPPORT_FREQ_SHIFT 29
+#define SUPPORT_FREQ_MASK 7
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
b/drivers/cpufreq/exynos4210-cpufreq.c
index 30e1949..8dcd9b1 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -60,6 +60,8 @@ static struct cpufreq_frequency_table exynos4_freq_table[]
= {
{0, CPUFREQ_TABLE_END},
};
+static unsigned int exynos4_volt_table[CPUFREQ_LEVEL_END];
+
/* This defines are for cpufreq lock */
#define CPUFREQ_MIN_LEVEL (CPUFREQ_LEVEL_END - 1)
unsigned int cpufreq_lock_id;
@@ -111,30 +113,6 @@ static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] =
{
{ 3, 0 },
};
-struct cpufreq_voltage_table {
- unsigned intindex; /* any */
- unsigned intarm_volt; /* uV */
-};
-
-static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] =
{
- {
- .index = L0,
- .arm_volt = 135,
- }, {
- .index = L1,
- .arm_volt = 130,
- }, {
- .index = L2,
- .arm_volt = 120,
- }, {
- .index = L3,
- .arm_volt = 110,
- }, {
- .index = L4,
- .arm_volt = 105,
- },
-};
-
static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
/* APLL FOUT L0: 1200MHz */
((150 16) | (3 8) | 1),
@@ -152,6 +130,26 @@ static unsigned int
exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
((200 16) | (6 8) | 3),
};
+/*
+ * ASV group voltage table
+ */
+static const unsigned int asv_voltage[CPUFREQ_LEVEL_END][8] = {
+ /*
+* SS, A1, A2, B1, B2, C1, C2, D
+* @1200 :
+* @1000 :
+* @800 : ASV_VOLTAGE_TABLE
+* @500 :
+* @200 :
+*/
+ { 135, 135, 130, 1275000, 125, 1225000, 120,
1175000 },
+ { 130, 125, 120, 1175000, 115, 1125000, 110,
1075000 },
+ { 120, 115, 110, 1075000, 105, 1025000, 100,
975000 },
+ { 110, 105, 100, 975000, 975000, 95, 925000, 925000
},
+ { 105, 100, 975000, 95, 95, 925000, 925000, 925000
},
+
+};
+
static int exynos4_verify_speed(struct cpufreq_policy *policy)
{
return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
@@ -312,7 +310,7 @@ static int exynos4_target(struct cpufreq_policy *policy,
}
/* get the voltage value */
- arm_volt = exynos4_volt_table[index].arm_volt;
+ arm_volt = exynos4_volt_table[index];
cpufreq_notify_transition(freqs, CPUFREQ_PRECHANGE);
@@ -392,7 +390,7 @@ int exynos4_cpufreq_lock(unsigned int id,
cpufreq_notify_transition(freqs, CPUFREQ_PRECHANGE);
/* get the voltage value */
- arm_volt = exynos4_volt_table[cpufreq_level].arm_volt;
+ arm_volt = exynos4_volt_table[cpufreq_level];
regulator_set_voltage(arm_regulator, arm_volt,
arm_volt);
@@ -518,11 +516,37 @@ static struct cpufreq_driver exynos4_driver = {
#endif
};
+static void __init set_volt_table(void)
+{
+ unsigned int tmp, i, asv_group = 0;
+
+ tmp = __raw_readl(S5P_INFORM2);
+
+ switch (tmp (SUPPORT_FREQ_MASK SUPPORT_FREQ_SHIFT)) {
+ case SUPPORT_1200MHZ:
+ asv_group = (tmp 0xF);
+ break;
+ case SUPPORT_1400MHZ:
+ case SUPPORT_1000MHZ:
+ default:
+ /* Not supported and assign typical ASV group */
+ asv_group = 2;
+ break;
+ }
+
+ printk(KERN_INFO DVFS: VDD_ARM Voltage table set with %d Group\n,
asv_group);
+
+ for (i = 0 ; i CPUFREQ_LEVEL_END ; i++)
+ exynos4_volt_table[i] = asv_voltage[i][asv_group];
+}
+
RE: Exynos4: Enable device tree support for GIC controller
Thomas Abraham wrote: Changes since v1: - Dropped device tree support for interrupt combiner controller from this patchset. Some rework in the interrupt combiner controller code is required to address the irq domain related comments from Grant Likely and hence those changes will be in another patchset. - As suggested by Grant Likely, linux virq number 0 is left unused. This patchset adds device tree support for GIC controller in Exynos4 SoC. Patch 1 moves the statically mapped timer irqs 11 to 15 to the end of the statically mapped linux irq space for Exynos4 platforms. For Exynos4 platforms, the five hardware timer irqs are connected to GIC at some hardware irq number (in exynos it is GIC_ID 69 to 73 for five timers). When any of these hardware interrupt occurs, its interrupt handler calls generic_handle_irq() with linux irq number 11/12/13/14/15 for timer 0/1/2/3/4 as the parameter. The code that needs to be notified about the timer interrupts would have already registered its handler for either of the interrupts 11 to 15. Instead of using linux irq number 11 to 15 to which consumers of timer interrupt attach their handler, this interrupt range is moved to the end of linux irq space used. So there will be no interrupts statically mapped between 0 to 31. The GIC hardware interrupts, which were previously statically mapped to start from linux irq 32 are now moved to start from linux irq 0. In case of exynos, GIC_ID[0] (which is SGI[0]) which was previously at linux irq 32, will not be at linux irq 0. This was required to use Rob Herring's GIC OF bindings patches for Exynos4. Patch 2 adds a interceptor for all ioremap calls targeted towards any of the statically remapped memory region. This was required because the GIC OF binding's patchset ioremaps the GIC memory-mapped regions in the gic_of_init() function. Without this patch, there would be two separate remap for GIC controller, one statically remapped and the other dynamically remapped by the gic_of_init() function. The patch will eventually be superseded by Nicolas Pitre's vmalloc patch series. Patch 3 adds device tree support for GIC controllers on Exynos4. For GIC controller, this patch is based on Rob Herring's, [PATCH 0/3] GIC OF bindings patchset. This patchset is based on the following tree: git://git.linaro.org/git/people/arnd/arm-soc.git branch: for-next Thomas Abraham (3): ARM: Exynos4: Move timer irq numbers to end of linux irq space ARM: Exynos4: Add ioremap interceptor for statically remapped regions ARM: Exynos4: Enable conversion of GIC dt irq specifier to linux virq arch/arm/mach-exynos4/cpu.c | 33 +- arch/arm/mach-exynos4/include/mach/entry-macro.S |1 - arch/arm/mach-exynos4/include/mach/io.h |5 +++ arch/arm/mach-exynos4/include/mach/irqs.h|8 +++-- arch/arm/mach-s5p64x0/include/mach/irqs.h|2 + arch/arm/mach-s5pc100/include/mach/irqs.h|2 + arch/arm/mach-s5pv210/include/mach/irqs.h|2 + arch/arm/plat-samsung/include/plat/irqs.h|3 +- 8 files changed, 50 insertions(+), 6 deletions(-) Looks ok to me, I replaced previous patches with this series. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 0/2] ARM: Samsung: Add basic device tree support for Exynos4 boards
Thomas Abraham wrote: Changes since v1: - Removed unique per-controller compatible string value from gpio controller nodes to align with the updated device tree support for exynos4 gpio controller. - Removed the interrupt combiner controller node. This patchset adds a new basic device tree enabled machine/board file which is based on the Samsung's Exynos4 family of SoC's. Also included in this patchset is the dts file for Exynos4210 SoC, Samsung's SMDKV310 board and Insignal's Origen board. The Exynos4210 dts file includes support for IRQ, GPIO, WDT, RTC, UART, SDHCI, Keypad, DMA and I2C controllers. As device tree coverage for Exynos4210 increases, additional device nodes to represent the controllers should be added. The device tree enabled machine file enables boot on two boards based on the Exynos4210 SoC. This provides a starting point to add additional device tree support on these boards, migrate other existing Exynos4 based boards to use device tree and enable device tree based boot on new upcoming boards. This patchset has been tested on the following tree: git://git.linaro.org/git/people/arnd/arm-soc.git branch: for-next Thomas Abraham (2): ARM: Samsung: Add Exynos4 device tree enabled board file ARM: dts: Add intial dts file for Exynos4210 SoC, SMDKV310 and Origen board .../devicetree/bindings/arm/insignal-boards.txt|8 + .../devicetree/bindings/arm/samsung-boards.txt |8 + arch/arm/boot/dts/exynos4210-origen.dts| 137 +++ arch/arm/boot/dts/exynos4210-smdkv310.dts | 182 + arch/arm/boot/dts/exynos4210.dtsi | 397 arch/arm/mach-exynos4/Kconfig | 14 + arch/arm/mach-exynos4/Makefile |2 + arch/arm/mach-exynos4/mach-exynos4-dt.c| 85 + 8 files changed, 833 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/insignal-boards.txt create mode 100644 Documentation/devicetree/bindings/arm/samsung-boards.txt create mode 100644 arch/arm/boot/dts/exynos4210-origen.dts create mode 100644 arch/arm/boot/dts/exynos4210-smdkv310.dts create mode 100644 arch/arm/boot/dts/exynos4210.dtsi create mode 100644 arch/arm/mach-exynos4/mach-exynos4-dt.c OK. replaced with this in next-samsung-dt branch. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 1/2] arm: samsung: support the second capability for hsmmc
Jaehoon Chung wrote:
Well...
Firstly, you need to add description here why this change is needed.
Secondly, you need to check latest maintainer's tree, in this case, the
dev-xxx.c are merged into plat-samsung/devs.c ago.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/plat-samsung/dev-hsmmc.c |2 ++
arch/arm/plat-samsung/dev-hsmmc1.c |2 ++
arch/arm/plat-samsung/dev-hsmmc2.c |2 ++
arch/arm/plat-samsung/dev-hsmmc3.c |2 ++
arch/arm/plat-samsung/include/plat/sdhci.h |1 +
5 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c
b/arch/arm/plat-samsung/dev-
hsmmc.c
index db7a65c..e6b0c58 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -74,6 +74,8 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata
*pd)
set-cfg_card = pd-cfg_card;
if (pd-host_caps)
set-host_caps |= pd-host_caps;
+ if (pd-host_caps2)
+ set-host_caps2 |= pd-host_caps2;
if (pd-clk_type)
set-clk_type = pd-clk_type;
}
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c
b/arch/arm/plat-samsung/dev-
hsmmc1.c
index 2497321..79a5ff2 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -74,6 +74,8 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata
*pd)
set-cfg_card = pd-cfg_card;
if (pd-host_caps)
set-host_caps |= pd-host_caps;
+ if (pd-host_caps2)
+ set-host_caps2 |= pd-host_caps2;
if (pd-clk_type)
set-clk_type = pd-clk_type;
}
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c
b/arch/arm/plat-samsung/dev-
hsmmc2.c
index f60aedb..a590d72 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -75,6 +75,8 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata
*pd)
set-cfg_card = pd-cfg_card;
if (pd-host_caps)
set-host_caps |= pd-host_caps;
+ if (pd-host_caps2)
+ set-host_caps2 |= pd-host_caps2;
if (pd-clk_type)
set-clk_type = pd-clk_type;
}
diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c
b/arch/arm/plat-samsung/dev-
hsmmc3.c
index ede776f..afa37c8 100644
--- a/arch/arm/plat-samsung/dev-hsmmc3.c
+++ b/arch/arm/plat-samsung/dev-hsmmc3.c
@@ -78,6 +78,8 @@ void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata
*pd)
set-cfg_card = pd-cfg_card;
if (pd-host_caps)
set-host_caps |= pd-host_caps;
+ if (pd-host_caps2)
+ set-host_caps2 |= pd-host_caps2;
if (pd-clk_type)
set-clk_type = pd-clk_type;
}
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-
samsung/include/plat/sdhci.h
index 058e096..7b48828 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -67,6 +67,7 @@ enum clk_types {
struct s3c_sdhci_platdata {
unsigned intmax_width;
unsigned inthost_caps;
+ unsigned inthost_caps2;
enum cd_types cd_type;
enum clk_types clk_type;
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RE: [PATCH 1/5] [CPUFREQ] EXYNOS4210: Remove code about bus on cpufreq
Kukjin Kim wrote:
From: Jongpill Lee boyko@samsung.com
This patch removes code for bus on cpufreq because the code
for bus frequency changing moves to busfreq driver.
So code about bus on cpufreq is not necessary.
Signed-off-by: Jongpill Lee boyko@samsung.com
Signed-off-by: SangWook Ju sw...@samsung.com
Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
drivers/cpufreq/exynos4210-cpufreq.c | 174
+-
1 files changed, 1 insertions(+), 173 deletions(-)
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
b/drivers/cpufreq/exynos4210-cpufreq.c
index b7c3a84..6ff3993 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -31,16 +31,8 @@ static struct clk *mout_mpll;
static struct clk *mout_apll;
static struct regulator *arm_regulator;
-static struct regulator *int_regulator;
static struct cpufreq_freqs freqs;
-static unsigned int memtype;
-
-enum exynos4_memory_type {
- DDR2 = 4,
- LPDDR2,
- DDR3,
-};
enum cpufreq_level_index {
L0, L1, L2, L3, CPUFREQ_LEVEL_END,
@@ -93,87 +85,24 @@ static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2]
=
{
{ 3, 0 },
};
-static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
- /*
- * Clock divider value for following
- * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
- * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
- */
-
- /* DMC L0: 400MHz */
- { 3, 1, 1, 1, 1, 1, 3, 1 },
-
- /* DMC L1: 400MHz */
- { 3, 1, 1, 1, 1, 1, 3, 1 },
-
- /* DMC L2: 266.7MHz */
- { 7, 1, 1, 2, 1, 1, 3, 1 },
-
- /* DMC L3: 200MHz */
- { 7, 1, 1, 3, 1, 1, 3, 1 },
-};
-
-static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
- /*
- * Clock divider value for following
- * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133,
DIVONENAND }
- */
-
- /* ACLK200 L0: 200MHz */
- { 3, 7, 4, 5, 1 },
-
- /* ACLK200 L1: 200MHz */
- { 3, 7, 4, 5, 1 },
-
- /* ACLK200 L2: 160MHz */
- { 4, 7, 5, 7, 1 },
-
- /* ACLK200 L3: 133.3MHz */
- { 5, 7, 7, 7, 1 },
-};
-
-static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
- /*
- * Clock divider value for following
- * { DIVGDL/R, DIVGPL/R }
- */
-
- /* ACLK_GDL/R L0: 200MHz */
- { 3, 1 },
-
- /* ACLK_GDL/R L1: 200MHz */
- { 3, 1 },
-
- /* ACLK_GDL/R L2: 160MHz */
- { 4, 1 },
-
- /* ACLK_GDL/R L3: 133.3MHz */
- { 5, 1 },
-};
-
struct cpufreq_voltage_table {
unsigned intindex; /* any */
unsigned intarm_volt; /* uV */
- unsigned intint_volt;
};
static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END]
=
{
{
.index = L0,
.arm_volt = 120,
- .int_volt = 110,
}, {
.index = L1,
.arm_volt = 110,
- .int_volt = 110,
}, {
.index = L2,
.arm_volt = 100,
- .int_volt = 100,
}, {
.index = L3,
.arm_volt = 90,
- .int_volt = 100,
},
};
@@ -242,80 +171,6 @@ static void exynos4_set_clkdiv(unsigned int
div_index)
do {
tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
} while (tmp 0x11);
-
- /* Change Divider - DMC0 */
-
- tmp = __raw_readl(S5P_CLKDIV_DMC0);
-
- tmp = ~(S5P_CLKDIV_DMC0_ACP_MASK |
S5P_CLKDIV_DMC0_ACPPCLK_MASK |
- S5P_CLKDIV_DMC0_DPHY_MASK |
S5P_CLKDIV_DMC0_DMC_MASK |
- S5P_CLKDIV_DMC0_DMCD_MASK |
S5P_CLKDIV_DMC0_DMCP_MASK |
- S5P_CLKDIV_DMC0_COPY2_MASK |
S5P_CLKDIV_DMC0_CORETI_MASK);
-
- tmp |= ((clkdiv_dmc0[div_index][0] S5P_CLKDIV_DMC0_ACP_SHIFT) |
- (clkdiv_dmc0[div_index][1]
S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
|
- (clkdiv_dmc0[div_index][2]
S5P_CLKDIV_DMC0_DPHY_SHIFT) |
- (clkdiv_dmc0[div_index][3] S5P_CLKDIV_DMC0_DMC_SHIFT)
|
- (clkdiv_dmc0[div_index][4]
S5P_CLKDIV_DMC0_DMCD_SHIFT) |
- (clkdiv_dmc0[div_index][5]
S5P_CLKDIV_DMC0_DMCP_SHIFT) |
- (clkdiv_dmc0[div_index][6]
S5P_CLKDIV_DMC0_COPY2_SHIFT) |
- (clkdiv_dmc0[div_index][7]
S5P_CLKDIV_DMC0_CORETI_SHIFT));
-
- __raw_writel(tmp, S5P_CLKDIV_DMC0);
-
- do {
- tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
- } while (tmp 0x);
-
- /* Change Divider - TOP */
-
- tmp = __raw_readl(S5P_CLKDIV_TOP);
-
- tmp = ~(S5P_CLKDIV_TOP_ACLK200_MASK |
S5P_CLKDIV_TOP_ACLK100_MASK |
- S5P_CLKDIV_TOP_ACLK160_MASK |
S5P_CLKDIV_TOP_ACLK133_MASK |
-
Re: [PATCH V4 0/4] Add SPI clkdev support
On Wed, Nov 02, 2011 at 05:06:40PM -0400, Padmavathi Venna wrote: This patchset modifies the existing clkdev to make SPI driver independent of the clock names send from platform data. No it does not. It modifies the clkdev lookup tables. When I read this I thought 'why are you modifying the clkdev stuff'. Only when I read the diffstat did it become clear that this was not the case. Please be more careful about describing your changes. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] gpio/samsung: Add device tree support for Exynos4
Hi Sylwester,
On 1 November 2011 13:52, Sylwester Nawrocki snj...@gmail.com wrote:
Hi Thomas,
thanks for your work on this.
On 11/01/2011 01:43 AM, Thomas Abraham wrote:
As gpio chips get registered, a device tree node which represents the
gpio chip is searched and attached to it. A translate function is also
provided to convert the gpio specifier into actual platform settings
for pin function selection, pull up/down and driver strength settings.
Signed-off-by: Thomas Abrahamthomas.abra...@linaro.org
Acked-by: Grant Likelygrant.lik...@secretlab.ca
---
Changes since v1:
- As suggested by Rob and Grant, the gpio controller node lookup is based
on the base address of the gpio controller instead of the unique
per-controller compatible property value.
This patch is based on the following tree and branch.
git://git.linaro.org/git/people/arnd/arm-soc.git branch: for-next
.../devicetree/bindings/gpio/gpio-samsung.txt | 40
drivers/gpio/gpio-samsung.c | 66
2 files changed, 106 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpio/gpio-samsung.txt
diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
new file mode 100644
index 000..c143058
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
@@ -0,0 +1,40 @@
+Samsung Exynos4 GPIO Controller
+
+Required properties:
+- compatible: Compatible property value should be samsung,exynos4-gpio.
+
+- reg: Physical base address of the controller and length of memory mapped
+ region.
+
+- #gpio-cells: Should be 4. The syntax of the gpio specifier used by client
nodes
+ should be the following with values derived from the SoC user manual.
+[phandle of the gpio controller node]
+ [pin number within the gpio controller]
+ [mux function]
+ [pull up/down]
+ [drive strength]
+
+ Values for gpio specifier:
+ - Pin number: is a value between 0 to 7.
+ - Pull Up/Down: 0 - Pull Up/Down Disabled.
+ 1 - Pull Down Enabled.
+ 3 - Pull Up Enabled.
+ - Drive Strength: 0 - 1x,
+ 1 - 3x,
+ 2 - 2x,
+ 3 - 4x
I wonder whether it's worth to have more regular mapping, i.e.
*) 0 - 1x,
1 - 2x,
2 - 3x,
3 - 4x
It doesn't give as much advantage, and introduces an overhead of doing
an additional remapping. However I find current mapping of the DT specifier
values to real driver strength slightly confusing.
Perhaps unlikely, the future SoCs could have different meaning of the
register values.
The dts file describes the hardware and the drive strength values
listed above are as per the Exynos4 SoC user manual. I would prefer to
do it the way you suggested, but that would mean dts is not exactly
matching the hardware manual.
[...]
+ };
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 8662518..0140756 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
[...]
+ if (gc-of_gpio_n_cells 4) {
+ WARN_ON(1);
+ return -EINVAL;
+ }
nit: Could be simplified to:
if (WARN_ON(gc-of_gpio_n_cells 4))
return -EINVAL;
Ok.
+
+ if (n gc-ngpio)
+ return -EINVAL;
+
+ s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(be32_to_cpu(gpio[1])));
+ s3c_gpio_setpull(pin, be32_to_cpu(gpio[2]));
+ s5p_gpio_set_drvstr(pin, be32_to_cpu(gpio[3]));
The above functions can fail and IMHO ignoring the return value here
makes the system harder to debug.
Ok.
Assuming GPIO drive strength specifier mapping *) the following code could
do the remapping (not tested):
unsigned int tmp = be32_to_cpu(gpio[3]);
u32 drvstr = ((tmp 1) ^ tmp) 1 ? ~tmp 3 : tmp;
s5p_gpio_set_drvstr(pin, drvstr);
+ return n;
+}
+
+static const struct of_device_id exynos4_gpio_dt_match[] __initdata = {
+ { .compatible = samsung,exynos4-gpio, },
+ {}
+};
+
+static __init void exynos4_gpiolib_attach_ofnode(struct samsung_gpio_chip
*chip,
+ u64 base, u64 offset)
+{
+ struct gpio_chip *gc =chip-chip;
+ u64 address;
+
+ if (!of_have_populated_dt())
+ return;
+
+ address = (chip-base) ? (base + ((u32)chip-base 0xfff)) :
+ (base + offset);
Could the extra parentheses be dropped ?
Can I postpone these changes for now so that this patch gets merged in
next-samsung-dt branch. I believe these are required changes but could
be done a little later.
Thanks for your review and comments on this patch.
Regards,
Thomas.
--
Regards,
Sylwester
--
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Re: [PATCH v2] gpio/samsung: Add device tree support for Exynos4
Hi Mr. Kim, On 2 November 2011 17:25, Kukjin Kim kgene@samsung.com wrote: Thomas Abraham wrote: As gpio chips get registered, a device tree node which represents the gpio chip is searched and attached to it. A translate function is also provided to convert the gpio specifier into actual platform settings for pin function selection, pull up/down and driver strength settings. Signed-off-by: Thomas Abraham thomas.abra...@linaro.org Acked-by: Grant Likely grant.lik...@secretlab.ca --- Changes since v1: - As suggested by Rob and Grant, the gpio controller node lookup is based on the base address of the gpio controller instead of the unique per-controller compatible property value. This patch is based on the following tree and branch. git://git.linaro.org/git/people/arnd/arm-soc.git branch: for-next .../devicetree/bindings/gpio/gpio-samsung.txt | 40 drivers/gpio/gpio-samsung.c | 66 2 files changed, 106 insertions(+), 0 deletions(-) create mode 100644 [...] diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c index 8662518..0140756 100644 --- a/drivers/gpio/gpio-samsung.c +++ b/drivers/gpio/gpio-samsung.c [...] Thomas, Happens following build error. drivers/gpio/gpio-samsung.c: In function 'samsung_gpiolib_init': drivers/gpio/gpio-samsung.c:2519: error: 'EXYNOS4_PA_GPIO1' undeclared (first use in this function) drivers/gpio/gpio-samsung.c:2519: error: (Each undeclared identifier is reported only once drivers/gpio/gpio-samsung.c:2519: error: for each function it appears in.) drivers/gpio/gpio-samsung.c:2533: error: 'EXYNOS4_PA_GPIO2' undeclared (first use in this function) drivers/gpio/gpio-samsung.c:2547: error: 'EXYNOS4_PA_GPIO3' undeclared (first use in this function) Can this be fixed while you apply this patch. If required, I can submit an updated patch for this. Thanks, Thomas. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] gpio/samsung: Add device tree support for Exynos4
On Wed, Nov 02, 2011 at 06:35:05PM +0530, Thomas Abraham wrote: On 1 November 2011 13:52, Sylwester Nawrocki snj...@gmail.com wrote: It doesn't give as much advantage, and introduces an overhead of doing an additional remapping. However I find current mapping of the DT specifier values to real driver strength slightly confusing. Perhaps unlikely, the future SoCs could have different meaning of the register values. The dts file describes the hardware and the drive strength values listed above are as per the Exynos4 SoC user manual. I would prefer to do it the way you suggested, but that would mean dts is not exactly matching the hardware manual. On the other hand it does mean that the user can directly read the values - there's nothing that obviously tells the user that the binding is using datasheet register values rather than the actual driver strength numbers and given that software is supposed to provide an abstraction to make things easier it seems reasonably natural to assume the latter. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/6] mmc: sdhci-s3c: Remove usage of clk_type member in platform data
SDHCI controllers on Exynos4 do not include the sdclk divider as per the
sdhci controller specification. This case can be represented using the
sdhci quirk SDHCI_QUIRK_NONSTANDARD_CLOCK instead of using an additional
enum type definition 'clk_types'.
Hence, usage of clk_type member in platform data is removed and the sdhci
quirk is used. In addition to that, since this qurik is SoC specific,
driver data is introduced to represent controllers on SoC's that require
this quirk.
Cc: Ben Dooks ben-li...@fluff.org
Cc: Jeongbae Seo jeongbae@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
drivers/mmc/host/sdhci-s3c.c | 74 +++--
1 files changed, 70 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 7551468..141fbbf 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -53,6 +53,18 @@ struct sdhci_s3c {
struct clk *clk_bus[MAX_BUS_CLK];
};
+/**
+ * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
+ * @sdhci_quirks: sdhci host specific quirks.
+ *
+ * Specifies platform specific configuration of sdhci controller.
+ * Note: A structure for driver specific platform data is used for future
+ * expansion of its usage.
+ */
+struct sdhci_s3c_drv_data {
+ unsigned intsdhci_quirks;
+};
+
static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
{
return sdhci_priv(host);
@@ -132,10 +144,10 @@ static unsigned int sdhci_s3c_consider_clock(struct
sdhci_s3c *ourhost,
return UINT_MAX;
/*
-* Clock divider's step is different as 1 from that of host controller
-* when 'clk_type' is S3C_SDHCI_CLK_DIV_EXTERNAL.
+* If controller uses a non-standard clock division, find the best clock
+* speed possible with selected clock source and skip the division.
*/
- if (ourhost-pdata-clk_type) {
+ if (ourhost-host-quirks SDHCI_QUIRK_NONSTANDARD_CLOCK) {
rate = clk_round_rate(clksrc, wanted);
return wanted - rate;
}
@@ -272,6 +284,8 @@ static unsigned int sdhci_cmu_get_min_clock(struct
sdhci_host *host)
static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
{
struct sdhci_s3c *ourhost = to_s3c(host);
+ unsigned long timeout;
+ u16 clk = 0;
/* don't bother if the clock is going off */
if (clock == 0)
@@ -282,6 +296,25 @@ static void sdhci_cmu_set_clock(struct sdhci_host *host,
unsigned int clock)
clk_set_rate(ourhost-clk_bus[ourhost-cur_clk], clock);
host-clock = clock;
+
+ clk = SDHCI_CLOCK_INT_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ /* Wait max 20 ms */
+ timeout = 20;
+ while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
+SDHCI_CLOCK_INT_STABLE)) {
+ if (timeout == 0) {
+ printk(KERN_ERR %s: Internal clock never
+ stabilised.\n, mmc_hostname(host-mmc));
+ return;
+ }
+ timeout--;
+ mdelay(1);
+ }
+
+ clk |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
}
/**
@@ -382,9 +415,17 @@ static void sdhci_s3c_setup_card_detect_gpio(struct
sdhci_s3c *sc)
}
}
+static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
+ struct platform_device *pdev)
+{
+ return (struct sdhci_s3c_drv_data *)
+ platform_get_device_id(pdev)-driver_data;
+}
+
static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
{
struct s3c_sdhci_platdata *pdata = pdev-dev.platform_data;
+ struct sdhci_s3c_drv_data *drv_data;
struct device *dev = pdev-dev;
struct sdhci_host *host;
struct sdhci_s3c *sc;
@@ -414,6 +455,7 @@ static int __devinit sdhci_s3c_probe(struct platform_device
*pdev)
return PTR_ERR(host);
}
+ drv_data = sdhci_s3c_get_driver_data(pdev);
sc = sdhci_priv(host);
sc-host = host;
@@ -491,6 +533,8 @@ static int __devinit sdhci_s3c_probe(struct platform_device
*pdev)
/* Setup quirks for the controller */
host-quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
+ if (drv_data)
+ host-quirks |= drv_data-sdhci_quirks;
#ifndef CONFIG_MMC_SDHCI_S3C_DMA
@@ -531,7 +575,7 @@ static int __devinit sdhci_s3c_probe(struct platform_device
*pdev)
* If controller does not have internal clock divider,
* we can use overriding functions instead of default.
*/
- if (pdata-clk_type) {
+ if (host-quirks SDHCI_QUIRK_NONSTANDARD_CLOCK) {
sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
sdhci_s3c_ops.get_min_clock =
[PATCH 0/6] mmc: sdhci-s3c: Rework platform data and add device tree support.
This patchset removes all uses of 'clk_type' member from the platform data of sdhci-s3c driver and adds device tree support for sdhci-s3c driver. This patchset has merged the following two patchsets submitted earlier into one patchset. [PATCH 0/3] mmc: sdhci-s3c: Remove 'clk_type' member from platform data [PATCH 0/3] mmc: sdhci-s3c: Add device tree support for Samsung's sdhci controller driver This patchset is rebased over the patches for sdhci clock lookup using generic names. In this patchset, all uses of 'clk_type' member from the platform data are removed from the sdhci-s3c driver and platform code. The clk_type is a SoC specific information and not a board/machine specific information. Hence, this information can be more aptly represented using SoC specific driver data in the sdhci-s3c driver. Hence all uses of 'clk_type' member in sdhci-s3c driver's platform data is removed. In place of that, the sdhci host qurik 'SDHCI_QUIRK_NONSTANDARD_CLOCK' is used to handle controllers that do not have a standard sdclk division (like those in the exynos4 SoC's). This is a pre-requisite for adding device tree support for sdhci-s3c driver. While migrating towards device tree support, retreving 'clk_type' information from device tree information does not seem correct and hence it has been added as SoC specific driver data. All this is handled in patches 1 to 3. Patch 4 to 6 add device tree support for sdhci-s3c driver. The fourth patch modifies the sdhci-s3c driver to mainatain a local copy of the platform data, which makes it easier to add device tree support for the driver. Fifth patch adds support for parsing of mmc host controller capabilities from a device node. This code would be reusable across other platforms as well. The last patch adds device tree based discovery for the sdhci-s3c driver. In this patchset, the comments from Rob Herring for the fifth patch in this series has been addressed. This patchset is based on the following tree. https://github.com/kgene/linux-samsung.git branch: next-samsung-dt Thomas Abraham (6): mmc: sdhci-s3c: Remove usage of clk_type member in platform data arm: exynos4: use 'exynos4-sdhci' as device name for sdhci controllers arm: samsung: remove all uses of clk_type member in sdhci platform data mmc: sdhci-s3c: Keep a copy of platform data and use it mmc: Add OF bindings support for mmc host controller capabilities mmc: sdhci-s3c: Add device tree support .../devicetree/bindings/mmc/linux-mmc-host.txt | 13 + .../devicetree/bindings/mmc/samsung-sdhci.txt | 75 +++ arch/arm/mach-exynos4/clock.c | 24 +- arch/arm/mach-exynos4/cpu.c|5 + arch/arm/mach-exynos4/mach-armlex4210.c|3 - arch/arm/mach-exynos4/mach-nuri.c |3 - arch/arm/mach-exynos4/mach-origen.c|2 - arch/arm/mach-exynos4/mach-smdk4x12.c |2 - arch/arm/mach-exynos4/mach-smdkv310.c |4 - arch/arm/mach-exynos4/mach-universal_c210.c|2 - arch/arm/plat-samsung/devs.c |4 - arch/arm/plat-samsung/include/plat/sdhci.h | 34 +++- arch/arm/plat-samsung/platformdata.c |2 - drivers/mmc/core/host.c| 31 +++ drivers/mmc/host/sdhci-s3c.c | 231 +++- include/linux/mmc/host.h |1 + 16 files changed, 386 insertions(+), 50 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/linux-mmc-host.txt create mode 100644 Documentation/devicetree/bindings/mmc/samsung-sdhci.txt -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/6] arm: exynos4: use 'exynos4-sdhci' as device name for sdhci controllers
With the addition of platform specific driver data in the sdhci driver
for exynos4, the device name of sdhci controllers on exynos4 is changed
accordingly.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/mach-exynos4/clock.c | 24
arch/arm/mach-exynos4/cpu.c|5 +
arch/arm/plat-samsung/include/plat/sdhci.h | 27 +++
3 files changed, 44 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 6eeabdd..94fc337 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -495,25 +495,25 @@ static struct clk init_clocks_off[] = {
.ctrlbit= (1 0),
}, {
.name = hsmmc,
- .devname= s3c-sdhci.0,
+ .devname= exynos4-sdhci.0,
.parent = clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit= (1 5),
}, {
.name = hsmmc,
- .devname= s3c-sdhci.1,
+ .devname= exynos4-sdhci.1,
.parent = clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit= (1 6),
}, {
.name = hsmmc,
- .devname= s3c-sdhci.2,
+ .devname= exynos4-sdhci.2,
.parent = clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit= (1 7),
}, {
.name = hsmmc,
- .devname= s3c-sdhci.3,
+ .devname= exynos4-sdhci.3,
.parent = clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit= (1 8),
@@ -1221,7 +1221,7 @@ static struct clksrc_clk clk_sclk_uart3 = {
static struct clksrc_clk clk_sclk_mmc0 = {
.clk= {
.name = sclk_mmc,
- .devname= s3c-sdhci.0,
+ .devname= exynos4-sdhci.0,
.parent = clk_dout_mmc0.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit= (1 0),
@@ -1232,7 +1232,7 @@ static struct clksrc_clk clk_sclk_mmc0 = {
static struct clksrc_clk clk_sclk_mmc1 = {
.clk= {
.name = sclk_mmc,
- .devname= s3c-sdhci.1,
+ .devname= exynos4-sdhci.1,
.parent = clk_dout_mmc1.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit= (1 4),
@@ -1243,7 +1243,7 @@ static struct clksrc_clk clk_sclk_mmc1 = {
static struct clksrc_clk clk_sclk_mmc2 = {
.clk= {
.name = sclk_mmc,
- .devname= s3c-sdhci.2,
+ .devname= exynos4-sdhci.2,
.parent = clk_dout_mmc2.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit= (1 8),
@@ -1254,7 +1254,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
static struct clksrc_clk clk_sclk_mmc3 = {
.clk= {
.name = sclk_mmc,
- .devname= s3c-sdhci.3,
+ .devname= exynos4-sdhci.3,
.parent = clk_dout_mmc3.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit= (1 12),
@@ -1317,10 +1317,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
CLKDEV_INIT(exynos4210-uart.1, clk_uart_baud0, clk_sclk_uart1.clk),
CLKDEV_INIT(exynos4210-uart.2, clk_uart_baud0, clk_sclk_uart2.clk),
CLKDEV_INIT(exynos4210-uart.3, clk_uart_baud0, clk_sclk_uart3.clk),
- CLKDEV_INIT(s3c-sdhci.0, mmc_busclk.2, clk_sclk_mmc0.clk),
- CLKDEV_INIT(s3c-sdhci.1, mmc_busclk.2, clk_sclk_mmc1.clk),
- CLKDEV_INIT(s3c-sdhci.2, mmc_busclk.2, clk_sclk_mmc2.clk),
- CLKDEV_INIT(s3c-sdhci.3, mmc_busclk.2, clk_sclk_mmc3.clk),
+ CLKDEV_INIT(exynos4-sdhci.0, mmc_busclk.2, clk_sclk_mmc0.clk),
+ CLKDEV_INIT(exynos4-sdhci.1, mmc_busclk.2, clk_sclk_mmc1.clk),
+ CLKDEV_INIT(exynos4-sdhci.2, mmc_busclk.2, clk_sclk_mmc2.clk),
+ CLKDEV_INIT(exynos4-sdhci.3, mmc_busclk.2, clk_sclk_mmc3.clk),
CLKDEV_INIT(dma-pl330.0, apb_pclk, clk_pdma0),
CLKDEV_INIT(dma-pl330.1, apb_pclk, clk_pdma1),
};
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 6ac9baf..152c8b1 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -195,6 +195,11 @@ void __init exynos4_map_io(void)
[PATCH 5/6] mmc: Add OF bindings support for mmc host controller capabilities
Device nodes representing sd/mmc controllers in a device tree would include
mmc host controller capabilities. Add support for parsing of mmc host
controller capabilities included in device nodes.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
.../devicetree/bindings/mmc/linux-mmc-host.txt | 13
drivers/mmc/core/host.c| 31
include/linux/mmc/host.h |1 +
3 files changed, 45 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/linux-mmc-host.txt
diff --git a/Documentation/devicetree/bindings/mmc/linux-mmc-host.txt
b/Documentation/devicetree/bindings/mmc/linux-mmc-host.txt
new file mode 100644
index 000..714b2b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/linux-mmc-host.txt
@@ -0,0 +1,13 @@
+* Linux MMC Host Controller Capabilities
+
+The following bindings can be used in a device node to specify any board
+specific mmc host controller capabilities.
+
+- linux,mmc_cap_4_bit_data - Host can do 4-bit transfers
+- linux,mmc_cap_mmc_highspeed - Host can do MMC high-speed timing
+- linux,mmc_cap_sd_highspeed - Host can do SD high-speed timing
+- linux,mmc_cap_needs_poll - Host needs polling for card detection
+- linux,mmc_cap_8_bit_data - Host can do 8-bit transfer
+- linux,mmc_cap_disable - Host can be disabled and re-enabled to save power
+- linux,mmc_cap_nonremovable - Host is connected to nonremovable media
+- linux,mmc_cap_erase - Host allows erase/trim commands
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index ca2e4f5..aabf440 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -19,6 +19,7 @@
#include linux/leds.h
#include linux/slab.h
#include linux/suspend.h
+#include linux/of.h
#include linux/mmc/host.h
#include linux/mmc/card.h
@@ -396,3 +397,33 @@ void mmc_free_host(struct mmc_host *host)
}
EXPORT_SYMBOL(mmc_free_host);
+
+#ifdef CONFIG_OF
+/**
+ * mmc_of_parse_host_caps - parse mmc host capabilities from device node
+ * @np: pointer to device node in device tree
+ * @caps: pointer to host caps value to be returned
+ *
+ * Search the device node in device tree for mmc host capabilities.
+ */
+void mmc_of_parse_host_caps(struct device_node *np, unsigned long *caps)
+{
+ if (of_find_property(np, linux,mmc_cap_4_bit_data, NULL))
+ *caps |= MMC_CAP_4_BIT_DATA;
+ if (of_find_property(np, linux,mmc_cap_mmc_highspeed, NULL))
+ *caps |= MMC_CAP_MMC_HIGHSPEED;
+ if (of_find_property(np, linux,mmc_cap_sd_highspeed, NULL))
+ *caps |= MMC_CAP_SD_HIGHSPEED;
+ if (of_find_property(np, linux,mmc_cap_needs_poll, NULL))
+ *caps |= MMC_CAP_NEEDS_POLL;
+ if (of_find_property(np, linux,mmc_cap_8_bit_data, NULL))
+ *caps |= MMC_CAP_8_BIT_DATA;
+ if (of_find_property(np, linux,mmc_cap_disable, NULL))
+ *caps |= MMC_CAP_DISABLE;
+ if (of_find_property(np, linux,mmc_cap_nonremovable, NULL))
+ *caps |= MMC_CAP_NONREMOVABLE;
+ if (of_find_property(np, linux,mmc_cap_erase, NULL))
+ *caps |= MMC_CAP_ERASE;
+}
+EXPORT_SYMBOL(mmc_of_parse_host_caps);
+#endif /* CONFIG_OF */
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index a3ac9c4..c81c6e8 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -330,6 +330,7 @@ extern struct mmc_host *mmc_alloc_host(int extra, struct
device *);
extern int mmc_add_host(struct mmc_host *);
extern void mmc_remove_host(struct mmc_host *);
extern void mmc_free_host(struct mmc_host *);
+extern void mmc_of_parse_host_caps(struct device_node *np, unsigned long
*caps);
static inline void *mmc_priv(struct mmc_host *host)
{
--
1.6.6.rc2
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[PATCH 6/6] mmc: sdhci-s3c: Add device tree support
Add device tree based discovery support for Samsung's sdhci controller
Cc: Ben Dooks ben-li...@fluff.org
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
.../devicetree/bindings/mmc/samsung-sdhci.txt | 75 ++
drivers/mmc/host/sdhci-s3c.c | 152 +++-
2 files changed, 221 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/samsung-sdhci.txt
diff --git a/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt
b/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt
new file mode 100644
index 000..a6dd6bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt
@@ -0,0 +1,75 @@
+* Samsung's SDHCI Controller device tree bindings
+
+Samsung's SDHCI controller is used as a connectivity interface with external
+MMC, SD and eMMC storage mediums.
+
+Required SoC Specific Properties:
+- compatible: should be one of the following
+ - samsung,s3c6410-sdhci: For controllers compatible with s3c6410 sdhci
+controller.
+ - samsung,exynos4210-sdhci: For controller compatible with Exynos4 sdhci
+controller.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- interrupts: The interrupt number to the cpu. The interrupt specifier format
+ depends on the interrupt controller.
+
+
+Required Board Specific Properties:
+- gpios: Should specify the gpios used for clock, command and data lines. The
+ gpio specifier format depends on the gpio controller. Note: There is no
+ particular order in which the gpio's have to be listed.
+
+
+Optional Board Specific Properties:
+- samsung,sdhci-bus-width: Number of data lines connected to the controller.
+ Note: This excludes the clock,command and card detect lines. If this property
+ is not specified, default value is 1.
+
+- samsung,cd-gpio-invert: If 'samsung,sdhci-cd-gpio' card detect method is
+ selected, this property can be optionally specified to invert the value of
+ external card detect gpio line.
+
+- One of the following properties for card detect type.
+ - samsung,sdhci-cd-internal: Card detect line from the card slot is
+connected to the card detect pad of the sdhci controller. A gpio is
+used for this connection (with possible pin function settings).
+ - samsung,sdhci-cd-gpio: A gpio line (with possible pin function settings)
+is used a card detect line. This gpio line is not connected to card detect
+pad of the sdhci controller.
+ - samsung,sdhci-cd-none: There is no card detect line. Polling is used to
+detect the presence of the card. (DEFAULT, if no card detect property
+is specified).
+ - samsung,sdhci-cd-permanent: There is no card detect line. The card is
+permanently connected to the sdhci controller.
+
+- gpio-cd: The gpio to be used as card detect line for
+ 'samsung,sdhci-cd-internal' or 'samsung,sdhci-cd-gpio' card detection method.
+ The gpio specifier format depends on the gpio controller.
+
+- One or more of the linux specific mmc host bindings.
+ See Documentation/devicetree/bindings/mmc/linux-mmc-host.txt for all the
+ linux mmc host controller specific bindings.
+
+Example:
+ sdhci@1253 {
+ compatible = samsung,exynos4210-sdhci;
+ reg = 0x1253 0x100;
+ interrupts = 139;
+ samsung,sdhci-bus-width = 4;
+ linux,mmc_cap_4_bit_data;
+ samsung,sdhci-cd-internal;
+ gpio-cd = gpk2 2 2 3 3;
+ gpios = gpk2 0 2 0 3, /* clock line */
+ gpk2 1 2 0 3, /* command line */
+ gpk2 3 2 3 3, /* data line 0 */
+ gpk2 4 2 3 3, /* data line 1 */
+ gpk2 5 2 3 3, /* data line 2 */
+ gpk2 6 2 3 3; /* data line 3 */
+ };
+
+ Note: This example shows both SoC specific and board specific properties
+ in a single device node. The properties can be actually be seperated
+ into SoC specific node and board specific node.
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index c77ec42..e77e301 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -20,6 +20,8 @@
#include linux/io.h
#include linux/gpio.h
#include linux/module.h
+#include linux/of.h
+#include linux/of_gpio.h
#include linux/mmc/host.h
@@ -29,6 +31,8 @@
#include sdhci.h
#define MAX_BUS_CLK(4)
+/* Number of gpio's used is max data bus width + command and clock lines */
+#define NUM_GPIOS(x) (x + 2)
/**
* struct sdhci_s3c - S3C SDHCI instance
@@ -48,6 +52,7 @@ struct sdhci_s3c {
unsigned intcur_clk;
int ext_cd_irq;
int ext_cd_gpio;
+ int *gpios;
struct clk *clk_io;
struct clk *clk_bus[MAX_BUS_CLK];
@@ -415,9 +420,112 @@ static void
[PATCH 4/6] mmc: sdhci-s3c: Keep a copy of platform data and use it
The platform data is copied into driver's private data and the copy is
used for all access to the platform data. This simpifies the addition
of device tree support for the sdhci-s3c driver.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
drivers/mmc/host/sdhci-s3c.c | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 141fbbf..c77ec42 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -424,7 +424,7 @@ static inline struct sdhci_s3c_drv_data
*sdhci_s3c_get_driver_data(
static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
{
- struct s3c_sdhci_platdata *pdata = pdev-dev.platform_data;
+ struct s3c_sdhci_platdata *pdata;
struct sdhci_s3c_drv_data *drv_data;
struct device *dev = pdev-dev;
struct sdhci_host *host;
@@ -432,7 +432,7 @@ static int __devinit sdhci_s3c_probe(struct platform_device
*pdev)
struct resource *res;
int ret, irq, ptr, clks;
- if (!pdata) {
+ if (!pdev-dev.platform_data) {
dev_err(dev, no device data specified\n);
return -ENOENT;
}
@@ -455,6 +455,13 @@ static int __devinit sdhci_s3c_probe(struct
platform_device *pdev)
return PTR_ERR(host);
}
+ pdata = devm_kzalloc(pdev-dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata) {
+ ret = -ENOMEM;
+ goto err_io_clk;
+ }
+ memcpy(pdata, pdev-dev.platform_data, sizeof(*pdata));
+
drv_data = sdhci_s3c_get_driver_data(pdev);
sc = sdhci_priv(host);
--
1.6.6.rc2
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[PATCH 3/6] arm: samsung: remove all uses of clk_type member in sdhci platform data
The sdhci driver is modified to be independent of clk_type member in the sdhci
platform data. Hence, all usage of clk_type in platform code is removed.
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: JeongHyeon Kim jh...@insignal.co.kr
Cc: Kukjin Kim kgene@samsung.com
Cc: Changhwan Youn chaos.y...@samsung.com
Cc: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/mach-exynos4/mach-armlex4210.c |3 ---
arch/arm/mach-exynos4/mach-nuri.c |3 ---
arch/arm/mach-exynos4/mach-origen.c |2 --
arch/arm/mach-exynos4/mach-smdk4x12.c |2 --
arch/arm/mach-exynos4/mach-smdkv310.c |4
arch/arm/mach-exynos4/mach-universal_c210.c |2 --
arch/arm/plat-samsung/devs.c|4
arch/arm/plat-samsung/include/plat/sdhci.h |7 ---
arch/arm/plat-samsung/platformdata.c|2 --
9 files changed, 0 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-exynos4/mach-armlex4210.c
b/arch/arm/mach-exynos4/mach-armlex4210.c
index f0ca6c1..426b9d2 100644
--- a/arch/arm/mach-exynos4/mach-armlex4210.c
+++ b/arch/arm/mach-exynos4/mach-armlex4210.c
@@ -75,7 +75,6 @@ static struct s3c2410_uartcfg armlex4210_uartcfgs[]
__initdata = {
static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
.cd_type= S3C_SDHCI_CD_PERMANENT,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
.max_width = 8,
.host_caps = MMC_CAP_8_BIT_DATA,
@@ -86,13 +85,11 @@ static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata
__initdata = {
.cd_type= S3C_SDHCI_CD_GPIO,
.ext_cd_gpio= EXYNOS4_GPX2(5),
.ext_cd_gpio_invert = 1,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
.max_width = 4,
};
static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
.cd_type= S3C_SDHCI_CD_PERMANENT,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
.max_width = 4,
};
diff --git a/arch/arm/mach-exynos4/mach-nuri.c
b/arch/arm/mach-exynos4/mach-nuri.c
index 236bbe1..4abf4e4 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -109,7 +109,6 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data
__initdata = {
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_DISABLE | MMC_CAP_ERASE),
.cd_type= S3C_SDHCI_CD_PERMANENT,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct regulator_consumer_supply emmc_supplies[] = {
@@ -151,7 +150,6 @@ static struct s3c_sdhci_platdata nuri_hsmmc2_data
__initdata = {
.ext_cd_gpio= EXYNOS4_GPX3(3), /* XEINT_27 */
.ext_cd_gpio_invert = 1,
.cd_type= S3C_SDHCI_CD_GPIO,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
/* WLAN */
@@ -160,7 +158,6 @@ static struct s3c_sdhci_platdata nuri_hsmmc3_data
__initdata = {
.host_caps = MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
.cd_type= S3C_SDHCI_CD_EXTERNAL,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static void __init nuri_sdhci_init(void)
diff --git a/arch/arm/mach-exynos4/mach-origen.c
b/arch/arm/mach-exynos4/mach-origen.c
index f80b563..47efb34 100644
--- a/arch/arm/mach-exynos4/mach-origen.c
+++ b/arch/arm/mach-exynos4/mach-origen.c
@@ -465,12 +465,10 @@ static struct i2c_board_info i2c0_devs[] __initdata = {
static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
.cd_type= S3C_SDHCI_CD_INTERNAL,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
.cd_type= S3C_SDHCI_CD_INTERNAL,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
/* USB EHCI */
diff --git a/arch/arm/mach-exynos4/mach-smdk4x12.c
b/arch/arm/mach-exynos4/mach-smdk4x12.c
index fcf2e0e..96c60df 100644
--- a/arch/arm/mach-exynos4/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos4/mach-smdk4x12.c
@@ -83,7 +83,6 @@ static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata
= {
static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
.cd_type= S3C_SDHCI_CD_INTERNAL,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
.max_width = 8,
.host_caps = MMC_CAP_8_BIT_DATA,
@@ -92,7 +91,6 @@ static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata
__initdata = {
static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
.cd_type=
Re: [PATCH V6] SDHCI: S3C: Use generic clock names for sdhci bus clock options
On 31 October 2011 11:14, Rajeshwari Shinde rajeshwar...@samsung.com wrote: This patch modifies the driver to stop depending on the clock names being passed from the platform and switch over to bus clock lookup using generic clock names. V6 Changes: Changed sprintf to snprintf as suggested by Chris Ball. The above two lines can be removed from the commit message. Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com --- drivers/mmc/host/sdhci-s3c.c | 7 ++- 1 files changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c index 82709b6..488223c 100644 --- a/drivers/mmc/host/sdhci-s3c.c +++ b/drivers/mmc/host/sdhci-s3c.c @@ -435,14 +435,11 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev) [...] -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 2/2] mmc: core: Support packed command for eMMC4.5 device
S, Venkatraman svenk...@ti.com wrote:
On Wed, Nov 2, 2011 at 1:33 PM, Seungwon Jeon tgih@samsung.com wrote:
This patch supports packed command of eMMC4.5 device.
Several reads(or writes) can be grouped in packed command
and all data of the individual commands can be sent in a
single transfer on the bus.
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
drivers/mmc/card/block.c | 355
--
drivers/mmc/card/queue.c | 48 ++-
drivers/mmc/card/queue.h | 12 ++
include/linux/mmc/core.h | 3 +
4 files changed, 404 insertions(+), 14 deletions(-)
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index a1cb21f..6c49656 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -59,6 +59,13 @@ MODULE_ALIAS(mmc:block);
#define INAND_CMD38_ARG_SECTRIM1 0x81
#define INAND_CMD38_ARG_SECTRIM2 0x88
+#define mmc_req_rel_wr(req) (((req-cmd_flags REQ_FUA) || \
+ (req-cmd_flags REQ_META)) \
+ (rq_data_dir(req) == WRITE))
+#define PACKED_CMD_VER 0x01
+#define PACKED_CMD_RD 0x01
+#define PACKED_CMD_WR 0x02
+
static DEFINE_MUTEX(block_mutex);
/*
@@ -943,7 +950,8 @@ static int mmc_blk_err_check(struct mmc_card *card,
* kind. If it was a write, we may have transitioned to
* program mode, which we have to wait for it to complete.
*/
- if (!mmc_host_is_spi(card-host) rq_data_dir(req) != READ) {
+ if ((!mmc_host_is_spi(card-host) rq_data_dir(req) != READ) ||
+ (mq_mrq-packed_cmd == MMC_PACKED_WR_HDR)) {
u32 status;
do {
int err = get_card_status(card, status, 5);
@@ -980,12 +988,67 @@ static int mmc_blk_err_check(struct mmc_card *card,
if (!brq-data.bytes_xfered)
return MMC_BLK_RETRY;
+ if (mq_mrq-packed_cmd != MMC_PACKED_NONE) {
+ if (unlikely(brq-data.blocks 9 !=
brq-data.bytes_xfered))
+ return MMC_BLK_PARTIAL;
+ else
+ return MMC_BLK_SUCCESS;
+ }
+
if (blk_rq_bytes(req) != brq-data.bytes_xfered)
return MMC_BLK_PARTIAL;
return MMC_BLK_SUCCESS;
}
+static int mmc_blk_packed_err_check(struct mmc_card *card,
+ struct mmc_async_req *areq)
+{
+ struct mmc_queue_req *mq_mrq = container_of(areq, struct
mmc_queue_req,
+ mmc_active);
+ int err, check, status;
+ u8 ext_csd[512];
+
+ check = mmc_blk_err_check(card, areq);
+
+ if (check == MMC_BLK_SUCCESS)
+ return check;
+
+ if (check == MMC_BLK_PARTIAL) {
+ err = get_card_status(card, status, 0);
+ if (err)
+ return MMC_BLK_ABORT;
+
+ if (status R1_EXP_EVENT) {
+ err = mmc_send_ext_csd(card, ext_csd);
+ if (err)
+ return MMC_BLK_ABORT;
+
+ if ((ext_csd[EXT_CSD_EXP_EVENTS_STATUS + 0]
+ EXT_CSD_PACKED_FAILURE)
+ (ext_csd[EXT_CSD_PACKED_CMD_STATUS]
+ EXT_CSD_PACKED_GENERIC_ERROR)) {
+ if (ext_csd[EXT_CSD_PACKED_CMD_STATUS]
+
EXT_CSD_PACKED_INDEXED_ERROR) {
+ /* Make be 0-based */
+ mq_mrq-packed_fail_idx =
+
ext_csd[EXT_CSD_PACKED_FAILURE_INDEX] - 1;
+ return MMC_BLK_PARTIAL;
+ } else {
+ return MMC_BLK_RETRY;
+ }
+ }
+ } else {
+ return MMC_BLK_RETRY;
+ }
+ }
+
+ if (check != MMC_BLK_ABORT)
+ return MMC_BLK_RETRY;
+ else
+ return MMC_BLK_ABORT;
+}
+
static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq,
struct mmc_card *card,
int disable_multi,
@@ -1129,6 +1192,211 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req
*mqrq,
mmc_queue_bounce_pre(mqrq);
}
+static u8 mmc_blk_chk_packable(struct mmc_queue *mq, struct request *req)
+{
+ struct request_queue *q = mq-queue;
+ struct mmc_card *card = mq-card;
+ struct request *cur = req, *next = NULL;
+ struct mmc_blk_data *md =
RE: [PATCH] ARM: SAMSUNG: Add clk enable/disable of pwm
Joonyoung Shim wrote:
PWM timers use pclk(timers clk) as parent clk. If this pclk is the
disabled state when PWM driver is probed, then it causes wrong read and
write operation about registers of PWM.
Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/plat-samsung/pwm.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c
index f37457c..dc1185d 100644
--- a/arch/arm/plat-samsung/pwm.c
+++ b/arch/arm/plat-samsung/pwm.c
@@ -299,6 +299,9 @@ static int s3c_pwm_probe(struct platform_device *pdev)
goto err_clk_tin;
}
+ clk_enable(pwm-clk);
+ clk_enable(pwm-clk_div);
+
local_irq_save(flags);
tcon = __raw_readl(S3C2410_TCON);
@@ -326,6 +329,8 @@ static int s3c_pwm_probe(struct platform_device *pdev)
return 0;
err_clk_tdiv:
+ clk_disable(pwm-clk_div);
+ clk_disable(pwm-clk);
clk_put(pwm-clk_div);
err_clk_tin:
@@ -340,6 +345,8 @@ static int __devexit s3c_pwm_remove(struct
platform_device *pdev)
{
struct pwm_device *pwm = platform_get_drvdata(pdev);
+ clk_disable(pwm-clk_div);
+ clk_disable(pwm-clk);
clk_put(pwm-clk_div);
clk_put(pwm-clk);
kfree(pwm);
--
1.7.5.4
Well, I wonder when this is needed. I think it should be enabled during
kernel booting...
Thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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RE: [PATCH 1/3 v3] ARM: EXYNOS4: Support for generic I/O power domains on EXYNOS4210/4212
Chanwoo Choi wrote:
This patch support the generic power domains to control power domain
of EXYNOS4.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos4/Kconfig |2 +
arch/arm/mach-exynos4/Makefile |1 +
arch/arm/mach-exynos4/include/mach/pm-exynos4.h | 50 +
arch/arm/mach-exynos4/include/mach/regs-clock.h |9 +
arch/arm/mach-exynos4/include/mach/regs-pmu.h |2 +
arch/arm/mach-exynos4/pm-exynos4.c | 237
+++
6 files changed, 301 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-exynos4/include/mach/pm-exynos4.h
create mode 100644 arch/arm/mach-exynos4/pm-exynos4.c
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 4924838..d042e53 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -14,6 +14,7 @@ config CPU_EXYNOS4210
select SAMSUNG_DMADEV
select S5P_PM if PM
select S5P_SLEEP if PM
+ select PM_GENERIC_DOMAINS if PM
help
Enable EXYNOS4210 CPU support
@@ -21,6 +22,7 @@ config SOC_EXYNOS4212
bool
select S5P_PM if PM
select S5P_SLEEP if PM
+ select PM_GENERIC_DOMAINS if PM
help
Enable EXYNOS4212 SoC support
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 2bb18f4..d73a4e7 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -14,6 +14,7 @@ obj-:=
obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o
+obj-$(CONFIG_ARCH_EXYNOS4) += pm-exynos4.o
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
obj-$(CONFIG_PM) += pm.o
diff --git a/arch/arm/mach-exynos4/include/mach/pm-exynos4.h b/arch/arm/mach-
exynos4/include/mach/pm-exynos4.h
new file mode 100644
index 000..31f6b75
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/pm-exynos4.h
@@ -0,0 +1,50 @@
+/* linux/arch/arm/mach-exynos4/include/mach/pm-exynos4.h
+ *
+ * EXYNOS4 series Power management support
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef PM_EXYNOS4_H
+#define PM_EXYNOS4_H
+
+#include linux/pm_domain.h
+
+#ifdef CONFIG_PM
+struct exynos4_pm_domain {
+ struct generic_pm_domain genpd;
+ const char *name;
+ void __iomem *base;
+ u32 clkgate_mask;
+};
+
+extern int exynos4_add_device_to_domain(struct exynos4_pm_domain
*exynos4_pd,
+ struct platform_device *pdev);
+extern void exynos4210_init_pm_domains(void);
+extern void exynos4x12_init_pm_domains(void);
+
+/* Common power domain for EXYNOS4 series */
+extern struct exynos4_pm_domain exynos4_pd_mfc;
+extern struct exynos4_pm_domain exynos4_pd_g3d;
+extern struct exynos4_pm_domain exynos4_pd_lcd0;
+extern struct exynos4_pm_domain exynos4_pd_tv;
+extern struct exynos4_pm_domain exynos4_pd_cam;
+extern struct exynos4_pm_domain exynos4_pd_gps;
+
+/* Only for EXYNOS4210 */
+extern struct exynos4_pm_domain exynos4_pd_lcd1;
+
+/* Only for EXYNOS4x12 */
+extern struct exynos4_pm_domain exynos4_pd_isp;
+
+#else
+#define exynos4_add_device_to_domain(exynos4_pd, pdev) { }
+#define exynos4210_init_pm_domains() { }
+#define exynos4x12_init_pm_domains() { }
+#endif /* CONFIG_PM */
+#endif /* PM_EXYNOS4_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-
exynos4/include/mach/regs-clock.h
index 6c37ebe..c519ade 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -194,6 +194,13 @@
#define S5P_CLKDIV_BUS_GPLR_SHIFT(4)
#define S5P_CLKDIV_BUS_GPLR_MASK (0x7
S5P_CLKDIV_BUS_GPLR_SHIFT)
+#define S5P_CLKGATE_BLOCK_CAM(1 0)
+#define S5P_CLKGATE_BLOCK_TV (1 1)
+#define S5P_CLKGATE_BLOCK_MFC(1 2)
+#define S5P_CLKGATE_BLOCK_G3D(1 3)
+#define S5P_CLKGATE_BLOCK_LCD0 (1 4)
+#define S5P_CLKGATE_BLOCK_GPS(1 7)
+
/* Only for EXYNOS4210 */
#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
@@ -201,6 +208,8 @@
#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
+#define S5P_CLKGATE_BLOCK_LCD1 (1 5)
+
/* Compatibility defines and inclusion */
#include mach/regs-pmu.h
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
RE: [PATCH V6] SDHCI: S3C: Use generic clock names for sdhci bus clock options
Chris Ball wrote: Hi Kukjin, On Wed, Nov 02 2011, Kukjin Kim wrote: This patch modifies the driver to stop depending on the clock names being passed from the platform and switch over to bus clock lookup using generic clock names. V6 Changes: Changed sprintf to snprintf as suggested by Chris Ball. Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com Acked-by: Kukjin Kim kgene@samsung.com Hi Chirs, Could you please pick this up in your tree for this merge window? Might be easier to have you send this, if you don't mind, since I'm still traveling and have already sent my main pull request. Thanks! Acked-by: Chris Ball c...@laptop.org Hi Chris, OK, I picked this up in my tree. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: SAMSUNG: Add clk enable/disable of pwm
11/03/2011 10:59 AM, Kukjin Kim 쓴 글:
Joonyoung Shim wrote:
PWM timers use pclk(timers clk) as parent clk. If this pclk is the
disabled state when PWM driver is probed, then it causes wrong read and
write operation about registers of PWM.
Signed-off-by: Joonyoung Shimjy0922.s...@samsung.com
Signed-off-by: Kyungmin Parkkyungmin.p...@samsung.com
---
arch/arm/plat-samsung/pwm.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c
index f37457c..dc1185d 100644
--- a/arch/arm/plat-samsung/pwm.c
+++ b/arch/arm/plat-samsung/pwm.c
@@ -299,6 +299,9 @@ static int s3c_pwm_probe(struct platform_device *pdev)
goto err_clk_tin;
}
+ clk_enable(pwm-clk);
+ clk_enable(pwm-clk_div);
+
local_irq_save(flags);
tcon = __raw_readl(S3C2410_TCON);
@@ -326,6 +329,8 @@ static int s3c_pwm_probe(struct platform_device *pdev)
return 0;
err_clk_tdiv:
+ clk_disable(pwm-clk_div);
+ clk_disable(pwm-clk);
clk_put(pwm-clk_div);
err_clk_tin:
@@ -340,6 +345,8 @@ static int __devexit s3c_pwm_remove(struct
platform_device *pdev)
{
struct pwm_device *pwm = platform_get_drvdata(pdev);
+ clk_disable(pwm-clk_div);
+ clk_disable(pwm-clk);
clk_put(pwm-clk_div);
clk_put(pwm-clk);
kfree(pwm);
--
1.7.5.4
Well, I wonder when this is needed. I think it should be enabled during
kernel booting...
The exynos4 machine using just timer turns on timer clock in the past,
but timer clock is disable state when boot since MCT is used. MCT
doesn't control timer clock.
I think pwm driver should control(enable/disable) using clocks
regardless of their parents clock.
Thanks.
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[PATCHv2 1/2] arm: samsung: support the second capability for samsung-soc
In mmc, there are capabilities and use the host_caps.
That capability is expressed with bit[0:31].
But now..already filled the bit[0:31]...
so we need to denote with the other capability field.
(if we want to use the cache, powerclass, etc for eMMC..this field is necessary)
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changelog v2:
- based-on samsung-soc's for-next tree.
arch/arm/plat-samsung/include/plat/sdhci.h |2 ++
arch/arm/plat-samsung/platformdata.c |2 ++
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h
b/arch/arm/plat-samsung/include/plat/sdhci.h
index dcff7dd..bf33ea1 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -40,6 +40,7 @@ enum clk_types {
* struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
* @max_width: The maximum number of data bits supported.
* @host_caps: Standard MMC host capabilities bit field.
+ * @host_caps2: The Second Standard MMC host capabilities bit field.
* @cd_type: Type of Card Detection method (see cd_types enum above)
* @clk_type: Type of clock divider method (see clk_types enum above)
* @ext_cd_init: Initialize external card detect subsystem. Called on
@@ -63,6 +64,7 @@ enum clk_types {
struct s3c_sdhci_platdata {
unsigned intmax_width;
unsigned inthost_caps;
+ unsigned inthost_caps2;
enum cd_types cd_type;
enum clk_types clk_type;
diff --git a/arch/arm/plat-samsung/platformdata.c
b/arch/arm/plat-samsung/platformdata.c
index 4c9a207..5ffcf46 100644
--- a/arch/arm/plat-samsung/platformdata.c
+++ b/arch/arm/plat-samsung/platformdata.c
@@ -54,4 +54,6 @@ void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
set-host_caps |= pd-host_caps;
if (pd-clk_type)
set-clk_type = pd-clk_type;
+ if (pd-host_caps2)
+ set-host_caps2 |= pd-host_caps2;
}
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[PATCHv2 2/2] mmc: sdhci-s3c: add platform data for the second capability
This patch is added host_caps2 in sdhci-s3c.c
It's necessary that use the second capabilities.
And removed the duplicated host_caps.
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changelog v2:
- remove the duplicated host_caps.
drivers/mmc/host/sdhci-s3c.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 3d00e72..6b8f8f6 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -521,9 +521,6 @@ static int __devinit sdhci_s3c_probe(struct platform_device
*pdev)
if (pdata-cd_type == S3C_SDHCI_CD_PERMANENT)
host-mmc-caps = MMC_CAP_NONREMOVABLE;
- if (pdata-host_caps)
- host-mmc-caps |= pdata-host_caps;
-
host-quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
SDHCI_QUIRK_32BIT_DMA_SIZE);
@@ -544,6 +541,9 @@ static int __devinit sdhci_s3c_probe(struct platform_device
*pdev)
if (pdata-host_caps)
host-mmc-caps |= pdata-host_caps;
+ if (pdata-host_caps2)
+ host-mmc-caps2 |= pdata-host_caps2;
+
ret = sdhci_add_host(host);
if (ret) {
dev_err(dev, sdhci_add_host() failed\n);
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Re: [PATCH 5/5] [CPUFREQ] EXYNOS4210: Add support ASV feature
Hello,
On Wed, Nov 2, 2011 at 9:43 PM, Kukjin Kim kgene@samsung.com wrote:
[]
+static void __init set_volt_table(void)
+{
+ unsigned int tmp, i, asv_group = 0;
+
+ tmp = __raw_readl(S5P_INFORM2);
As I've mentioned in the ASV patch thread, do we really need to use an
INFORM register simply to save the id of supported voltage ranges?
Why aren't we using an extern variable here? For example, extern int
asv_group_id; and define it at asv.h or somewhere else.
At reboot, we are going to init ASV driver and will get the ASV value
again; thus, we don't need to use such a preserving register anyway.
At suspend/resume, the value in RAM does not disappear and the IPL
does not care this value; thus, it is meaningless to use INFORM2 for
this value.
+
+ switch (tmp (SUPPORT_FREQ_MASK SUPPORT_FREQ_SHIFT)) {
+ case SUPPORT_1200MHZ:
+ asv_group = (tmp 0xF);
+ break;
+ case SUPPORT_1400MHZ:
+ case SUPPORT_1000MHZ:
+ default:
+ /* Not supported and assign typical ASV group */
+ asv_group = 2;
+ break;
+ }
+
+ printk(KERN_INFO DVFS: VDD_ARM Voltage table set with %d Group\n,
asv_group);
+
+ for (i = 0 ; i CPUFREQ_LEVEL_END ; i++)
+ exynos4_volt_table[i] = asv_voltage[i][asv_group];
+}
+
static int __init exynos4_cpufreq_init(void)
{
int i;
unsigned int tmp;
+ set_volt_table();
+
cpu_clk = clk_get(NULL, armclk);
if (IS_ERR(cpu_clk))
return PTR_ERR(cpu_clk);
--
1.7.1
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--
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab, DMC Business, Samsung Electronics
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Re: [PATCH 4/5] [CPUFREQ] EXYNOS4210: Add DVS lock feature for other driver
On Wed, Nov 2, 2011 at 9:43 PM, Kukjin Kim kgene@samsung.com wrote:
From: Jongpill Lee boyko@samsung.com
This patch adds DVS lock feature for other driver and pm/
reboot notifier to enhance stability.
Signed-off-by: Jongpill Lee boyko@samsung.com
Signed-off-by: SangWook Ju sw...@samsung.com
Signed-off-by: Jonghwan Choi jhbird.c...@samsung.com
Signed-off-by: Jaecheol Lee jc@samsung.com
---
arch/arm/mach-exynos4/include/mach/cpufreq.h | 39 ++
drivers/cpufreq/exynos4210-cpufreq.c | 174
+-
2 files changed, 207 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/mach-exynos4/include/mach/cpufreq.h
diff --git a/arch/arm/mach-exynos4/include/mach/cpufreq.h
b/arch/arm/mach-exynos4/include/mach/cpufreq.h
new file mode 100644
index 000..7e00931
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/cpufreq.h
@@ -0,0 +1,39 @@
+/* linux/arch/arm/mach-exynos4/include/mach/cpufreq.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS4 - CPUFreq support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * CPU frequency level index for using cpufreq lock API
+ * This should be same with cpufreq_frequency_table
+ */
+enum cpufreq_level_request {
+ CPU_L0, /* 1200MHz */
+ CPU_L1, /* 1000MHz */
+ CPU_L2, /* 800MHz */
+ CPU_L3, /* 500MHz */
+ CPU_L4, /* 200MHz */
+ CPU_LEVEL_END,
+};
+
+enum cpufreq_lock_ID {
+ DVFS_LOCK_ID_G2D, /* G2D */
+ DVFS_LOCK_ID_TV, /* TV */
+ DVFS_LOCK_ID_MFC, /* MFC */
+ DVFS_LOCK_ID_USB, /* USB */
+ DVFS_LOCK_ID_CAM, /* CAM */
+ DVFS_LOCK_ID_PM, /* PM */
+ DVFS_LOCK_ID_USER, /* USER */
+ DVFS_LOCK_ID_END,
+};
+
+int exynos4_cpufreq_lock(unsigned int nId,
+ enum cpufreq_level_request cpufreq_level);
+void exynos4_cpufreq_lock_free(unsigned int nId);
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
b/drivers/cpufreq/exynos4210-cpufreq.c
index 246f9e2..30e1949 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -17,14 +17,21 @@
#include linux/slab.h
#include linux/regulator/consumer.h
#include linux/cpufreq.h
+#include linux/suspend.h
+#include linux/reboot.h
#include mach/map.h
#include mach/regs-clock.h
#include mach/regs-mem.h
+#include mach/cpufreq.h
#include plat/clock.h
#include plat/pm.h
+static bool exynos4_cpufreq_init_done;
+static DEFINE_MUTEX(set_freq_lock);
+static DEFINE_MUTEX(set_cpu_freq_lock);
+
static struct clk *cpu_clk;
static struct clk *moutcore;
static struct clk *mout_mpll;
@@ -53,6 +60,12 @@ static struct cpufreq_frequency_table
exynos4_freq_table[] = {
{0, CPUFREQ_TABLE_END},
};
+/* This defines are for cpufreq lock */
+#define CPUFREQ_MIN_LEVEL (CPUFREQ_LEVEL_END - 1)
+unsigned int cpufreq_lock_id;
+unsigned int cpufreq_lock_val[DVFS_LOCK_ID_END];
+unsigned int cpufreq_lock_level = CPUFREQ_MIN_LEVEL;
+
static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
/*
* Clock divider value for following
@@ -272,22 +285,31 @@ static int exynos4_target(struct cpufreq_policy
*policy,
{
unsigned int index, old_index;
unsigned int arm_volt;
+ int ret = 0;
+
+ mutex_lock(set_freq_lock);
freqs.old = exynos4_getspeed(policy-cpu);
if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
- freqs.old, relation, old_index))
- return -EINVAL;
+ freqs.old, relation, old_index))
{
+ ret = -EINVAL;
+ goto out;
+ }
if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
- target_freq, relation, index))
- return -EINVAL;
+ target_freq, relation, index)) {
+ ret = -EINVAL;
+ goto out;
+ }
freqs.new = exynos4_freq_table[index].frequency;
freqs.cpu = policy-cpu;
- if (freqs.new == freqs.old)
- return 0;
+ if (freqs.new == freqs.old) {
+ ret = -EINVAL;
+ goto out;
+ }
/* get the voltage value */
arm_volt = exynos4_volt_table[index].arm_volt;
@@ -311,8 +333,98 @@ static int exynos4_target(struct cpufreq_policy
*policy,
regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
}
+out:
+ mutex_unlock(set_freq_lock);
+
+ return ret;
+}
+
+atomic_t
Re: [PATCH 1/5] [CPUFREQ] EXYNOS4210: Remove code about bus on cpufreq
On Wed, Nov 2, 2011 at 9:42 PM, Kukjin Kim kgene@samsung.com wrote: From: Jongpill Lee boyko@samsung.com This patch removes code for bus on cpufreq because the code for bus frequency changing moves to busfreq driver. So code about bus on cpufreq is not necessary. Signed-off-by: Jongpill Lee boyko@samsung.com Signed-off-by: SangWook Ju sw...@samsung.com Signed-off-by: Jaecheol Lee jc@samsung.com Signed-off-by: Kukjin Kim kgene@samsung.com --- drivers/cpufreq/exynos4210-cpufreq.c | 174 +- 1 files changed, 1 insertions(+), 173 deletions(-) Cool! Now, it's compatible with the Exynos4210 bus devfreq driver. Are you going to upstream the busfreq in the devfreq framework (at /drivers/devfreq/) or do you want me to submit the Exynos4210 bus devfreq driver that is currently on http://git.infradead.org/users/kmpark/linux-2.6-samsung/shortlog/refs/heads/devfreq (drivers/devfreq/exynos4210_memorybus.c) Devfreq is a framework to support DVFS feature for non-CPU devices, which is at 3.2-next tree. Cheers! MyungJoo -- MyungJoo Ham, Ph.D. Mobile Software Platform Lab, DMC Business, Samsung Electronics -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
