Hello Kukjin,
On Mon, Nov 24, 2014 at 6:41 AM, Vivek Gautam gautam.vi...@samsung.com wrote:
DP PHY now require pmu-system-controller to handle PMU register
to control PHY's power isolation. Adding the same to dp-phy
node.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Reviewed-by:
On Tue, 2014-12-02 at 15:17 +0900, Heesub Shin wrote:
Hello Simons,
On 12/01/2014 09:59 PM, Sjoerd Simons wrote:
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free
Hello Kukjin,
On 11/20/2014 02:55 AM, Kukjin Kim wrote:
Yeah, it could be a best solution at this moment. Let me revert the commit
0ef76aea7a34 (ARM: exynos_defconfig: Enable options for display panel
support)
from -next in samsung tree.
Maybe now that all the issues with the Exynos DRM
On Tuesday, December 02, 2014 5:17 PM, Javier Martinez Canillas wrote:
Hello Kukjin,
On Mon, Nov 24, 2014 at 6:41 AM, Vivek Gautam gautam.vi...@samsung.com
wrote:
DP PHY now require pmu-system-controller to handle PMU register
to control PHY's power isolation. Adding the same to dp-phy
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim
This patchset adds new 64-bit Exynos5433 Samsung SoC which contains quad
Cortex-A57 and quad Cortex-A53. It is desigend with the 20nm low power process.
This patchset include some patches such as:
- Support booting of Exynos5433
- Support UART/MCT/GIC/HSI2C/SPI/PDMA/MSHC
- Support the clock
This patch adds the support for Exynos 64bit SoC. The delay_timer is only used
for Exynos 32bit SoC.
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Signed-off-by: Chanwoo Choi
This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A6/Bus/Audio clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
PSCI (Power State Coordination Interface) v0.1.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier
From: Jaehoon Chung jh80.ch...@samsung.com
This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433
SoC. MSHC is an interface between the system the SD/MMC card.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
This patch enable Exynos5433 SoC in the arm64 defconfig.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special clocks of CMU_PERIS use fin_pll source clock directly.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi
This patch adds the necessary Kconfig entries to enable
support for the ARMv8 based Exynos5433 SoC.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
Acked-by: Inki Dae
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks
is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
related to CMU_DISP should be always on state.
Also, CMU_DISP must
This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other CMU domains.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae
This patch adds SPI (Serial Peripheral Interface) dt node for Exynos5433 SoC.
SPI transfers serial data by using various peripherals. SPI includes
8-bit/16-bit/32-bit shift registers to transmit and receive data. PDMA is used
for SPI communication.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and
This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains
the clocks for GPU(3D Graphics Engine).
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
This patch adds ths mux/divider/gate clocksof CMU_G2D domain which includes
G2D/MDMA IPs. The CMU_G2D must need the clocks related to G2D by providing
CMU_TOP domain. So, this patch add several clocks for G2D from CMU_TOP domain.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa
This patch adds the support for CMU (Clock Management Units) of Exynos5433
which is 64bit SoC and has Octa-cores. This patch supports necessary clocks
(PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation
for Exynos5433 clock controller.
Cc: Sylwester Nawrocki
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa
Hey Marek, Inki,
On Wed, 2014-11-19 at 12:15 +0100, Marek Szyprowski wrote:
Hello Everyone,
This is another attempt to finally make Exynos SYSMMU driver fully
integrated with DMA-mapping subsystem. The main change from previous
version is a rebase onto latest automatic DMA configuration for
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi-
functional input/output port pins and 135 memory port pins. There are 41 general
port groups and 2 memory port groups.
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Linus
On Mon, Dec 01, 2014 at 02:21:46AM +, Chanwoo Choi wrote:
Dear Mark,
On 11/28/2014 11:00 PM, Mark Rutland wrote:
On Fri, Nov 28, 2014 at 01:18:25PM +, Chanwoo Choi wrote:
Dear Mark,
On 11/27/2014 08:18 PM, Mark Rutland wrote:
On Thu, Nov 27, 2014 at 07:35:13AM +, Chanwoo
Hi,
On Tue, Dec 02, 2014 at 08:49:51AM +, Chanwoo Choi wrote:
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
PSCI (Power State Coordination Interface) v0.1.
Cc: Kukjin Kim
Dear Mark,
On 12/02/2014 08:09 PM, Mark Rutland wrote:
Hi,
On Tue, Dec 02, 2014 at 08:49:51AM +, Chanwoo Choi wrote:
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433
supports
PSCI
Hi,
+ psci {
+ compatible = arm,psci;
+ method = smc;
+ cpu_off = 0x8402;
+ cpu_on = 0xC403;
+ };
Given your comments on the latest posting, has CPU_OFF been tested, and
does it work for _all_ CPUs
rtc have different i2c client than power(pmic) block. So rtc device should
sit under its own i2c client in device hierarchy, which reflects in sysfs also.
This patch modifies code to register rtc cell with rtc-dev as parent.
Without this patch :
driver max77686-pmic modalias power
Hi Inki,
Can you please review this? I also have sent other two patch sets that sits on
top of this one. Thanks.
Gustavo
2014-11-24 Gustavo Padovan gust...@padovan.org:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Hi Inki,
rtc have different i2c client than power(pmic) block. So rtc device should
sit under its own i2c client in device hierarchy, which reflects in sysfs also.
This patch modifies code to register rtc cell with rtc-dev as parent.
Without this patch :
# ls /sys/class/i2c-adapter/i2c-0/0-0009/
driver
On 02.12.2014 13:45, Yadwinder Singh Brar wrote:
rtc have different i2c client than power(pmic) block. So rtc device should
sit under its own i2c client in device hierarchy, which reflects in sysfs
also.
This patch modifies code to register rtc cell with rtc-dev as parent.
Without this
On 11/29/2014 11:18 PM, Kukjin Kim wrote:
Tobias Jakobi wrote:
EXYNOS4_MCT_L_MASK is defined as 0xff00, so applying this bitmask
produces a number outside the range 0x00 to 0xff, which always results
in execution of the default switch statement.
Obviously this is wrong and git history
Hi Pankaj,
On 27/09/14 07:41, Pankaj Dubey wrote:
Let's remove unnecessary include of header files from clk.h and add
required one in clk.c
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
drivers/clk/samsung/clk.c |3 ++-
drivers/clk/samsung/clk.h |4
2 files
Since there has been quite a lot of development going on for
ARM Exynos cpuidle driver recently I would like to add separate
MAINTAINERS entry for it and add myself as the primary maintainer.
The merging process would remain (almost) unchanged with patches
going (with my Ack) through Daniel's or
Dear Mark,
On Tue, Dec 2, 2014 at 9:13 PM, Mark Rutland mark.rutl...@arm.com wrote:
Hi,
+ psci {
+ compatible = arm,psci;
+ method = smc;
+ cpu_off = 0x8402;
+ cpu_on = 0xC403;
+ };
Given your comments
On 12/02/2014 06:38 AM, Padma Venkat wrote:
Hi Vinod/Lars,
On 11/26/14, Padmavathi Venna padm...@samsung.com wrote:
Fill txstate.residue with the amount of bytes remaining in the current
transfer if the transfer is not complete. This will be of particular
use to i2s DMA transfers, providing
On Tuesday, December 02, 2014 04:41:35 PM Bartlomiej Zolnierkiewicz wrote:
Since there has been quite a lot of development going on for
ARM Exynos cpuidle driver recently I would like to add separate
MAINTAINERS entry for it and add myself as the primary maintainer.
The merging process would
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
CONFIG_PM is defined as the alternative of CONFIG_PM_RUNTIME and
CONFIG_PM_SLEEP, so it can be used instead of that.
Besides, after commit b2b49ccbdd54 (PM: Kconfig: Set PM_RUNTIME if
PM_SLEEP is selected) PM_RUNTIME is always set if PM is set,
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
After commit b2b49ccbdd54 (PM: Kconfig: Set PM_RUNTIME if PM_SLEEP is
selected) PM_RUNTIME is always set if PM is set, so #ifdef blocks
depending on CONFIG_PM_RUNTIME may now be changed to depend on
CONFIG_PM.
Replace CONFIG_PM_RUNTIME with
On Wednesday, December 03, 2014 10:54 AM, Rafael J. Wysocki wrote:
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
After commit b2b49ccbdd54 (PM: Kconfig: Set PM_RUNTIME if PM_SLEEP is
selected) PM_RUNTIME is always set if PM is set, so #ifdef blocks
depending on CONFIG_PM_RUNTIME may
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
After commit b2b49ccbdd54 (PM: Kconfig: Set PM_RUNTIME if PM_SLEEP is
selected) PM_RUNTIME is always set if PM is set, so #ifdef blocks
depending on CONFIG_PM_RUNTIME may now be changed to depend on
CONFIG_PM.
The alternative of CONFIG_PM_SLEEP
On Wed, Dec 03, 2014 at 02:40:35AM +0100, Rafael J. Wysocki wrote:
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
CONFIG_PM is defined as the alternative of CONFIG_PM_RUNTIME and
CONFIG_PM_SLEEP, so it can be used instead of that.
Besides, after commit b2b49ccbdd54 (PM: Kconfig: Set
Hi Lars,
[snip]
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret == DMA_COMPLETE || !txstate)
+ return ret;
+
+ used = txstate-used;
+
+ spin_lock_irqsave(pch-lock, flags);
+ sar = readl(regs + SA(thrd-id));
+ dar = readl(regs + DA(thrd-id));
+
+
On 2014년 12월 01일 01:16, Pankaj Dubey wrote:
This patch splits up exynos-pmu.c file, and moves PMU configuration data
and functions handing those data into SoC specific PMU files, keeping
driver structure and common functionality into exynos-pmu.c.
At the same time it also separates
Hi Jaewon,
On Mon, Dec 01, 2014 at 11:11:12AM +0900, Jaewon Kim wrote:
This patch adds support for haptic driver controlled by
voltage of regulator. And this driver support for
Force Feedback interface from input framework
Signed-off-by: Jaewon Kim jaewon02@samsung.com
Signed-off-by:
Hi Dmitry,
2014년 12월 03일 15:02에 Dmitry Torokhov 이(가) 쓴 글:
Hi Jaewon,
On Mon, Dec 01, 2014 at 11:11:12AM +0900, Jaewon Kim wrote:
This patch adds support for haptic driver controlled by
voltage of regulator. And this driver support for
Force Feedback interface from input framework
On 28 November 2014 at 20:23, Eduardo Valentin edubez...@gmail.com wrote:
diff --git a/drivers/thermal/cpu_cooling.c b/drivers/thermal/cpu_cooling.c
index 1ab0018..88d2775 100644
--- a/drivers/thermal/cpu_cooling.c
+++ b/drivers/thermal/cpu_cooling.c
@@ -440,6 +440,9 @@
On 3 December 2014 at 10:17, Padma Venkat padma@gmail.com wrote:
Hi Lars,
[snip]
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret == DMA_COMPLETE || !txstate)
+ return ret;
+
+ used = txstate-used;
+
+ spin_lock_irqsave(pch-lock, flags);
+ sar =
Exynos SoC's DT files are using Chipid device nodes, but it's binding
information is missing. This patch adds exynos-chipid binding information.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
.../bindings/arm/samsung/exynos-chipid.txt | 12
1 file changed, 12
This patch adds regulator-haptic device node controlled by regulator.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
Reviewed-by: Chanwoo Choi cw00.c...@samsung.com
---
arch/arm/boot/dts/exynos3250-rinato.dts |7 +++
1 file changed, 7 insertions(+)
diff --git
This patch adds support for haptic driver controlled by
voltage of regulator. And this driver support for
Force Feedback interface from input framework
Signed-off-by: Jaewon Kim jaewon02@samsung.com
Signed-off-by: Hyunhee Kim hyunhee@samsung.com
Acked-by: Kyungmin Park
52 matches
Mail list logo