Re: [PATCH v2 5/7] ARM: dts: Update DP controller DT Node for Exynos5 based SoCs
Hi Mr. Jingoo Han,
On 26 August 2013 08:27, Jingoo Han jg1@samsung.com wrote:
On Tuesday, July 30, 2013 8:20 PM, Vikas Sajjan wrote:
Moves the properties of DP controller to exynos5.dtsi which are common
across exynos5 SoCs like Exynos5250 and Exynos5420.
The PHY DP Node is based on Jingoo Han's jg1@samsung.com patch at
https://patchwork.linuxtv.org/patch/19189/
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
arch/arm/boot/dts/exynos5.dtsi| 11 +++
arch/arm/boot/dts/exynos5250-arndale.dts |3 ++-
arch/arm/boot/dts/exynos5250-smdk5250.dts |3 ++-
arch/arm/boot/dts/exynos5250.dtsi | 21 +
4 files changed, 24 insertions(+), 14 deletions(-)
[]
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 238bdb2..1c017dc 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -614,20 +614,17 @@
interrupts = 0 94 0;
};
- dp-controller {
- compatible = samsung,exynos5-dp;
- reg = 0x145b 0x1000;
- interrupts = 10 3;
- interrupt-parent = combiner;
+ dp_phy: video-phy@10040720 {
+ compatible = samsung,exynos5250-dp-video-phy;
+ reg = 0x10040720 4;
+ #phy-cells = 0;
+ };
Oops!!!
This patch should be reverted.
Or, fix patch should be re-sent.
'dp phy' driver is not yet merged to mainline kernel.
As you suggest, since the DP-PHY driver is NOT yet in mainline, we may
have to keep this patch reverted till your patch series gets merged to
have DP working on exynos5 .
+
+ dp-controller@145b {
clocks = clock 342;
clock-names = dp;
- #address-cells = 1;
- #size-cells = 0;
-
- dptx-phy {
- reg = 0x10040720;
- samsung,enable-mask = 1;
- };
+ phys = dp_phy;
+ phy-names = dp;
};
Thus, 'dptx-phy' node should be used until dp phy driver is merged.
Vikas Sajjan,
Please test your patch on real boards when you send your patch.
I tested the patch before sending on Exynos5250-SMDK5250 using Kishon
Vijay Abraham's series at http://lwn.net/Articles/559487/
which contains DP-PHY driver posted by you
1. phy: Add driver for Exynos DP PHY
2. video: exynos_dp: remove non-DT support for Exynos Display Port
3. video: exynos_dp: Use the generic PHY driver
Best regards,
Jingoo Han
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[PATCH] ARM: dts: Remove DP PHY node from exynos5250.dtsi
Since DP PHY driver is not yet merged, DP PHY node should be
removed from exynos5250.dtsi.
Signed-off-by: Jingoo Han jg1@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 864ae90..72aec7f 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -625,17 +625,16 @@
interrupts = 0 94 0;
};
- dp_phy: video-phy@10040720 {
- compatible = samsung,exynos5250-dp-video-phy;
- reg = 0x10040720 4;
- #phy-cells = 0;
- };
-
dp-controller@145B {
clocks = clock 342;
clock-names = dp;
- phys = dp_phy;
- phy-names = dp;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ dptx-phy {
+ reg = 0x10040720;
+ samsung,enable-mask = 1;
+ };
};
fimd@1440 {
--
1.7.10.4
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Re: [PATCH] ARM: dts: Remove DP PHY node from exynos5250.dtsi
Hi Mr. Han,
On 26 August 2013 11:59, Jingoo Han jg1@samsung.com wrote:
Since DP PHY driver is not yet merged, DP PHY node should be
removed from exynos5250.dtsi.
Signed-off-by: Jingoo Han jg1@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 864ae90..72aec7f 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -625,17 +625,16 @@
interrupts = 0 94 0;
};
- dp_phy: video-phy@10040720 {
- compatible = samsung,exynos5250-dp-video-phy;
- reg = 0x10040720 4;
- #phy-cells = 0;
- };
-
dp-controller@145B {
clocks = clock 342;
clock-names = dp;
- phys = dp_phy;
- phy-names = dp;
+ #address-cells = 1;
+ #size-cells = 0;
+
I think you can skip the above 2 lines, as those are already present
in exynos5.dtsi.
+ dptx-phy {
+ reg = 0x10040720;
+ samsung,enable-mask = 1;
+ };
};
fimd@1440 {
--
1.7.10.4
--
Thanks and Regards
Vikas Sajjan
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Re: [PATCH] ARM: dts: Remove DP PHY node from exynos5250.dtsi
On Monday, August 26, 2013 3:43 PM, Vikas Sajjan wrote:
On 26 August 2013 11:59, Jingoo Han jg1@samsung.com wrote:
Since DP PHY driver is not yet merged, DP PHY node should be
removed from exynos5250.dtsi.
Signed-off-by: Jingoo Han jg1@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
[.]
dp-controller@145B {
clocks = clock 342;
clock-names = dp;
- phys = dp_phy;
- phy-names = dp;
+ #address-cells = 1;
+ #size-cells = 0;
+
I think you can skip the above 2 lines, as those are already present
in exynos5.dtsi.
OK, I see.
I will remove above 2 lines, and send V2 patch soon.
Thank you for your comment.
Best regards,
Jingoo Han
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[PATCH V2] ARM: dts: Remove DP PHY node from exynos5250.dtsi
Since DP PHY driver is not yet merged, DP PHY node should be
removed from exynos5250.dtsi.
Signed-off-by: Jingoo Han jg1@samsung.com
---
Changes since v1:
- Removed duplicated properties such as #address-cells, #size-cells.
arch/arm/boot/dts/exynos5250.dtsi | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 864ae90..c3d6e3b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -625,17 +625,14 @@
interrupts = 0 94 0;
};
- dp_phy: video-phy@10040720 {
- compatible = samsung,exynos5250-dp-video-phy;
- reg = 0x10040720 4;
- #phy-cells = 0;
- };
-
dp-controller@145B {
clocks = clock 342;
clock-names = dp;
- phys = dp_phy;
- phy-names = dp;
+
+ dptx-phy {
+ reg = 0x10040720;
+ samsung,enable-mask = 1;
+ };
};
fimd@1440 {
--
1.7.10.4
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Re: [PATCH V2] ARM: dts: Remove DP PHY node from exynos5250.dtsi
On 26 August 2013 12:23, Jingoo Han jg1@samsung.com wrote:
Since DP PHY driver is not yet merged, DP PHY node should be
removed from exynos5250.dtsi.
Signed-off-by: Jingoo Han jg1@samsung.com
---
Changes since v1:
- Removed duplicated properties such as #address-cells, #size-cells.
arch/arm/boot/dts/exynos5250.dtsi | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 864ae90..c3d6e3b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -625,17 +625,14 @@
interrupts = 0 94 0;
};
- dp_phy: video-phy@10040720 {
- compatible = samsung,exynos5250-dp-video-phy;
- reg = 0x10040720 4;
- #phy-cells = 0;
- };
-
dp-controller@145B {
clocks = clock 342;
clock-names = dp;
- phys = dp_phy;
- phy-names = dp;
+
+ dptx-phy {
+ reg = 0x10040720;
+ samsung,enable-mask = 1;
+ };
};
Reviewed-by: Vikas Sajjan vikas.saj...@linaro.org
fimd@1440 {
--
1.7.10.4
--
Thanks and Regards
Vikas Sajjan
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Re: [PATCH v11 0/8] PHY framework
Hi Greg, On Wednesday 21 August 2013 11:16 AM, Kishon Vijay Abraham I wrote: Added a generic PHY framework that provides a set of APIs for the PHY drivers to create/destroy a PHY and APIs for the PHY users to obtain a reference to the PHY with or without using phandle. This framework will be of use only to devices that uses external PHY (PHY functionality is not embedded within the controller). The intention of creating this framework is to bring the phy drivers spread all over the Linux kernel to drivers/phy to increase code re-use and to increase code maintainability. Comments to make PHY as bus wasn't done because PHY devices can be part of other bus and making a same device attached to multiple bus leads to bad design. If the PHY driver has to send notification on connect/disconnect, the PHY driver should make use of the extcon framework. Using this susbsystem to use extcon framwork will have to be analysed. You can find this patch series @ git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git testing Looks like there are not further comments on this series. Can you take this in your misc tree? Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/5] clk/exynos5420: add gate clock for mixer sysmmu
Adding sysmmu clock for mixer for exynos5420.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
Documentation/devicetree/bindings/clock/exynos5420-clock.txt |1 +
drivers/clk/samsung/clk-exynos5420.c |3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 596a368..5758a69 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -180,6 +180,7 @@ clock which they consume.
fimc_lite3 495
aclk_g3d 500
g3d 501
+ smmu_mixer 502
Example 1: An example of a clock controller node is listed below.
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index a86cadc..4e0c13e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -138,7 +138,7 @@ enum exynos5420_clks {
aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
- smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d,
+ smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer,
nr_clks,
};
@@ -725,6 +725,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[]
__initdata = {
GATE(smmu_mscl0, smmu_mscl0, aclk400_mscl, GATE_IP_MSCL, 8, 0, 0),
GATE(smmu_mscl1, smmu_mscl1, aclk400_mscl, GATE_IP_MSCL, 9, 0, 0),
GATE(smmu_mscl2, smmu_mscl2, aclk400_mscl, GATE_IP_MSCL, 10, 0, 0),
+ GATE(smmu_mixer, smmu_mixer, aclk200_disp1, GATE_IP_DISP1, 9, 0, 0),
};
static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
--
1.7.10.4
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[PATCH v3 4/5] clk/exynos5420: add hdmi mux to change parents in hdmi driver
hdmi driver needs to change the parent of hdmi clock
to pixel clock or hdmiphy clock, based on the stability
of hdmiphy. This patch is exposing the mux for changing
the parent.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
Documentation/devicetree/bindings/clock/exynos5420-clock.txt |5 +
drivers/clk/samsung/clk-exynos5420.c |5 -
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 5758a69..6f16aa8 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -182,6 +182,11 @@ clock which they consume.
g3d 501
smmu_mixer 502
+ Mux ID
+
+
+ mout_hdmi1024
+
Example 1: An example of a clock controller node is listed below.
clock: clock-controller@0x1001 {
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 522c033..5f9bc63 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -140,6 +140,9 @@ enum exynos5420_clks {
aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer,
+ /* mux clocks */
+ mout_hdmi = 1024,
+
nr_clks,
};
@@ -400,7 +403,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[]
__initdata = {
MUX(none, mout_mipi1, group2_p, SRC_DISP10, 16, 3),
MUX(none, mout_dp1, group2_p, SRC_DISP10, 20, 3),
MUX(none, mout_pixel, group2_p, SRC_DISP10, 24, 3),
- MUX(none, mout_hdmi, hdmi_p, SRC_DISP10, 28, 1),
+ MUX(mout_hdmi, mout_hdmi, hdmi_p, SRC_DISP10, 28, 1),
/* MAU Block */
MUX(none, mout_maudio0, maudio0_p, SRC_MAU, 28, 3),
--
1.7.10.4
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[PATCH v3 1/5] clk/exynos5420: add sclk_hdmiphy to the list of special clocks
Add sclk_hdmiphy to the list of exposed clocks. This is required
by hdmi driver to change the parent of hdmi clock.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
Documentation/devicetree/bindings/clock/exynos5420-clock.txt |1 +
drivers/clk/samsung/clk-exynos5420.c |4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 9bcc4b1..596a368 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -59,6 +59,7 @@ clock which they consume.
sclk_pwm 155
sclk_gscl_wa 156
sclk_gscl_wb 157
+ sclk_hdmiphy 158
[Peripheral Clock Gates]
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index e035fd0..a86cadc 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -120,7 +120,7 @@ enum exynos5420_clks {
sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
- sclk_pwm, sclk_gscl_wa, sclk_gscl_wb,
+ sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy,
/* gate clocks */
aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
@@ -297,7 +297,7 @@ static struct samsung_fixed_rate_clock
exynos5420_fixed_rate_ext_clks[] __initda
/* fixed rate clocks generated inside the soc */
static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata
= {
- FRATE(none, sclk_hdmiphy, NULL, CLK_IS_ROOT, 2400),
+ FRATE(sclk_hdmiphy, sclk_hdmiphy, NULL, CLK_IS_ROOT, 2400),
FRATE(none, sclk_pwi, NULL, CLK_IS_ROOT, 2400),
FRATE(none, sclk_usbh20, NULL, CLK_IS_ROOT, 4800),
FRATE(none, mphy_refclk_ixtal24, NULL, CLK_IS_ROOT, 4800),
--
1.7.10.4
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[PATCH v3 5/5] clk/exynos5420: assign dout_pixel id to pixel clock divider
dout_pixel is a new ID allocated for pixel clock divider. It is
queried in the driver to pass as the parent to hdmi clock while
switching between parents.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
Documentation/devicetree/bindings/clock/exynos5420-clock.txt |5 +
drivers/clk/samsung/clk-exynos5420.c |5 -
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 6f16aa8..4c069bd 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -187,6 +187,11 @@ clock which they consume.
mout_hdmi1024
+ Divider ID
+
+
+ dout_pixel 2048
+
Example 1: An example of a clock controller node is listed below.
clock: clock-controller@0x1001 {
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 5f9bc63..e55b223 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -143,6 +143,9 @@ enum exynos5420_clks {
/* mux clocks */
mout_hdmi = 1024,
+ /* divider clocks */
+ dout_pixel = 2048,
+
nr_clks,
};
@@ -463,7 +466,7 @@ static struct samsung_div_clock exynos5420_div_clks[]
__initdata = {
DIV(none, dout_fimd1, mout_fimd1, DIV_DISP10, 0, 4),
DIV(none, dout_mipi1, mout_mipi1, DIV_DISP10, 16, 8),
DIV(none, dout_dp1, mout_dp1, DIV_DISP10, 24, 4),
- DIV(none, dout_hdmi_pixel, mout_pixel, DIV_DISP10, 28, 4),
+ DIV(dout_pixel, dout_hdmi_pixel, mout_pixel, DIV_DISP10, 28, 4),
/* Audio Block */
DIV(none, dout_maudio0, mout_maudio0, DIV_MAU, 20, 4),
--
1.7.10.4
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[PATCH v3 0/5] clk/exynos5420: add clocks for hdmi subsystem
Add clock changes for hdmi subsystem for exynos5250 SoC. These include addition of new clocks like mout_hdmi and smmu_tv, associating ID to clk_hdmiphy and some essential corrections. V3: 1) Assign new ID to divider clock keeping sclk_pixel gate same. V2: 1) Rebase to Mike's Tree. 2) Change smmu_tv to smmu_mixer. This set is based on Mike's clk-next branch at https://git.linaro.org/gitweb?p=people/mturquette/linux.git Rahul Sharma (5): clk/exynos5420: add sclk_hdmiphy to the list of special clocks clk/exynos5420: add gate clock for mixer sysmmu clk/exynos5420: fix the order of parents of hdmi mux clk/exynos5420: add hdmi mux to change parents in hdmi driver clk/exynos5420: assign dout_pixel id to pixel clock divider .../devicetree/bindings/clock/exynos5420-clock.txt | 12 drivers/clk/samsung/clk-exynos5420.c| 19 +-- 2 files changed, 25 insertions(+), 6 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 3/5] clk/exynos5420: fix the order of parents of hdmi mux
Listing sclk_hdmiphy at 0th position in the list of parents is
causing wrong configuration in reg SRC_DISP10.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
drivers/clk/samsung/clk-exynos5420.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 4e0c13e..522c033 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -286,7 +286,7 @@ PNAME(audio2_p) = { fin_pll, cdclk2, sclk_dpll,
sclk_mpll,
sclk_spll, sclk_ipll, sclk_epll, sclk_rpll };
PNAME(spdif_p) = { fin_pll, dout_audio0, dout_audio1, dout_audio2,
spdif_extclk, sclk_ipll, sclk_epll, sclk_rpll };
-PNAME(hdmi_p) = { sclk_hdmiphy, dout_hdmi_pixel };
+PNAME(hdmi_p) = { dout_hdmi_pixel, sclk_hdmiphy };
PNAME(maudio0_p) = { fin_pll, maudio_clk, sclk_dpll, sclk_mpll,
sclk_spll, sclk_ipll, sclk_epll, sclk_rpll };
--
1.7.10.4
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[PATCH V7 0/3] Generic PHY driver for the Exynos SoC DP PHY
This patch series adds a simple driver for the Samsung Exynos SoC series DP transmitter PHY, using the generic PHY framework [1]. Previously the DP PHY used an internal DT node to control the PHY power enable bit. These patches was tested on Exynos5250. This PATCH v7 follows: * PATCH v6, sent on July, 9th 2013 * PATCH v5, sent on July, 8th 2013 * PATCH v4, sent on July, 2nd 2013 * PATCH v3, sent on July, 1st 2013 * PATCH v2, sent on June, 28th 2013 * PATCH v1, sent on June, 28th 2013 Changes from v6: * Re-based on git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git Changes from v5: * Re-based on git://gitorious.org/linuxphy/linuxphy.git Changes from v4: * Marked original bindings as deprecated in 'exynos_dp.txt' * Fixed typo of commit message. * Added Tomasz Figa's Reviewed-by. Changes from v3: * Added OF dependancy. * Removed redundant local variable 'void __iomem *addr'. * Removed unnecessary dev_set_drvdata(). * Added a patch that remove non-DT support for Exynos Display Port driver. * Removed unnecessary 'struct exynos_dp_platdata'. * Kept supporting the original bindings for DT compatibility. Changes from v2: * Removed redundant spinlock * Removed 'struct phy' from 'struct exynos_dp_video_phy' * Updated 'samsung-phy.txt', instead of creating 'samsung,exynos5250-dp-video-phy.txt'. * Removed unnecessary additional specifier from 'phys' DT property. * Added 'phys', 'phy-names' properties to 'exynos_dp.txt' file. * Added Felipe Balbi's Acked-by. Changes from v1: * Replaced exynos_dp_video_phy_xlate() with of_phy_simple_xlate(), as Kishon Vijay Abraham I guided. * Set the value of phy-cells as 0, because the phy_provider implements only one PHY. * Removed unnecessary header include. * Added '#ifdef CONFIG_OF' and of_match_ptr macro. This series depends on the generic PHY framework [1]. These patches refer to Sylwester Nawrocki's patches about Exynos MIPI [2]. [1] http://lwn.net/Articles/564188/ [2] http://www.spinics.net/lists/linux-samsung-soc/msg20098.html Jingoo Han (3): phy: Add driver for Exynos DP PHY video: exynos_dp: remove non-DT support for Exynos Display Port video: exynos_dp: Use the generic PHY driver .../devicetree/bindings/phy/samsung-phy.txt|7 ++ .../devicetree/bindings/video/exynos_dp.txt| 17 +-- drivers/phy/Kconfig|7 ++ drivers/phy/Makefile |7 +- drivers/phy/phy-exynos-dp-video.c | 111 drivers/video/exynos/Kconfig |2 +- drivers/video/exynos/exynos_dp_core.c | 132 ++-- drivers/video/exynos/exynos_dp_core.h | 110 drivers/video/exynos/exynos_dp_reg.c |2 - include/video/exynos_dp.h | 131 --- 10 files changed, 286 insertions(+), 240 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/samsung-phy.txt create mode 100644 drivers/phy/phy-exynos-dp-video.c delete mode 100644 include/video/exynos_dp.h -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] phy: Add driver for Exynos DP PHY
Add a PHY provider driver for the Samsung Exynos SoC Display Port PHY.
Signed-off-by: Jingoo Han jg1@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Acked-by: Felipe Balbi ba...@ti.com
---
.../devicetree/bindings/phy/samsung-phy.txt|7 ++
drivers/phy/Kconfig|7 ++
drivers/phy/Makefile |7 +-
drivers/phy/phy-exynos-dp-video.c | 111
4 files changed, 129 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/samsung-phy.txt
create mode 100644 drivers/phy/phy-exynos-dp-video.c
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
new file mode 100644
index 000..ee262238
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -0,0 +1,7 @@
+Samsung EXYNOS SoC series Display Port PHY
+-
+
+Required properties:
+- compatible : should be samsung,exynos5250-dp-video-phy;
+- reg : offset and length of the Display Port PHY register set;
+- #phy-cells : from the generic PHY bindings, must be 0;
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ac239ac..fed26a0 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -38,4 +38,11 @@ config TWL4030_USB
This transceiver supports high and full speed devices plus,
in host mode, low speed.
+config PHY_EXYNOS_DP_VIDEO
+ tristate EXYNOS SoC series Display Port PHY driver
+ depends on OF
+ select GENERIC_PHY
+ help
+ Support for Display Port PHY found on Samsung EXYNOS SoCs.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 0dd8a98..433e685 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -2,6 +2,7 @@
# Makefile for the phy drivers.
#
-obj-$(CONFIG_GENERIC_PHY) += phy-core.o
-obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o
-obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
+obj-$(CONFIG_GENERIC_PHY) += phy-core.o
+obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o
+obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
+obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
diff --git a/drivers/phy/phy-exynos-dp-video.c
b/drivers/phy/phy-exynos-dp-video.c
new file mode 100644
index 000..1dbe6ce
--- /dev/null
+++ b/drivers/phy/phy-exynos-dp-video.c
@@ -0,0 +1,111 @@
+/*
+ * Samsung EXYNOS SoC series Display Port PHY driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han jg1@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/phy/phy.h
+#include linux/platform_device.h
+
+/* DPTX_PHY_CONTROL register */
+#define EXYNOS_DPTX_PHY_ENABLE (1 0)
+
+struct exynos_dp_video_phy {
+ void __iomem *regs;
+};
+
+static int __set_phy_state(struct exynos_dp_video_phy *state, unsigned int on)
+{
+ u32 reg;
+
+ reg = readl(state-regs);
+ if (on)
+ reg |= EXYNOS_DPTX_PHY_ENABLE;
+ else
+ reg = ~EXYNOS_DPTX_PHY_ENABLE;
+ writel(reg, state-regs);
+
+ return 0;
+}
+
+static int exynos_dp_video_phy_power_on(struct phy *phy)
+{
+ struct exynos_dp_video_phy *state = phy_get_drvdata(phy);
+
+ return __set_phy_state(state, 1);
+}
+
+static int exynos_dp_video_phy_power_off(struct phy *phy)
+{
+ struct exynos_dp_video_phy *state = phy_get_drvdata(phy);
+
+ return __set_phy_state(state, 0);
+}
+
+static struct phy_ops exynos_dp_video_phy_ops = {
+ .power_on = exynos_dp_video_phy_power_on,
+ .power_off = exynos_dp_video_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int exynos_dp_video_phy_probe(struct platform_device *pdev)
+{
+ struct exynos_dp_video_phy *state;
+ struct device *dev = pdev-dev;
+ struct resource *res;
+ struct phy_provider *phy_provider;
+ struct phy *phy;
+
+ state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
+ if (!state)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ state-regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(state-regs))
+ return PTR_ERR(state-regs);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(phy_provider))
+ return PTR_ERR(phy_provider);
+
+ phy = devm_phy_create(dev, exynos_dp_video_phy_ops, NULL);
+ if (IS_ERR(phy)) {
+ dev_err(dev, failed to
[PATCH 2/3] video: exynos_dp: remove non-DT support for Exynos Display Port
Exynos Display Port can be used only for Exynos SoCs. In addition,
non-DT for EXYNOS SoCs is not supported from v3.11; thus, there is
no need to support non-DT for Exynos Display Port.
The 'include/video/exynos_dp.h' file has been used for non-DT
support and the content of file include/video/exynos_dp.h is moved
to drivers/video/exynos/exynos_dp_core.h. Thus, the 'exynos_dp.h'
file is removed. Also, 'struct exynos_dp_platdata' is removed,
because it is not used any more.
Signed-off-by: Jingoo Han jg1@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
drivers/video/exynos/Kconfig |2 +-
drivers/video/exynos/exynos_dp_core.c | 116 +++--
drivers/video/exynos/exynos_dp_core.h | 109 +++
drivers/video/exynos/exynos_dp_reg.c |2 -
include/video/exynos_dp.h | 131 -
5 files changed, 135 insertions(+), 225 deletions(-)
delete mode 100644 include/video/exynos_dp.h
diff --git a/drivers/video/exynos/Kconfig b/drivers/video/exynos/Kconfig
index 1b035b2..fab9019 100644
--- a/drivers/video/exynos/Kconfig
+++ b/drivers/video/exynos/Kconfig
@@ -29,7 +29,7 @@ config EXYNOS_LCD_S6E8AX0
config EXYNOS_DP
bool EXYNOS DP driver support
- depends on ARCH_EXYNOS
+ depends on OF ARCH_EXYNOS
default n
help
This enables support for DP device.
diff --git a/drivers/video/exynos/exynos_dp_core.c
b/drivers/video/exynos/exynos_dp_core.c
index 12bbede..05fed7d 100644
--- a/drivers/video/exynos/exynos_dp_core.c
+++ b/drivers/video/exynos/exynos_dp_core.c
@@ -20,8 +20,6 @@
#include linux/delay.h
#include linux/of.h
-#include video/exynos_dp.h
-
#include exynos_dp_core.h
static int exynos_dp_init_dp(struct exynos_dp_device *dp)
@@ -894,26 +892,17 @@ static void exynos_dp_hotplug(struct work_struct *work)
dev_err(dp-dev, unable to config video\n);
}
-#ifdef CONFIG_OF
-static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev)
+static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
{
struct device_node *dp_node = dev-of_node;
- struct exynos_dp_platdata *pd;
struct video_info *dp_video_config;
- pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
- if (!pd) {
- dev_err(dev, memory allocation for pdata failed\n);
- return ERR_PTR(-ENOMEM);
- }
dp_video_config = devm_kzalloc(dev,
sizeof(*dp_video_config), GFP_KERNEL);
-
if (!dp_video_config) {
dev_err(dev, memory allocation for video config failed\n);
return ERR_PTR(-ENOMEM);
}
- pd-video_info = dp_video_config;
dp_video_config-h_sync_polarity =
of_property_read_bool(dp_node, hsync-active-high);
@@ -960,7 +949,7 @@ static struct exynos_dp_platdata
*exynos_dp_dt_parse_pdata(struct device *dev)
return ERR_PTR(-EINVAL);
}
- return pd;
+ return dp_video_config;
}
static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp)
@@ -1003,48 +992,30 @@ err:
static void exynos_dp_phy_init(struct exynos_dp_device *dp)
{
- u32 reg;
+ if (dp-phy_addr) {
+ u32 reg;
- reg = __raw_readl(dp-phy_addr);
- reg |= dp-enable_mask;
- __raw_writel(reg, dp-phy_addr);
+ reg = __raw_readl(dp-phy_addr);
+ reg |= dp-enable_mask;
+ __raw_writel(reg, dp-phy_addr);
+ }
}
static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
{
- u32 reg;
-
- reg = __raw_readl(dp-phy_addr);
- reg = ~(dp-enable_mask);
- __raw_writel(reg, dp-phy_addr);
-}
-#else
-static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev)
-{
- return NULL;
-}
-
-static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp)
-{
- return -EINVAL;
-}
-
-static void exynos_dp_phy_init(struct exynos_dp_device *dp)
-{
- return;
-}
+ if (dp-phy_addr) {
+ u32 reg;
-static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
-{
- return;
+ reg = __raw_readl(dp-phy_addr);
+ reg = ~(dp-enable_mask);
+ __raw_writel(reg, dp-phy_addr);
+ }
}
-#endif /* CONFIG_OF */
static int exynos_dp_probe(struct platform_device *pdev)
{
struct resource *res;
struct exynos_dp_device *dp;
- struct exynos_dp_platdata *pdata;
int ret = 0;
@@ -1057,21 +1028,13 @@ static int exynos_dp_probe(struct platform_device *pdev)
dp-dev = pdev-dev;
- if (pdev-dev.of_node) {
- pdata = exynos_dp_dt_parse_pdata(pdev-dev);
- if (IS_ERR(pdata))
- return PTR_ERR(pdata);
+ dp-video_info = exynos_dp_dt_parse_pdata(pdev-dev);
+ if (IS_ERR(dp-video_info))
+ return
[PATCH 3/3] video: exynos_dp: Use the generic PHY driver
Use the generic PHY API to control the DP PHY.
Signed-off-by: Jingoo Han jg1@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
Documentation/devicetree/bindings/video/exynos_dp.txt | 17 +
drivers/video/exynos/exynos_dp_core.c | 16
drivers/video/exynos/exynos_dp_core.h |1 +
3 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt
b/Documentation/devicetree/bindings/video/exynos_dp.txt
index 84f10c1..3289d76 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -6,10 +6,10 @@ We use two nodes:
-dptx-phy node(defined inside dp-controller node)
For the DP-PHY initialization, we use the dptx-phy node.
-Required properties for dptx-phy:
- -reg:
+Required properties for dptx-phy: deprecated, use phys and phy-names
+ -reg: deprecated
Base address of DP PHY register.
- -samsung,enable-mask:
+ -samsung,enable-mask: deprecated
The bit-mask used to enable/disable DP PHY.
For the Panel initialization, we read data from dp-controller node.
@@ -27,6 +27,10 @@ Required properties for dp-controller:
from common clock binding: Shall be dp.
-interrupt-parent:
phandle to Interrupt combiner node.
+ -phys:
+ from general PHY binding: the phandle for the PHY device.
+ -phy-names:
+ from general PHY binding: Should be dp.
-samsung,color-space:
input video data format.
COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
@@ -68,11 +72,8 @@ SOC specific portion:
clocks = clock 342;
clock-names = dp;
- dptx-phy {
- reg = 0x10040720;
- samsung,enable-mask = 1;
- };
-
+ phys = dp_phy;
+ phy-names = dp;
};
Board Specific portion:
diff --git a/drivers/video/exynos/exynos_dp_core.c
b/drivers/video/exynos/exynos_dp_core.c
index 05fed7d..5e1a715 100644
--- a/drivers/video/exynos/exynos_dp_core.c
+++ b/drivers/video/exynos/exynos_dp_core.c
@@ -19,6 +19,7 @@
#include linux/interrupt.h
#include linux/delay.h
#include linux/of.h
+#include linux/phy/phy.h
#include exynos_dp_core.h
@@ -960,8 +961,11 @@ static int exynos_dp_dt_parse_phydata(struct
exynos_dp_device *dp)
dp_phy_node = of_find_node_by_name(dp_phy_node, dptx-phy);
if (!dp_phy_node) {
- dev_err(dp-dev, could not find dptx-phy node\n);
- return -ENODEV;
+ dp-phy = devm_phy_get(dp-dev, dp);
+ if (IS_ERR(dp-phy))
+ return PTR_ERR(dp-phy);
+ else
+ return 0;
}
if (of_property_read_u32(dp_phy_node, reg, phy_base)) {
@@ -992,7 +996,9 @@ err:
static void exynos_dp_phy_init(struct exynos_dp_device *dp)
{
- if (dp-phy_addr) {
+ if (dp-phy) {
+ phy_power_on(dp-phy);
+ } else if (dp-phy_addr) {
u32 reg;
reg = __raw_readl(dp-phy_addr);
@@ -1003,7 +1009,9 @@ static void exynos_dp_phy_init(struct exynos_dp_device
*dp)
static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
{
- if (dp-phy_addr) {
+ if (dp-phy) {
+ phy_power_off(dp-phy);
+ } else if (dp-phy_addr) {
u32 reg;
reg = __raw_readl(dp-phy_addr);
diff --git a/drivers/video/exynos/exynos_dp_core.h
b/drivers/video/exynos/exynos_dp_core.h
index 56cfec8..607e36d 100644
--- a/drivers/video/exynos/exynos_dp_core.h
+++ b/drivers/video/exynos/exynos_dp_core.h
@@ -151,6 +151,7 @@ struct exynos_dp_device {
struct video_info *video_info;
struct link_train link_train;
struct work_struct hotplug_work;
+ struct phy *phy;
};
/* exynos_dp_reg.c */
--
1.7.10.4
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[PATCH v5 4/6] ARM: dts: add dt nodes for exynos5420 hdmi subsystem
Add hdmi, mixer, ddc device tree nodes for Exynos 5420 SoC.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 15 +++
arch/arm/boot/dts/exynos5420.dtsi | 19 +++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index bafba25..140565f 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -61,4 +61,19 @@
};
};
+ hdmi@1453 {
+ status = okay;
+ hpd-gpio = gpx3 7 0;
+ };
+
+ i2c_2: i2c@12C8 {
+ samsung,i2c-sda-delay = 100;
+ samsung,i2c-max-bus-freq = 66000;
+ status = okay;
+
+ hdmiddc@50 {
+ compatible = samsung,exynos4210-hdmiddc;
+ reg = 0x50;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 05dee86..aff1679 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -274,4 +274,23 @@
pinctrl-0 = i2c3_bus;
status = disabled;
};
+
+ hdmi@1453 {
+ compatible = samsung,exynos4212-hdmi;
+ reg = 0x1453 0x7;
+ interrupts = 0 95 0;
+ clocks = clock 413, clock 143, clock 2048,
+ clock 158, clock 1024;
+ clock-names = hdmi, sclk_hdmi, sclk_pixel,
+ sclk_hdmiphy, mout_hdmi;
+ status = disabled;
+ };
+
+ mixer@1445 {
+ compatible = samsung,exynos5420-mixer;
+ reg = 0x1445 0x1;
+ interrupts = 0 94 0;
+ clocks = clock 431, clock 143;
+ clock-names = mixer, sclk_hdmi;
+ };
};
--
1.7.10.4
--
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[PATCH v5 0/6] ARM: dts: add support for exynos hdmi subsystem
It adds Device tree nodes and clocks information for HDMI subsystem for exynos5420 and exynos5250 SoCs. It adds pinctrl node for hdmi hpd gpio and update binding documents. This set is based on kukjin's for-next branch at http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git. v5: 1) Merged Clock addition patch to DT nmde addition patch. 2) Add dout_pixel clock for hdmi in place of sclk_pixel. 3) Enable mixer node in soc dtsi file. v4: 1) Remove the movement of common properties to Exynos5.dtsi for I2C and hdmi subsystem. 2) Change the title of the patches. v3: 1) Rebase to kgene for-next based on 3.11-rc1. 2) Changes clock numbers as per updated clocks file for exyno5250 and exynos5420. 3) Dropped Sachin patch as already got merged. v2: 1) Added patch for moving common i2c properties to exynos5.dtsi 2) Added patch for moving common hdmi, mixer properties to exynos5.dtsi 3) moved hpd pinctrl node to board file. 4) Added Sachin's patch to update binding document for hdmi with hpd information. Andrew Bresticker (1): ARM: dts: add i2c device nodes for Exynos5420 Rahul Sharma (4): ARM: dts: add clocks to hdmi dt node for exynos5250 ARM: dts: add dt nodes for hdmi subsystem for exynos5420 ARM: dts: add hdmi hpd gpio pinctrl node for exynos5420 of/documentation: update with clock information for exynos hdmi subsystem Sean Paul (1): ARM: dts: add mixer clocks to mixer node for Exynos5250 .../devicetree/bindings/video/exynos_hdmi.txt | 14 +++- .../devicetree/bindings/video/exynos_mixer.txt |4 ++ arch/arm/boot/dts/exynos5250.dtsi |8 ++- arch/arm/boot/dts/exynos5420-smdk5420.dts | 26 +++ arch/arm/boot/dts/exynos5420.dtsi | 75 5 files changed, 123 insertions(+), 4 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 6/6] of/documentation: update with clock information for exynos hdmi subsystem
Adding information about clocks to the binding documentation
for exynos mixer and hdmi.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
Documentation/devicetree/bindings/video/exynos_hdmi.txt | 14 +-
Documentation/devicetree/bindings/video/exynos_mixer.txt |4
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..94aaa7d 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -12,7 +12,19 @@ Required properties:
a) phandle of the gpio controller node.
b) pin number within the gpio controller.
c) optional flags and pull up/down.
-
+- clocks: list of clock IDs from SoC clock driver.
+ a) hdmi: It is required for gate operation on aclk_200_disp1 clock
+ which clocks the display1 block.
+ b) sclk_hdmi: It is required for gate operation on sclk_hdmi clock
+ which clocks hdmi IP.
+ c) sclk_pixel: Parent for mux mout_hdmi.
+ d) sclk_hdmiphy: Parent for mux mout_hdmi.
+ e) mout_hdmi: It is required by the driver to switch between the 2
+ parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable
+ after configuration, parent is set to sclk_hdmiphy else
+ sclk_pixel.
+- clock-names: aliases as per driver requirements for above clock IDs:
+ hdmi, sclk_hdmi, sclk_pixel, sclk_hdmiphy and mout_hdmi.
Example:
hdmi {
diff --git a/Documentation/devicetree/bindings/video/exynos_mixer.txt
b/Documentation/devicetree/bindings/video/exynos_mixer.txt
index 3334b0a..94b40b6 100644
--- a/Documentation/devicetree/bindings/video/exynos_mixer.txt
+++ b/Documentation/devicetree/bindings/video/exynos_mixer.txt
@@ -10,6 +10,10 @@ Required properties:
- reg: physical base address of the mixer and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
+- clocks: list of clock IDs from SoC clock driver.
+ a) mixer: It is required for gate operation on aclk_200_disp1 clock
+ which clocks the display1 block.
+ b) sclk_hdmi: Parent for mux mout_mixer.
Example:
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[PATCH v5 1/6] ARM: dts: add mixer clocks to mixer node for Exynos5250
From: Sean Paul seanp...@chromium.org
This patch adds the mixer clocks to the mixer node in the
exynos 5250 dts file.
Signed-off-by: Sean Paul seanp...@chromium.org
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 1eec646..dcb6c03 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -622,6 +622,8 @@
compatible = samsung,exynos5250-mixer;
reg = 0x1445 0x1;
interrupts = 0 94 0;
+ clocks = clock 343, clock 136;
+ clock-names = mixer, sclk_hdmi;
};
dp_phy: video-phy@10040720 {
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[PATCH v5 2/6] ARM: dts: add clocks to hdmi dt node for exynos5250
Fix wrong clock numbers in hdmi dt node. Removed hdmiphy
clock which was a dummy clock earlier and not required now.
Also added mux clock to change the clock parent.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index dcb6c03..19c8174 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -612,10 +612,10 @@
compatible = samsung,exynos4212-hdmi;
reg = 0x1453 0x7;
interrupts = 0 95 0;
- clocks = clock 333, clock 136, clock 137,
- clock 333, clock 333;
+ clocks = clock 344, clock 136, clock 137,
+ clock 159, clock 1024;
clock-names = hdmi, sclk_hdmi, sclk_pixel,
- sclk_hdmiphy, hdmiphy;
+ sclk_hdmiphy, mout_hdmi;
};
mixer {
--
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[PATCH v5 5/6] ARM: dts: add hdmi hpd gpio pinctrl node for exynos5420
Add pinctrl node for hdmi-hpd gpio pin to exynos5420
device tree files.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 140565f..79524c7 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -61,9 +61,20 @@
};
};
+ pinctrl@1340 {
+ hdmi_hpd_irq: hdmi-hpd-irq {
+ samsung,pins = gpx3-7;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+ };
+
hdmi@1453 {
status = okay;
hpd-gpio = gpx3 7 0;
+ pinctrl-names = default;
+ pinctrl-0 = hdmi_hpd_irq;
};
i2c_2: i2c@12C8 {
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[PATCH v5 3/6] ARM: dts: add i2c device nodes for Exynos5420
From: Andrew Bresticker abres...@chromium.org
This adds device-tree nodes for the i2c busses on Exynos
5420 platforms.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 56 +
1 file changed, 56 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 5353e32..05dee86 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -27,6 +27,10 @@
pinctrl2 = pinctrl_2;
pinctrl3 = pinctrl_3;
pinctrl4 = pinctrl_4;
+ i2c0 = i2c_0;
+ i2c1 = i2c_1;
+ i2c2 = i2c_2;
+ i2c3 = i2c_3;
};
cpus {
@@ -218,4 +222,56 @@
clocks = clock 147, clock 421;
clock-names = sclk_fimd, fimd;
};
+
+ i2c_0: i2c@12C6 {
+ compatible = samsung,s3c2440-i2c;
+ reg = 0x12C6 0x100;
+ interrupts = 0 56 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = clock 261;
+ clock-names = i2c;
+ pinctrl-names = default;
+ pinctrl-0 = i2c0_bus;
+ status = disabled;
+ };
+
+ i2c_1: i2c@12C7 {
+ compatible = samsung,s3c2440-i2c;
+ reg = 0x12C7 0x100;
+ interrupts = 0 57 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = clock 262;
+ clock-names = i2c;
+ pinctrl-names = default;
+ pinctrl-0 = i2c1_bus;
+ status = disabled;
+ };
+
+ i2c_2: i2c@12C8 {
+ compatible = samsung,s3c2440-i2c;
+ reg = 0x12C8 0x100;
+ interrupts = 0 58 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = clock 263;
+ clock-names = i2c;
+ pinctrl-names = default;
+ pinctrl-0 = i2c2_bus;
+ status = disabled;
+ };
+
+ i2c_3: i2c@12C9 {
+ compatible = samsung,s3c2440-i2c;
+ reg = 0x12C9 0x100;
+ interrupts = 0 59 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = clock 264;
+ clock-names = i2c;
+ pinctrl-names = default;
+ pinctrl-0 = i2c3_bus;
+ status = disabled;
+ };
};
--
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Re: [RFC V2 1/4] mmc: dw_mmc: exynos: move the exynos private init
On Fri, Aug 23, 2013 at 7:14 PM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi Yuvaraj,
On 08/23/2013 08:15 PM, Yuvaraj Kumar C D wrote:
Currently platform specific private data initialisation is done by
dw_mci_exynos_priv_init and dw_mci_exynos_parse_dt.As we already have
separate platform specific device tree parser dw_mci_exynos_parse_dt,
move the dw_mci_exynos_priv_init code to dw_mci_exynos_parse_dt.
We can use the dw_mci_exynos_priv_init to do some actual platform
specific initialisation of SMU and etc.
changes since V1: none
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
drivers/mmc/host/dw_mmc-exynos.c | 31 +++
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c
b/drivers/mmc/host/dw_mmc-exynos.c
index 9990f98..19c845b 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -72,22 +72,8 @@ static struct dw_mci_exynos_compatible {
static int dw_mci_exynos_priv_init(struct dw_mci *host)
{
- struct dw_mci_exynos_priv_data *priv;
- int idx;
-
- priv = devm_kzalloc(host-dev, sizeof(*priv), GFP_KERNEL);
- if (!priv) {
- dev_err(host-dev, mem alloc failed for private data\n);
- return -ENOMEM;
- }
-
- for (idx = 0; idx ARRAY_SIZE(exynos_compat); idx++) {
- if (of_device_is_compatible(host-dev-of_node,
- exynos_compat[idx].compatible))
- priv-ctrl_type = exynos_compat[idx].ctrl_type;
- }
+ struct dw_mci_exynos_priv_data *priv = host-priv;
- host-priv = priv;
return 0;
}
@@ -177,12 +163,24 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host,
struct mmc_ios *ios)
static int dw_mci_exynos_parse_dt(struct dw_mci *host)
{
- struct dw_mci_exynos_priv_data *priv = host-priv;
+ struct dw_mci_exynos_priv_data *priv;
struct device_node *np = host-dev-of_node;
u32 timing[2];
u32 div = 0;
+ int idx;
int ret;
+ priv = devm_kzalloc(host-dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ dev_err(host-dev, mem alloc failed for private data\n);
+ return -ENOMEM;
+ }
+
+ for (idx = 0; idx ARRAY_SIZE(exynos_compat); idx++) {
+ if (of_device_is_compatible(np, exynos_compat[idx].compatible))
+ priv-ctrl_type = exynos_compat[idx].ctrl_type;
+ }
+
of_property_read_u32(np, samsung,dw-mshc-ciu-div, div);
priv-ciu_div = div;
@@ -199,6 +197,7 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
return ret;
priv-ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
+ host-priv = priv;
I'm not sure whether my thinking is right or not.
if host-pdata is present, then dw_mci_parse_dt() didn't called at
dw_mci_probe.
Yes, you are right.
then how host-priv set to priv?
Earlier host-priv set to priv in both non-DT and DT case.True, with
this patch it does it only in DT case.
Is there any platform/board which still uses dw_mmc and its platform
extension driver with non DT case?
I found a reference of non-DT case where host-pdata is present in
dw_mmc-pci.c driver but does not
use platform extension driver (exynos/socfpga).
Best Regards,
Jaehoon Chung
return 0;
}
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Re: [PATCH V7 0/3] Generic PHY driver for the Exynos SoC DP PHY
On Monday 26 August 2013 02:25 PM, Jingoo Han wrote: This patch series adds a simple driver for the Samsung Exynos SoC series DP transmitter PHY, using the generic PHY framework [1]. Previously the DP PHY used an internal DT node to control the PHY power enable bit. These patches was tested on Exynos5250. This PATCH v7 follows: * PATCH v6, sent on July, 9th 2013 * PATCH v5, sent on July, 8th 2013 * PATCH v4, sent on July, 2nd 2013 * PATCH v3, sent on July, 1st 2013 * PATCH v2, sent on June, 28th 2013 * PATCH v1, sent on June, 28th 2013 Changes from v6: * Re-based on git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git Changes from v5: * Re-based on git://gitorious.org/linuxphy/linuxphy.git Changes from v4: * Marked original bindings as deprecated in 'exynos_dp.txt' * Fixed typo of commit message. * Added Tomasz Figa's Reviewed-by. Changes from v3: * Added OF dependancy. * Removed redundant local variable 'void __iomem *addr'. * Removed unnecessary dev_set_drvdata(). * Added a patch that remove non-DT support for Exynos Display Port driver. * Removed unnecessary 'struct exynos_dp_platdata'. * Kept supporting the original bindings for DT compatibility. Changes from v2: * Removed redundant spinlock * Removed 'struct phy' from 'struct exynos_dp_video_phy' * Updated 'samsung-phy.txt', instead of creating 'samsung,exynos5250-dp-video-phy.txt'. * Removed unnecessary additional specifier from 'phys' DT property. * Added 'phys', 'phy-names' properties to 'exynos_dp.txt' file. * Added Felipe Balbi's Acked-by. Changes from v1: * Replaced exynos_dp_video_phy_xlate() with of_phy_simple_xlate(), as Kishon Vijay Abraham I guided. * Set the value of phy-cells as 0, because the phy_provider implements only one PHY. * Removed unnecessary header include. * Added '#ifdef CONFIG_OF' and of_match_ptr macro. This series depends on the generic PHY framework [1]. These patches refer to Sylwester Nawrocki's patches about Exynos MIPI [2]. [1] http://lwn.net/Articles/564188/ [2] http://www.spinics.net/lists/linux-samsung-soc/msg20098.html Jingoo Han (3): phy: Add driver for Exynos DP PHY video: exynos_dp: remove non-DT support for Exynos Display Port video: exynos_dp: Use the generic PHY driver FWIW, Acked-by: Kishon Vijay Abraham I kis...@ti.com -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL 3/3] 2nd Round Samsung mach-exynos for v3.12
Hi,
On Monday, August 26, 2013 09:14:42 AM Kukjin Kim wrote:
The following changes since commit ad81f0545ef01ea651886dddac4bef6cec930092:
Linux 3.11-rc1 (2013-07-14 15:18:27 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/samsung-mach-exynos
for you to fetch changes up to f52616f4233d71d0fb00f06f86d046d18d2b7f3b:
ARM: EXYNOS: always enable PM domains support for EXYNOS4X12 (2013-08-19
05:05:16 +0900)
update mach-exynos
- enable ARCH_HAS_BANDGAP for exynos SoCs
- skip C1 cpuidle for exynos5440 because non-supporting
- always enable PM domains for exynos4x12
Amit Daniel Kachhap (2):
ARM: EXYNOS: enable ARCH_HAS_BANDGAP
ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
The patch ARM: EXYNOS: Skip C1 cpuidle state for exynos5440:
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -210,7 +210,7 @@ static int __init exynos4_init_cpuidle(void)
device-cpu = cpu_id;
/* Support IDLE only */
- if (cpu_id != 0)
+ if (soc_is_exynos5440() || cpu_id != 0)
device-state_count = 1;
ret = cpuidle_register_device(device);
is incorrect as noted a month ago in:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/186355.html
[ Because of the deficiency in the core cpuidle core (device-state_count
not being used by governors' code) only sysfs entries for C1 state will be
disabled and EXYNOS cpuidle driver will still attempt to use C1 state.
also non-working device-state_count is planned to be removed by:
http://permalink.gmane.org/gmane.linux.power-management.general/37390
To disable C1 state on EXYNOS5440 something like:
static int __init exynos4_init_cpuidle(void)
{
...
if (soc_is_exynos5440())
exynos4_idle_driver.state_count = 1;
...
}
should be done instead.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
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Re: [GIT PULL 3/3] 2nd Round Samsung mach-exynos for v3.12
Hi,
On Mon, Aug 26, 2013 at 3:36 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
Hi,
On Monday, August 26, 2013 09:14:42 AM Kukjin Kim wrote:
The following changes since commit ad81f0545ef01ea651886dddac4bef6cec930092:
Linux 3.11-rc1 (2013-07-14 15:18:27 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/samsung-mach-exynos
for you to fetch changes up to f52616f4233d71d0fb00f06f86d046d18d2b7f3b:
ARM: EXYNOS: always enable PM domains support for EXYNOS4X12 (2013-08-19
05:05:16 +0900)
update mach-exynos
- enable ARCH_HAS_BANDGAP for exynos SoCs
- skip C1 cpuidle for exynos5440 because non-supporting
- always enable PM domains for exynos4x12
Amit Daniel Kachhap (2):
ARM: EXYNOS: enable ARCH_HAS_BANDGAP
ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
The patch ARM: EXYNOS: Skip C1 cpuidle state for exynos5440:
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -210,7 +210,7 @@ static int __init exynos4_init_cpuidle(void)
device-cpu = cpu_id;
/* Support IDLE only */
- if (cpu_id != 0)
+ if (soc_is_exynos5440() || cpu_id != 0)
device-state_count = 1;
ret = cpuidle_register_device(device);
is incorrect as noted a month ago in:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/186355.html
[ Because of the deficiency in the core cpuidle core (device-state_count
not being used by governors' code) only sysfs entries for C1 state will be
disabled and EXYNOS cpuidle driver will still attempt to use C1 state.
also non-working device-state_count is planned to be removed by:
http://permalink.gmane.org/gmane.linux.power-management.general/37390
I looked at your patch series and it seems reasonable. I will repost
this patch on top of yours.
But I suggest to keep this patch temporary till your patch series gets merged.
Thanks,
Amit Daniel
To disable C1 state on EXYNOS5440 something like:
static int __init exynos4_init_cpuidle(void)
{
...
if (soc_is_exynos5440())
exynos4_idle_driver.state_count = 1;
...
}
should be done instead.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
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On Mon, Aug 26, 2013 at 3:36 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
Hi,
On Monday, August 26, 2013 09:14:42 AM Kukjin Kim wrote:
The following changes since commit ad81f0545ef01ea651886dddac4bef6cec930092:
Linux 3.11-rc1 (2013-07-14 15:18:27 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/samsung-mach-exynos
for you to fetch changes up to f52616f4233d71d0fb00f06f86d046d18d2b7f3b:
ARM: EXYNOS: always enable PM domains support for EXYNOS4X12 (2013-08-19
05:05:16 +0900)
update mach-exynos
- enable ARCH_HAS_BANDGAP for exynos SoCs
- skip C1 cpuidle for exynos5440 because non-supporting
- always enable PM domains for exynos4x12
Amit Daniel Kachhap (2):
ARM: EXYNOS: enable ARCH_HAS_BANDGAP
ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
The patch ARM: EXYNOS: Skip C1 cpuidle state for exynos5440:
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -210,7 +210,7 @@ static int __init exynos4_init_cpuidle(void)
device-cpu = cpu_id;
/* Support IDLE only */
- if (cpu_id != 0)
+ if (soc_is_exynos5440() || cpu_id != 0)
device-state_count = 1;
ret = cpuidle_register_device(device);
is incorrect as noted a month ago in:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/186355.html
[ Because of the deficiency in the core cpuidle core (device-state_count
not being used by governors' code) only sysfs entries for C1 state will be
disabled and EXYNOS cpuidle driver will still attempt to use C1 state.
also non-working device-state_count is planned to be removed by:
http://permalink.gmane.org/gmane.linux.power-management.general/37390
To disable C1 state on EXYNOS5440 something like:
static int __init exynos4_init_cpuidle(void)
{
...
if (soc_is_exynos5440())
exynos4_idle_driver.state_count = 1;
...
}
Re: [GIT PULL 3/3] 2nd Round Samsung mach-exynos for v3.12
On Monday, August 26, 2013 04:33:55 PM amit daniel kachhap wrote:
Hi,
On Mon, Aug 26, 2013 at 3:36 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
Hi,
On Monday, August 26, 2013 09:14:42 AM Kukjin Kim wrote:
The following changes since commit
ad81f0545ef01ea651886dddac4bef6cec930092:
Linux 3.11-rc1 (2013-07-14 15:18:27 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/samsung-mach-exynos
for you to fetch changes up to f52616f4233d71d0fb00f06f86d046d18d2b7f3b:
ARM: EXYNOS: always enable PM domains support for EXYNOS4X12 (2013-08-19
05:05:16 +0900)
update mach-exynos
- enable ARCH_HAS_BANDGAP for exynos SoCs
- skip C1 cpuidle for exynos5440 because non-supporting
- always enable PM domains for exynos4x12
Amit Daniel Kachhap (2):
ARM: EXYNOS: enable ARCH_HAS_BANDGAP
ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
The patch ARM: EXYNOS: Skip C1 cpuidle state for exynos5440:
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -210,7 +210,7 @@ static int __init exynos4_init_cpuidle(void)
device-cpu = cpu_id;
/* Support IDLE only */
- if (cpu_id != 0)
+ if (soc_is_exynos5440() || cpu_id != 0)
device-state_count = 1;
ret = cpuidle_register_device(device);
is incorrect as noted a month ago in:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/186355.html
[ Because of the deficiency in the core cpuidle core (device-state_count
not being used by governors' code) only sysfs entries for C1 state will be
disabled and EXYNOS cpuidle driver will still attempt to use C1 state.
also non-working device-state_count is planned to be removed by:
http://permalink.gmane.org/gmane.linux.power-management.general/37390
I looked at your patch series and it seems reasonable. I will repost
this patch on top of yours.
If you correctly use driver's state_count (instead of device's) there will be
no dependency on my patch series and the new patch can be applied immediately.
But I suggest to keep this patch temporary till your patch series gets merged.
The current patch (the one Kukjin merged) is incorrect as it just doesn't
do what it advertises. I see no reason to keep it.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
Thanks,
Amit Daniel
To disable C1 state on EXYNOS5440 something like:
static int __init exynos4_init_cpuidle(void)
{
...
if (soc_is_exynos5440())
exynos4_idle_driver.state_count = 1;
...
}
should be done instead.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
___
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On Mon, Aug 26, 2013 at 3:36 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
Hi,
On Monday, August 26, 2013 09:14:42 AM Kukjin Kim wrote:
The following changes since commit
ad81f0545ef01ea651886dddac4bef6cec930092:
Linux 3.11-rc1 (2013-07-14 15:18:27 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/samsung-mach-exynos
for you to fetch changes up to f52616f4233d71d0fb00f06f86d046d18d2b7f3b:
ARM: EXYNOS: always enable PM domains support for EXYNOS4X12 (2013-08-19
05:05:16 +0900)
update mach-exynos
- enable ARCH_HAS_BANDGAP for exynos SoCs
- skip C1 cpuidle for exynos5440 because non-supporting
- always enable PM domains for exynos4x12
Amit Daniel Kachhap (2):
ARM: EXYNOS: enable ARCH_HAS_BANDGAP
ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
The patch ARM: EXYNOS: Skip C1 cpuidle state for exynos5440:
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -210,7 +210,7 @@ static int __init exynos4_init_cpuidle(void)
device-cpu = cpu_id;
/* Support IDLE only */
- if (cpu_id != 0)
+ if (soc_is_exynos5440() || cpu_id != 0)
device-state_count = 1;
ret = cpuidle_register_device(device);
is incorrect as noted a month ago in:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/186355.html
[ Because of the deficiency in the
[PATCH RFC 0/5] ARM: s5pv210: move to common clk framework
This patch series is the new s5pv210 clock implementation (using common clk framework). This implementation is compatible with device tree definition and board files. This patch series is based on linux-next and has been tested on goni and aquila boards using board file. This patch series require adding new registration method for PLL45xx and PLL46xx, which is included in this patch series: clk: samsung: pll: Use new registration method for PLL46xx http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg21653.html clk: samsung: pll: Use new registration method for PLL45xx http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg21652.html clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls http://www.spinics.net/lists/arm-kernel/msg268486.html Mateusz Krawczuk (5): media: s5p-tv: Fix sdo driver to work with CCF media: s5p-tv: Fix mixer driver to work with CCF ARM: samsung: add clock setup for FIMC and FIMD clk: samsung: Add clock driver for s5pc110/s5pv210 ARM: s5pv210: Migrate clock handling to Common Clock Framework .../bindings/clock/samsung,s5pv210-clock.txt | 72 ++ arch/arm/mach-s5pv210/Kconfig | 9 + arch/arm/mach-s5pv210/Makefile | 4 +- arch/arm/mach-s5pv210/common.c | 22 + arch/arm/mach-s5pv210/common.h | 13 + arch/arm/mach-s5pv210/mach-aquila.c| 1 + arch/arm/mach-s5pv210/mach-goni.c | 51 +- arch/arm/mach-s5pv210/mach-smdkc110.c | 1 + arch/arm/mach-s5pv210/mach-smdkv210.c | 1 + arch/arm/mach-s5pv210/mach-torbreck.c | 1 + arch/arm/plat-samsung/Kconfig | 2 +- arch/arm/plat-samsung/init.c | 2 - drivers/clk/samsung/Makefile | 3 +- drivers/clk/samsung/clk-s5pv210.c | 732 + drivers/media/platform/s5p-tv/mixer_drv.c | 33 +- drivers/media/platform/s5p-tv/sdo_drv.c| 44 +- include/dt-bindings/clock/samsung,s5pv210-clock.h | 221 +++ 17 files changed, 1189 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt create mode 100644 drivers/clk/samsung/clk-s5pv210.c create mode 100644 include/dt-bindings/clock/samsung,s5pv210-clock.h -- 1.8.1.2 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC 5/5] ARM: s5pv210: Migrate clock handling to Common Clock Framework
This patch migrates the s5pv210 platform to use new clock driver
using Common Clock Framework.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
---
arch/arm/mach-s5pv210/Kconfig | 9 +
arch/arm/mach-s5pv210/Makefile| 4 ++--
arch/arm/mach-s5pv210/common.c| 22 ++
arch/arm/mach-s5pv210/common.h| 13 +
arch/arm/mach-s5pv210/mach-aquila.c | 1 +
arch/arm/mach-s5pv210/mach-goni.c | 3 ++-
arch/arm/mach-s5pv210/mach-smdkc110.c | 1 +
arch/arm/mach-s5pv210/mach-smdkv210.c | 1 +
arch/arm/mach-s5pv210/mach-torbreck.c | 1 +
arch/arm/plat-samsung/Kconfig | 2 +-
arch/arm/plat-samsung/init.c | 2 --
11 files changed, 53 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index caaedaf..ad4546e 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -15,6 +15,7 @@ config CPU_S5PV210
select S5P_PM if PM
select S5P_SLEEP if PM
select SAMSUNG_DMADEV
+ select S5P_CLOCK if !COMMON_CLK
help
Enable S5PV210 CPU support
@@ -69,6 +70,14 @@ config S5PV210_SETUP_USB_PHY
help
Common setup code for USB PHY controller
+config COMMON_CLK_S5PV210
+ bool Common Clock Framework support
+ default y
+ select COMMON_CLK
+ help
+ Enable this option to use new clock driver
+ based on Common Clock Framework.
+
menu S5PC110 Machines
config MACH_AQUILA
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 1c4e419..0c67fe2 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -12,8 +12,8 @@ obj- :=
# Core
-obj-y += common.o clock.o
-
+obj-y += common.o
+obj-$(CONFIG_S5P_CLOCK)+= clock.o
obj-$(CONFIG_PM) += pm.o
obj-y += dma.o
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 26027a2..3c3dd05 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -34,7 +34,13 @@
#include mach/regs-clock.h
#include plat/cpu.h
+
+#ifdef CONFIG_S5P_CLOCK
#include plat/clock.h
+#else
+#include linux/clk-provider.h
+#endif
+
#include plat/devs.h
#include plat/sdhci.h
#include plat/adc-core.h
@@ -50,6 +56,19 @@
#include common.h
+/* External clock frequency */
+static unsigned long xxti_f, xusbxti_f;
+
+void __init s5pv210_set_xxti_freq(unsigned long freq)
+{
+ xxti_f = freq;
+}
+
+void __init s5pv210_set_xusbxti_freq(unsigned long freq)
+{
+ xusbxti_f = freq;
+}
+
static const char name_s5pv210[] = S5PV210/S5PC110;
static struct cpu_table cpu_ids[] __initdata = {
@@ -229,12 +248,14 @@ void __init s5pv210_map_io(void)
void __init s5pv210_init_clocks(int xtal)
{
+#ifdef CONFIG_S5P_CLOCK
printk(KERN_DEBUG %s: initializing clocks\n, __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
s5pv210_register_clocks();
s5pv210_setup_clocks();
+#endif
}
void __init s5pv210_init_irq(void)
@@ -248,6 +269,7 @@ void __init s5pv210_init_irq(void)
vic[3] = ~0;
s5p_init_irq(vic, ARRAY_SIZE(vic));
+ s5pv210_clk_init(NULL, xxti_f, xusbxti_f, S3C_VA_SYS);
}
struct bus_type s5pv210_subsys = {
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index fe1beb5..2db2a15 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -14,6 +14,19 @@
#include linux/reboot.h
+void s5pv210_set_xxti_freq(unsigned long freq);
+void s5pv210_set_xusbxti_freq(unsigned long freq);
+
+#ifdef CONFIG_COMMON_CLK_S5PV210
+void s5pv210_clk_init(struct device_node *np,
+ unsigned long xxti_f, unsigned long xusbxti_f,
+ void __iomem *reg_base);
+#else
+static inline void s5pv210_clk_init(struct device_node *np,
+ unsigned long xxti_f, unsigned long xusbxti_f,
+ void __iomem *reg_base) {}
+#endif
+
void s5pv210_init_io(struct map_desc *mach_desc, int size);
void s5pv210_init_irq(void);
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c
b/arch/arm/mach-s5pv210/mach-aquila.c
index ad40ab0..e37a311 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -646,6 +646,7 @@ static void __init aquila_map_io(void)
{
s5pv210_init_io(NULL, 0);
s3c24xx_init_clocks(2400);
+ s5pv210_set_xusbxti_freq(2400);
s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
}
diff --git a/arch/arm/mach-s5pv210/mach-goni.c
b/arch/arm/mach-s5pv210/mach-goni.c
index 309b5ad..a306c3b 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++
[PATCH RFC 3/5] ARM: samsung: add clock setup for FIMC and FIMD
This patch adds code that sets correct parents and rates for clocks
used by FIMC and FIMD on Goni board.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
---
arch/arm/mach-s5pv210/mach-goni.c | 48 +++
1 file changed, 48 insertions(+)
diff --git a/arch/arm/mach-s5pv210/mach-goni.c
b/arch/arm/mach-s5pv210/mach-goni.c
index e5cd9fb..309b5ad 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -55,6 +55,7 @@
#include media/s5p_fimc.h
#include media/noon010pc30.h
+#include linux/clk.h
#include common.h
/* Following are default values for UCON, ULCON and UFCON UART registers */
@@ -195,6 +196,49 @@ static struct platform_device goni_spi_gpio = {
},
};
+static void set_fimd_clock(void)
+{
+ struct clk *lcd_clk, *parent_clk;
+
+ lcd_clk = clk_get(NULL, sclk_fimd);
+ parent_clk = clk_get(NULL, mout_mpll);
+ clk_set_parent(lcd_clk, parent_clk);
+ clk_set_rate(lcd_clk, clk_get_rate(parent_clk)/3);
+
+ clk_put(parent_clk);
+ clk_put(lcd_clk);
+}
+
+static void set_fimc_clock(void)
+{
+ struct clk *cam0_clk, *cam1_clk, *fimc2_clk, *fimc1_clk,
+ *fimc0_clk, *parent_clk, *vpll_clk, *csis_clk;
+
+ parent_clk = clk_get(NULL, mout_mpll);
+ vpll_clk = clk_get(NULL, mout_vpll);
+ cam0_clk = clk_get(NULL, mout_cam0);
+ cam1_clk = clk_get(NULL, mout_cam1);
+ fimc2_clk = clk_get(NULL, mout_fimc2);
+ fimc1_clk = clk_get(NULL, mout_fimc1);
+ fimc0_clk = clk_get(NULL, mout_fimc0);
+ csis_clk = clk_get(NULL, mout_csis);
+
+ clk_set_parent(cam0_clk, vpll_clk);
+ clk_set_parent(cam1_clk, vpll_clk);
+ clk_set_parent(fimc2_clk, parent_clk);
+ clk_set_parent(fimc1_clk, parent_clk);
+ clk_set_parent(fimc0_clk, parent_clk);
+ clk_set_parent(csis_clk, parent_clk);
+
+ clk_put(parent_clk);
+ clk_put(vpll_clk);
+ clk_put(cam0_clk);
+ clk_put(cam1_clk);
+ clk_put(fimc2_clk);
+ clk_put(fimc1_clk);
+ clk_put(fimc0_clk);
+}
+
/* KEYPAD */
static uint32_t keymap[] __initdata = {
/* KEY(row, col, keycode) */
@@ -931,6 +975,10 @@ static void __init goni_machine_init(void)
s3c_i2c2_set_platdata(i2c2_data);
i2c_register_board_info(2, i2c2_devs, ARRAY_SIZE(i2c2_devs));
+ /* FIMD AND FIMC set clock config */
+ set_fimd_clock();
+ set_fimc_clock();
+
/* PMIC */
goni_pmic_init();
i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs,
--
1.8.1.2
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[PATCH RFC 4/5] clk: samsung: Add clock driver for s5pc110/s5pv210
This patch adds new, Common Clock Framework-based clock driver for Samsung
S5PV210 SoCs. The driver is just added, without enabling it yet.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
---
.../bindings/clock/samsung,s5pv210-clock.txt | 72 ++
drivers/clk/samsung/Makefile | 3 +-
drivers/clk/samsung/clk-s5pv210.c | 732 +
include/dt-bindings/clock/samsung,s5pv210-clock.h | 221 +++
4 files changed, 1027 insertions(+), 1 deletion(-)
create mode 100644
Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
create mode 100644 drivers/clk/samsung/clk-s5pv210.c
create mode 100644 include/dt-bindings/clock/samsung,s5pv210-clock.h
diff --git a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
new file mode 100644
index 000..753c8f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
@@ -0,0 +1,72 @@
+* Samsung S5PC110/S5PV210 Clock Controller
+
+The S5PV210 clock controller generates and supplies clock to various
controllers
+within the SoC. The clock binding described here is applicable to all SoCs in
+the S5PC110/S5PV210 family.
+
+Required Properties:
+
+- compatible: should be one of the following.
+ - samsung,s5pv210-clock - controller compatible with S5PC110/S5PV210 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. Some of the clocks are available only
+on a particular S5PC110/S5PV210 SoC and this is specified where applicable.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/samsung,s5pv210-clock.h header and can be used in device
+tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - xxti- xtal - required
+ - xusbxti - USB xtal - required,
+
+
+Example: Clock controller node:
+
+ clock: clock-controller@7e00f000 {
+ compatible = samsung,s5pv210-clock;
+ reg = 0x7e00f000 0x1000;
+ #clock-cells = 1;
+ };
+
+Example: Required external clocks:
+
+ fin_pll: clock-xxti {
+ compatible = fixed-clock;
+ clock-output-names = xxti;
+ clock-frequency = 1200;
+ #clock-cells = 0;
+ };
+
+ xusbxti: clock-xusbxti {
+ compatible = fixed-clock;
+ clock-output-names = xusbxti;
+ clock-frequency = 4800;
+ #clock-cells = 0;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller (refer to the standard clock bindings for information about
+ clocks and clock-names properties):
+
+ uart0: serial@7f005000 {
+ compatible = samsung,s5pv210-uart;
+ reg = 0x7f005000 0x100;
+ interrupt-parent = vic1;
+ interrupts = 5;
+ clock-names = uart, clk_uart_baud2,
+ clk_uart_baud3;
+ clocks = clock PCLK_UART0, clocks PCLK_UART0,
+ clock SCLK_UART;
+ status = disabled;
+ };
\ No newline at end of file
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 3413380..aeef616 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -10,4 +10,5 @@ obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
ifdef CONFIG_COMMON_CLK
obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
-endif
+obj-$(CONFIG_ARCH_S5PV210) += clk-s5pv210.o
+endif
\ No newline at end of file
diff --git a/drivers/clk/samsung/clk-s5pv210.c
b/drivers/clk/samsung/clk-s5pv210.c
new file mode 100644
index 000..861d37d
--- /dev/null
+++ b/drivers/clk/samsung/clk-s5pv210.c
@@ -0,0 +1,732 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Mateusz Krawczuk m.krawc...@partner.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all S5PC110/S5PV210 SoCs.
+*/
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+#include mach/regs-clock.h
+
+#include clk.h
+#include clk-pll.h
+
+#include dt-bindings/clock/samsung,s5pv210-clock.h
+
+/* S5PC110/S5PV210 clock controller register offsets */
+#define
[PATCH RFC 2/5] media: s5p-tv: Fix mixer driver to work with CCF
Replace clk_enable by clock_enable_prepare and clk_disable with
clk_disable_unprepare.
Clock prepare is required by Clock Common Framework, and old clock driver
didn`t support it.
Without it Common Clock Framework prints a warning.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
---
drivers/media/platform/s5p-tv/mixer_drv.c | 33 +--
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/media/platform/s5p-tv/mixer_drv.c
b/drivers/media/platform/s5p-tv/mixer_drv.c
index 51805a5..f889591 100644
--- a/drivers/media/platform/s5p-tv/mixer_drv.c
+++ b/drivers/media/platform/s5p-tv/mixer_drv.c
@@ -345,21 +345,42 @@ fail:
static int mxr_runtime_resume(struct device *dev)
{
+ int ret = 0;
struct mxr_device *mdev = to_mdev(dev);
struct mxr_resources *res = mdev-res;
mxr_dbg(mdev, resume - start\n);
mutex_lock(mdev-mutex);
/* turn clocks on */
- clk_enable(res-mixer);
- clk_enable(res-vp);
- clk_enable(res-sclk_mixer);
+ ret = clk_prepare_enable(res-mixer);
+ if (ret 0) {
+ dev_err(dev, clk_prepare_enable(mixer) failed\n);
+ goto fail;
+ }
+ ret = clk_prepare_enable(res-vp);
+ if (ret 0) {
+ dev_err(dev, clk_prepare_enable(vp) failed\n);
+ goto fail_mixer;
+ }
+ ret = clk_prepare_enable(res-sclk_mixer);
+ if (ret 0) {
+ dev_err(dev, clk_prepare_enable(sclk_mixer) failed\n);
+ goto fail_vp;
+ }
/* apply default configuration */
mxr_reg_reset(mdev);
mxr_dbg(mdev, resume - finished\n);
mutex_unlock(mdev-mutex);
return 0;
+fail_vp:
+ clk_disable_unprepare(res-vp);
+fail_mixer:
+ clk_disable_unprepare(res-mixer);
+fail:
+ mutex_unlock(mdev-mutex);
+ dev_info(dev, resume failed\n);
+ return ret;
}
static int mxr_runtime_suspend(struct device *dev)
@@ -369,9 +390,9 @@ static int mxr_runtime_suspend(struct device *dev)
mxr_dbg(mdev, suspend - start\n);
mutex_lock(mdev-mutex);
/* turn clocks off */
- clk_disable(res-sclk_mixer);
- clk_disable(res-vp);
- clk_disable(res-mixer);
+ clk_disable_unprepare(res-sclk_mixer);
+ clk_disable_unprepare(res-vp);
+ clk_disable_unprepare(res-mixer);
mutex_unlock(mdev-mutex);
mxr_dbg(mdev, suspend - finished\n);
return 0;
--
1.8.1.2
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[PATCH RFC 1/5] media: s5p-tv: Fix sdo driver to work with CCF
Replace clk_enable by clock_enable_prepare and clk_disable with
clk_disable_unprepare.
Clock prepare is required by Clock Common Framework, and old clock driver
didn`t support it.
Without it Common Clock Framework prints a warning.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
---
drivers/media/platform/s5p-tv/sdo_drv.c | 44 +
1 file changed, 34 insertions(+), 10 deletions(-)
diff --git a/drivers/media/platform/s5p-tv/sdo_drv.c
b/drivers/media/platform/s5p-tv/sdo_drv.c
index 0afa90f..77eac6d 100644
--- a/drivers/media/platform/s5p-tv/sdo_drv.c
+++ b/drivers/media/platform/s5p-tv/sdo_drv.c
@@ -55,6 +55,8 @@ struct sdo_device {
struct clk *dacphy;
/** clock for control of VPLL */
struct clk *fout_vpll;
+ /** vpll rate before sdo stream was on */
+ int vpll_rate;
/** regulator for SDO IP power */
struct regulator *vdac;
/** regulator for SDO plug detection */
@@ -193,17 +195,34 @@ static int sdo_s_power(struct v4l2_subdev *sd, int on)
static int sdo_streamon(struct sdo_device *sdev)
{
+ int ret = 0;
+
/* set proper clock for Timing Generator */
- clk_set_rate(sdev-fout_vpll, 5400);
+ sdev-vpll_rate = clk_get_rate(sdev-fout_vpll);
+ ret = clk_set_rate(sdev-fout_vpll, 5400);
+ if (ret 0) {
+ dev_err(sdev-dev,
+ %s: Failed to set vpll rate!\n, __func__);
+ return ret;
+ }
dev_info(sdev-dev, fout_vpll.rate = %lu\n,
clk_get_rate(sdev-fout_vpll));
/* enable clock in SDO */
sdo_write_mask(sdev, SDO_CLKCON, ~0, SDO_TVOUT_CLOCK_ON);
- clk_enable(sdev-dacphy);
+ ret = clk_prepare_enable(sdev-dacphy);
+ if (ret 0) {
+ dev_err(sdev-dev,
+ %s: Failed to prepare and enable clock !\n, __func__);
+ goto fail;
+ }
/* enable DAC */
sdo_write_mask(sdev, SDO_DAC, ~0, SDO_POWER_ON_DAC);
sdo_reg_debug(sdev);
return 0;
+fail:
+ sdo_write_mask(sdev, SDO_CLKCON, 0, SDO_TVOUT_CLOCK_ON);
+ clk_set_rate(sdev-fout_vpll, sdev-vpll_rate);
+ return ret;
}
static int sdo_streamoff(struct sdo_device *sdev)
@@ -211,7 +230,7 @@ static int sdo_streamoff(struct sdo_device *sdev)
int tries;
sdo_write_mask(sdev, SDO_DAC, 0, SDO_POWER_ON_DAC);
- clk_disable(sdev-dacphy);
+ clk_disable_unprepare(sdev-dacphy);
sdo_write_mask(sdev, SDO_CLKCON, 0, SDO_TVOUT_CLOCK_ON);
for (tries = 100; tries; --tries) {
if (sdo_read(sdev, SDO_CLKCON) SDO_TVOUT_CLOCK_READY)
@@ -220,6 +239,7 @@ static int sdo_streamoff(struct sdo_device *sdev)
}
if (tries == 0)
dev_err(sdev-dev, failed to stop streaming\n);
+ clk_set_rate(sdev-fout_vpll, sdev-vpll_rate);
return tries ? 0 : -EIO;
}
@@ -254,7 +274,7 @@ static int sdo_runtime_suspend(struct device *dev)
dev_info(dev, suspend\n);
regulator_disable(sdev-vdet);
regulator_disable(sdev-vdac);
- clk_disable(sdev-sclk_dac);
+ clk_disable_unprepare(sdev-sclk_dac);
return 0;
}
@@ -266,7 +286,7 @@ static int sdo_runtime_resume(struct device *dev)
dev_info(dev, resume\n);
- ret = clk_enable(sdev-sclk_dac);
+ ret = clk_prepare_enable(sdev-sclk_dac);
if (ret 0)
return ret;
@@ -299,7 +319,7 @@ static int sdo_runtime_resume(struct device *dev)
vdac_r_dis:
regulator_disable(sdev-vdac);
dac_clk_dis:
- clk_disable(sdev-sclk_dac);
+ clk_disable_unprepare(sdev-sclk_dac);
return ret;
}
@@ -403,10 +423,14 @@ static int sdo_probe(struct platform_device *pdev)
ret = PTR_ERR(sdev-vdet);
goto fail_fout_vpll;
}
-
/* enable gate for dac clock, because mixer uses it */
- clk_enable(sdev-dac);
-
+ clk_prepare_enable(sdev-dac);
+ if (IS_ERR(sdev-dac)) {
+ dev_err(dev,
+ %s: Failed to prepare and enable clock !\n, __func__);
+ ret = PTR_ERR(sdev-dac);
+ goto fail_fout_vpll;
+ }
/* configure power management */
pm_runtime_enable(dev);
@@ -444,7 +468,7 @@ static int sdo_remove(struct platform_device *pdev)
struct sdo_device *sdev = sd_to_sdev(sd);
pm_runtime_disable(pdev-dev);
- clk_disable(sdev-dac);
+ clk_disable_unprepare(sdev-dac);
clk_put(sdev-fout_vpll);
clk_put(sdev-dacphy);
clk_put(sdev-dac);
--
1.8.1.2
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RE: [GIT PULL 3/3] 2nd Round Samsung mach-exynos for v3.12
Bartlomiej Zolnierkiewicz wrote: [...] is incorrect as noted a month ago in: http://lists.infradead.org/pipermail/linux-arm-kernel/2013- July/186355.html [ Because of the deficiency in the core cpuidle core (device- state_count not being used by governors' code) only sysfs entries for C1 state will be disabled and EXYNOS cpuidle driver will still attempt to use C1 state. also non-working device-state_count is planned to be removed by: http://permalink.gmane.org/gmane.linux.power-management.general/37390 I looked at your patch series and it seems reasonable. I will repost this patch on top of yours. If you correctly use driver's state_count (instead of device's) there will be no dependency on my patch series and the new patch can be applied immediately. But I suggest to keep this patch temporary till your patch series gets merged. The current patch (the one Kukjin merged) is incorrect as it just doesn't do what it advertises. I see no reason to keep it. Well, I don't think so, because if the patch is missing, following kernel panic happens on exynos5440 platform. Unable to handle kernel paging request at virtual address f8180608 pgd = c0003000 [f8180608] *pgd=8080007003, *pmd=af7fb003, *pte= Internal error: Oops: a07 [#1] PREEMPT ARM Modules linked in: CPU: 0 PID: 0 Comm: swapper Not tainted 3.11.0-0-generic #1~d20130819t044008~3372c79 task: c0529d80 ti: c051e000 task.ti: c051e000 PC is at exynos4_enter_lowpower+0x18/0x130 LR is at cpuidle_enter_state+0x3c/0xe8 pc : []lr : []psr: 200f0093 sp : c051ff68 ip : 0018 fp : r10: r9 : 412fc0f3 r8 : r7 : c052c9cc r6 : 0001 r5 : r4 : d5c3cc94 r3 : f818 r2 : ff3e r1 : c052c980 r0 : c052cc98 Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 30c5387d Table: af139b00 DAC: fffd Process swapper (pid: 0, stack limit = 0xc051e230) Stack: (0xc051ff68 to 0xc052) ff60: d5c3cc94 c052cc98 c02c1310 d5c3cc94 ff80: c0550288 c052c980 c058898c c052cc98 0001 c052c980 c058898c c02c1458 ffa0: c051e000 c0550288 c0550288 0001 c05260dc c001b2cc 01fe c00573e4 ffc0: c04f07d8 c04f0290 c05134d8 ffe0: 30c7387d c0526064 c05134d4 c052b5b4 80007000 80008080 [] (exynos4_enter_lowpower+0x18/0x130) from [] (cpuidle_enter_state+0x3c/0xe8) [] (cpuidle_enter_state+0x3c/0xe8) from [] (cpuidle_idle_call+0x9c/0x140) [] (cpuidle_idle_call+0x9c/0x140) from [] (arch_cpu_idle+0x8/0x38) [] (arch_cpu_idle+0x8/0x38) from [] (cpu_startup_entry+0x4c/0x114) [] (cpu_startup_entry+0x4c/0x114) from [] (start_kernel+0x324/0x37c) Code: 0a43 e3a03000 e30f2f3e e34f3818 (e5832608) ---[ end trace 617b9e1a4ff91d2f ]--- Kernel panic - not syncing: Attempted to kill the idle task! In addition, I didn't see your patches in linux-next for upcoming merge window. So I think, if any fixup is required, it should be done on top of current shape. - Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC] cleanup mach-s5p*
Hi Kukjin, On 8/26/2013 2:52 AM, Kukjin Kim wrote: Hi all, I have a plan to remove supporting following SoCs in mainline in the near future. - s5pc100 - smdkc100 - s5pv210(s5c110) - aquial, goni, smdkc110, smdkv210, torbreck - s5p64x0(s5p6440, s5p6450)- smdk6440, smdk6450 I think users don't seem to use that any more with mainline. If so, we are able to consider, it is not right now though. How do you think? I am against removing support for S5PC110/S5PV210. We still use it for some of our internal development. DT support patches will be posted soon (pinctrl and clocks). Support for S5PC100 can be easily added the same way (we also have DT patches almost ready). S5PV210, S5PC100 and the older S3C64xx can all be handled by the same Samsung-DT 'machine file'. However we don't have any s5p64x0 based boards to develop DT support for them. Best regards -- Marek Szyprowski Samsung RD Institute Poland -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2] ARM: EXYNOS: cpuidle: Skip C1 cpuidle state for exynos5440
This patch skips the deep C1(AFTR -Arm off top running) state for exynos5440
soc as this soc does not support this state. The cpu's only allows the basic
C0 state. The C1 state is filtered by re-initialising the driver state_count
value to 1.
Cc: Kukjin Kim kg...@kernel.org
Cc: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---
Changes in V2:
* Used driver state_count variable to filter the C1 state
instead of device state count variable. Although this V2 patch is also
not complete as there are suggestions to make this driver platform driver.
arch/arm/mach-exynos/cpuidle.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 225ee84..ac13922 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -200,6 +200,9 @@ static int __init exynos4_init_cpuidle(void)
if (soc_is_exynos5250())
exynos5_core_down_clk();
+ if (soc_is_exynos5440())
+ exynos4_idle_driver.state_count = 1;
+
ret = cpuidle_register_driver(exynos4_idle_driver);
if (ret) {
printk(KERN_ERR CPUidle failed to register driver\n);
--
1.7.1
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Re: [GIT PULL 3/3] 2nd Round Samsung mach-exynos for v3.12
Submitted the V2 version of this patch with your suggestion.
Thanks
Amit
On Mon, Aug 26, 2013 at 4:49 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
On Monday, August 26, 2013 04:33:55 PM amit daniel kachhap wrote:
Hi,
On Mon, Aug 26, 2013 at 3:36 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
Hi,
On Monday, August 26, 2013 09:14:42 AM Kukjin Kim wrote:
The following changes since commit
ad81f0545ef01ea651886dddac4bef6cec930092:
Linux 3.11-rc1 (2013-07-14 15:18:27 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/samsung-mach-exynos
for you to fetch changes up to f52616f4233d71d0fb00f06f86d046d18d2b7f3b:
ARM: EXYNOS: always enable PM domains support for EXYNOS4X12 (2013-08-19
05:05:16 +0900)
update mach-exynos
- enable ARCH_HAS_BANDGAP for exynos SoCs
- skip C1 cpuidle for exynos5440 because non-supporting
- always enable PM domains for exynos4x12
Amit Daniel Kachhap (2):
ARM: EXYNOS: enable ARCH_HAS_BANDGAP
ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
The patch ARM: EXYNOS: Skip C1 cpuidle state for exynos5440:
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -210,7 +210,7 @@ static int __init exynos4_init_cpuidle(void)
device-cpu = cpu_id;
/* Support IDLE only */
- if (cpu_id != 0)
+ if (soc_is_exynos5440() || cpu_id != 0)
device-state_count = 1;
ret = cpuidle_register_device(device);
is incorrect as noted a month ago in:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/186355.html
[ Because of the deficiency in the core cpuidle core (device-state_count
not being used by governors' code) only sysfs entries for C1 state will
be
disabled and EXYNOS cpuidle driver will still attempt to use C1 state.
also non-working device-state_count is planned to be removed by:
http://permalink.gmane.org/gmane.linux.power-management.general/37390
I looked at your patch series and it seems reasonable. I will repost
this patch on top of yours.
If you correctly use driver's state_count (instead of device's) there will be
no dependency on my patch series and the new patch can be applied immediately.
But I suggest to keep this patch temporary till your patch series gets
merged.
The current patch (the one Kukjin merged) is incorrect as it just doesn't
do what it advertises. I see no reason to keep it.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
Thanks,
Amit Daniel
To disable C1 state on EXYNOS5440 something like:
static int __init exynos4_init_cpuidle(void)
{
...
if (soc_is_exynos5440())
exynos4_idle_driver.state_count = 1;
...
}
should be done instead.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
___
linux-arm-kernel mailing list
linux-arm-ker...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Mon, Aug 26, 2013 at 3:36 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
Hi,
On Monday, August 26, 2013 09:14:42 AM Kukjin Kim wrote:
The following changes since commit
ad81f0545ef01ea651886dddac4bef6cec930092:
Linux 3.11-rc1 (2013-07-14 15:18:27 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/samsung-mach-exynos
for you to fetch changes up to f52616f4233d71d0fb00f06f86d046d18d2b7f3b:
ARM: EXYNOS: always enable PM domains support for EXYNOS4X12 (2013-08-19
05:05:16 +0900)
update mach-exynos
- enable ARCH_HAS_BANDGAP for exynos SoCs
- skip C1 cpuidle for exynos5440 because non-supporting
- always enable PM domains for exynos4x12
Amit Daniel Kachhap (2):
ARM: EXYNOS: enable ARCH_HAS_BANDGAP
ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
The patch ARM: EXYNOS: Skip C1 cpuidle state for exynos5440:
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -210,7 +210,7 @@ static int __init exynos4_init_cpuidle(void)
device-cpu = cpu_id;
/* Support IDLE only */
- if (cpu_id != 0)
+ if (soc_is_exynos5440() || cpu_id != 0)
device-state_count = 1;
ret =
Re: [PATCH v2 4/5] [media] exynos-mscl: Add DT bindings for M-Scaler driver
Hi Sylwester,
Thanks for the comments.
Please find the response inline...
Actually, I am waiting for your comments only :)
are you also reviewing the driver code? If yes, I can delay the next
version until your post your comments.
On Sun, Aug 25, 2013 at 3:56 AM, Sylwester Nawrocki
sylvester.nawro...@gmail.com wrote:
On 08/19/2013 02:57 PM, Inki Dae wrote:
-Original Message-
From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
ow...@vger.kernel.org] On Behalf Of Shaik Ameer Basha
Sent: Monday, August 19, 2013 7:59 PM
To: linux-me...@vger.kernel.org; linux-samsung-soc@vger.kernel.org
Cc: s.nawro...@samsung.com; posc...@google.com; arun...@samsung.com;
shaik.am...@samsung.com
Subject: [PATCH v2 4/5] [media] exynos-mscl: Add DT bindings for M-Scaler
driver
This patch adds the DT binding documentation for the exynos5
You may want to say to which specific SoC it applies.
Ok. will update this.
Only 5410 and 5420 has this IP as of now.
based M-Scaler device driver.
Signed-off-by: Shaik Ameer Bashashaik.am...@samsung.com
---
.../devicetree/bindings/media/exynos5-mscl.txt | 34
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/exynos5-
mscl.txt
diff --git a/Documentation/devicetree/bindings/media/exynos5-mscl.txt
b/Documentation/devicetree/bindings/media/exynos5-mscl.txt
new file mode 100644
index 000..5c9d1b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos5-mscl.txt
@@ -0,0 +1,34 @@
+* Samsung Exynos5 M-Scaler device
+
+M-Scaler is used for scaling, blending, color fill and color space
+conversion on EXYNOS5 SoCs.
+
+Required properties:
+- compatible: should be samsung,exynos5-mscl
What is an exact name of this IP in the datasheet ?
It is named as SCALER. But when i got the Initial doc, it was also
known as memory to memory scaler.
so, i am using M-Scaler.
Can i change this name to SCALER instead ?
If Exynos5410/5420 have same IP,
samsung,exynos5410-mscl for M Scaler IP in Exynos5410/5420
Else,
Compatible: should be one of the following:
(a) samsung,exynos5410-mscl for M Scaler IP in Exynos5410
(b) samsung,exynos5420-mscl for M Scaler IP in Exynos5420
Yes, except I suspect mscl is incorrect. It sounds like an unclear
abbreviation of real name of the IP. It likely should be mscaler.
+- reg: should contain M-Scaler physical address location and length.
+- interrupts: should contain M-Scaler interrupt number
+- clocks: should contain the clock number according to CCF
Hmm, this sounds like a Linux specific term in the binding. Perhaps:
- clocks: should contain the M-Scaler clock specifier, from the common
clock bindings
?
+- clock-names: should be mscl
+
+Example:
+
+ mscl_0: mscl@0x1280 {
s/0x//
Ok. Like this?
mscl_0: mscl@1280 {
+ compatible = samsung,exynos5-mscl;
samsung,exynos5410-mscl;
+ reg =0x1280 0x1000;
+ interrupts =0 220 0;
+ clocks =clock 381;
+ clock-names = mscl;
+ };
+
+Aliases:
+Each M-Scaler node should have a numbered alias in the aliases node,
+in the form of msclN, N = 0...2. M-Scaler driver uses these aliases
+to retrieve the device IDs using of_alias_get_id() call.
So except in debug logs and for selecting variant data (which is same for
all IP instances) are the aliases used for anything else ?
I suspect you could do without these aliases. Device name includes start
address of the IP register region, so that could be used to identify the
M-Scaler instance in the logs.
Ok. I will check more.
If it is only used for logs, then i will remove the aliases.
Regards,
Shaik Ameer Basha
--
Regards,
Sylwester
--
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Re: [PATCH v7] s5k5baf: add camera sensor driver
Hi Laurent,
Thank you for the review.
On 08/23/2013 02:53 PM, Laurent Pinchart wrote:
Hi Andrzej,
Thank you for the patch.
On Wednesday 21 August 2013 16:41:31 Andrzej Hajda wrote:
Driver for Samsung S5K5BAF UXGA 1/5 2M CMOS Image Sensor
with embedded SoC ISP.
The driver exposes the sensor as two V4L2 subdevices:
- S5K5BAF-CIS - pure CMOS Image Sensor, fixed 1600x1200 format,
no controls.
- S5K5BAF-ISP - Image Signal Processor, formats up to 1600x1200,
pre/post ISP cropping, downscaling via selection API, controls.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Hi,
This patch incorporates Stephen's suggestions, thanks.
Regards
Andrzej
v7
- changed description of 'clock-frequency' DT property
v6
- endpoint node presence is now optional,
- added asynchronous subdev registration support and clock
handling,
- use named gpios in DT bindings
v5
- removed hflip/vflip device tree properties
v4
- GPL changed to GPLv2,
- bitfields replaced by u8,
- cosmetic changes,
- corrected s_stream flow,
- gpio pins are no longer exported,
- added I2C addresses to subdev names,
- CIS subdev registration postponed after
succesfull HW initialization,
- added enums for pads,
- selections are initialized only during probe,
- default resolution changed to 1600x1200,
- state-error pattern removed from few other functions,
- entity link creation moved to registered callback.
v3:
- narrowed state-error usage to i2c and power errors,
- private gain controls replaced by red/blue balance user controls,
- added checks to devicetree gpio node parsing
v2:
- lower-cased driver name,
- removed underscore from regulator names,
- removed platform data code,
- v4l controls grouped in anonymous structs,
- added s5k5baf_clear_error function,
- private controls definitions moved to uapi header file,
- added v4l2-controls.h reservation for private controls,
- corrected subdev registered/unregistered code,
- .log_status sudbev op set to v4l2 helper,
- moved entity link creation to probe routines,
- added cleanup on error to probe function.
---
.../devicetree/bindings/media/samsung-s5k5baf.txt | 59 +
MAINTAINERS|7 +
drivers/media/i2c/Kconfig |7 +
drivers/media/i2c/Makefile |1 +
drivers/media/i2c/s5k5baf.c| 2045 +
5 files changed, 2119 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/samsung-s5k5baf.txt create mode
100644 drivers/media/i2c/s5k5baf.c
[snip]
diff --git a/drivers/media/i2c/s5k5baf.c b/drivers/media/i2c/s5k5baf.c
new file mode 100644
index 000..f21d9f1
--- /dev/null
+++ b/drivers/media/i2c/s5k5baf.c
[snip]
+enum s5k5baf_pads_id {
+PAD_CIS,
+PAD_OUT,
+CIS_PAD_NUM = 1,
+ISP_PAD_NUM = 2
+};
You can just use #define's here, the enum doesn't bring any additional value
and isn't very explicit.
OK
+static struct v4l2_rect s5k5baf_cis_rect = { 0, 0, S5K5BAF_CIS_WIDTH,
+ S5K5BAF_CIS_HEIGHT };
Shouldn't this be const ?
OK
+static u16 s5k5baf_i2c_read(struct s5k5baf *state, u16 addr)
+{
+struct i2c_client *c = v4l2_get_subdevdata(state-sd);
+u16 w, r;
You should declare these variables as __be16.
OK
+struct i2c_msg msg[] = {
+{ .addr = c-addr, .flags = 0,
+ .len = 2, .buf = (u8 *)w },
+{ .addr = c-addr, .flags = I2C_M_RD,
+ .len = 2, .buf = (u8 *)r },
+};
+int ret;
+
+if (state-error)
+return 0;
+
+w = htons(addr);
Wouldln't cpu_to_be16() be more appropriate ?
OK
+ret = i2c_transfer(c-adapter, msg, 2);
+r = ntohs(r);
And be16_to_cpu() here.
OK
+
+v4l2_dbg(3, debug, c, i2c_read: 0x%04x : 0x%04x\n, addr, r);
+
+if (ret != 2) {
+v4l2_err(c, i2c_read: error during transfer (%d)\n, ret);
+state-error = ret;
+}
+return r;
+}
[snip]
+static void s5k5baf_write_arr_seq(struct s5k5baf *state, u16 addr,
+ u16 count, const u16 *seq)
+{
+struct i2c_client *c = v4l2_get_subdevdata(state-sd);
+u16 buf[count + 1];
+int ret, n;
+
+s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr);
+if (state-error)
+return;
I would have a preference for returning an error directly from the write
function instead of storing it in state-error, that would be more explicit.
The same is true for all read/write functions.
I have introduced state-error to avoid code bloat. With this 'pattern'
error is checked in about 10 places in the code, of course without
scarifying code correctness.
Replacing this pattern with classic 'return error directly from function'
would result with adding error checks after
Re: [GIT PULL 3/3] 2nd Round Samsung mach-exynos for v3.12
On Monday, August 26, 2013 08:52:44 PM Kukjin Kim wrote:
Bartlomiej Zolnierkiewicz wrote:
[...]
is incorrect as noted a month ago in:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-
July/186355.html
[ Because of the deficiency in the core cpuidle core (device-
state_count
not being used by governors' code) only sysfs entries for C1 state
will be
disabled and EXYNOS cpuidle driver will still attempt to use C1
state.
also non-working device-state_count is planned to be removed by:
http://permalink.gmane.org/gmane.linux.power-management.general/37390
I looked at your patch series and it seems reasonable. I will repost
this patch on top of yours.
If you correctly use driver's state_count (instead of device's) there will
be
no dependency on my patch series and the new patch can be applied
immediately.
But I suggest to keep this patch temporary till your patch series gets
merged.
The current patch (the one Kukjin merged) is incorrect as it just doesn't
do what it advertises. I see no reason to keep it.
Well, I don't think so, because if the patch is missing, following kernel
panic happens on exynos5440 platform.
Unable to handle kernel paging request at virtual address f8180608
pgd = c0003000
[f8180608] *pgd=8080007003, *pmd=af7fb003, *pte=
Internal error: Oops: a07 [#1] PREEMPT ARM
Modules linked in:
CPU: 0 PID: 0 Comm: swapper Not tainted 3.11.0-0-generic
#1~d20130819t044008~3372c79
task: c0529d80 ti: c051e000 task.ti: c051e000
PC is at exynos4_enter_lowpower+0x18/0x130
LR is at cpuidle_enter_state+0x3c/0xe8
pc : []lr : []psr: 200f0093
sp : c051ff68 ip : 0018 fp :
r10: r9 : 412fc0f3 r8 :
r7 : c052c9cc r6 : 0001 r5 : r4 : d5c3cc94
r3 : f818 r2 : ff3e r1 : c052c980 r0 : c052cc98
Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 30c5387d Table: af139b00 DAC: fffd
Process swapper (pid: 0, stack limit = 0xc051e230)
Stack: (0xc051ff68 to 0xc052)
ff60: d5c3cc94 c052cc98 c02c1310 d5c3cc94
ff80: c0550288 c052c980 c058898c c052cc98 0001 c052c980 c058898c
c02c1458
ffa0: c051e000 c0550288 c0550288 0001 c05260dc c001b2cc 01fe
c00573e4
ffc0: c04f07d8 c04f0290
c05134d8
ffe0: 30c7387d c0526064 c05134d4 c052b5b4 80007000 80008080
[] (exynos4_enter_lowpower+0x18/0x130) from []
(cpuidle_enter_state+0x3c/0xe8)
[] (cpuidle_enter_state+0x3c/0xe8) from [] (cpuidle_idle_call+0x9c/0x140)
[] (cpuidle_idle_call+0x9c/0x140) from [] (arch_cpu_idle+0x8/0x38)
[] (arch_cpu_idle+0x8/0x38) from [] (cpu_startup_entry+0x4c/0x114)
[] (cpu_startup_entry+0x4c/0x114) from [] (start_kernel+0x324/0x37c)
Code: 0a43 e3a03000 e30f2f3e e34f3818 (e5832608)
---[ end trace 617b9e1a4ff91d2f ]---
Kernel panic - not syncing: Attempted to kill the idle task!
1) samsung-mach-exynos kernel (from your pull request) doesn't have neither
exynos5440_defconfig nor EXYNOS5440 enabled in exynos_defconfig so could
you please tell me what kernel version and kernel config are you using to
get the above panic?
Could you also see what does exynos4_enter_lowpower+0x18 map to in your
source code?
2) dev-state_count is used only for managing sysfs entries (and clearing
dev-states_usage) in the cpuidle core.
$ git grep state_count drivers/cpuidle/
drivers/cpuidle/cpuidle-calxeda.c: .state_count = 2,
drivers/cpuidle/cpuidle-kirkwood.c: .state_count = KIRKWOOD_MAX_STATES,
drivers/cpuidle/cpuidle-zynq.c: .state_count = ZYNQ_MAX_STATES,
drivers/cpuidle/cpuidle.c: for (i = drv-state_count - 1; i =
CPUIDLE_DRIVER_STATE_START; i--)
drivers/cpuidle/cpuidle.c: if (!dev-state_count)
drivers/cpuidle/cpuidle.c: dev-state_count = drv-state_count;
drivers/cpuidle/cpuidle.c: for (i = 0; i dev-state_count; i++) {
drivers/cpuidle/driver.c: for (i = drv-state_count - 1; i = 0 ; i--) {
drivers/cpuidle/driver.c: if (!drv || !drv-state_count)
drivers/cpuidle/governors/ladder.c: if (last_idx drv-state_count - 1
drivers/cpuidle/governors/ladder.c: for (i = 0; i drv-state_count; i++) {
drivers/cpuidle/governors/ladder.c: if (i drv-state_count - 1)
drivers/cpuidle/governors/menu.c: for (i = CPUIDLE_DRIVER_STATE_START; i
drv-state_count; i++) {
drivers/cpuidle/sysfs.c:for (i = 0; i device-state_count; i++) {
drivers/cpuidle/sysfs.c:for (i = 0; i device-state_count; i++)
With the current code I fail to see how it is possible that dev-state_count
smaller than drv-state_count affects anything besides sysfs cpuidle entries
in the practice.
IOW I worry that the current patch may be just masking some other issue.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
--
Re: [PATCH V2] ARM: EXYNOS: cpuidle: Skip C1 cpuidle state for exynos5440
On Monday, August 26, 2013 05:46:03 PM Amit Daniel Kachhap wrote:
This patch skips the deep C1(AFTR -Arm off top running) state for exynos5440
soc as this soc does not support this state. The cpu's only allows the basic
C0 state. The C1 state is filtered by re-initialising the driver state_count
value to 1.
Cc: Kukjin Kim kg...@kernel.org
Cc: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Thanks for fixing this.
Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---
Changes in V2:
* Used driver state_count variable to filter the C1 state
instead of device state count variable. Although this V2 patch is also
not complete as there are suggestions to make this driver platform driver.
I'm going to look into making it a platform driver later this week.
arch/arm/mach-exynos/cpuidle.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 225ee84..ac13922 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -200,6 +200,9 @@ static int __init exynos4_init_cpuidle(void)
if (soc_is_exynos5250())
exynos5_core_down_clk();
+ if (soc_is_exynos5440())
+ exynos4_idle_driver.state_count = 1;
+
ret = cpuidle_register_driver(exynos4_idle_driver);
if (ret) {
printk(KERN_ERR CPUidle failed to register driver\n);
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
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Re: [PATCH RFC 1/5] media: s5p-tv: Fix sdo driver to work with CCF
Hi,
On Monday, August 26, 2013 01:38:30 PM Mateusz Krawczuk wrote:
Replace clk_enable by clock_enable_prepare and clk_disable with
clk_disable_unprepare.
Clock prepare is required by Clock Common Framework, and old clock driver
didn`t support it.
Without it Common Clock Framework prints a warning.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
---
drivers/media/platform/s5p-tv/sdo_drv.c | 44
+
1 file changed, 34 insertions(+), 10 deletions(-)
diff --git a/drivers/media/platform/s5p-tv/sdo_drv.c
b/drivers/media/platform/s5p-tv/sdo_drv.c
index 0afa90f..77eac6d 100644
--- a/drivers/media/platform/s5p-tv/sdo_drv.c
+++ b/drivers/media/platform/s5p-tv/sdo_drv.c
@@ -55,6 +55,8 @@ struct sdo_device {
struct clk *dacphy;
/** clock for control of VPLL */
struct clk *fout_vpll;
+ /** vpll rate before sdo stream was on */
+ int vpll_rate;
/** regulator for SDO IP power */
struct regulator *vdac;
/** regulator for SDO plug detection */
@@ -193,17 +195,34 @@ static int sdo_s_power(struct v4l2_subdev *sd, int on)
static int sdo_streamon(struct sdo_device *sdev)
{
+ int ret = 0;
There is no need to initialize ret to 0 here.
/* set proper clock for Timing Generator */
- clk_set_rate(sdev-fout_vpll, 5400);
+ sdev-vpll_rate = clk_get_rate(sdev-fout_vpll);
+ ret = clk_set_rate(sdev-fout_vpll, 5400);
+ if (ret 0) {
+ dev_err(sdev-dev,
+ %s: Failed to set vpll rate!\n, __func__);
+ return ret;
+ }
dev_info(sdev-dev, fout_vpll.rate = %lu\n,
clk_get_rate(sdev-fout_vpll));
/* enable clock in SDO */
sdo_write_mask(sdev, SDO_CLKCON, ~0, SDO_TVOUT_CLOCK_ON);
- clk_enable(sdev-dacphy);
+ ret = clk_prepare_enable(sdev-dacphy);
+ if (ret 0) {
+ dev_err(sdev-dev,
+ %s: Failed to prepare and enable clock !\n, __func__);
+ goto fail;
+ }
/* enable DAC */
sdo_write_mask(sdev, SDO_DAC, ~0, SDO_POWER_ON_DAC);
sdo_reg_debug(sdev);
return 0;
+fail:
+ sdo_write_mask(sdev, SDO_CLKCON, 0, SDO_TVOUT_CLOCK_ON);
+ clk_set_rate(sdev-fout_vpll, sdev-vpll_rate);
There is not a word about this change in the patch description.
+ return ret;
}
static int sdo_streamoff(struct sdo_device *sdev)
@@ -211,7 +230,7 @@ static int sdo_streamoff(struct sdo_device *sdev)
int tries;
sdo_write_mask(sdev, SDO_DAC, 0, SDO_POWER_ON_DAC);
- clk_disable(sdev-dacphy);
+ clk_disable_unprepare(sdev-dacphy);
sdo_write_mask(sdev, SDO_CLKCON, 0, SDO_TVOUT_CLOCK_ON);
for (tries = 100; tries; --tries) {
if (sdo_read(sdev, SDO_CLKCON) SDO_TVOUT_CLOCK_READY)
@@ -220,6 +239,7 @@ static int sdo_streamoff(struct sdo_device *sdev)
}
if (tries == 0)
dev_err(sdev-dev, failed to stop streaming\n);
+ clk_set_rate(sdev-fout_vpll, sdev-vpll_rate);
ditto
sdev-fout_vpll rate related changes should be moved to a separate patch
(or at least described properly in the patch description).
return tries ? 0 : -EIO;
}
@@ -254,7 +274,7 @@ static int sdo_runtime_suspend(struct device *dev)
dev_info(dev, suspend\n);
regulator_disable(sdev-vdet);
regulator_disable(sdev-vdac);
- clk_disable(sdev-sclk_dac);
+ clk_disable_unprepare(sdev-sclk_dac);
return 0;
}
@@ -266,7 +286,7 @@ static int sdo_runtime_resume(struct device *dev)
dev_info(dev, resume\n);
- ret = clk_enable(sdev-sclk_dac);
+ ret = clk_prepare_enable(sdev-sclk_dac);
if (ret 0)
return ret;
@@ -299,7 +319,7 @@ static int sdo_runtime_resume(struct device *dev)
vdac_r_dis:
regulator_disable(sdev-vdac);
dac_clk_dis:
- clk_disable(sdev-sclk_dac);
+ clk_disable_unprepare(sdev-sclk_dac);
return ret;
}
@@ -403,10 +423,14 @@ static int sdo_probe(struct platform_device *pdev)
ret = PTR_ERR(sdev-vdet);
goto fail_fout_vpll;
}
-
/* enable gate for dac clock, because mixer uses it */
- clk_enable(sdev-dac);
-
+ clk_prepare_enable(sdev-dac);
+ if (IS_ERR(sdev-dac)) {
It doesn't seem correct to check sdev-dac with IS_ERR() here, especially
since we have the following code earlier:
sdev-dac = clk_get(dev, dac);
if (IS_ERR(sdev-dac)) {
dev_err(dev, failed to get clock 'dac'\n);
ret = PTR_ERR(sdev-dac);
goto fail_sclk_dac;
}
I think you should just check clk_prepare_enable() return value instead.
+ dev_err(dev,
+ %s: Failed to prepare and enable clock !\n, __func__);
+ ret = PTR_ERR(sdev-dac);
+ goto fail_fout_vpll;
+ }
/* configure power management */
Re: [PATCH RFC 2/5] media: s5p-tv: Fix mixer driver to work with CCF
Hi,
On Monday, August 26, 2013 01:38:31 PM Mateusz Krawczuk wrote:
Replace clk_enable by clock_enable_prepare and clk_disable with
clk_disable_unprepare.
Clock prepare is required by Clock Common Framework, and old clock driver
didn`t support it.
Without it Common Clock Framework prints a warning.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
---
drivers/media/platform/s5p-tv/mixer_drv.c | 33
+--
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/media/platform/s5p-tv/mixer_drv.c
b/drivers/media/platform/s5p-tv/mixer_drv.c
index 51805a5..f889591 100644
--- a/drivers/media/platform/s5p-tv/mixer_drv.c
+++ b/drivers/media/platform/s5p-tv/mixer_drv.c
@@ -345,21 +345,42 @@ fail:
static int mxr_runtime_resume(struct device *dev)
{
+ int ret = 0;
There is no need to initialize it to 0 here.
struct mxr_device *mdev = to_mdev(dev);
struct mxr_resources *res = mdev-res;
mxr_dbg(mdev, resume - start\n);
mutex_lock(mdev-mutex);
/* turn clocks on */
- clk_enable(res-mixer);
- clk_enable(res-vp);
- clk_enable(res-sclk_mixer);
+ ret = clk_prepare_enable(res-mixer);
+ if (ret 0) {
+ dev_err(dev, clk_prepare_enable(mixer) failed\n);
There is no consistency in the error messages between patch #1 and #2.
How's about changing error messages in the patch #2 to use
%s: Failed to prepare and enable mixer clock!, __func__
form?
+ goto fail;
+ }
+ ret = clk_prepare_enable(res-vp);
+ if (ret 0) {
+ dev_err(dev, clk_prepare_enable(vp) failed\n);
+ goto fail_mixer;
+ }
+ ret = clk_prepare_enable(res-sclk_mixer);
+ if (ret 0) {
+ dev_err(dev, clk_prepare_enable(sclk_mixer) failed\n);
+ goto fail_vp;
+ }
/* apply default configuration */
mxr_reg_reset(mdev);
mxr_dbg(mdev, resume - finished\n);
While at it the above mxr_dbg() can be moved outside the mutex lock.
mutex_unlock(mdev-mutex);
return 0;
+fail_vp:
+ clk_disable_unprepare(res-vp);
+fail_mixer:
+ clk_disable_unprepare(res-mixer);
+fail:
+ mutex_unlock(mdev-mutex);
+ dev_info(dev, resume failed\n);
Shouldn't it be dev_err()?
Please also add mxr_dbg(mdev, resume - finished\n) call here
to match the earlier mxr_dbg(mdev, resume - start\n) one.
+ return ret;
}
static int mxr_runtime_suspend(struct device *dev)
@@ -369,9 +390,9 @@ static int mxr_runtime_suspend(struct device *dev)
mxr_dbg(mdev, suspend - start\n);
mutex_lock(mdev-mutex);
/* turn clocks off */
- clk_disable(res-sclk_mixer);
- clk_disable(res-vp);
- clk_disable(res-mixer);
+ clk_disable_unprepare(res-sclk_mixer);
+ clk_disable_unprepare(res-vp);
+ clk_disable_unprepare(res-mixer);
mutex_unlock(mdev-mutex);
mxr_dbg(mdev, suspend - finished\n);
return 0;
While at this driver please note that currently it defines its own macros to
use instead of dev_err(), dev_warn() and dev_info().
drivers/media/platform/s5p-tv/mixer.h:
...
#define mxr_err(mdev, fmt, ...) dev_err(mdev-dev, fmt, ##__VA_ARGS__)
#define mxr_warn(mdev, fmt, ...) dev_warn(mdev-dev, fmt, ##__VA_ARGS__)
#define mxr_info(mdev, fmt, ...) dev_info(mdev-dev, fmt, ##__VA_ARGS__)
...
Since your patch adds dev_err() and dev_info() instances it would be a good
thing to remove mxr_*() macros in the preparatory patch.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
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Re: [PATCH RFC 3/5] ARM: samsung: add clock setup for FIMC and FIMD
Hi,
On Monday, August 26, 2013 01:38:32 PM Mateusz Krawczuk wrote:
This patch adds code that sets correct parents and rates for clocks
used by FIMC and FIMD on Goni board.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
---
arch/arm/mach-s5pv210/mach-goni.c | 48
+++
1 file changed, 48 insertions(+)
diff --git a/arch/arm/mach-s5pv210/mach-goni.c
b/arch/arm/mach-s5pv210/mach-goni.c
index e5cd9fb..309b5ad 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -55,6 +55,7 @@
#include media/s5p_fimc.h
#include media/noon010pc30.h
+#include linux/clk.h
#include common.h
/* Following are default values for UCON, ULCON and UFCON UART registers */
@@ -195,6 +196,49 @@ static struct platform_device goni_spi_gpio = {
},
};
+static void set_fimd_clock(void)
It can be marked as __init.
+{
+ struct clk *lcd_clk, *parent_clk;
+
+ lcd_clk = clk_get(NULL, sclk_fimd);
+ parent_clk = clk_get(NULL, mout_mpll);
+ clk_set_parent(lcd_clk, parent_clk);
+ clk_set_rate(lcd_clk, clk_get_rate(parent_clk)/3);
+
+ clk_put(parent_clk);
+ clk_put(lcd_clk);
+}
+
+static void set_fimc_clock(void)
ditto
+{
+ struct clk *cam0_clk, *cam1_clk, *fimc2_clk, *fimc1_clk,
+ *fimc0_clk, *parent_clk, *vpll_clk, *csis_clk;
+
+ parent_clk = clk_get(NULL, mout_mpll);
+ vpll_clk = clk_get(NULL, mout_vpll);
+ cam0_clk = clk_get(NULL, mout_cam0);
+ cam1_clk = clk_get(NULL, mout_cam1);
+ fimc2_clk = clk_get(NULL, mout_fimc2);
+ fimc1_clk = clk_get(NULL, mout_fimc1);
+ fimc0_clk = clk_get(NULL, mout_fimc0);
+ csis_clk = clk_get(NULL, mout_csis);
Shouldn't you check clk_get() return value with IS_ERR()?
You can do one big check here and than just do clk_put() if !IS_ERR(), i.e.
if (IS_ERR(parent_clk) || IS_ERR(vpll_clk) || ...)
...
clk_set_parent()
...
if (!IS_ERR(parent_clk))
clk_put(parent_clk);
...
+ clk_set_parent(cam0_clk, vpll_clk);
+ clk_set_parent(cam1_clk, vpll_clk);
+ clk_set_parent(fimc2_clk, parent_clk);
+ clk_set_parent(fimc1_clk, parent_clk);
+ clk_set_parent(fimc0_clk, parent_clk);
+ clk_set_parent(csis_clk, parent_clk);
+
+ clk_put(parent_clk);
+ clk_put(vpll_clk);
+ clk_put(cam0_clk);
+ clk_put(cam1_clk);
+ clk_put(fimc2_clk);
+ clk_put(fimc1_clk);
+ clk_put(fimc0_clk);
+}
+
/* KEYPAD */
static uint32_t keymap[] __initdata = {
/* KEY(row, col, keycode) */
@@ -931,6 +975,10 @@ static void __init goni_machine_init(void)
s3c_i2c2_set_platdata(i2c2_data);
i2c_register_board_info(2, i2c2_devs, ARRAY_SIZE(i2c2_devs));
+ /* FIMD AND FIMC set clock config */
+ set_fimd_clock();
+ set_fimc_clock();
+
/* PMIC */
goni_pmic_init();
i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs,
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
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[PATCH] clocksource: exynos_mct: Set IRQ affinity when the CPU goes online
Some variants of Exynos MCT, namely exynos4210-mct at the moment, use
normal, shared interrupts for local timers. This means that each
interrupt must have correct affinity set to fire only on CPU
corresponding to given local timer.
However after recent conversion of clocksource drivers to not use the
local timer API for local timer initialization any more, the point of
time when local timers get initialized changed and irq_set_affinity()
fails because the CPU is not marked as online yet.
This patch fixes this by moving the call to irq_set_affinity() to
CPU_ONLINE notification, so the affinity is being set when the CPU goes
online.
This fixes a problem with Exynos4210 failing to boot, present since commit
ee98d27df6 ARM: EXYNOS4: Divorce mct from local timer API
due to failing irq_set_affinity().
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clocksource/exynos_mct.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 5b34768..62b0de6 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -428,7 +428,6 @@ static int exynos4_local_timer_setup(struct
clock_event_device *evt)
evt-irq);
return -EIO;
}
- irq_set_affinity(evt-irq, cpumask_of(cpu));
} else {
enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
}
@@ -449,6 +448,7 @@ static int exynos4_mct_cpu_notify(struct notifier_block
*self,
unsigned long action, void *hcpu)
{
struct mct_clock_event_device *mevt;
+ unsigned int cpu;
/*
* Grab cpu pointer in each case to avoid spurious
@@ -459,6 +459,12 @@ static int exynos4_mct_cpu_notify(struct notifier_block
*self,
mevt = this_cpu_ptr(percpu_mct_tick);
exynos4_local_timer_setup(mevt-evt);
break;
+ case CPU_ONLINE:
+ cpu = (unsigned long)hcpu;
+ if (mct_int_type == MCT_INT_SPI)
+ irq_set_affinity(mct_irqs[MCT_L0_IRQ + cpu],
+ cpumask_of(cpu));
+ break;
case CPU_DYING:
mevt = this_cpu_ptr(percpu_mct_tick);
exynos4_local_timer_stop(mevt-evt);
@@ -500,6 +506,8 @@ static void __init exynos4_timer_resources(struct
device_node *np, void __iomem
percpu_mct_tick);
WARN(err, MCT: can't request IRQ %d (%d)\n,
mct_irqs[MCT_L0_IRQ], err);
+ } else {
+ irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
}
err = register_cpu_notifier(exynos4_mct_cpu_nb);
--
1.8.3.2
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Re: [PATCH RFC 5/5] ARM: s5pv210: Migrate clock handling to Common Clock Framework
Hi,
On Monday, August 26, 2013 01:38:34 PM Mateusz Krawczuk wrote:
This patch migrates the s5pv210 platform to use new clock driver
using Common Clock Framework.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
---
arch/arm/mach-s5pv210/Kconfig | 9 +
arch/arm/mach-s5pv210/Makefile| 4 ++--
arch/arm/mach-s5pv210/common.c| 22 ++
arch/arm/mach-s5pv210/common.h| 13 +
arch/arm/mach-s5pv210/mach-aquila.c | 1 +
arch/arm/mach-s5pv210/mach-goni.c | 3 ++-
arch/arm/mach-s5pv210/mach-smdkc110.c | 1 +
arch/arm/mach-s5pv210/mach-smdkv210.c | 1 +
arch/arm/mach-s5pv210/mach-torbreck.c | 1 +
arch/arm/plat-samsung/Kconfig | 2 +-
arch/arm/plat-samsung/init.c | 2 --
11 files changed, 53 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index caaedaf..ad4546e 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -15,6 +15,7 @@ config CPU_S5PV210
select S5P_PM if PM
select S5P_SLEEP if PM
select SAMSUNG_DMADEV
+ select S5P_CLOCK if !COMMON_CLK
help
Enable S5PV210 CPU support
@@ -69,6 +70,14 @@ config S5PV210_SETUP_USB_PHY
help
Common setup code for USB PHY controller
+config COMMON_CLK_S5PV210
+ bool Common Clock Framework support
+ default y
+ select COMMON_CLK
+ help
+ Enable this option to use new clock driver
+ based on Common Clock Framework.
+
menu S5PC110 Machines
config MACH_AQUILA
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 1c4e419..0c67fe2 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -12,8 +12,8 @@ obj-:=
# Core
-obj-y+= common.o clock.o
-
+obj-y+= common.o
+obj-$(CONFIG_S5P_CLOCK) += clock.o
obj-$(CONFIG_PM) += pm.o
obj-y+= dma.o
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 26027a2..3c3dd05 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -34,7 +34,13 @@
#include mach/regs-clock.h
#include plat/cpu.h
+
+#ifdef CONFIG_S5P_CLOCK
#include plat/clock.h
+#else
+#include linux/clk-provider.h
+#endif
+
#include plat/devs.h
#include plat/sdhci.h
#include plat/adc-core.h
@@ -50,6 +56,19 @@
#include common.h
+/* External clock frequency */
+static unsigned long xxti_f, xusbxti_f;
+
+void __init s5pv210_set_xxti_freq(unsigned long freq)
+{
+ xxti_f = freq;
+}
This function is not used anywhere while xxti_f is used in
s5pv210_init_irq(). Please fix it.
+void __init s5pv210_set_xusbxti_freq(unsigned long freq)
+{
+ xusbxti_f = freq;
+}
+
static const char name_s5pv210[] = S5PV210/S5PC110;
static struct cpu_table cpu_ids[] __initdata = {
@@ -229,12 +248,14 @@ void __init s5pv210_map_io(void)
void __init s5pv210_init_clocks(int xtal)
{
+#ifdef CONFIG_S5P_CLOCK
printk(KERN_DEBUG %s: initializing clocks\n, __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
s5pv210_register_clocks();
s5pv210_setup_clocks();
+#endif
}
void __init s5pv210_init_irq(void)
@@ -248,6 +269,7 @@ void __init s5pv210_init_irq(void)
vic[3] = ~0;
s5p_init_irq(vic, ARRAY_SIZE(vic));
+ s5pv210_clk_init(NULL, xxti_f, xusbxti_f, S3C_VA_SYS);
}
struct bus_type s5pv210_subsys = {
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index fe1beb5..2db2a15 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -14,6 +14,19 @@
#include linux/reboot.h
+void s5pv210_set_xxti_freq(unsigned long freq);
+void s5pv210_set_xusbxti_freq(unsigned long freq);
+
+#ifdef CONFIG_COMMON_CLK_S5PV210
+void s5pv210_clk_init(struct device_node *np,
+ unsigned long xxti_f, unsigned long xusbxti_f,
+ void __iomem *reg_base);
+#else
+static inline void s5pv210_clk_init(struct device_node *np,
+ unsigned long xxti_f, unsigned long xusbxti_f,
+ void __iomem *reg_base) {}
+#endif
+
void s5pv210_init_io(struct map_desc *mach_desc, int size);
void s5pv210_init_irq(void);
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c
b/arch/arm/mach-s5pv210/mach-aquila.c
index ad40ab0..e37a311 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -646,6 +646,7 @@ static void __init aquila_map_io(void)
{
s5pv210_init_io(NULL, 0);
s3c24xx_init_clocks(2400);
+ s5pv210_set_xusbxti_freq(2400);
[PATCH v2 15/16] clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4x12 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 49 +++
1 file changed, 49 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 722bf7c..ad5ff50 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1026,6 +1026,46 @@ static struct samsung_pll_rate_table
exynos4210_vpll_rates[] __initdata = {
{ /* sentinel */ }
};
+static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = {
+ PLL_35XX_RATE(15, 250, 4, 0),
+ PLL_35XX_RATE(14, 175, 3, 0),
+ PLL_35XX_RATE(13, 325, 6, 0),
+ PLL_35XX_RATE(12, 200, 4, 0),
+ PLL_35XX_RATE(11, 275, 6, 0),
+ PLL_35XX_RATE(10, 125, 3, 0),
+ PLL_35XX_RATE( 9, 150, 4, 0),
+ PLL_35XX_RATE( 8, 100, 3, 0),
+ PLL_35XX_RATE( 7, 175, 3, 1),
+ PLL_35XX_RATE( 6, 200, 4, 1),
+ PLL_35XX_RATE( 5, 125, 3, 1),
+ PLL_35XX_RATE( 4, 100, 3, 1),
+ PLL_35XX_RATE( 3, 200, 4, 2),
+ PLL_35XX_RATE( 2, 100, 3, 2),
+ { /* sentinel */ }
+};
+
+static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = {
+ PLL_36XX_RATE(19200, 48, 3, 1, 0),
+ PLL_36XX_RATE(180633605, 45, 3, 1, 10381),
+ PLL_36XX_RATE(18000, 45, 3, 1, 0),
+ PLL_36XX_RATE( 73727996, 73, 3, 3, 47710),
+ PLL_36XX_RATE( 67737602, 90, 4, 3, 20762),
+ PLL_36XX_RATE( 49151992, 49, 3, 3, 9961),
+ PLL_36XX_RATE( 45158401, 45, 3, 3, 10381),
+ { /* sentinel */ }
+};
+
+static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = {
+ PLL_36XX_RATE(53300, 133, 3, 1, 16384),
+ PLL_36XX_RATE(44000, 110, 3, 1, 0),
+ PLL_36XX_RATE(35000, 175, 3, 2, 0),
+ PLL_36XX_RATE(26600, 133, 3, 2, 0),
+ PLL_36XX_RATE(16000, 160, 3, 3, 0),
+ PLL_36XX_RATE(106031250, 53, 3, 2, 1024),
+ PLL_36XX_RATE( 53015625, 53, 3, 3, 1024),
+ { /* sentinel */ }
+};
+
static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
[apll] = PLL_A(pll_4508, fout_apll, fout_apll, fin_pll, APLL_LOCK,
APLL_CON0, fout_apll, NULL),
@@ -1090,6 +1130,15 @@ static void __init exynos4_clk_init(struct device_node
*np,
samsung_clk_register_pll(exynos4210_plls,
ARRAY_SIZE(exynos4210_plls), reg_base);
} else {
+ if (_get_rate(fin_pll) == 2400) {
+ exynos4x12_plls[apll].rate_table =
+ exynos4x12_apll_rates;
+ exynos4x12_plls[epll].rate_table =
+ exynos4x12_epll_rates;
+ exynos4x12_plls[vpll].rate_table =
+ exynos4x12_vpll_rates;
+ }
+
samsung_clk_register_pll(exynos4x12_plls,
ARRAY_SIZE(exynos4x12_plls), reg_base);
}
--
1.8.3.2
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[PATCH v2 03/16] clocksource: samsung_pwm_timer: Get clock from device tree
When booting with device tree static clkdev aliases should not be used.
This patch modifies the samsung_pwm_timer driver to use DT-based clock
lookup when booting with device tree.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clocksource/samsung_pwm_timer.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/clocksource/samsung_pwm_timer.c
b/drivers/clocksource/samsung_pwm_timer.c
index ac60f8b..ab29476 100644
--- a/drivers/clocksource/samsung_pwm_timer.c
+++ b/drivers/clocksource/samsung_pwm_timer.c
@@ -368,10 +368,6 @@ static void __init samsung_clocksource_init(void)
static void __init samsung_timer_resources(void)
{
- pwm.timerclk = clk_get(NULL, timers);
- if (IS_ERR(pwm.timerclk))
- panic(failed to get timers clock for timer);
-
clk_prepare_enable(pwm.timerclk);
pwm.tcnt_max = (1UL pwm.variant.bits) - 1;
@@ -416,6 +412,10 @@ void __init samsung_pwm_clocksource_init(void __iomem
*base,
memcpy(pwm.variant, variant, sizeof(pwm.variant));
memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));
+ pwm.timerclk = clk_get(NULL, timers);
+ if (IS_ERR(pwm.timerclk))
+ panic(failed to get timers clock for timer);
+
_samsung_pwm_clocksource_init();
}
@@ -447,6 +447,10 @@ static void __init samsung_pwm_alloc(struct device_node
*np,
return;
}
+ pwm.timerclk = of_clk_get_by_name(np, timers);
+ if (IS_ERR(pwm.timerclk))
+ panic(failed to get timers clock for timer);
+
_samsung_pwm_clocksource_init();
}
--
1.8.3.2
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[PATCH v2 00/16] Exynos clock clean-up for 3.12
This series fixes various functional and non-functional (e.g. stylistic) issues in Common Clock Framework drivers for Samsung Exynos SoCs. See particular patches for more detailed descriptions. Changes since v1: [http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg21665.html] - Addressed comments from Yadwinder Singh Brar: - added missing __initdata keywords, - various typoes fixed, - other minor stylistic improvements. Tomasz Figa (16): pwm: samsung: Update DT bindings documentation to cover clocks ARM: dts: exynos4: Specify PWM clocks in PWM node clocksource: samsung_pwm_timer: Get clock from device tree clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos5250: Simplify registration of PLL rate tables .../devicetree/bindings/pwm/pwm-samsung.txt| 12 + arch/arm/boot/dts/exynos4.dtsi | 2 + drivers/clk/samsung/clk-exynos4.c | 539 - drivers/clk/samsung/clk-exynos5250.c | 12 +- drivers/clk/samsung/clk-exynos5440.c | 2 +- drivers/clk/samsung/clk-pll.c | 285 --- drivers/clk/samsung/clk-pll.h | 59 ++- drivers/clk/samsung/clk.c | 10 +- drivers/clocksource/samsung_pwm_timer.c| 12 +- 9 files changed, 602 insertions(+), 331 deletions(-) -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 04/16] clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
Exynos cpufreq driver is the only remaining piece of code that needs
static clkdev aliases for operation, because it can not do device tree
based clock lookups yet.
This patch moves clock alias definitions for those clocks to separate
arrays that can be used with samsung_clk_register_alias() helper.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 35 +++
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index f53658b..7de0769 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -392,9 +392,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
MUX(none, mout_g2d, mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
MUX(none, mout_fimd1, group1_p4210, E4210_SRC_LCD1, 0, 4),
MUX(none, mout_mipi1, group1_p4210, E4210_SRC_LCD1, 12, 4),
- MUX_A(sclk_mpll, sclk_mpll, mout_mpll_p, SRC_CPU, 8, 1, mout_mpll),
- MUX_A(mout_core, mout_core, mout_core_p4210,
- SRC_CPU, 16, 1, moutcore),
+ MUX(sclk_mpll, sclk_mpll, mout_mpll_p, SRC_CPU, 8, 1),
+ MUX(mout_core, mout_core, mout_core_p4210, SRC_CPU, 16, 1),
MUX_A(sclk_vpll, sclk_vpll, sclk_vpll_p4210,
SRC_TOP0, 8, 1, sclk_vpll),
MUX(mout_fimc0, mout_fimc0, group1_p4210, SRC_CAM, 0, 4),
@@ -431,8 +430,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
/* list of mux clocks supported in exynos4x12 soc */
static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
- MUX_A(mout_mpll_user_c, mout_mpll_user_c, mout_mpll_user_p4x12,
- SRC_CPU, 24, 1, mout_mpll),
+ MUX(mout_mpll_user_c, mout_mpll_user_c, mout_mpll_user_p4x12,
+ SRC_CPU, 24, 1),
MUX(none, mout_aclk266_gps, aclk_p4412, SRC_TOP1, 4, 1),
MUX(none, mout_aclk400_mcuisp, aclk_p4412, SRC_TOP1, 8, 1),
MUX(mout_mpll_user_t, mout_mpll_user_t, mout_mpll_user_p4x12,
@@ -456,8 +455,7 @@ static struct samsung_mux_clock exynos4x12_mux_clks[]
__initdata = {
SRC_DMC, 12, 1, sclk_mpll),
MUX_A(sclk_vpll, sclk_vpll, mout_vpll_p,
SRC_TOP0, 8, 1, sclk_vpll),
- MUX_A(mout_core, mout_core, mout_core_p4x12,
- SRC_CPU, 16, 1, moutcore),
+ MUX(mout_core, mout_core, mout_core_p4x12, SRC_CPU, 16, 1),
MUX(mout_fimc0, mout_fimc0, group1_p4x12, SRC_CAM, 0, 4),
MUX(mout_fimc1, mout_fimc1, group1_p4x12, SRC_CAM, 4, 4),
MUX(mout_fimc2, mout_fimc2, group1_p4x12, SRC_CAM, 8, 4),
@@ -545,7 +543,7 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(none, div_spi_pre2, div_spi2, DIV_PERIL2, 8, 8),
DIV(none, div_audio1, mout_audio1, DIV_PERIL4, 0, 4),
DIV(none, div_audio2, mout_audio2, DIV_PERIL4, 16, 4),
- DIV_A(arm_clk, arm_clk, div_core2, DIV_CPU0, 28, 3, armclk),
+ DIV(arm_clk, arm_clk, div_core2, DIV_CPU0, 28, 3),
DIV_A(sclk_apll, sclk_apll, mout_apll,
DIV_CPU0, 24, 3, sclk_apll),
DIV_F(none, div_mipi_pre0, div_mipi0, DIV_LCD0, 20, 4,
@@ -930,6 +928,20 @@ static struct samsung_gate_clock exynos4x12_gate_clks[]
__initdata = {
GATE(tmu_apbif, tmu_apbif, aclk100, E4X12_GATE_IP_PERIR, 17, 0, 0),
};
+static struct samsung_clock_alias exynos4_aliases[] __initdata = {
+ ALIAS(mout_core, NULL, moutcore),
+ ALIAS(arm_clk, NULL, armclk),
+ ALIAS(sclk_apll, NULL, mout_apll),
+};
+
+static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
+ ALIAS(sclk_mpll, NULL, mout_mpll),
+};
+
+static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
+ ALIAS(mout_mpll_user_c, NULL, mout_mpll),
+};
+
/*
* The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
* resides in chipid register space, outside of the clock controller memory
@@ -1065,6 +1077,8 @@ static void __init exynos4_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos4210_div_clks));
samsung_clk_register_gate(exynos4210_gate_clks,
ARRAY_SIZE(exynos4210_gate_clks));
+ samsung_clk_register_alias(exynos4210_aliases,
+ ARRAY_SIZE(exynos4210_aliases));
} else {
samsung_clk_register_mux(exynos4x12_mux_clks,
ARRAY_SIZE(exynos4x12_mux_clks));
@@ -1072,8 +1086,13 @@ static void __init exynos4_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos4x12_div_clks));
samsung_clk_register_gate(exynos4x12_gate_clks,
ARRAY_SIZE(exynos4x12_gate_clks));
+ samsung_clk_register_alias(exynos4x12_aliases,
+
[PATCH v2 01/16] pwm: samsung: Update DT bindings documentation to cover clocks
PWM driver consumes at least one and up to three clocks, which need to be specified in device tree when used. This patch updates bindings documentation to add information about clocks. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com Acked-by: Stephen Warren swar...@nvidia.com --- Documentation/devicetree/bindings/pwm/pwm-samsung.txt | 12 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt index 4caa1a7..d61fccd 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt @@ -19,6 +19,16 @@ Required properties: - reg: base address and size of register area - interrupts: list of timer interrupts (one interrupt per timer, starting at timer 0) +- clock-names: should contain all following required clock names: +- timers - PWM base clock used to generate PWM signals, + and any subset of following optional clock names: +- pwm-tclk0 - first external PWM clock source, +- pwm-tclk1 - second external PWM clock source. + Note that not all IP variants allow using all external clock sources. + Refer to SoC documentation to learn which clock source configurations + are available. +- clocks: should contain clock specifiers of all clocks, which input names + have been specified in clock-names property, in same order. - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -34,6 +44,8 @@ Example: reg = 0x7f006000 0x1000; interrupt-parent = vic0; interrupts = 23, 24, 25, 27, 28; + clocks = clock 67; + clock-names = timers; samsung,pwm-outputs = 0, 1; #pwm-cells = 3; } -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 16/16] clk: samsung: exynos5250: Simplify registration of PLL rate tables
Since the _get_rate() helper has been modified to use __clk_lookup()
internally, checking of PLL input rates can be done using it and so the
registration code can be simplified.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos5250.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index a9916a4..00a80e4 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -543,8 +543,6 @@ static struct of_device_id ext_clk_match[] __initdata = {
static void __init exynos5250_clk_init(struct device_node *np)
{
void __iomem *reg_base;
- struct clk *vpllsrc;
- unsigned long fin_pll_rate, mout_vpllsrc_rate = 0;
if (np) {
reg_base = of_iomap(np, 0);
@@ -563,16 +561,10 @@ static void __init exynos5250_clk_init(struct device_node
*np)
samsung_clk_register_mux(exynos5250_pll_pmux_clks,
ARRAY_SIZE(exynos5250_pll_pmux_clks));
- fin_pll_rate = _get_rate(fin_pll);
-
- if (fin_pll_rate == 24 * MHZ)
+ if (_get_rate(fin_pll) == 24 * MHZ)
exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
- vpllsrc = __clk_lookup(mout_vpllsrc);
- if (vpllsrc)
- mout_vpllsrc_rate = clk_get_rate(vpllsrc);
-
- if (mout_vpllsrc_rate == 24 * MHZ)
+ if (_get_rate(mout_vpllsrc) == 24 * MHZ)
exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls),
--
1.8.3.2
--
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[PATCH v2 02/16] ARM: dts: exynos4: Specify PWM clocks in PWM node
Since pwm-samsung bindings require at least one clock to be specified, this patch adds the missing clocks and clock-names properties to specify clocks used by PWM block on Exynos4 SoCs. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/boot/dts/exynos4.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 93c2501..caadc02 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -448,6 +448,8 @@ compatible = samsung,exynos4210-pwm; reg = 0x139D 0x1000; interrupts = 0 37 0, 0 38 0, 0 39 0, 0 40 0, 0 41 0; + clocks = clock 336; + clock-names = timers; #pwm-cells = 2; status = disabled; }; -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 08/16] clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
This array defines PLLs specific to Exynos 4x12 SoCs and not for all
Exynos 4 SoCs, so the name should represent that.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index f1b61fe..febdce2 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -988,7 +988,7 @@ static struct of_device_id ext_clk_match[] __initdata = {
{},
};
-static struct samsung_pll_clock exynos4_plls[nr_plls] __initdata = {
+static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
[apll] = PLL(pll_35xx, fout_apll, fout_apll, fin_pll,
APLL_LOCK, APLL_CON0, NULL),
[mpll] = PLL(pll_35xx, fout_mpll, fout_mpll, fin_pll,
@@ -1040,8 +1040,8 @@ static void __init exynos4_clk_init(struct device_node
*np,
samsung_clk_add_lookup(epll, fout_epll);
samsung_clk_add_lookup(vpll, fout_vpll);
} else {
- samsung_clk_register_pll(exynos4_plls,
- ARRAY_SIZE(exynos4_plls), reg_base);
+ samsung_clk_register_pll(exynos4x12_plls,
+ ARRAY_SIZE(exynos4x12_plls), reg_base);
}
samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
--
1.8.3.2
--
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[PATCH v2 06/16] clk: samsung: exynos4: Remove unused static clkdev aliases
Since Exynos does not support legacy non-DT boot anymore, most of clock
lookups happen using device tree, so most of static clkdev aliases are no
longer necessary. This patch removes them.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 356 ++
1 file changed, 172 insertions(+), 184 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index a974a56..457b15a 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -374,7 +374,7 @@ static struct samsung_mux_clock exynos4_mux_clks[]
__initdata = {
CLK_SET_RATE_PARENT, 0),
MUX(none, mout_spdif, mout_spdif_p, SRC_PERIL1, 8, 2),
MUX(none, mout_onenand1, mout_onenand1_p, SRC_TOP0, 0, 1),
- MUX_A(sclk_epll, sclk_epll, mout_epll_p, SRC_TOP0, 4, 1, sclk_epll),
+ MUX(sclk_epll, sclk_epll, mout_epll_p, SRC_TOP0, 4, 1),
MUX(none, mout_onenand, mout_onenand_p, SRC_TOP0, 28, 1),
};
@@ -394,8 +394,7 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
MUX(none, mout_mipi1, group1_p4210, E4210_SRC_LCD1, 12, 4),
MUX(sclk_mpll, sclk_mpll, mout_mpll_p, SRC_CPU, 8, 1),
MUX(mout_core, mout_core, mout_core_p4210, SRC_CPU, 16, 1),
- MUX_A(sclk_vpll, sclk_vpll, sclk_vpll_p4210,
- SRC_TOP0, 8, 1, sclk_vpll),
+ MUX(sclk_vpll, sclk_vpll, sclk_vpll_p4210, SRC_TOP0, 8, 1),
MUX(mout_fimc0, mout_fimc0, group1_p4210, SRC_CAM, 0, 4),
MUX(mout_fimc1, mout_fimc1, group1_p4210, SRC_CAM, 4, 4),
MUX(mout_fimc2, mout_fimc2, group1_p4210, SRC_CAM, 8, 4),
@@ -451,10 +450,8 @@ static struct samsung_mux_clock exynos4x12_mux_clks[]
__initdata = {
MUX(none, mout_jpeg0, sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
MUX(none, mout_jpeg1, sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
MUX(none, mout_jpeg, mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
- MUX_A(sclk_mpll, sclk_mpll, mout_mpll_p,
- SRC_DMC, 12, 1, sclk_mpll),
- MUX_A(sclk_vpll, sclk_vpll, mout_vpll_p,
- SRC_TOP0, 8, 1, sclk_vpll),
+ MUX(sclk_mpll, sclk_mpll, mout_mpll_p, SRC_DMC, 12, 1),
+ MUX(sclk_vpll, sclk_vpll, mout_vpll_p, SRC_TOP0, 8, 1),
MUX(mout_core, mout_core, mout_core_p4x12, SRC_CPU, 16, 1),
MUX(mout_fimc0, mout_fimc0, group1_p4x12, SRC_CAM, 0, 4),
MUX(mout_fimc1, mout_fimc1, group1_p4x12, SRC_CAM, 4, 4),
@@ -544,8 +541,7 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(none, div_audio1, mout_audio1, DIV_PERIL4, 0, 4),
DIV(none, div_audio2, mout_audio2, DIV_PERIL4, 16, 4),
DIV(arm_clk, arm_clk, div_core2, DIV_CPU0, 28, 3),
- DIV_A(sclk_apll, sclk_apll, mout_apll,
- DIV_CPU0, 24, 3, sclk_apll),
+ DIV(sclk_apll, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
DIV_F(none, div_mipi_pre0, div_mipi0, DIV_LCD0, 20, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(none, div_mmc_pre0, div_mmc0, DIV_FSYS1, 8, 8,
@@ -634,160 +630,147 @@ static struct samsung_gate_clock exynos4_gate_clks[]
__initdata = {
CLK_SET_RATE_PARENT, 0),
GATE(sclk_audio1, sclk_audio1, div_audio1, SRC_MASK_PERIL1, 0,
CLK_SET_RATE_PARENT, 0),
- GATE_D(vp, s5p-mixer, vp, aclk160, GATE_IP_TV, 0, 0, 0),
- GATE_D(mixer, s5p-mixer, mixer, aclk160, GATE_IP_TV, 1, 0, 0),
- GATE_D(hdmi, exynos4-hdmi, hdmi, aclk160, GATE_IP_TV, 3, 0, 0),
- GATE_A(pwm, pwm, aclk100, GATE_IP_PERIL, 24, 0, 0, timers),
- GATE_A(sdmmc4, sdmmc4, aclk133, GATE_IP_FSYS, 9, 0, 0, biu),
- GATE_A(usb_host, usb_host, aclk133,
- GATE_IP_FSYS, 12, 0, 0, usbhost),
- GATE_DA(sclk_fimc0, exynos4-fimc.0, sclk_fimc0, div_fimc0,
- SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, sclk_fimc),
- GATE_DA(sclk_fimc1, exynos4-fimc.1, sclk_fimc1, div_fimc1,
- SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, sclk_fimc),
- GATE_DA(sclk_fimc2, exynos4-fimc.2, sclk_fimc2, div_fimc2,
- SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, sclk_fimc),
- GATE_DA(sclk_fimc3, exynos4-fimc.3, sclk_fimc3, div_fimc3,
- SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, sclk_fimc),
- GATE_DA(sclk_csis0, s5p-mipi-csis.0, sclk_csis0, div_csis0,
- SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, sclk_csis),
- GATE_DA(sclk_csis1, s5p-mipi-csis.1, sclk_csis1, div_csis1,
- SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, sclk_csis),
- GATE_DA(sclk_fimd0, exynos4-fb.0, sclk_fimd0, div_fimd0,
- SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, sclk_fimd),
- GATE_DA(sclk_mmc0, exynos4-sdhci.0, sclk_mmc0, div_mmc_pre0,
-
[PATCH v2 12/16] clk: samsung: pll: Add support for rate configuration of PLL46xx
This patch implements round_rate and set_rate callbacks of PLL46xx
driver to allow reconfiguration of PLL at runtime.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-pll.c | 111 +-
drivers/clk/samsung/clk-pll.h | 25 ++
2 files changed, 135 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 14bd83e..d8ea6ca 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -411,10 +411,13 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops =
{
/*
* PLL46xx Clock Type
*/
+#define PLL46XX_LOCK_FACTOR3000
+#define PLL46XX_VSEL_MASK (1)
#define PLL46XX_MDIV_MASK (0x1FF)
#define PLL46XX_PDIV_MASK (0x3F)
#define PLL46XX_SDIV_MASK (0x7)
+#define PLL46XX_VSEL_SHIFT (27)
#define PLL46XX_MDIV_SHIFT (16)
#define PLL46XX_PDIV_SHIFT (8)
#define PLL46XX_SDIV_SHIFT (0)
@@ -422,6 +425,15 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = {
#define PLL46XX_KDIV_MASK (0x)
#define PLL4650C_KDIV_MASK (0xFFF)
#define PLL46XX_KDIV_SHIFT (0)
+#define PLL46XX_MFR_MASK (0x3F)
+#define PLL46XX_MRR_MASK (0x1F)
+#define PLL46XX_KDIV_SHIFT (0)
+#define PLL46XX_MFR_SHIFT (16)
+#define PLL46XX_MRR_SHIFT (24)
+
+#define PLL46XX_ENABLE BIT(31)
+#define PLL46XX_LOCKED BIT(29)
+#define PLL46XX_VSEL BIT(27)
static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -446,8 +458,102 @@ static unsigned long samsung_pll46xx_recalc_rate(struct
clk_hw *hw,
return (unsigned long)fvco;
}
+static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1,
+ const struct samsung_pll_rate_table *rate)
+{
+ u32 old_mdiv, old_pdiv, old_kdiv;
+
+ old_mdiv = (pll_con0 PLL46XX_MDIV_SHIFT) PLL46XX_MDIV_MASK;
+ old_pdiv = (pll_con0 PLL46XX_PDIV_SHIFT) PLL46XX_PDIV_MASK;
+ old_kdiv = (pll_con1 PLL46XX_KDIV_SHIFT) PLL46XX_KDIV_MASK;
+
+ return (old_mdiv != rate-mdiv || old_pdiv != rate-pdiv
+ || old_kdiv != rate-kdiv);
+}
+
+static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 con0, con1, lock;
+ ktime_t start;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err(%s: Invalid rate : %lu for pll clk %s\n, __func__,
+ drate, __clk_get_name(hw-clk));
+ return -EINVAL;
+ }
+
+ con0 = __raw_readl(pll-con_reg);
+ con1 = __raw_readl(pll-con_reg + 0x4);
+
+ if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
+ /* If only s change, change just s value only*/
+ con0 = ~(PLL46XX_SDIV_MASK PLL46XX_SDIV_SHIFT);
+ con0 |= rate-sdiv PLL46XX_SDIV_SHIFT;
+ __raw_writel(con0, pll-con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time. */
+ lock = rate-pdiv * PLL46XX_LOCK_FACTOR;
+ if (lock 0x)
+ /* Maximum lock time bitfield is 16-bit. */
+ lock = 0x;
+
+ /* Set PLL PMS and VSEL values. */
+ con0 = ~((PLL46XX_MDIV_MASK PLL46XX_MDIV_SHIFT) |
+ (PLL46XX_PDIV_MASK PLL46XX_PDIV_SHIFT) |
+ (PLL46XX_SDIV_MASK PLL46XX_SDIV_SHIFT) |
+ (PLL46XX_VSEL_MASK PLL46XX_VSEL_SHIFT));
+ con0 |= (rate-mdiv PLL46XX_MDIV_SHIFT) |
+ (rate-pdiv PLL46XX_PDIV_SHIFT) |
+ (rate-sdiv PLL46XX_SDIV_SHIFT) |
+ (rate-vsel PLL46XX_VSEL_SHIFT);
+
+ /* Set PLL K, MFR and MRR values. */
+ con1 = __raw_readl(pll-con_reg + 0x4);
+ con1 = ~((PLL46XX_KDIV_MASK PLL46XX_KDIV_SHIFT) |
+ (PLL46XX_MFR_MASK PLL46XX_MFR_SHIFT) |
+ (PLL46XX_MRR_MASK PLL46XX_MRR_SHIFT));
+ con1 |= (rate-kdiv PLL46XX_KDIV_SHIFT) |
+ (rate-mfr PLL46XX_MFR_SHIFT) |
+ (rate-mrr PLL46XX_MRR_SHIFT);
+
+ /* Write configuration to PLL */
+ __raw_writel(lock, pll-lock_reg);
+ __raw_writel(con0, pll-con_reg);
+ __raw_writel(con1, pll-con_reg + 0x4);
+
+ /* Wait for locking. */
+ start = ktime_get();
+ while (!(__raw_readl(pll-con_reg) PLL46XX_LOCKED)) {
+ ktime_t delta = ktime_sub(ktime_get(), start);
+
+ if (ktime_to_ms(delta) PLL_TIMEOUT_MS) {
+ pr_err(%s: could not lock PLL %s\n,
+
[PATCH v2 09/16] clk: samsung: pll: Use new registration method for PLL45xx
This patch modifies PLL45xx support code and its users to use the
recently introduced common PLL registration helper.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 18 --
drivers/clk/samsung/clk-pll.c | 52 +--
drivers/clk/samsung/clk-pll.h | 12 +++--
3 files changed, 20 insertions(+), 62 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index febdce2..36b36b7 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -104,6 +104,7 @@
#define DIV_DMC1 0x10504
#define GATE_IP_DMC0x10900
#define APLL_LOCK 0x14000
+#define E4210_MPLL_LOCK0x14008
#define APLL_CON0 0x14100
#define E4210_MPLL_CON00x14108
#define SRC_CPU0x14200
@@ -988,6 +989,13 @@ static struct of_device_id ext_clk_match[] __initdata = {
{},
};
+static struct samsung_pll_clock exynos4210_plls[] __initdata = {
+ [apll] = PLL_A(pll_4508, fout_apll, fout_apll, fin_pll, APLL_LOCK,
+ APLL_CON0, fout_apll, NULL),
+ [mpll] = PLL_A(pll_4508, fout_mpll, fout_mpll, fin_pll,
+ E4210_MPLL_LOCK, E4210_MPLL_CON0, fout_mpll, NULL),
+};
+
static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
[apll] = PLL(pll_35xx, fout_apll, fout_apll, fin_pll,
APLL_LOCK, APLL_CON0, NULL),
@@ -1004,7 +1012,7 @@ static void __init exynos4_clk_init(struct device_node
*np,
enum exynos4_soc exynos4_soc,
void __iomem *reg_base, unsigned long xom)
{
- struct clk *apll, *mpll, *epll, *vpll;
+ struct clk *epll, *vpll;
reg_base = of_iomap(np, 0);
if (!reg_base)
@@ -1026,17 +1034,13 @@ static void __init exynos4_clk_init(struct device_node
*np,
exynos4_clk_register_finpll(xom);
if (exynos4_soc == EXYNOS4210) {
- apll = samsung_clk_register_pll45xx(fout_apll, fin_pll,
- reg_base + APLL_CON0, pll_4508);
- mpll = samsung_clk_register_pll45xx(fout_mpll, fin_pll,
- reg_base + E4210_MPLL_CON0, pll_4508);
+ samsung_clk_register_pll(exynos4210_plls,
+ ARRAY_SIZE(exynos4210_plls), reg_base);
epll = samsung_clk_register_pll46xx(fout_epll, fin_pll,
reg_base + EPLL_CON0, pll_4600);
vpll = samsung_clk_register_pll46xx(fout_vpll, mout_vpllsrc,
reg_base + VPLL_CON0, pll_4650c);
- samsung_clk_add_lookup(apll, fout_apll);
- samsung_clk_add_lookup(mpll, fout_mpll);
samsung_clk_add_lookup(epll, fout_epll);
samsung_clk_add_lookup(vpll, fout_vpll);
} else {
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 0775554..b0398d2 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -280,18 +280,10 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops =
{
#define PLL45XX_PDIV_SHIFT (8)
#define PLL45XX_SDIV_SHIFT (0)
-struct samsung_clk_pll45xx {
- struct clk_hw hw;
- enum pll45xx_type type;
- const void __iomem *con_reg;
-};
-
-#define to_clk_pll45xx(_hw) container_of(_hw, struct samsung_clk_pll45xx, hw)
-
static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct samsung_clk_pll45xx *pll = to_clk_pll45xx(hw);
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, pll_con;
u64 fvco = parent_rate;
@@ -313,43 +305,6 @@ static const struct clk_ops samsung_pll45xx_clk_ops = {
.recalc_rate = samsung_pll45xx_recalc_rate,
};
-struct clk * __init samsung_clk_register_pll45xx(const char *name,
- const char *pname, const void __iomem *con_reg,
- enum pll45xx_type type)
-{
- struct samsung_clk_pll45xx *pll;
- struct clk *clk;
- struct clk_init_data init;
-
- pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (!pll) {
- pr_err(%s: could not allocate pll clk %s\n, __func__, name);
- return NULL;
- }
-
- init.name = name;
- init.ops = samsung_pll45xx_clk_ops;
- init.flags = CLK_GET_RATE_NOCACHE;
- init.parent_names = pname;
- init.num_parents = 1;
-
- pll-hw.init = init;
- pll-con_reg = con_reg;
- pll-type = type;
-
- clk = clk_register(NULL, pll-hw);
- if (IS_ERR(clk)) {
- pr_err(%s: failed to register pll
[PATCH v2 07/16] clk: samsung: exynos4: Remove checks for DT node
Exynos 4 supports only DT based bootup, so non-DT cases does not need to
be handled anymore.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 457b15a..f1b61fe 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1006,11 +1006,9 @@ static void __init exynos4_clk_init(struct device_node
*np,
{
struct clk *apll, *mpll, *epll, *vpll;
- if (np) {
- reg_base = of_iomap(np, 0);
- if (!reg_base)
- panic(%s: failed to map registers\n, __func__);
- }
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic(%s: failed to map registers\n, __func__);
if (exynos4_soc == EXYNOS4210)
samsung_clk_init(np, reg_base, nr_clks,
@@ -1021,8 +1019,7 @@ static void __init exynos4_clk_init(struct device_node
*np,
exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
- if (np)
- samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
+ samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
ext_clk_match);
--
1.8.3.2
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[PATCH v2 14/16] clk: samsung: exynos4: Register PLL rate tables for Exynos4210
This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4210 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 45 +++
1 file changed, 45 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 9734042..722bf7c 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -992,6 +992,40 @@ static struct of_device_id ext_clk_match[] __initdata = {
{},
};
+/* PLLs PMS values */
+static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = {
+ PLL_45XX_RATE(12, 150, 3, 1, 28),
+ PLL_45XX_RATE(10, 250, 6, 1, 28),
+ PLL_45XX_RATE( 8, 200, 6, 1, 28),
+ PLL_45XX_RATE( 666857142, 389, 14, 1, 13),
+ PLL_45XX_RATE( 6, 100, 4, 1, 13),
+ PLL_45XX_RATE( 53300, 533, 24, 1, 5),
+ PLL_45XX_RATE( 5, 250, 6, 2, 28),
+ PLL_45XX_RATE( 4, 200, 6, 2, 28),
+ PLL_45XX_RATE( 2, 200, 6, 3, 28),
+ { /* sentinel */ }
+};
+
+static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = {
+ PLL_4600_RATE(19200, 48, 3, 1, 0, 0),
+ PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0),
+ PLL_4600_RATE(18000, 45, 3, 1, 0, 0),
+ PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1),
+ PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1),
+ PLL_4600_RATE( 49151992, 49, 3, 3, 9961, 0),
+ PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0),
+ { /* sentinel */ }
+};
+
+static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = {
+ PLL_4650_RATE(36000, 44, 3, 0, 1024, 0, 14, 0),
+ PLL_4650_RATE(32400, 53, 2, 1, 1024, 1, 1, 1),
+ PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1),
+ PLL_4650_RATE(11000, 53, 3, 2, 2048, 0, 17, 0),
+ PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0),
+ { /* sentinel */ }
+};
+
static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
[apll] = PLL_A(pll_4508, fout_apll, fout_apll, fin_pll, APLL_LOCK,
APLL_CON0, fout_apll, NULL),
@@ -1042,6 +1076,17 @@ static void __init exynos4_clk_init(struct device_node
*np,
samsung_clk_register_mux(exynos4210_mux_early,
ARRAY_SIZE(exynos4210_mux_early));
+ if (_get_rate(fin_pll) == 2400) {
+ exynos4210_plls[apll].rate_table =
+ exynos4210_apll_rates;
+ exynos4210_plls[epll].rate_table =
+ exynos4210_epll_rates;
+ }
+
+ if (_get_rate(mout_vpllsrc) == 2400)
+ exynos4210_plls[vpll].rate_table =
+ exynos4210_vpll_rates;
+
samsung_clk_register_pll(exynos4210_plls,
ARRAY_SIZE(exynos4210_plls), reg_base);
} else {
--
1.8.3.2
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[PATCH v2 05/16] clk: samsung: Modify _get_rate() helper to use __clk_lookup()
There is no need to use clkdev inside the clock driver to retrieve the
clocks for internal use. Instead __clk_lookup() helper can be used to
look up clocks by their platform name.
This patch modifies the behavior of _get_rate() helper to look up clocks
by platform name and adjusts all users of it to pass platform names
instead of clkdev aliases.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c| 4 ++--
drivers/clk/samsung/clk-exynos5440.c | 2 +-
drivers/clk/samsung/clk.c| 10 --
3 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 7de0769..a974a56 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1096,9 +1096,9 @@ static void __init exynos4_clk_init(struct device_node
*np,
pr_info(%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n
\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n,
exynos4_soc == EXYNOS4210 ? Exynos4210 : Exynos4x12,
- _get_rate(sclk_apll), _get_rate(mout_mpll),
+ _get_rate(sclk_apll), _get_rate(sclk_mpll),
_get_rate(sclk_epll), _get_rate(sclk_vpll),
- _get_rate(armclk));
+ _get_rate(arm_clk));
}
diff --git a/drivers/clk/samsung/clk-exynos5440.c
b/drivers/clk/samsung/clk-exynos5440.c
index 4ef38e0..f865894 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -132,7 +132,7 @@ static void __init exynos5440_clk_init(struct device_node
*np)
samsung_clk_register_gate(exynos5440_gate_clks,
ARRAY_SIZE(exynos5440_gate_clks));
- pr_info(Exynos5440: arm_clk = %ldHz\n, _get_rate(armclk));
+ pr_info(Exynos5440: arm_clk = %ldHz\n, _get_rate(arm_clk));
pr_info(exynos5440 clock initialization complete\n);
}
CLK_OF_DECLARE(exynos5440_clk, samsung,exynos5440-clock,
exynos5440_clk_init);
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index cd3c40a..f503f32 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -307,14 +307,12 @@ void __init samsung_clk_of_register_fixed_ext(
unsigned long _get_rate(const char *clk_name)
{
struct clk *clk;
- unsigned long rate;
- clk = clk_get(NULL, clk_name);
- if (IS_ERR(clk)) {
+ clk = __clk_lookup(clk_name);
+ if (!clk) {
pr_err(%s: could not find clock %s\n, __func__, clk_name);
return 0;
}
- rate = clk_get_rate(clk);
- clk_put(clk);
- return rate;
+
+ return clk_get_rate(clk);
}
--
1.8.3.2
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[PATCH v2 13/16] clk: samsung: exynos4: Reorder registration of mout_vpllsrc
Since PLL input frequency must be known before PLL registration,
mout_vpllsrc clock which is a reference clock of VPLL must be registered
before VPLL.
This patch reorders clock registration to register mout_vpllsrc before
VPLL.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 5195c86..9734042 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -380,12 +380,15 @@ static struct samsung_mux_clock exynos4_mux_clks[]
__initdata = {
};
/* list of mux clocks supported in exynos4210 soc */
+static struct samsung_mux_clock exynos4210_mux_early[] __initdata = {
+ MUX(none, mout_vpllsrc, mout_vpllsrc_p, SRC_TOP1, 0, 1),
+};
+
static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
MUX(none, mout_aclk200, sclk_ampll_p4210, SRC_TOP0, 12, 1),
MUX(none, mout_aclk100, sclk_ampll_p4210, SRC_TOP0, 16, 1),
MUX(none, mout_aclk160, sclk_ampll_p4210, SRC_TOP0, 20, 1),
MUX(none, mout_aclk133, sclk_ampll_p4210, SRC_TOP0, 24, 1),
- MUX(none, mout_vpllsrc, mout_vpllsrc_p, SRC_TOP1, 0, 1),
MUX(none, mout_mixer, mout_mixer_p4210, SRC_TV, 4, 1),
MUX(none, mout_dac, mout_dac_p4210, SRC_TV, 8, 1),
MUX(none, mout_g2d0, sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
@@ -1036,6 +1039,9 @@ static void __init exynos4_clk_init(struct device_node
*np,
exynos4_clk_register_finpll(xom);
if (exynos4_soc == EXYNOS4210) {
+ samsung_clk_register_mux(exynos4210_mux_early,
+ ARRAY_SIZE(exynos4210_mux_early));
+
samsung_clk_register_pll(exynos4210_plls,
ARRAY_SIZE(exynos4210_plls), reg_base);
} else {
--
1.8.3.2
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[PATCH v2 10/16] clk: samsung: pll: Add support for rate configuration of PLL45xx
This patch implements round_rate and set_rate callbacks of PLL45xx
driver to allow reconfiguration of PLL at runtime.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-pll.c | 110 +-
drivers/clk/samsung/clk-pll.h | 10
2 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index b0398d2..052fc37 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -10,9 +10,12 @@
*/
#include linux/errno.h
+#include linux/hrtimer.h
#include clk.h
#include clk-pll.h
+#define PLL_TIMEOUT_MS 10
+
struct samsung_clk_pll {
struct clk_hw hw;
void __iomem*lock_reg;
@@ -272,13 +275,20 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops =
{
/*
* PLL45xx Clock Type
*/
+#define PLL4502_LOCK_FACTOR400
+#define PLL4508_LOCK_FACTOR240
#define PLL45XX_MDIV_MASK (0x3FF)
#define PLL45XX_PDIV_MASK (0x3F)
#define PLL45XX_SDIV_MASK (0x7)
+#define PLL45XX_AFC_MASK (0x1F)
#define PLL45XX_MDIV_SHIFT (16)
#define PLL45XX_PDIV_SHIFT (8)
#define PLL45XX_SDIV_SHIFT (0)
+#define PLL45XX_AFC_SHIFT (0)
+
+#define PLL45XX_ENABLE BIT(31)
+#define PLL45XX_LOCKED BIT(29)
static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -301,8 +311,101 @@ static unsigned long samsung_pll45xx_recalc_rate(struct
clk_hw *hw,
return (unsigned long)fvco;
}
+static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1,
+ const struct samsung_pll_rate_table *rate)
+{
+ u32 old_mdiv, old_pdiv, old_afc;
+
+ old_mdiv = (pll_con0 PLL45XX_MDIV_SHIFT) PLL45XX_MDIV_MASK;
+ old_pdiv = (pll_con0 PLL45XX_PDIV_SHIFT) PLL45XX_PDIV_MASK;
+ old_afc = (pll_con1 PLL45XX_AFC_SHIFT) PLL45XX_AFC_MASK;
+
+ return (old_mdiv != rate-mdiv || old_pdiv != rate-pdiv
+ || old_afc != rate-afc);
+}
+
+static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 con0, con1;
+ ktime_t start;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err(%s: Invalid rate : %lu for pll clk %s\n, __func__,
+ drate, __clk_get_name(hw-clk));
+ return -EINVAL;
+ }
+
+ con0 = __raw_readl(pll-con_reg);
+ con1 = __raw_readl(pll-con_reg + 0x4);
+
+ if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
+ /* If only s change, change just s value only*/
+ con0 = ~(PLL45XX_SDIV_MASK PLL45XX_SDIV_SHIFT);
+ con0 |= rate-sdiv PLL45XX_SDIV_SHIFT;
+ __raw_writel(con0, pll-con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL PMS values. */
+ con0 = ~((PLL45XX_MDIV_MASK PLL45XX_MDIV_SHIFT) |
+ (PLL45XX_PDIV_MASK PLL45XX_PDIV_SHIFT) |
+ (PLL45XX_SDIV_MASK PLL45XX_SDIV_SHIFT));
+ con0 |= (rate-mdiv PLL45XX_MDIV_SHIFT) |
+ (rate-pdiv PLL45XX_PDIV_SHIFT) |
+ (rate-sdiv PLL45XX_SDIV_SHIFT);
+
+ /* Set PLL AFC value. */
+ con1 = __raw_readl(pll-con_reg + 0x4);
+ con1 = ~(PLL45XX_AFC_MASK PLL45XX_AFC_SHIFT);
+ con1 |= (rate-afc PLL45XX_AFC_SHIFT);
+
+ /* Set PLL lock time. */
+ switch (pll-type) {
+ case pll_4502:
+ __raw_writel(rate-pdiv * PLL4502_LOCK_FACTOR, pll-lock_reg);
+ break;
+ case pll_4508:
+ __raw_writel(rate-pdiv * PLL4508_LOCK_FACTOR, pll-lock_reg);
+ break;
+ default:
+ break;
+ };
+
+ /* Set new configuration. */
+ __raw_writel(con1, pll-con_reg + 0x4);
+ __raw_writel(con0, pll-con_reg);
+
+ /* Wait for locking. */
+ start = ktime_get();
+ while (!(__raw_readl(pll-con_reg) PLL45XX_LOCKED)) {
+ ktime_t delta = ktime_sub(ktime_get(), start);
+
+ if (ktime_to_ms(delta) PLL_TIMEOUT_MS) {
+ pr_err(%s: could not lock PLL %s\n,
+ __func__, __clk_get_name(hw-clk));
+ return -EFAULT;
+ }
+
+ cpu_relax();
+ }
+
+ return 0;
+}
+
static const struct clk_ops samsung_pll45xx_clk_ops = {
.recalc_rate = samsung_pll45xx_recalc_rate,
+ .round_rate = samsung_pll_round_rate,
+ .set_rate = samsung_pll45xx_set_rate,
+};
+
+static const struct clk_ops
Re: [PATCH] ARM: dts: exynos4210: Work around lack of cpufreq regulator lookup
On Tuesday 20 of August 2013 19:35:36 Tomasz Figa wrote:
Exynos cpufreq drivers does not support device tree based regulator
lookup, so it can get the VDD ARM regulator only by its name. To get
cpufreq working for now, this patch works this around by renaming the
regulator in board dts files to vdd_arm, which is the name expected by
the driver.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts | 7 ++-
arch/arm/boot/dts/exynos4210-trats.dts | 7 ++-
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts index 382d8c7..46378fe 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -192,7 +192,12 @@
};
buck1_reg: BUCK1 {
- regulator-name = VDD_ARM_1.2V;
+ /*
+ * HACK: The real name is VDD_ARM_1.2V,
+ * but exynos-cpufreq does not support
+ * DT-based regulator lookup yet.
+ */
+ regulator-name = vdd_arm;
regulator-min-microvolt = 95;
regulator-max-microvolt = 135;
regulator-always-on;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts index 1c164f2..63cc571 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -290,7 +290,12 @@
};
varm_breg: BUCK1 {
- regulator-name = VARM_1.2V_C210;
+ /*
+ * HACK: The real name is VARM_1.2V_C210,
+ * but exynos-cpufreq does not support
+ * DT-based regulator lookup yet.
+ */
+ regulator-name = vdd_arm;
regulator-min-microvolt = 90;
regulator-max-microvolt = 135;
regulator-always-on;
Ping.
This patch fixes broken cpufreq on above two boards, so it would be nice to
have it merged for 3.12, even if it's a bit hacky, since it's too late for
proper solution at the moment. (It's already in development, though.)
Best regards,
Tomasz
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Re: [PATCH RFC 4/5] clk: samsung: Add clock driver for s5pc110/s5pv210
On Monday, August 26, 2013 01:38:33 PM Mateusz Krawczuk wrote:
This patch adds new, Common Clock Framework-based clock driver for Samsung
S5PV210 SoCs. The driver is just added, without enabling it yet.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
---
.../bindings/clock/samsung,s5pv210-clock.txt | 72 ++
drivers/clk/samsung/Makefile | 3 +-
drivers/clk/samsung/clk-s5pv210.c | 732
+
include/dt-bindings/clock/samsung,s5pv210-clock.h | 221 +++
4 files changed, 1027 insertions(+), 1 deletion(-)
create mode 100644
Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
create mode 100644 drivers/clk/samsung/clk-s5pv210.c
create mode 100644 include/dt-bindings/clock/samsung,s5pv210-clock.h
[...]
diff --git a/drivers/clk/samsung/clk-s5pv210.c
b/drivers/clk/samsung/clk-s5pv210.c
new file mode 100644
index 000..861d37d
--- /dev/null
+++ b/drivers/clk/samsung/clk-s5pv210.c
[...]
+static unsigned long s5pv210_get_xom(void)
This function can be marked with __init.
+{
+ unsigned long xom = 1;
+ void __iomem *chipid_base;
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, samsung,s5pv210-chipid);
+ if (np) {
+ chipid_base = of_iomap(np, 0);
How's about printing an error if !chipid_base?
Also the code can be made a bit shorter:
if (np) {
void __iomem *chipid_base = of_iomap(np, 0);
...
}
+ if (chipid_base)
+ xom = readl(chipid_base + 8);
+
+ iounmap(chipid_base);
It seems that at least generic iounmap() accepts NULL argument but it
will be better not to call it if of_iomap() failed.
+ }
+
+ return xom;
+}
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
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[PATCH v2 1/8] Documentation: devicetree: Update Exynos MCT bindings description
This patch updates description of device tree bindings for Exynos MCT
(multicore timers). Namely:
- added note about simplified specification of local timer interrupts,
when using single per-processor interrupt for all local timers,
- changed first example that was incorrectly suggesting that global
timer interrupts are optional,
- simplified example interrupt map,
- added example showing simplified local timer interrupt specification.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
.../bindings/timer/samsung,exynos4210-mct.txt | 54 +++---
1 file changed, 37 insertions(+), 17 deletions(-)
Changes since v1:
- corrected typo reported by Stephen Warren,
- edited last example to use separate properties to represent possible
alternatives, as suggested by Stephen Warren.
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
index b5a86d2..167d5da 100644
--- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
@@ -31,38 +31,58 @@ Required properties:
7: ..
i: Local Timer Interrupt n
-Example 1: In this example, the system uses only the first global timer
- interrupt generated by MCT and the remaining three global timer
- interrupts are unused. Two local timer interrupts have been
- specified.
+ For MCT block that uses a per-processor interrupt for local timers, such
+ as ones compatible with samsung,exynos4412-mct, only one local timer
+ interrupt might be specified, meaning that all local timers use the same
+ per processor interrupt.
+
+Example 1: In this example, the IP contains two local timers, using separate
+ interrupts, so two local timer interrupts have been specified,
+ in addition to four global timer interrupts.
mct@1005 {
compatible = samsung,exynos4210-mct;
reg = 0x1005 0x800;
- interrupts = 0 57 0, 0 0 0, 0 0 0, 0 0 0,
+ interrupts = 0 57 0, 0 69 0, 0 70 0, 0 71 0,
0 42 0, 0 48 0;
};
-Example 2: In this example, the MCT global and local timer interrupts are
- connected to two separate interrupt controllers. Hence, an
- interrupt-map is created to map the interrupts to the respective
- interrupt controllers.
+Example 2: In this example, the timer interrupts are connected to two separate
+ interrupt controllers. Hence, an interrupt-map is created to map
+ the interrupts to the respective interrupt controllers.
mct@101C {
compatible = samsung,exynos4210-mct;
reg = 0x101C 0x800;
- interrupt-controller;
- #interrups-cells = 2;
interrupt-parent = mct_map;
- interrupts = 0 0, 1 0, 2 0, 3 0,
-4 0, 5 0;
+ interrupts = 0, 1, 2, 3, 4, 5;
mct_map: mct-map {
- #interrupt-cells = 2;
+ #interrupt-cells = 1;
#address-cells = 0;
#size-cells = 0;
- interrupt-map = 0x0 0 combiner 23 3,
- 0x4 0 gic 0 120 0,
- 0x5 0 gic 0 121 0;
+ interrupt-map = 0 gic 0 57 0,
+ 1 gic 0 69 0,
+ 2 combiner 12 6,
+ 3 combiner 12 7,
+ 4 gic 0 42 0,
+ 5 gic 0 48 0;
};
};
+
+Example 3: In this example, the IP contains four local timers, but using
+ a per-processor interrupt to handle them. Either all the local
+ timer interrupts can be specified, with the same interrupt specifier
+ value or just the first one.
+
+ mct@1005 {
+ compatible = samsung,exynos4412-mct;
+ reg = 0x1005 0x800;
+
+ /* Both ways are possible in this case. Either: */
+ interrupts = 0 57 0, 0 69 0, 0 70 0, 0 71 0,
+0 42 0;
+ /* or: */
+ interrupts = 0 57 0, 0 69 0, 0 70 0, 0 71 0,
+0 42 0, 0 42 0, 0 42 0, 0 42 0;
+ };
--
1.8.3.2
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[PATCH] gpio: samsung: Drop support for Exynos SoCs
GPIO support on Exynos SoCs is provided by pinctrl-samsung driver,
leaving all the support code in gpio-samsung driver unused. This dead
code can be safely removed and so it is done by this patch.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpio/gpio-samsung.c | 871
1 file changed, 871 deletions(-)
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index a1392f4..358a21c 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -161,28 +161,6 @@ int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip
*chip,
return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
}
-static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
- unsigned int off, samsung_gpio_pull_t pull)
-{
- if (pull == S3C_GPIO_PULL_UP)
- pull = 3;
-
- return samsung_gpio_setpull_updown(chip, off, pull);
-}
-
-static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
- unsigned int off)
-{
- samsung_gpio_pull_t pull;
-
- pull = samsung_gpio_getpull_updown(chip, off);
-
- if (pull == 3)
- pull = S3C_GPIO_PULL_UP;
-
- return pull;
-}
-
/*
* samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
* @chip: The gpio chip that is being configured.
@@ -444,15 +422,6 @@ static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
};
#endif
-#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_SOC_EXYNOS5250)
-static struct samsung_gpio_cfg exynos_gpio_cfg = {
- .set_pull = exynos_gpio_setpull,
- .get_pull = exynos_gpio_getpull,
- .set_config = samsung_gpio_setcfg_4bit,
- .get_config = samsung_gpio_getcfg_4bit,
-};
-#endif
-
#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
.cfg_eint = 0x3,
@@ -495,15 +464,6 @@ static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
.set_config = samsung_gpio_setcfg_2bit,
.get_config = samsung_gpio_getcfg_2bit,
},
- [8] = {
- .set_pull = exynos_gpio_setpull,
- .get_pull = exynos_gpio_getpull,
- },
- [9] = {
- .cfg_eint = 0x3,
- .set_pull = exynos_gpio_setpull,
- .get_pull = exynos_gpio_getpull,
- }
};
/*
@@ -2115,833 +2075,6 @@ static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
#endif
};
-/*
- * Followings are the gpio banks in EXYNOS SoCs
- *
- * The 'config' member when left to NULL, is initialized to the default
- * structure exynos_gpio_cfg in the init function below.
- *
- * The 'base' member is also initialized in the init function below.
- * Note: The initialization of 'base' member of samsung_gpio_chip structure
- * uses the above macro and depends on the banks being listed in order here.
- */
-
-#ifdef CONFIG_ARCH_EXYNOS4
-static struct samsung_gpio_chip exynos4_gpios_1[] = {
- {
- .chip = {
- .base = EXYNOS4_GPA0(0),
- .ngpio = EXYNOS4_GPIO_A0_NR,
- .label = GPA0,
- },
- }, {
- .chip = {
- .base = EXYNOS4_GPA1(0),
- .ngpio = EXYNOS4_GPIO_A1_NR,
- .label = GPA1,
- },
- }, {
- .chip = {
- .base = EXYNOS4_GPB(0),
- .ngpio = EXYNOS4_GPIO_B_NR,
- .label = GPB,
- },
- }, {
- .chip = {
- .base = EXYNOS4_GPC0(0),
- .ngpio = EXYNOS4_GPIO_C0_NR,
- .label = GPC0,
- },
- }, {
- .chip = {
- .base = EXYNOS4_GPC1(0),
- .ngpio = EXYNOS4_GPIO_C1_NR,
- .label = GPC1,
- },
- }, {
- .chip = {
- .base = EXYNOS4_GPD0(0),
- .ngpio = EXYNOS4_GPIO_D0_NR,
- .label = GPD0,
- },
- }, {
- .chip = {
- .base = EXYNOS4_GPD1(0),
- .ngpio = EXYNOS4_GPIO_D1_NR,
- .label = GPD1,
- },
- }, {
- .chip = {
- .base = EXYNOS4_GPE0(0),
- .ngpio = EXYNOS4_GPIO_E0_NR,
- .label = GPE0,
- },
- }, {
- .chip = {
- .base = EXYNOS4_GPE1(0),
- .ngpio = EXYNOS4_GPIO_E1_NR,
-
Re: [RFC] cleanup mach-s5p*
On Monday 26 August 2013 13:54:59 Marek Szyprowski wrote: Hi Kukjin, On 8/26/2013 2:52 AM, Kukjin Kim wrote: Hi all, I have a plan to remove supporting following SoCs in mainline in the near future. - s5pc100 - smdkc100 - s5pv210(s5c110) - aquial, goni, smdkc110, smdkv210, torbreck - s5p64x0(s5p6440, s5p6450)- smdk6440, smdk6450 I think users don't seem to use that any more with mainline. If so, we are able to consider, it is not right now though. How do you think? I am against removing support for S5PC110/S5PV210. We still use it for some of our internal development. DT support patches will be posted soon (pinctrl and clocks). Support for S5PC100 can be easily added the same way (we also have DT patches almost ready). S5PV210, S5PC100 and the older S3C64xx can all be handled by the same Samsung-DT 'machine file'. However we don't have any s5p64x0 based boards to develop DT support for them. I agree regarding s5pv210 -- there are multiple real boards supported besides the smdk development boards, so it would be a regression to lose those. For s5pc100 and s5p64x0, the kernel currently only supports the smdk board, which is not meant for production use as far as I know, so I would not be too sad to see them gone. I guess converting them to DT would however make it possible to use other boards without changes in the kernel, which does sound useful if other boards exist. Marek, can you give some insight into what hardware you are using? Do you in fact use the smdkc100 or are you interested in adding support for other boards? Speaking in more general terms, the rule we usually apply is that any hardware that people are still interested in using stays supported in mainline, but if the current maintainer isn't interested in dealing with them any more, it's up to whoever wants to keep them alive to ensure they don't hold up progress in other areas. Arnd -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFC 3/5] ARM: samsung: add clock setup for FIMC and FIMD
(dropping linux-doc mailing list from Cc) On 08/26/2013 06:19 PM, Bartlomiej Zolnierkiewicz wrote: On Monday, August 26, 2013 01:38:32 PM Mateusz Krawczuk wrote: This patch adds code that sets correct parents and rates for clocks used by FIMC and FIMD on Goni board. This patch is supposed to be a workaround to make the display and camera subsystem working even without properly configured parent clocks in the boot-loader, right ? And as such it doesn't really belong to this series and has been written primarily for the clocks testing purposes ? I think it can be dropped in the next iteration of this series. -- Thanks, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/5] [media] exynos-mscl: Add new driver for M-Scaler
On 08/19/2013 12:58 PM, Shaik Ameer Basha wrote:
This patch adds support for M-Scaler (M2M Scaler) device which is a
new device for scaling, blending, color fill and color space
conversion on EXYNOS5 SoCs.
This device supports the followings as key feature.
input image format
- YCbCr420 2P(UV/VU), 3P
- YCbCr422 1P(YUYV/UYVY/YVYU), 2P(UV,VU), 3P
- YCbCr444 2P(UV,VU), 3P
- RGB565, ARGB1555, ARGB, ARGB, RGBA
- Pre-multiplexed ARGB, L8A8 and L8
output image format
- YCbCr420 2P(UV/VU), 3P
- YCbCr422 1P(YUYV/UYVY/YVYU), 2P(UV,VU), 3P
- YCbCr444 2P(UV,VU), 3P
- RGB565, ARGB1555, ARGB, ARGB, RGBA
- Pre-multiplexed ARGB
input rotation
- 0/90/180/270 degree, X/Y/XY Flip
scale ratio
- 1/4 scale down to 16 scale up
color space conversion
- RGB to YUV / YUV to RGB
Size
- Input : 16x16 to 8192x8192
- Output: 4x4 to 8192x8192
alpha blending, color fill
We don't have good support for alpha blending in v4l2. For example, the
s5p-g2d v4l2 driver only supports a subset of features of the device.
The G2D IP is probably better utilized through the exynos drm driver.
It might be a matter of designing proper controls though for such devices
that generate image by blending data from the output and capture buffers.
Signed-off-by: Shaik Ameer Bashashaik.am...@samsung.com
---
drivers/media/platform/exynos-mscl/mscl-regs.c | 318
drivers/media/platform/exynos-mscl/mscl-regs.h | 282 +
Shouldn't we call this driver exynos5-scaler and this files would be
renamed to drivers/media/platform/exynos5-scaler/scaler-regs.[ch].
Or maybe put maybe put the SCALER, G-SCALER drivers into common exynos5-is
directory ? I don't have strong preference. But we planned gscaler to be
moved into the exynos5-is directory.
2 files changed, 600 insertions(+)
create mode 100644 drivers/media/platform/exynos-mscl/mscl-regs.c
create mode 100644 drivers/media/platform/exynos-mscl/mscl-regs.h
diff --git a/drivers/media/platform/exynos-mscl/mscl-regs.c
b/drivers/media/platform/exynos-mscl/mscl-regs.c
new file mode 100644
index 000..9354afc
--- /dev/null
+++ b/drivers/media/platform/exynos-mscl/mscl-regs.c
@@ -0,0 +1,318 @@
+/*
+ * Copyright (c) 2013 - 2014 Samsung Electronics Co., Ltd.
Just make it 2013 ? I think we can manage to merge this diver this year :)
+ * http://www.samsung.com
+ *
+ * Samsung EXYNOS5 SoC series M-Scaler driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation, either version 2 of the License,
+ * or (at your option) any later version.
Are you sure you want to have this or (at your option) any later version
clause ?
+ */
+
+#includelinux/delay.h
+#includelinux/platform_device.h
+
+#include mscl-core.h
How about defining register access helpers like:
u32 mscl_read(struct mscl_dev *dev, u32 offset)
{
readl(dev-regs + offset);
}
void mscl_write(struct mscl_dev *dev, u32 offset, u32 value)
{
writel(value, dev-regs + offset);
}
perhaps as static inline in mscl-regs.h ?
+void mscl_hw_set_sw_reset(struct mscl_dev *dev)
+{
+ u32 cfg;
+
+ cfg = readl(dev-regs + MSCL_CFG);
+ cfg |= MSCL_CFG_SOFT_RESET;
+
+ writel(cfg, dev-regs + MSCL_CFG);
+}
+
+int mscl_wait_reset(struct mscl_dev *dev)
+{
+ unsigned long end = jiffies + msecs_to_jiffies(50);
Don't you want a #define for this timeout ?
+ u32 cfg, reset_done = 0;
+
+ while (time_before(jiffies, end)) {
+ cfg = readl(dev-regs + MSCL_CFG);
+ if (!(cfg MSCL_CFG_SOFT_RESET)) {
+ reset_done = 1;
+ break;
+ }
+ usleep_range(10, 20);
+ }
+
+ /* write any value to r/w reg and read it back */
+ while (reset_done) {
+
+ /* [TBD] need to define number of tries before returning
+* -EBUSY to the caller
+*/
CodingStyle: wrong multi-line comment style
+ writel(MSCL_CFG_SOFT_RESET_CHECK_VAL,
+ dev-regs + MSCL_CFG_SOFT_RESET_CHECK_REG);
+ if (MSCL_CFG_SOFT_RESET_CHECK_VAL ==
+ readl(dev-regs + MSCL_CFG_SOFT_RESET_CHECK_REG))
+ return 0;
+ }
+
+ return -EBUSY;
+}
+
+void mscl_hw_set_irq_mask(struct mscl_dev *dev, int interrupt, bool mask)
+{
+ u32 cfg;
+
+ switch (interrupt) {
+ case MSCL_INT_TIMEOUT:
+ case MSCL_INT_ILLEGAL_BLEND:
+ case MSCL_INT_ILLEGAL_RATIO:
+ case MSCL_INT_ILLEGAL_DST_HEIGHT:
+ case MSCL_INT_ILLEGAL_DST_WIDTH:
+ case MSCL_INT_ILLEGAL_DST_V_POS:
+ case
Re: [PATCH] clocksource: exynos_mct: Set IRQ affinity when the CPU goes online
On 08/26, Tomasz Figa wrote: Some variants of Exynos MCT, namely exynos4210-mct at the moment, use normal, shared interrupts for local timers. This means that each interrupt must have correct affinity set to fire only on CPU corresponding to given local timer. However after recent conversion of clocksource drivers to not use the local timer API for local timer initialization any more, the point of time when local timers get initialized changed and irq_set_affinity() fails because the CPU is not marked as online yet. This patch fixes this by moving the call to irq_set_affinity() to CPU_ONLINE notification, so the affinity is being set when the CPU goes online. This fixes a problem with Exynos4210 failing to boot, present since commit ee98d27df6 ARM: EXYNOS4: Divorce mct from local timer API due to failing irq_set_affinity(). Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- Looks good to me if you want to go this route. Acked-by: Stephen Boyd sb...@codeaurora.org -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] clocksource: exynos_mct: Set IRQ affinity when the CPU goes online
On Monday 26 of August 2013 16:09:41 Stephen Boyd wrote: On 08/26, Tomasz Figa wrote: Some variants of Exynos MCT, namely exynos4210-mct at the moment, use normal, shared interrupts for local timers. This means that each interrupt must have correct affinity set to fire only on CPU corresponding to given local timer. However after recent conversion of clocksource drivers to not use the local timer API for local timer initialization any more, the point of time when local timers get initialized changed and irq_set_affinity() fails because the CPU is not marked as online yet. This patch fixes this by moving the call to irq_set_affinity() to CPU_ONLINE notification, so the affinity is being set when the CPU goes online. This fixes a problem with Exynos4210 failing to boot, present since commit ee98d27df6 ARM: EXYNOS4: Divorce mct from local timer API due to failing irq_set_affinity(). Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- Looks good to me if you want to go this route. Acked-by: Stephen Boyd sb...@codeaurora.org Thanks. After some testing this seems to work fine and I don't see any reason how the timer could be programmed to fire an interrupt before the CPU goes online, so it should be fine. Anyway, we want this to be fixed for 3.12 for sure and since I don't really see any better solution we should take this one. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 4/6] ARM: dts: add dt nodes for exynos5420 hdmi subsystem
Hi Rahul,
On Monday 26 of August 2013 15:08:19 Rahul Sharma wrote:
Add hdmi, mixer, ddc device tree nodes for Exynos 5420 SoC.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 15 +++
arch/arm/boot/dts/exynos5420.dtsi | 19 +++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts index bafba25..140565f
100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -61,4 +61,19 @@
};
};
+ hdmi@1453 {
+ status = okay;
+ hpd-gpio = gpx3 7 0;
+ };
+
+ i2c_2: i2c@12C8 {
+ samsung,i2c-sda-delay = 100;
+ samsung,i2c-max-bus-freq = 66000;
+ status = okay;
+
+ hdmiddc@50 {
+ compatible = samsung,exynos4210-hdmiddc;
+ reg = 0x50;
+ };
+ };
};
As I mentioned in my reply for previous version of this patch, changes
done to this board dts file should be moved to next patch instead and its
subject appropriately modified.
Best regards,
Tomasz
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Re: [PATCH v5 6/6] of/documentation: update with clock information for exynos hdmi subsystem
Hi Rahul,
On Monday 26 of August 2013 15:08:21 Rahul Sharma wrote:
Adding information about clocks to the binding documentation
for exynos mixer and hdmi.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
Documentation/devicetree/bindings/video/exynos_hdmi.txt | 14
+- Documentation/devicetree/bindings/video/exynos_mixer.txt
|4 2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt index
323983b..94aaa7d 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -12,7 +12,19 @@ Required properties:
a) phandle of the gpio controller node.
b) pin number within the gpio controller.
c) optional flags and pull up/down.
-
+- clocks: list of clock IDs from SoC clock driver.
+ a) hdmi: It is required for gate operation on aclk_200_disp1 clock
+ which clocks the display1 block.
Isn't aclk_200_disp1 a name specific to Exynos5 SoCs? AFAIK this binding
is also used for other SoCs, including Exynos4 and probably S5PV210, so it
should be written to either be SoC-agnostic or account for all supported
SoCs. What about following descriptions:
Gate of HDMI IP block bus clock.
+ b) sclk_hdmi: It is required for gate operation on sclk_hdmi clock
+ which clocks hdmi IP.
Gate of HDMI special clock.
+ c) sclk_pixel: Parent for mux mout_hdmi.
Pixel special clock, one of two possible inputs of HDMI clock mux.
+ d) sclk_hdmiphy: Parent for mux mout_hdmi.
HDMI PHY clock output, one of two possible inputs of HDMI clock mux.
+ e) mout_hdmi: It is required by the driver to switch between the 2
+ parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is
stable
+ after configuration, parent is set to sclk_hdmiphy else
+ sclk_pixel.
HDMI clock mux, used to select between clock generated by HDMI PHY and
alternative clock source that can be used until HDMI PHY is set up.
+- clock-names: aliases as per driver requirements for above clock IDs:
+ hdmi, sclk_hdmi, sclk_pixel, sclk_hdmiphy and mout_hdmi.
Example:
hdmi {
diff --git a/Documentation/devicetree/bindings/video/exynos_mixer.txt
b/Documentation/devicetree/bindings/video/exynos_mixer.txt index
3334b0a..94b40b6 100644
--- a/Documentation/devicetree/bindings/video/exynos_mixer.txt
+++ b/Documentation/devicetree/bindings/video/exynos_mixer.txt
@@ -10,6 +10,10 @@ Required properties:
- reg: physical base address of the mixer and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
+- clocks: list of clock IDs from SoC clock driver.
+ a) mixer: It is required for gate operation on aclk_200_disp1
clock
Gate of Mixer IP bus clock.
+ which clocks the display1 block.
+ b) sclk_hdmi: Parent for mux mout_mixer.
I'm not sure why this clock is needed here. Could you explain what role it
plays in functioning of the Mixer IP?
Best regards,
Tomasz
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Re: [PATCH v5 0/6] ARM: dts: add support for exynos hdmi subsystem
Hi Rahul, On Monday 26 of August 2013 15:08:15 Rahul Sharma wrote: It adds Device tree nodes and clocks information for HDMI subsystem for exynos5420 and exynos5250 SoCs. It adds pinctrl node for hdmi hpd gpio and update binding documents. This set is based on kukjin's for-next branch at http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git. v5: 1) Merged Clock addition patch to DT nmde addition patch. 2) Add dout_pixel clock for hdmi in place of sclk_pixel. 3) Enable mixer node in soc dtsi file. v4: 1) Remove the movement of common properties to Exynos5.dtsi for I2C and hdmi subsystem. 2) Change the title of the patches. v3: 1) Rebase to kgene for-next based on 3.11-rc1. 2) Changes clock numbers as per updated clocks file for exyno5250 and exynos5420. 3) Dropped Sachin patch as already got merged. v2: 1) Added patch for moving common i2c properties to exynos5.dtsi 2) Added patch for moving common hdmi, mixer properties to exynos5.dtsi 3) moved hpd pinctrl node to board file. 4) Added Sachin's patch to update binding document for hdmi with hpd information. Andrew Bresticker (1): ARM: dts: add i2c device nodes for Exynos5420 Rahul Sharma (4): ARM: dts: add clocks to hdmi dt node for exynos5250 ARM: dts: add dt nodes for hdmi subsystem for exynos5420 ARM: dts: add hdmi hpd gpio pinctrl node for exynos5420 of/documentation: update with clock information for exynos hdmi subsystem Sean Paul (1): ARM: dts: add mixer clocks to mixer node for Exynos5250 .../devicetree/bindings/video/exynos_hdmi.txt | 14 +++- .../devicetree/bindings/video/exynos_mixer.txt |4 ++ arch/arm/boot/dts/exynos5250.dtsi |8 ++- arch/arm/boot/dts/exynos5420-smdk5420.dts | 26 +++ arch/arm/boot/dts/exynos5420.dtsi | 75 5 files changed, 123 insertions(+), 4 deletions(-) Except patches 4-6, which I have commented on, for the series: Reviewed-by: Tomasz Figa t.f...@samsung.com Also one minor comment: It would be better if you updated the documentation as first patch. This would make all the following patches to be based on already existing documentation. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 4/5] clk/exynos5420: add hdmi mux to change parents in hdmi driver
Hi Rahul, On Monday 26 of August 2013 14:43:02 Rahul Sharma wrote: hdmi driver needs to change the parent of hdmi clock to pixel clock or hdmiphy clock, based on the stability of hdmiphy. This patch is exposing the mux for changing the parent. Signed-off-by: Rahul Sharma rahul.sha...@samsung.com --- Documentation/devicetree/bindings/clock/exynos5420-clock.txt |5 + drivers/clk/samsung/clk-exynos5420.c | 5 - 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index 5758a69..6f16aa8 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -182,6 +182,11 @@ clock which they consume. g3d501 smmu_mixer 502 + MuxID + + + mout_hdmi 1024 Is there a need for such big hole between smm_mixer and this clock? I believe that based on the documentation, the total amount of clocks that can be defined may be approximated and some extra margin added, so you don't waste so much of numbering space and memory used for lookup array. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 5/5] clk/exynos5420: assign dout_pixel id to pixel clock divider
Hi Rahul, On Monday 26 of August 2013 14:43:03 Rahul Sharma wrote: dout_pixel is a new ID allocated for pixel clock divider. It is queried in the driver to pass as the parent to hdmi clock while switching between parents. Signed-off-by: Rahul Sharma rahul.sha...@samsung.com --- Documentation/devicetree/bindings/clock/exynos5420-clock.txt |5 + drivers/clk/samsung/clk-exynos5420.c | 5 - 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index 6f16aa8..4c069bd 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -187,6 +187,11 @@ clock which they consume. mout_hdmi 1024 + DividerID + + + dout_pixel 2048 That's an even bigger hole. Could you check in the documentation how many muxes are present in the clock controller of Exynos5420, add some margin (presumably rounding up to some nice value, not necessarily to a power of two) and calculate a more reasonable start value for dividers? Best regards, Tomasz' -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC] cleanup mach-s5p*
Hi Kukjin,
On Monday 26 of August 2013 09:52:47 Kukjin Kim wrote:
Hi all,
I have a plan to remove supporting following SoCs in mainline in the
near future.
- s5pc100 - smdkc100
We already have this almost moved to device tree. A common clock framework
and pin control drivers should be posted soon. Supporting this platform
should be reasonably easy, as it has a lot in common with other SoCs like
S3C64xx and S5PV210.
- s5pv210(s5c110) - aquial, goni, smdkc110, smdkv210, torbreck
We already have support for device tree for this in our internal tree.
Some RFC patches have been already posted by Mateusz Krawczuk. We intend
to mostly support Aquila and Goni as they are the platforms we are still
using for our work.
I also have plans to add support for FriendlyARM's {Mini,Tiny}210 board
series, which would just translate to adding appropriate board dts files.
It's also worth noting that S5PV210 (FriendlyARM's board specifically) is
being supported by Pengutronix in their Barebox bootloader [1][2].
I'd be all for completely dropping legacy board files of this platform and
others mentioned in this thread, though.
- s5p64x0(s5p6440, s5p6450)- smdk6440, smdk6450
I haven't seen any hardware on this platform myself. As Marek said, we
don't have any boards to test mainline support on it and I'm not aware of
any interested users. This is probably the primary candidate to be
dropped.
My personal addition to the above list would be:
- unused boards based on s3c64xx
I'm yet to investigate which ones are virtually dead today. The active
ones that I would want to be kept are Cragganmore, Mini6410 and both SMDK
boards. They are going to be moved to DT, though. AFAIK mach-ncp could be
safely dropped, as from what I know, it isn't used anymore.
I think users don't seem to use that any more with mainline. If so, we
are able to consider, it is not right now though.
How do you think?
Well, if we could drop legacy board file support for them and keep them as
DT only, support for them could be reasonably simple. Basically the code
in arch/arm would be limited to a single .c file per SoC (e.g. mach-
s5pv210-dt.c), a bunch of SoC-level .dtsi files and a bunch of board dts
files.
IMHO the best thing we could do would be creating a single mach-samsung,
where all the DT-only platforms could be located, including Exynos after
some remaining consolidation.
Best regards,
Tomasz
[1]
http://barebox.org/index.html
[2]
http://git.pengutronix.de/?p=barebox.git;a=tree;f=arch/arm/boards/friendlyarm-tiny210;h=ee3306d5e6770b8e6568fb58e9e1824cfe59fbce;hb=HEAD
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[patch] pinctrl: s3c24xx: off by one in s3c24xx_eint_init()
If irq == NUM_EINT then it writes one space beyond the end of the
eint_data-domains[] array.
Signed-off-by: Dan Carpenter dan.carpen...@oracle.com
diff --git a/drivers/pinctrl/pinctrl-s3c24xx.c
b/drivers/pinctrl/pinctrl-s3c24xx.c
index 24446da..ad3eaad 100644
--- a/drivers/pinctrl/pinctrl-s3c24xx.c
+++ b/drivers/pinctrl/pinctrl-s3c24xx.c
@@ -549,7 +549,7 @@ static int s3c24xx_eint_init(struct
samsung_pinctrl_drv_data *d)
irq = bank-eint_offset;
mask = bank-eint_mask;
for (pin = 0; mask; ++pin, mask = 1) {
- if (irq NUM_EINT)
+ if (irq = NUM_EINT)
break;
if (!(mask 1))
continue;
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Re: [RFC V2 1/4] mmc: dw_mmc: exynos: move the exynos private init
Dear Yuvaraj,
On 08/26/2013 06:20 PM, Yuvaraj Kumar wrote:
On Fri, Aug 23, 2013 at 7:14 PM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi Yuvaraj,
On 08/23/2013 08:15 PM, Yuvaraj Kumar C D wrote:
Currently platform specific private data initialisation is done by
dw_mci_exynos_priv_init and dw_mci_exynos_parse_dt.As we already have
separate platform specific device tree parser dw_mci_exynos_parse_dt,
move the dw_mci_exynos_priv_init code to dw_mci_exynos_parse_dt.
We can use the dw_mci_exynos_priv_init to do some actual platform
specific initialisation of SMU and etc.
changes since V1: none
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
drivers/mmc/host/dw_mmc-exynos.c | 31 +++
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c
b/drivers/mmc/host/dw_mmc-exynos.c
index 9990f98..19c845b 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -72,22 +72,8 @@ static struct dw_mci_exynos_compatible {
static int dw_mci_exynos_priv_init(struct dw_mci *host)
{
- struct dw_mci_exynos_priv_data *priv;
- int idx;
-
- priv = devm_kzalloc(host-dev, sizeof(*priv), GFP_KERNEL);
- if (!priv) {
- dev_err(host-dev, mem alloc failed for private data\n);
- return -ENOMEM;
- }
-
- for (idx = 0; idx ARRAY_SIZE(exynos_compat); idx++) {
- if (of_device_is_compatible(host-dev-of_node,
- exynos_compat[idx].compatible))
- priv-ctrl_type = exynos_compat[idx].ctrl_type;
- }
+ struct dw_mci_exynos_priv_data *priv = host-priv;
- host-priv = priv;
return 0;
}
@@ -177,12 +163,24 @@ static void dw_mci_exynos_set_ios(struct dw_mci
*host, struct mmc_ios *ios)
static int dw_mci_exynos_parse_dt(struct dw_mci *host)
{
- struct dw_mci_exynos_priv_data *priv = host-priv;
+ struct dw_mci_exynos_priv_data *priv;
struct device_node *np = host-dev-of_node;
u32 timing[2];
u32 div = 0;
+ int idx;
int ret;
+ priv = devm_kzalloc(host-dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ dev_err(host-dev, mem alloc failed for private data\n);
+ return -ENOMEM;
+ }
+
+ for (idx = 0; idx ARRAY_SIZE(exynos_compat); idx++) {
+ if (of_device_is_compatible(np,
exynos_compat[idx].compatible))
+ priv-ctrl_type = exynos_compat[idx].ctrl_type;
+ }
+
of_property_read_u32(np, samsung,dw-mshc-ciu-div, div);
priv-ciu_div = div;
@@ -199,6 +197,7 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
return ret;
priv-ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
+ host-priv = priv;
I'm not sure whether my thinking is right or not.
if host-pdata is present, then dw_mci_parse_dt() didn't called at
dw_mci_probe.
Yes, you are right.
then how host-priv set to priv?
Earlier host-priv set to priv in both non-DT and DT case.True, with
this patch it does it only in DT case.
Is there any platform/board which still uses dw_mmc and its platform
extension driver with non DT case?
You're right. i didn't see the extension driver with non DT-case?
Then we can also modify the host-pdata into dw_mci_probe().
Best Regards,
Jaehoon Chung
I found a reference of non-DT case where host-pdata is present in
dw_mmc-pci.c driver but does not
use platform extension driver (exynos/socfpga).
Best Regards,
Jaehoon Chung
return 0;
}
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RE: [PATCH 0/3] drm/exynos: fimd: get signal polarities from device tree
-Original Message- From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-soc- ow...@vger.kernel.org] On Behalf Of Andrzej Hajda Sent: Wednesday, August 21, 2013 11:22 PM To: open list:DRM DRIVERS FOR E... Cc: Andrzej Hajda; Inki Dae; Joonyoung Shim; Seung-Woo Kim; Kyungmin Park; David Airlie; moderated list:ARM/S5P EXYNOS AR...; t.f...@samsung.com; s.nawro...@samsung.com Subject: [PATCH 0/3] drm/exynos: fimd: get signal polarities from device tree Hi, This patch series adds signal polarities parsing from display-timings devicetree node. To do it efficiently struct fb_videomode is replaced with struct videomode and some additional code cleaning is performed. Good patch set. Applied. Thanks, Inki Dae The patches are for drm-exynos/exynos-drm-next branch. Regards Andrzej Hajda Andrzej Hajda (3): drm/exynos: fimd: replace struct fb_videomode with videomode drm/exynos: fimd: get signal polarities from device tree drm/exynos: fimd: move platform data parsing to separate function drivers/gpu/drm/exynos/exynos_drm_connector.c | 33 + drivers/gpu/drm/exynos/exynos_drm_fimd.c | 189 +- include/drm/exynos_drm.h | 3 +- 3 files changed, 103 insertions(+), 122 deletions(-) -- 1.8.1.2 -- To unsubscribe from this list: send the line unsubscribe linux-samsung- soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] drm/exynos: Add fallback option to get non physically contiguous memory for gem_dumb_create
Thanks.
On 27 August 2013 08:14, Inki Dae inki@samsung.com wrote:
Applied.
Thanks,
Inki Dae
-Original Message-
From: Vikas Sajjan [mailto:vikas.saj...@linaro.org]
Sent: Friday, August 23, 2013 3:35 PM
To: dri-de...@lists.freedesktop.org; inki@samsung.com
Cc: kgene@samsung.com; s.nawro...@samsung.com; robdcl...@gmail.com;
tomasz.f...@gmail.com; laurent.pinch...@ideasonboard.com;
patc...@linaro.org; linaro-...@lists.linaro.org
Subject: [PATCH] drm/exynos: Add fallback option to get non physically
contiguous memory for gem_dumb_create
To address the case where physically contiguous memory MAY NOT be a
mandatory
requirement for framebuffer for the application calling
exynos_drm_gem_dumb_create,
the patch adds a feature to get non physically contiguous memory for
framebuffer,
if physically contiguous memory allocation fails and if IOMMU is
supported.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
Signed-off-by: Arun Kumar arun...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_gem.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c
b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index 2eabe1a..66d1b40 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -17,6 +17,7 @@
#include exynos_drm_drv.h
#include exynos_drm_gem.h
#include exynos_drm_buf.h
+#include exynos_drm_iommu.h
static unsigned int convert_to_vm_err_msg(int msg)
{
@@ -666,6 +667,18 @@ int exynos_drm_gem_dumb_create(struct drm_file
*file_priv,
exynos_gem_obj = exynos_drm_gem_create(dev, EXYNOS_BO_CONTIG |
EXYNOS_BO_WC, args-size);
+ /*
+ * If physically contiguous memory allocation fails and if IOMMU is
+ * supported then try to get buffer from non physically contiguous
+ * memory area.
+ */
+ if (IS_ERR(exynos_gem_obj) is_drm_iommu_supported(dev)) {
+ dev_warn(dev-dev, contiguous FB allocation failed, falling
back to non-contiguous\n);
+ exynos_gem_obj = exynos_drm_gem_create(dev,
+ EXYNOS_BO_NONCONTIG | EXYNOS_BO_WC,
+ args-size);
+ }
+
if (IS_ERR(exynos_gem_obj))
return PTR_ERR(exynos_gem_obj);
--
1.7.9.5
--
Thanks and Regards
Vikas Sajjan
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Re: [PATCH RFC 3/5] ARM: samsung: add clock setup for FIMC and FIMD
On Tuesday, August 27, 2013 3:38 AM, Sylwester Nawrocki wrote: On 08/26/2013 06:19 PM, Bartlomiej Zolnierkiewicz wrote: On Monday, August 26, 2013 01:38:32 PM Mateusz Krawczuk wrote: This patch adds code that sets correct parents and rates for clocks used by FIMC and FIMD on Goni board. This patch is supposed to be a workaround to make the display and camera subsystem working even without properly configured parent clocks in the boot-loader, right ? And as such it doesn't really belong to this series and has been written primarily for the clocks testing purposes ? I think it can be dropped in the next iteration of this series. Agreed. :-) This patch can be dropped next. Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 4/6] ARM: dts: add dt nodes for exynos5420 hdmi subsystem
On 27 August 2013 04:59, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Rahul,
On Monday 26 of August 2013 15:08:19 Rahul Sharma wrote:
Add hdmi, mixer, ddc device tree nodes for Exynos 5420 SoC.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 15 +++
arch/arm/boot/dts/exynos5420.dtsi | 19 +++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts index bafba25..140565f
100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -61,4 +61,19 @@
};
};
+ hdmi@1453 {
+ status = okay;
+ hpd-gpio = gpx3 7 0;
+ };
+
+ i2c_2: i2c@12C8 {
+ samsung,i2c-sda-delay = 100;
+ samsung,i2c-max-bus-freq = 66000;
+ status = okay;
+
+ hdmiddc@50 {
+ compatible = samsung,exynos4210-hdmiddc;
+ reg = 0x50;
+ };
+ };
};
As I mentioned in my reply for previous version of this patch, changes
done to this board dts file should be moved to next patch instead and its
subject appropriately modified.
Hi Tomasz,
Sorry. I missed that. I will move the hpd-gpio related change to patch 5.
I will spin off a new patch for Hdmi ddc related additions.
regards,
Rahul Sharma.
Best regards,
Tomasz
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Re: [GIT PULL 3/3] 2nd Round Samsung mach-exynos for v3.12
amit daniel kachhap amit.dan...@samsung.com writes:
Submitted the V2 version of this patch with your suggestion.
So will there be an updated branch (and pull request) with these changes?
Kevin
On Mon, Aug 26, 2013 at 4:49 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
On Monday, August 26, 2013 04:33:55 PM amit daniel kachhap wrote:
Hi,
On Mon, Aug 26, 2013 at 3:36 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
Hi,
On Monday, August 26, 2013 09:14:42 AM Kukjin Kim wrote:
The following changes since commit
ad81f0545ef01ea651886dddac4bef6cec930092:
Linux 3.11-rc1 (2013-07-14 15:18:27 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/samsung-mach-exynos
for you to fetch changes up to f52616f4233d71d0fb00f06f86d046d18d2b7f3b:
ARM: EXYNOS: always enable PM domains support for EXYNOS4X12
(2013-08-19
05:05:16 +0900)
update mach-exynos
- enable ARCH_HAS_BANDGAP for exynos SoCs
- skip C1 cpuidle for exynos5440 because non-supporting
- always enable PM domains for exynos4x12
Amit Daniel Kachhap (2):
ARM: EXYNOS: enable ARCH_HAS_BANDGAP
ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
The patch ARM: EXYNOS: Skip C1 cpuidle state for exynos5440:
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -210,7 +210,7 @@ static int __init exynos4_init_cpuidle(void)
device-cpu = cpu_id;
/* Support IDLE only */
- if (cpu_id != 0)
+ if (soc_is_exynos5440() || cpu_id != 0)
device-state_count = 1;
ret = cpuidle_register_device(device);
is incorrect as noted a month ago in:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/186355.html
[ Because of the deficiency in the core cpuidle core (device-state_count
not being used by governors' code) only sysfs entries for C1 state will
be
disabled and EXYNOS cpuidle driver will still attempt to use C1 state.
also non-working device-state_count is planned to be removed by:
http://permalink.gmane.org/gmane.linux.power-management.general/37390
I looked at your patch series and it seems reasonable. I will repost
this patch on top of yours.
If you correctly use driver's state_count (instead of device's) there will be
no dependency on my patch series and the new patch can be applied
immediately.
But I suggest to keep this patch temporary till your patch series gets
merged.
The current patch (the one Kukjin merged) is incorrect as it just doesn't
do what it advertises. I see no reason to keep it.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
Thanks,
Amit Daniel
To disable C1 state on EXYNOS5440 something like:
static int __init exynos4_init_cpuidle(void)
{
...
if (soc_is_exynos5440())
exynos4_idle_driver.state_count = 1;
...
}
should be done instead.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
___
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linux-arm-ker...@lists.infradead.org
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On Mon, Aug 26, 2013 at 3:36 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
Hi,
On Monday, August 26, 2013 09:14:42 AM Kukjin Kim wrote:
The following changes since commit
ad81f0545ef01ea651886dddac4bef6cec930092:
Linux 3.11-rc1 (2013-07-14 15:18:27 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/samsung-mach-exynos
for you to fetch changes up to f52616f4233d71d0fb00f06f86d046d18d2b7f3b:
ARM: EXYNOS: always enable PM domains support for EXYNOS4X12
(2013-08-19
05:05:16 +0900)
update mach-exynos
- enable ARCH_HAS_BANDGAP for exynos SoCs
- skip C1 cpuidle for exynos5440 because non-supporting
- always enable PM domains for exynos4x12
Amit Daniel Kachhap (2):
ARM: EXYNOS: enable ARCH_HAS_BANDGAP
ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
The patch ARM: EXYNOS: Skip C1 cpuidle state for exynos5440:
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -210,7 +210,7 @@ static int __init exynos4_init_cpuidle(void)
device-cpu = cpu_id;
/* Support IDLE only */
- if (cpu_id != 0)
+ if
RE: [PATCH] drm/exynos: Add fallback option to get non physically contiguous memory for gem_dumb_create
One more thing, changed the subject to Consider fallback option to
allocation fail. The subject is too long :)
Thanks,
Inki Dae
-Original Message-
From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-soc-
ow...@vger.kernel.org] On Behalf Of Vikas Sajjan
Sent: Tuesday, August 27, 2013 12:05 PM
To: Inki Dae
Cc: DRI mailing list; kgene.kim; Sylwester Nawrocki; Rob Clark; Tomasz
Figa; Laurent Pinchart; Patch Tracking; linaro-...@lists.linaro.org; sunil
joshi; linux-samsung-soc@vger.kernel.org
Subject: Re: [PATCH] drm/exynos: Add fallback option to get non physically
contiguous memory for gem_dumb_create
Thanks.
On 27 August 2013 08:14, Inki Dae inki@samsung.com wrote:
Applied.
Thanks,
Inki Dae
-Original Message-
From: Vikas Sajjan [mailto:vikas.saj...@linaro.org]
Sent: Friday, August 23, 2013 3:35 PM
To: dri-de...@lists.freedesktop.org; inki@samsung.com
Cc: kgene@samsung.com; s.nawro...@samsung.com; robdcl...@gmail.com;
tomasz.f...@gmail.com; laurent.pinch...@ideasonboard.com;
patc...@linaro.org; linaro-...@lists.linaro.org
Subject: [PATCH] drm/exynos: Add fallback option to get non physically
contiguous memory for gem_dumb_create
To address the case where physically contiguous memory MAY NOT be a
mandatory
requirement for framebuffer for the application calling
exynos_drm_gem_dumb_create,
the patch adds a feature to get non physically contiguous memory for
framebuffer,
if physically contiguous memory allocation fails and if IOMMU is
supported.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
Signed-off-by: Arun Kumar arun...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_gem.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c
b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index 2eabe1a..66d1b40 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -17,6 +17,7 @@
#include exynos_drm_drv.h
#include exynos_drm_gem.h
#include exynos_drm_buf.h
+#include exynos_drm_iommu.h
static unsigned int convert_to_vm_err_msg(int msg)
{
@@ -666,6 +667,18 @@ int exynos_drm_gem_dumb_create(struct drm_file
*file_priv,
exynos_gem_obj = exynos_drm_gem_create(dev, EXYNOS_BO_CONTIG |
EXYNOS_BO_WC,
args-size);
+ /*
+ * If physically contiguous memory allocation fails and if IOMMU
is
+ * supported then try to get buffer from non physically
contiguous
+ * memory area.
+ */
+ if (IS_ERR(exynos_gem_obj) is_drm_iommu_supported(dev)) {
+ dev_warn(dev-dev, contiguous FB allocation failed,
falling
back to non-contiguous\n);
+ exynos_gem_obj = exynos_drm_gem_create(dev,
+ EXYNOS_BO_NONCONTIG |
EXYNOS_BO_WC,
+ args-size);
+ }
+
if (IS_ERR(exynos_gem_obj))
return PTR_ERR(exynos_gem_obj);
--
1.7.9.5
--
Thanks and Regards
Vikas Sajjan
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Re: [PATCH] drm/exynos: Add fallback option to get non physically contiguous memory for gem_dumb_create
OK.
On 27 August 2013 09:44, Inki Dae inki@samsung.com wrote:
One more thing, changed the subject to Consider fallback option to
allocation fail. The subject is too long :)
Thanks,
Inki Dae
-Original Message-
From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-soc-
ow...@vger.kernel.org] On Behalf Of Vikas Sajjan
Sent: Tuesday, August 27, 2013 12:05 PM
To: Inki Dae
Cc: DRI mailing list; kgene.kim; Sylwester Nawrocki; Rob Clark; Tomasz
Figa; Laurent Pinchart; Patch Tracking; linaro-...@lists.linaro.org; sunil
joshi; linux-samsung-soc@vger.kernel.org
Subject: Re: [PATCH] drm/exynos: Add fallback option to get non physically
contiguous memory for gem_dumb_create
Thanks.
On 27 August 2013 08:14, Inki Dae inki@samsung.com wrote:
Applied.
Thanks,
Inki Dae
-Original Message-
From: Vikas Sajjan [mailto:vikas.saj...@linaro.org]
Sent: Friday, August 23, 2013 3:35 PM
To: dri-de...@lists.freedesktop.org; inki@samsung.com
Cc: kgene@samsung.com; s.nawro...@samsung.com; robdcl...@gmail.com;
tomasz.f...@gmail.com; laurent.pinch...@ideasonboard.com;
patc...@linaro.org; linaro-...@lists.linaro.org
Subject: [PATCH] drm/exynos: Add fallback option to get non physically
contiguous memory for gem_dumb_create
To address the case where physically contiguous memory MAY NOT be a
mandatory
requirement for framebuffer for the application calling
exynos_drm_gem_dumb_create,
the patch adds a feature to get non physically contiguous memory for
framebuffer,
if physically contiguous memory allocation fails and if IOMMU is
supported.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
Signed-off-by: Arun Kumar arun...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_gem.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c
b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index 2eabe1a..66d1b40 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -17,6 +17,7 @@
#include exynos_drm_drv.h
#include exynos_drm_gem.h
#include exynos_drm_buf.h
+#include exynos_drm_iommu.h
static unsigned int convert_to_vm_err_msg(int msg)
{
@@ -666,6 +667,18 @@ int exynos_drm_gem_dumb_create(struct drm_file
*file_priv,
exynos_gem_obj = exynos_drm_gem_create(dev, EXYNOS_BO_CONTIG |
EXYNOS_BO_WC,
args-size);
+ /*
+ * If physically contiguous memory allocation fails and if IOMMU
is
+ * supported then try to get buffer from non physically
contiguous
+ * memory area.
+ */
+ if (IS_ERR(exynos_gem_obj) is_drm_iommu_supported(dev)) {
+ dev_warn(dev-dev, contiguous FB allocation failed,
falling
back to non-contiguous\n);
+ exynos_gem_obj = exynos_drm_gem_create(dev,
+ EXYNOS_BO_NONCONTIG |
EXYNOS_BO_WC,
+ args-size);
+ }
+
if (IS_ERR(exynos_gem_obj))
return PTR_ERR(exynos_gem_obj);
--
1.7.9.5
--
Thanks and Regards
Vikas Sajjan
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Re: [PATCH v3 4/5] clk/exynos5420: add hdmi mux to change parents in hdmi driver
On 27 August 2013 05:16, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Rahul, On Monday 26 of August 2013 14:43:02 Rahul Sharma wrote: hdmi driver needs to change the parent of hdmi clock to pixel clock or hdmiphy clock, based on the stability of hdmiphy. This patch is exposing the mux for changing the parent. Signed-off-by: Rahul Sharma rahul.sha...@samsung.com --- Documentation/devicetree/bindings/clock/exynos5420-clock.txt |5 + drivers/clk/samsung/clk-exynos5420.c | 5 - 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index 5758a69..6f16aa8 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -182,6 +182,11 @@ clock which they consume. g3d501 smmu_mixer 502 + MuxID + + + mout_hdmi 1024 Is there a need for such big hole between smm_mixer and this clock? I believe that based on the documentation, the total amount of clocks that can be defined may be approximated and some extra margin added, so you don't waste so much of numbering space and memory used for lookup array. Total number of Gates are coming upto the enum value 540. I can leave gap of 64 in between for first mux. Similarly, total muxes in system are 118. Optimum gab would be between 128~150. What you say about these values? regards, Rahul Sharma. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 6/6] of/documentation: update with clock information for exynos hdmi subsystem
On 27 August 2013 05:10, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Rahul,
On Monday 26 of August 2013 15:08:21 Rahul Sharma wrote:
Adding information about clocks to the binding documentation
for exynos mixer and hdmi.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
Documentation/devicetree/bindings/video/exynos_hdmi.txt | 14
+- Documentation/devicetree/bindings/video/exynos_mixer.txt
|4 2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt index
323983b..94aaa7d 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -12,7 +12,19 @@ Required properties:
a) phandle of the gpio controller node.
b) pin number within the gpio controller.
c) optional flags and pull up/down.
-
+- clocks: list of clock IDs from SoC clock driver.
+ a) hdmi: It is required for gate operation on aclk_200_disp1 clock
+ which clocks the display1 block.
Isn't aclk_200_disp1 a name specific to Exynos5 SoCs? AFAIK this binding
is also used for other SoCs, including Exynos4 and probably S5PV210, so it
should be written to either be SoC-agnostic or account for all supported
SoCs. What about following descriptions:
Gate of HDMI IP block bus clock.
+ b) sclk_hdmi: It is required for gate operation on sclk_hdmi clock
+ which clocks hdmi IP.
Gate of HDMI special clock.
+ c) sclk_pixel: Parent for mux mout_hdmi.
Pixel special clock, one of two possible inputs of HDMI clock mux.
+ d) sclk_hdmiphy: Parent for mux mout_hdmi.
HDMI PHY clock output, one of two possible inputs of HDMI clock mux.
+ e) mout_hdmi: It is required by the driver to switch between the 2
+ parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is
stable
+ after configuration, parent is set to sclk_hdmiphy else
+ sclk_pixel.
HDMI clock mux, used to select between clock generated by HDMI PHY and
alternative clock source that can be used until HDMI PHY is set up.
+- clock-names: aliases as per driver requirements for above clock IDs:
+ hdmi, sclk_hdmi, sclk_pixel, sclk_hdmiphy and mout_hdmi.
Example:
hdmi {
diff --git a/Documentation/devicetree/bindings/video/exynos_mixer.txt
b/Documentation/devicetree/bindings/video/exynos_mixer.txt index
3334b0a..94b40b6 100644
--- a/Documentation/devicetree/bindings/video/exynos_mixer.txt
+++ b/Documentation/devicetree/bindings/video/exynos_mixer.txt
@@ -10,6 +10,10 @@ Required properties:
- reg: physical base address of the mixer and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
+- clocks: list of clock IDs from SoC clock driver.
+ a) mixer: It is required for gate operation on aclk_200_disp1
clock
Gate of Mixer IP bus clock.
+ which clocks the display1 block.
+ b) sclk_hdmi: Parent for mux mout_mixer.
I'm not sure why this clock is needed here. Could you explain what role it
plays in functioning of the Mixer IP?
I have done above rephrasing.
For exynos4 socs, sclk_mixer can have sclk_hdmi or sclk_dac as inputs.
mout_mixer
is configured to select sclk_hdmi. I am not sure that how sclk_mixer
is utilized inside
mixer hardware.
regards,
Rahul Sharma.
Best regards,
Tomasz
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Re: [PATCH v5 0/6] ARM: dts: add support for exynos hdmi subsystem
On 27 August 2013 05:12, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Rahul, On Monday 26 of August 2013 15:08:15 Rahul Sharma wrote: It adds Device tree nodes and clocks information for HDMI subsystem for exynos5420 and exynos5250 SoCs. It adds pinctrl node for hdmi hpd gpio and update binding documents. This set is based on kukjin's for-next branch at http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git. v5: 1) Merged Clock addition patch to DT nmde addition patch. 2) Add dout_pixel clock for hdmi in place of sclk_pixel. 3) Enable mixer node in soc dtsi file. v4: 1) Remove the movement of common properties to Exynos5.dtsi for I2C and hdmi subsystem. 2) Change the title of the patches. v3: 1) Rebase to kgene for-next based on 3.11-rc1. 2) Changes clock numbers as per updated clocks file for exyno5250 and exynos5420. 3) Dropped Sachin patch as already got merged. v2: 1) Added patch for moving common i2c properties to exynos5.dtsi 2) Added patch for moving common hdmi, mixer properties to exynos5.dtsi 3) moved hpd pinctrl node to board file. 4) Added Sachin's patch to update binding document for hdmi with hpd information. Andrew Bresticker (1): ARM: dts: add i2c device nodes for Exynos5420 Rahul Sharma (4): ARM: dts: add clocks to hdmi dt node for exynos5250 ARM: dts: add dt nodes for hdmi subsystem for exynos5420 ARM: dts: add hdmi hpd gpio pinctrl node for exynos5420 of/documentation: update with clock information for exynos hdmi subsystem Sean Paul (1): ARM: dts: add mixer clocks to mixer node for Exynos5250 .../devicetree/bindings/video/exynos_hdmi.txt | 14 +++- .../devicetree/bindings/video/exynos_mixer.txt |4 ++ arch/arm/boot/dts/exynos5250.dtsi |8 ++- arch/arm/boot/dts/exynos5420-smdk5420.dts | 26 +++ arch/arm/boot/dts/exynos5420.dtsi | 75 5 files changed, 123 insertions(+), 4 deletions(-) Except patches 4-6, which I have commented on, for the series: Reviewed-by: Tomasz Figa t.f...@samsung.com Also one minor comment: It would be better if you updated the documentation as first patch. This would make all the following patches to be based on already existing documentation. Done. I reordered them. regards, Rahul Sharma. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
