On pią, 2014-07-04 at 22:24 +0200, Javier Martinez Canillas wrote:
The MAX7802 PMIC has a Real-Time-Clock (RTC) with two alarms.
This patch adds support for the RTC and is based on a driver
added by Simon Glass to the Chrome OS kernel 3.8 tree.
Signed-off-by: Javier Martinez Canillas
On pią, 2014-07-04 at 22:24 +0200, Javier Martinez Canillas wrote:
The MAX77686 RTC chip has two features called SMPL (Sudden Momentary
Power Loss) and WTSR (Watchdog Timeout and Software Resets).
Support for these features seems to be implemented in the driver but
compilation is disabled
Hello Mark,
Thanks for the review.
On 2 July 2014 22:26, Mark Brown broo...@kernel.org wrote:
On Fri, Jun 13, 2014 at 09:29:50AM +0530, Naveen Krishna Chatradhi wrote:
Hence, spi-s3c64xx.c is broken since Jun 21 11:26:12 2013 and
considering the time with no compliants about the breakage.
Hello Krzysztof,
On 07/07/2014 08:06 AM, Krzysztof Kozlowski wrote:
On pią, 2014-07-04 at 22:24 +0200, Javier Martinez Canillas wrote:
The MAX7802 PMIC has a Real-Time-Clock (RTC) with two alarms.
This patch adds support for the RTC and is based on a driver
added by Simon Glass to the Chrome
Hi Jaehoon,
Please check one thing below.
On Mon, June 30, 2014, Jaehoon Chung wrote:
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
Hi, Seungwon.
I will fix it, and add dt-file related with exynos3250.
Best Regards,
Jaehoon Chung
On 07/07/2014 04:29 PM, Seungwon Jeon wrote:
Hi Jaehoon,
Please check one thing below.
On Mon, June 30, 2014, Jaehoon Chung wrote:
dw-mmc controller can support multiple slots.
But,
On Mon, Jul 07, 2014 at 11:51:38AM +0530, Naveen Krishna Ch wrote:
On 2 July 2014 22:26, Mark Brown broo...@kernel.org wrote:
On Fri, Jun 13, 2014 at 09:29:50AM +0530, Naveen Krishna Chatradhi wrote:
Hence, spi-s3c64xx.c is broken since Jun 21 11:26:12 2013 and
considering the time with no
Hello Mark,
On 7 July 2014 13:02, Mark Brown broo...@kernel.org wrote:
On Mon, Jul 07, 2014 at 11:51:38AM +0530, Naveen Krishna Ch wrote:
On 2 July 2014 22:26, Mark Brown broo...@kernel.org wrote:
On Fri, Jun 13, 2014 at 09:29:50AM +0530, Naveen Krishna Chatradhi wrote:
Hence,
Sorry for late review.
If you're in progress for next, please consider it.
On Mon, June 30, 2014, Jaehoon Chung wrote:
Replaced the disable-wp into host's quirks.
(Because the slot-node is removed at dt-file.)
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
This patch adds support for Exynos3250 SoC to Exynos2USB PHY driver.
Although Exynos3250 has only one device phy interface, the register
layout and all operations that are required to get it enabled are almost
same as on Exynos4x12. The only different is one more register
(REFCLKSEL) which need to
This patch adds device tree nodes required to enable support for USB
device controller.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
Changelog:
v2:
- removed phandle to syscon, because mode switch register is not needed for
3250.
---
arch/arm/boot/dts/exynos3250.dtsi | 21
Rebased on
1] Kukjin Kim's tree, for-next branch
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
2] Pankaj Dubey's v6 PMU patchset
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg33660.html
changes since v5:
- Refactored pm.c to use DT
From: Abhilash Kesavan a.kesa...@samsung.com
Add intial PMU settings for exynos5420. This is required for
future S2R and Switching support.
Signed-off-by: Thomas Abraham thomas...@samsung.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Vikas Sajjan
Prior to suspending the system, we need to ensure that certain
clock source and gate registers are unmasked.
while at it, add these clks to save/restore list also.
Signed-off-by: Vikas Sajjan vikas.saj...@samsung.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
On Fri, 04 Jul 2014, Kishon Vijay Abraham I wrote:
In case of multi-phy PHY providers, each PHY should be modeled as a sub
node of the PHY provider. Then each PHY will have a different node pointer
(node pointer of sub node) than that of PHY provider. Added this provision
in the PHY core.
Hi Andrej, Inki,
On 18 June 2014 12:06, Rahul Sharma rahul.sha...@samsung.com wrote:
Hi Andrej,
On 18 June 2014 11:46, Andrzej Hajda a.ha...@samsung.com wrote:
On 06/17/2014 07:49 AM, Rahul Sharma wrote:
Hi All,
Please review this patch.
Regards,
Rahul Sharma
On 9 June 2014 16:58,
On Fri, 04 Jul 2014, Kishon Vijay Abraham I wrote:
Fixed of_phy_provider_lookup to return 'phy_provider' if _of_phy_get
passes the node pointer of the sub-node of phy provider node. This is
needed when phy provider implements multiple PHYs and each PHY is
modelled as the sub-node of PHY
On Mon, 07 Jul 2014, Kishon Vijay Abraham I wrote:
Hi,
On Monday 07 July 2014 06:42 PM, Lee Jones wrote:
On Fri, 04 Jul 2014, Kishon Vijay Abraham I wrote:
In case of multi-phy PHY providers, each PHY should be modeled as a sub
node of the PHY provider. Then each PHY will have a
Could this patch be applied for v3.17 please?
[ It still applies fine to next-20140707. ]
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
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the body of a message to majord
Hi,
On Mon, Jun 2, 2014 at 10:24 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
This is needed for suspend/resume and cpuidle AFTR mode support.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
against
On Mon, Jun 30, 2014 at 11:32 PM, Kukjin Kim kgene@samsung.com wrote:
This patch removes gpio codes for s5p6440 and s5p6450 SoCs.
Signed-off-by: Kukjin Kim kgene@samsung.com
Cc: Linus Walleij linus.wall...@linaro.org
Acked-by: Linus Walleij linus.wall...@linaro.org
Yours,
Linus
On Mon, Jun 30, 2014 at 11:32 PM, Kukjin Kim kgene@samsung.com wrote:
This patch removes gpio codes for s5pc100 SoC.
Signed-off-by: Kukjin Kim kgene@samsung.com
Cc: Linus Walleij linus.wall...@linaro.org
Acked-by: Linus Walleij linus.wall...@linaro.org
Yours,
Linus Walleij
--
To
When parsing JPEG header s5p_jpeg_parse_hdr function
should return immediately in case there was an error
while reading a byte.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/media/platform/s5p-jpeg/jpeg-core.c |4
This patch adds support for jpeg codec on Exynos3250 SoC to
the s5p-jpeg driver. Supported raw formats are: YUYV, YVYU, UYVY,
VYUY, RGB565, RGB565X, RGB32, NV12, NV21. The support includes
also scaling and cropping features.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Signed-off-by:
The jpeg_bound_align_image function needs to know the context
in which it is called, as it needs to align image dimensions in
a slight different manner for Exynos3250, which crops pixels for
specific values in case the format is RGB.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Assure proper crop_rect initialization in case
the user space doesn't call S_SELECTION ioctl.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/media/platform/s5p-jpeg/jpeg-core.c | 15 +++
1 file changed, 15
JPEG codec on Exynos3250 SoC produces broken raw image if
a JPEG is decoded to YUV420 format and downscaling by
more then 2 is applied. Prevent this by asserting downscale
ratio to 2.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
V4L2_SEL_TGT_COMPOSE_DEFAULT switch case should select whole
available area of the image and V4L2_SEL_TGT_COMPOSE
should apply user settings.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: Kumar Gala
JPEG IP on Exynos3250 SoC requires enabling two clock
gates for its operation. This patch documents this
requirement.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll
Take into account limitations specific to the Exynos3250 SoC,
regarding setting chroma subsampling control value.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/media/platform/s5p-jpeg/jpeg-core.c | 59
On Tue, Jul 1, 2014 at 4:15 PM, Kamil Debski k.deb...@samsung.com wrote:
The Exynos4412 USB 2.0 PHY hardware differs from the description provided
in the documentation. Some register bits have different function. This
patch fixes the defines of register bits and changes the way how phys are
Andreas,
On Fri, Jul 4, 2014 at 6:06 AM, Andreas Färber afaer...@suse.de wrote:
Doug can help you in adding changes required for tps65090.
Hm, Doug had pointed out an issue with tps65090 in my v1, so I dropped
it: https://patchwork.kernel.org/patch/4397321/
tps65090 on Spring is nowhere near
Hi,
On Wed, Jul 2, 2014 at 10:19 PM, Andreas Färber afaer...@suse.de wrote:
With these 10 patches applied on top of my dt on top of kgene's tree,
the last U-Boot screen stays visible for ~50 seconds, then the screen
goes blank, and I can ssh in some time later.
If I comment out the
On 07/04/14 17:10, Tomasz Figa wrote:
Hi Kukjin,
Tomasz,
On 30.06.2014 23:32, Kukjin Kim wrote:
This patch removes supporting s5p64x0 related pwm codes because of
no more support for S5P6440 and S5P6450 SoCs. And this patch changes
the name of s5p6440-pwm to exynos-pwm instead.
On 07/07/14 12:50, Pankaj Dubey wrote:
This series is doing code cleanup under arch/arm/mach-exynos.
These patches have been separated from main exynos pmu v4 patch
posted here [1].
[1]: https://lkml.org/lkml/2014/5/10/29
Changes Since v5:
- Rebased on latest for-next of Kukjin Kim's tree.
On 07/07/14 12:50, Pankaj Dubey wrote:
As exynos_cpuidle_init and exynos_cpufreq_init function have just one lines
of code for registering platform devices. We can move these lines to
exynos_dt_machine_init and delete exynos_cpuidle_init and exynos_cpufreq_init
function. This will help in
The following changes since commit a497c3ba1d97fc69c1e78e7b96435ba8c2cb42ee:
Linux 3.16-rc2 (2014-06-21 19:02:54 -1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/s5p-cleanup
for you to fetch changes up to
The following changes since commit 4c834452aad01531db949414f94f817a86348d59:
Linux 3.16-rc3 (2014-06-29 14:11:36 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/samsung-fixes-2
for you to fetch changes up to
On 07/05/14 04:31, Mark Brown wrote:
On Fri, Jul 04, 2014 at 02:50:52PM +0530, Tushar Behera wrote:
Add sound-card name property to Snow/Peach-Pit/Peach-Pi boards.
Acked-by: Mark Brownbroo...@linaro.org
Thanks, applied.
- Kukjin
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On 07/01/14 22:54, Tomasz Figa wrote:
Hi,
On 24.06.2014 15:57, Tomasz Figa wrote:
This series inteds to fix various issues spotted while testing v3.16-rc2.
The patches should be reasonably independent from each other and so could be
picked to respective trees. See descriptions of individual
On 07/01/14 20:59, Tushar Behera wrote:
On 06/27/2014 08:18 PM, Kevin Hilman wrote:
On Fri, Jun 27, 2014 at 7:18 AM, Kevin Hilmankhil...@linaro.org wrote:
On Thu, Jun 26, 2014 at 8:38 PM, Tushar Beheratrbli...@gmail.com wrote:
Would you please provide me the environment setting of your
This configuration could be used in MIPI DSI command mode also.
And adds user manual description for display configuration.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Reviewed-by: Andrzej Hajda
In case of using MIPI DSI based I80 interface panel,
the relevant registers should be set.
So this patch adds relevant DT bindings.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
Hi,
This series adds LCD I80 interface display support for Exynos DRM driver.
The FIMD(display controller) specification describes it as LCD I80 interface
and the DSI specification describes it as Command mode interface.
This is based on exynos-drm-next branch.
The previous patches,
RFC:
This patch adds sysreg property to fimd device node
which is required to use I80 interface.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos4.dtsi | 1 +
1 file changed, 1
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources and display timings.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
To support LCD I80 interface, the panel should generate
Tearing Effect synchronization signal between MCU and FB
to display video images.
And the display controller should trigger to transfer
video image at this signal.
So the panel receives the TE IRQ, then calls these handler
chains to notify it
To support MIPI command mode based I80 interface panel,
FIMD should do followings:
- Sets LCD I80 interface timings configuration.
- Uses lcd_sys as an IRQ resource and sets relevant IRQ configuration.
- Sets LCD block configuration for I80 interface.
- Sets ideal(pixel) clock is 2 times faster
This patch adds relevant to exynos5410 compatible
for exynos5410 / 5420 / 5440 SoCs support.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
Documentation/devicetree/bindings/video/exynos_dsim.txt | 4
The offset of register DSIM_PLLTMR_REG in Exynos5410 / 5420 / 5440
SoCs is different from the one in Exynos4 SoCs.
In case of Exynos5410 / 5420 / 5440 SoCs, there is no frequency
band bit in DSIM_PLLCTRL_REG, and it uses DSIM_PHYCTRL_REG and
DSIM_PHYTIMING*_REG instead.
So this patch adds driver
To support LCD I80 interface, the DSI host calls this function
to notify the panel tearing effect synchronization signal to
the CRTC device manager to trigger to transfer video image.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park
This patch adds common part of dsi node.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git
This patch adds sysreg property to fimd device node
which is required to use I80 interface.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi | 1 +
1 file changed, 1
This patch adds MIPI DSI command mode based
S6E3FA0 AMOLED LCD Panel driver.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/panel/Kconfig | 7 +
On 7/1/2014 7:03 PM, Laura Abbott wrote:
Currently, early_init_dt_scan validates the header, sets the
boot params, and scans for chosen/memory all in one function.
Split this up into two separate functions (validation/setting
boot params in one, scanning in another) to allow for
additional
On 07/08/2014 05:04 AM, Kukjin Kim wrote:
On 07/01/14 20:59, Tushar Behera wrote:
On 06/27/2014 08:18 PM, Kevin Hilman wrote:
On Fri, Jun 27, 2014 at 7:18 AM, Kevin Hilmankhil...@linaro.org
wrote:
On Thu, Jun 26, 2014 at 8:38 PM, Tushar Beheratrbli...@gmail.com
wrote:
Would you please
On Mon, Jun 30, 2014 at 2:26 PM, Sachin Kamat sachin.ka...@samsung.com wrote:
Since the USB 2.0 PHYs are required only with EHCI/OHCI USB drivers,
make it depend on them and default to ARCH_EXYNOS as they are meant
for Exynos platforms. Also, make the sub-drivers silent options enabling
them
On Mon, Jul 7, 2014 at 10:53 AM, Seungwon Jeon tgih@samsung.com wrote:
On Fri, July 04, 2014, Seungwon Jeon wrote:
On Tue, July 01, 2014. Yuvaraj Kumar wrote:
On Fri, Jun 27, 2014 at 4:48 PM, Seungwon Jeon tgih@samsung.com
wrote:
Hi Yuvaraj,
On Fri, June 27, 2014, Yuvaraj
Hi Kukjin,
On Mon, Jun 30, 2014 at 11:28 PM, Tomasz Figa t.f...@samsung.com wrote:
Hi Vikas, Abhilash,
On 26.06.2014 13:12, Vikas Sajjan wrote:
Prior to suspending the system, we need to ensure that certain
clock source and gate registers are unmasked.
while at it, add these clks to
From: Prathyush K prathyus...@samsung.com
While powering on/off a local powerdomain in exynos5 chipsets, the input
clocks to each device gets modified. This behaviour is based on the
SYSCLK_SYS_PWR_REG registers.
E.g. SYSCLK_MFC_SYS_PWR_REG = 0x0, the parent of input clock to MFC
Adds IDs for MUX clocks to be used by power domain for MFC
for doing re-parenting while pd on/off.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
Acked-by: Tomasz Figa t.f...@samsung.com
---
drivers/clk/samsung/clk-exynos5420.c |6
Adding the optional clock property for the mfc_pd for
handling the re-parenting while pd on/off.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi |3 +++
This patch series for clock handling in power domain is
re-send for merging after rebasing onto latest linux-samsung.git,
for-next branch.
Original series and discussion can be found here:
https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg31550.html
Arun Kumar K (2):
clk:
Hi Arnd/Rob/Mike et al,
We didn't conclude anything out of this thread and so kicking it
again as we need to close bindings to support cpufreq-cpu0
better for platforms not sharing clock lines across all CPUs.
https://lkml.org/lkml/2014/7/1/358
On 14 May 2014 20:03, Arnd Bergmann a...@arndb.de
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