Re: [PATCH v5] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

Hi Sekhar,

>
>> +
>> + codec  1100 {
>> + samsung,mfc-r = <0x4300 0x80>;
>> + samsung,mfc-l = <0x5100 0x80>;
>> + };
>
> How are these addresses determined? Are they defined by hardware (so they are
> not user configurable) or is the user free to choose them depending on where
> he intends the contiguous memory to lie? If it is the later, I wonder if it
> is considered okay to define this in device tree since it is supposed to be
> a description of the hardware.
>

These addresses are not really user defined but board specific.
So these properties are separated out from exynos5250.dtsi and put
inside exynos5250-smdk5250.dts file where the board specific parameters
are defined. The addresses signifies different memory bank areas as per
the board configuration. So its still a hardware description and hence included
in the dt file.

Regards
Arun
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[RFC 00/12] Exynos5 FIMC-IS driver

[Arun Kumar K]

This patchset adds a new driver for the FIMC-IS IP available in
Samsung Exynos5 SoC onwards. The camera subsystem in Exynos5 is significantly
different from that of Exynos4 and before. 
In Exynos4, the FIMC-IS is a sub component of the camera subsystem which
takes input from fimc-lite and does post processing of the image and passes
it to the fimc-capture which writes to the output DMA.

But in case of Exynos5, the fimc-capture IP is removed and instead a more 
powerful fimc-is takes the role of giving scaled image output via DMA.
FIMC-IS internally has two scalers for this in addition to other
post-processing components like dynamic range compression,
optical distortion correction, digital image stabilization, 3D noise reduction
and face detection.

FIMC-IS also has capability to directly control certain sensors and the
sensors compatible with the fimc-is will be termed as fimc-is sensors.
This patchset adds support for two such fimc-is sensors - s5k4e5 and s5k6a3.
These sensors are controlled exclusively by the fimc-is firmware.
They provide only SRGB unscaled output which will reach fimc-is
via mipi-csis and fimc-lite. The color space conversion, scaling and all other
post processing will be then done by the fimc-is IP components.

The fimc-is driver operates in the following manner:
The sensor subdevice created by this driver will be used by the exynos5
media-device's pipeline0 which connects it with mipi-csis and fimc-lite.

|fimc-is-sensor|--->|mipi-csis|--->|fimc-lite|--->|Memory|

The output bayer image dumped by the fimc-lite subdev into memory is fed
into the ISP subdev of fimc-is driver. For that the pipeline1 of exynos5
media-device will look like this:

|Memory|--->|fimc-is-isp|--->|fimc-is-scaler-codec|--->|fimc-is-scaler-preview|

The isp subdev accepts bayer input buffer at its OUTPUT_MPLANE. It will
do a set of post processing operations and passes it on-the-fly to the
scalers. The two scalers can give two different scaled outputs which can
be used for recording and preview simultaneously. Both scaler-codec and
scaler-preview dumps DMA data out through its CAPTURE_MPLANE.

This first RFC contains the basic version of the driver which accepts
bayer input data and provides 2 different scaled outputs with most of
the post processing blocks disabled.

This has to be applied on exynos5 media device patchset posted by
Shaik Ameer Basha [1] and its based on media-tree v3.9.

[1] http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg16191.html

Arun Kumar K (12):
  exynos-fimc-is: Adding device tree nodes
  exynos-fimc-is: Adding ARCH support for fimc-is
  exynos-fimc-is: Adds fimc-is driver core files
  exynos-fimc-is: Adds common driver header files
  exynos-fimc-is: Adds the register definition and context header
  exynos-fimc-is: Adds the sensor subdev
  exynos-fimc-is: Adds isp subdev
  exynos-fimc-is: Adds scaler subdev
  exynos-fimc-is: Adds the hardware pipeline control
  exynos-fimc-is: Adds the hardware interface module
  exynos-fimc-is: Adds the Kconfig and Makefile
  mipi-csis: Enable all interrupts for fimc-is usage

 .../devicetree/bindings/media/soc/exynos5-is.txt   |   81 +
 arch/arm/boot/dts/exynos5250-pinctrl.dtsi  |   60 +
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |   54 +-
 arch/arm/boot/dts/exynos5250.dtsi  |8 +
 arch/arm/mach-exynos/clock-exynos5.c   |  129 ++
 arch/arm/mach-exynos/include/mach/map.h|2 +
 arch/arm/mach-exynos/include/mach/regs-clock.h |7 +
 arch/arm/mach-exynos/mach-exynos5-dt.c |2 +
 drivers/media/platform/exynos5-is/Kconfig  |   12 +
 drivers/media/platform/exynos5-is/Makefile |3 +
 drivers/media/platform/exynos5-is/fimc-is-cmd.h|  211 ++
 drivers/media/platform/exynos5-is/fimc-is-core.c   |  421 
 drivers/media/platform/exynos5-is/fimc-is-core.h   |  140 ++
 drivers/media/platform/exynos5-is/fimc-is-err.h|  258 +++
 .../media/platform/exynos5-is/fimc-is-interface.c  | 1003 +
 .../media/platform/exynos5-is/fimc-is-interface.h  |  130 ++
 drivers/media/platform/exynos5-is/fimc-is-isp.c|  546 +
 drivers/media/platform/exynos5-is/fimc-is-isp.h|   88 +
 .../media/platform/exynos5-is/fimc-is-metadata.h   |  771 +++
 drivers/media/platform/exynos5-is/fimc-is-param.h  | 2163 
 .../media/platform/exynos5-is/fimc-is-pipeline.c   | 1961 ++
 .../media/platform/exynos5-is/fimc-is-pipeline.h   |  129 ++
 drivers/media/platform/exynos5-is/fimc-is-regs.h   |  352 
 drivers/media/platform/exynos5-is/fimc-is-scaler.c |  595 ++
 drivers/media/platform/exynos5-is/fimc-is-scaler.h |  107 +
 drivers/media/platform/exynos5-is/fimc-is-sensor.c |  337 +++
 drivers/media/platform/exynos5-is/fimc-is-sensor.h |  170 ++
 drivers/media/platform/exynos5-is/fimc-is.h|  151 ++
 drivers/media/platform/s5p-fimc/mipi-csis.c|2 +-
 29 files changed

[RFC 01/12] exynos-fimc-is: Adding device tree nodes

[Arun Kumar K]

Add the fimc-is node and the required pinctrl nodes for
fimc-is driver for Exynos5. Also adds the DT binding documentation
for the new fimc-is node.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 .../devicetree/bindings/media/soc/exynos5-is.txt   |   81 
 arch/arm/boot/dts/exynos5250-pinctrl.dtsi  |   60 +++
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |   54 -
 arch/arm/boot/dts/exynos5250.dtsi  |8 ++
 4 files changed, 201 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/soc/exynos5-is.txt
 mode change 100644 => 100755 arch/arm/boot/dts/exynos5250-smdk5250.dts
 mode change 100644 => 100755 arch/arm/boot/dts/exynos5250.dtsi

diff --git a/Documentation/devicetree/bindings/media/soc/exynos5-is.txt 
b/Documentation/devicetree/bindings/media/soc/exynos5-is.txt
new file mode 100644
index 000..e0fdf02
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/soc/exynos5-is.txt
@@ -0,0 +1,81 @@
+Samsung EXYNOS SoC Camera Subsystem
+---
+
+The camera subsystem on Samsung Exynos5 SoC has some changes relative
+to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
+FIMC-LITE IPs but removed the FIMC-CAPTURE. Instead it has an improved
+FIMC-IS which can provide imate data DMA output.
+
+The device tree binding remain similar to the Exynos4 bindings which can
+be seen at samsung-fimc.txt with the addition of fimc-is sub-node which will
+be explained here.
+
+fimc-is subnode of camera node
+--
+
+Required properties:
+
+- compatible   : must be "samsung,exynos5250-fimc-is"
+- reg  : physical base address and size of the memory mapped
+ registers
+- interrupt-parent : Parent interrupt controller
+- interrupts   : fimc-is interrupt to the parent combiner
+
+Board specific properties:
+
+- pinctrl-names: pinctrl names for camera port pinmux control, at least
+"default" needs to be specified.
+- pinctrl-0...N   : pinctrl properties corresponding to pinctrl-names
+
+Sensor sub-nodes:
+
+FIMC-IS IP supports custom built sensors to be controlled exclusively by
+the FIMC-IS firmware. These sensor properties are to be defined here.
+Sensor nodes are described in the same way as in generic sensors used in
+Exynos4 and described in samsung-fimc.txt.
+
+Example:
+
+SoC common node:
+
+   fimc_is: fimc-is@1300 {
+   compatible = "samsung,exynos5250-fimc-is";
+   reg = <0x1300 0x20>;
+   interrupt-parent = <&combiner>;
+   interrupts = <19 1>;
+   status = "disabled";
+   };
+
+Board specific node:
+
+   fimc-is@1300 {
+   status = "okay";
+   pinctrl-0 =
+   <&cam_port_a_clk_active
+   &cam_bayer_clk_active
+   &isp_uart
+   &cam_i2c0
+   &cam_i2c1>;
+   pinctrl-names = "default";
+   s5k4e5 {
+   compatible = "samsung,s5k4e5";
+   gpios = <&gpx1 2 1>;
+   clock-frequency = <2400>;
+   port {
+   is_s5k4e5_ep: endpoint {
+   remote-endpoint = <&csis0_ep>;
+   };
+   };
+   };
+   s5k6a3 {
+   compatible = "samsung,s5k6a3";
+   gpios = <&gpx1 0 1>;
+   clock-frequency = <2400>;
+   port {
+   is_s5k6a3_ep: endpoint {
+   remote-endpoint = <&csis1_ep>;
+   };
+   };
+   };
+   };
+
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi 
b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index 3caaa21..320c22b 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -556,6 +556,38 @@
};
 
pinctrl@1340 {
+   gpe1: gpe1 {
+   gpio-controller;
+   #gpio-cells = <2>;
+
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   };
+
+  

[RFC 02/12] exynos-fimc-is: Adding ARCH support for fimc-is

[Arun Kumar K]

Adds new clocks needed for ISP submodules in the camera
subsystem of Exynos5250. Also adds the AUXDATA entry in
mach-exynos5-dt.c.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 arch/arm/mach-exynos/clock-exynos5.c   |  129 
 arch/arm/mach-exynos/include/mach/map.h|2 +
 arch/arm/mach-exynos/include/mach/regs-clock.h |7 ++
 arch/arm/mach-exynos/mach-exynos5-dt.c |2 +
 4 files changed, 140 insertions(+)

diff --git a/arch/arm/mach-exynos/clock-exynos5.c 
b/arch/arm/mach-exynos/clock-exynos5.c
index 4536515..b2c0825 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -28,6 +28,8 @@
 
 #include "common.h"
 
+#define FIMC_IS_NAME "exynos5-fimc-is"
+
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos5_clock_save[] = {
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
@@ -863,6 +865,16 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_gscl_ctrl,
.ctrlbit= (1 << 4),
}, {
+   .name   = "fimc-is0",
+   .devname= FIMC_IS_NAME,
+   .enable = exynos5_clk_ip_isp0_ctrl,
+   .ctrlbit= (0xFFC << 20) | (0xFF << 0),
+   }, {
+   .name   = "fimc-is1",
+   .devname= FIMC_IS_NAME,
+   .enable = exynos5_clk_ip_isp1_ctrl,
+   .ctrlbit= (0x3 << 12) | (0x7 << 0)
+   }, {
.name   = "csis",
.devname= "s5p-mipi-csis.0",
.enable = exynos5_clk_ip_gscl_ctrl,
@@ -1248,6 +1260,107 @@ static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
 };
 
+/* For ACLK_400_ISP */
+static struct clksrc_clk exynos5_clk_mout_aclk_400_isp = {
+   .clk= {
+   .name   = "mout_aclk_400_isp",
+   .parent = &exynos5_clk_mout_mpll_user.clk,
+   },
+   .sources = &exynos5_clkset_aclk,
+   .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_aclk_400_isp = {
+   .clk= {
+   .name   = "dout_aclk_400_isp",
+   .parent = &exynos5_clk_mout_aclk_400_isp.clk,
+   },
+   .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 20, .size = 3 },
+};
+
+static struct clk *exynos5_clkset_aclk_400_isp_list[] = {
+   [0] = &clk_ext_xtal_mux,
+   [1] = &exynos5_clk_dout_aclk_400_isp.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_400_isp = {
+   .sources= exynos5_clkset_aclk_400_isp_list,
+   .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_400_isp_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400_isp = {
+   .clk= {
+   .name   = "aclk_400_isp",
+   .devname= FIMC_IS_NAME,
+   },
+   .sources = &exynos5_clkset_aclk_400_isp,
+   .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266_isp = {
+   .clk= {
+   .name   = "aclk_266_isp",
+   .devname= FIMC_IS_NAME,
+
+   },
+   .sources = &clk_src_gscl_266,
+   .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266_isp_div0 = {
+   .clk= {
+   .name   = "aclk_266_isp_div0",
+   .devname= FIMC_IS_NAME,
+   .parent = &exynos5_clk_aclk_266_isp.clk,
+   },
+   .reg_div = { .reg = EXYNOS5_CLKDIV_ISP0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266_isp_div1 = {
+   .clk= {
+   .name   = "aclk_266_isp_div1",
+   .devname= FIMC_IS_NAME,
+   .parent = &exynos5_clk_aclk_266_isp.clk,
+   },
+   .reg_div = { .reg = EXYNOS5_CLKDIV_ISP0, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266_isp_divmpwm = {
+   .clk= {
+   .name   = "aclk_266_isp_divmpwm",
+   .devname= FIMC_IS_NAME,
+   .parent = &exynos5_clk_aclk_266_isp_div1.clk,
+   },
+   .reg_div = { .reg = EXYNOS5_CLKDIV_ISP2, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400_isp_div0 = {
+   .clk= {
+   .name   = "aclk_400_isp_div0",
+   .devname= FIMC_IS_NAME,
+   .parent = &exynos5_clk_aclk_400_isp.clk,
+   },
+ 

[RFC 03/12] exynos-fimc-is: Adds fimc-is driver core files

[Arun Kumar K]

This driver is for the FIMC-IS IP available in Samsung Exynos5
SoC onwards. This patch adds the core files for the new driver.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 drivers/media/platform/exynos5-is/fimc-is-core.c |  421 ++
 drivers/media/platform/exynos5-is/fimc-is-core.h |  140 +++
 2 files changed, 561 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c 
b/drivers/media/platform/exynos5-is/fimc-is-core.c
new file mode 100644
index 000..2a257c5
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
@@ -0,0 +1,421 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "fimc-is.h"
+
+int fimc_is_debug;
+module_param(fimc_is_debug, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(fimc_is_debug, "Debug level for exynos-fimc-is driver");
+
+static char *fimc_is_clock_name[] = {
+   [IS_CLK_GATE0]  = "fimc-is0",
+   [IS_CLK_GATE1]  = "fimc-is1",
+   [IS_CLK_266]= "aclk_266_isp",
+   [IS_CLK_266_DIV0]   = "aclk_266_isp_div0",
+   [IS_CLK_266_DIV1]   = "aclk_266_isp_div1",
+   [IS_CLK_266_DIV_MPWM]   = "aclk_266_isp_divmpwm",
+   [IS_CLK_400]= "aclk_400_isp",
+   [IS_CLK_400_DIV0]   = "aclk_400_isp_div0",
+   [IS_CLK_400_DIV1]   = "aclk_400_isp_div1",
+};
+
+static int fimc_is_create_sensor_subdevs(struct fimc_is *is)
+{
+   struct fimc_is_platdata *pdata = is->pdata;
+   int ret;
+
+   if (pdata->sensor_data[SENSOR_CAM0].enabled) {
+   /* Sensor0 */
+   ret = fimc_is_sensor_subdev_create(&is->sensor[SENSOR_CAM0],
+   &pdata->sensor_data[SENSOR_CAM0],
+   &is->pipeline);
+   if (ret < 0)
+   is_err("Error creating sensor0 subdev");
+   }
+
+   if (pdata->sensor_data[SENSOR_CAM1].enabled) {
+   /* Sensor1 */
+   ret = fimc_is_sensor_subdev_create(&is->sensor[SENSOR_CAM1],
+   &pdata->sensor_data[SENSOR_CAM1],
+   &is->pipeline);
+   if (ret < 0)
+   is_err("Error creating sensor1 subdev");
+   }
+
+   return 0;
+}
+
+static int fimc_is_unregister_sensor_subdevs(struct fimc_is *is)
+{
+   struct fimc_is_platdata *pdata = is->pdata;
+
+   if (pdata->sensor_data[SENSOR_CAM0].enabled)
+   fimc_is_sensor_subdev_destroy(&is->sensor[SENSOR_CAM0]);
+   if (pdata->sensor_data[SENSOR_CAM1].enabled)
+   fimc_is_sensor_subdev_destroy(&is->sensor[SENSOR_CAM1]);
+
+   return 0;
+}
+
+static struct fimc_is_platdata *fimc_is_parse_dt(struct device *dev)
+{
+   struct device_node *np = dev->of_node;
+   struct device_node *child, *ep, *port;
+   struct fimc_is_platdata *pdata;
+   struct fimc_is_sensor_data *sensor_data;
+   struct v4l2_of_endpoint endpoint;
+   unsigned int i, snum;
+   int num_gpios;
+
+   pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+   if (!pdata) {
+   is_err("Memory allocation for pdata failed\n");
+   return NULL;
+   }
+
+   /* Parse sensor properties */
+   for (snum = 0; snum < FIMC_IS_NUM_SENSORS; snum++) {
+
+   child = of_get_next_child(np, child);
+   if (!child) {
+   is_err("Child node not found\n");
+   continue;
+   }
+
+   sensor_data = &pdata->sensor_data[snum];
+   num_gpios = of_gpio_named_count(child, "gpios");
+   if (num_gpios < 0) {
+   is_err("Sensor gpio property not found\n");
+   of_node_put(child);
+   goto exit;
+   }
+   sensor_data->num_gpios = num_gpios;
+   of_property_read_string(child, "compatible",
+  

[RFC 05/12] exynos-fimc-is: Adds the register definition and context header

[Arun Kumar K]

This patch adds the register definition file for the fimc-is driver
and also the header file containing the main context for the driver.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 drivers/media/platform/exynos5-is/fimc-is-regs.h |  352 ++
 drivers/media/platform/exynos5-is/fimc-is.h  |  151 ++
 2 files changed, 503 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-regs.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-regs.h 
b/drivers/media/platform/exynos5-is/fimc-is-regs.h
new file mode 100644
index 000..43ed011
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-regs.h
@@ -0,0 +1,352 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_REGS_H
+#define FIMC_IS_REGS_H
+
+#include 
+
+/* WDT_ISP register */
+#define WDT0x0017
+/* MCUCTL register */
+#define MCUCTL 0x0018
+/* MCU Controller Register */
+#define MCUCTLR(MCUCTL+0x00)
+#define MCUCTLR_AXI_ISPX_AWCACHE(x)((x) << 16)
+#define MCUCTLR_AXI_ISPX_ARCACHE(x)((x) << 12)
+#define MCUCTLR_MSWRST (1 << 0)
+/* Boot Base OFfset Address Register */
+#define BBOAR  (MCUCTL+0x04)
+#define BBOAR_BBOA(x)  ((x) << 0)
+/* Interrupt Generation Register 0 from Host CPU to VIC */
+#define INTGR0 (MCUCTL+0x08)
+#define INTGR0_INTGC9  (1 << 25)
+#define INTGR0_INTGC8  (1 << 24)
+#define INTGR0_INTGC7  (1 << 23)
+#define INTGR0_INTGC6  (1 << 22)
+#define INTGR0_INTGC5  (1 << 21)
+#define INTGR0_INTGC4  (1 << 20)
+#define INTGR0_INTGC3  (1 << 19)
+#define INTGR0_INTGC2  (1 << 18)
+#define INTGR0_INTGC1  (1 << 17)
+#define INTGR0_INTGC0  (1 << 16)
+#define INTGR0_INTGD5  (1 << 5)
+#define INTGR0_INTGD4  (1 << 4)
+#define INTGR0_INTGD3  (1 << 3)
+#define INTGR0_INTGD2  (1 << 2)
+#define INTGR0_INTGD1  (1 << 1)
+#define INTGR0_INTGD0  (1 << 0)
+/* Interrupt Clear Register 0 from Host CPU to VIC */
+#define INTCR0 (MCUCTL+0x0c)
+#define INTCR0_INTCC9  (1 << 25)
+#define INTCR0_INTCC8  (1 << 24)
+#define INTCR0_INTCC7  (1 << 23)
+#define INTCR0_INTCC6  (1 << 22)
+#define INTCR0_INTCC5  (1 << 21)
+#define INTCR0_INTCC4  (1 << 20)
+#define INTCR0_INTCC3  (1 << 19)
+#define INTCR0_INTCC2  (1 << 18)
+#define INTCR0_INTCC1  (1 << 17)
+#define INTCR0_INTCC0  (1 << 16)
+#define INTCR0_INTCD5  (1 << 5)
+#define INTCR0_INTCD4  (1 << 4)
+#define INTCR0_INTCD3  (1 << 3)
+#define INTCR0_INTCD2  (1 << 2)
+#define INTCR0_INTCD1  (1 << 1)
+#define INTCR0_INTCD0  (1 << 0)
+/* Interrupt Mask Register 0 from Host CPU to VIC */
+#define INTMR0 (MCUCTL+0x10)
+#define INTMR0_INTMC9  (1 << 25)
+#define INTMR0_INTMC8  (1 << 24)
+#define INTMR0_INTMC7  (1 << 23)
+#define INTMR0_INTMC6  (1 << 22)
+#define INTMR0_INTMC5  (1 << 21)
+#define INTMR0_INTMC4  (1 << 20)
+#define INTMR0_INTMC3  (1 << 19)
+#define INTMR0_INTMC2  (1 << 18)
+#define INTMR0_INTMC1  (1 << 17)
+#define INTMR0_INTMC0  (1 << 16)
+#define INTMR0_INTMD5  (1 << 5)
+#define INTMR0_INTMD4  (1 << 4)
+#define INTMR0_INTMD3  (1 << 3)
+#define INTMR0_INTMD2  (1 << 2)
+#define INTMR0_INTMD1  (1 << 1)
+#define INTMR0_INTMD0  (1 << 0)
+/* Interrupt Status Register 0 from Host CPU to VIC */
+#define INTSR0 (MCUCTL+0x14)
+#define INTSR0_GET_INTSD0(x)   (((x) >> 0) & 0x1)
+#define INTSR0_GET_INTSD1(x)   (((x) >> 1) & 0x1)
+#define INTSR0_GET_INTSD2(x)   (((x) >> 2) & 0x1)

[RFC 06/12] exynos-fimc-is: Adds the sensor subdev

[Arun Kumar K]

FIMC-IS uses certain sensors which are exclusively controlled
from the IS firmware. This patch adds the sensor subdev for the
fimc-is sensors.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 drivers/media/platform/exynos5-is/fimc-is-sensor.c |  337 
 drivers/media/platform/exynos5-is/fimc-is-sensor.h |  170 ++
 2 files changed, 507 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.c 
b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
new file mode 100644
index 000..c031493
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
@@ -0,0 +1,337 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K 
+ * Kil-yeon Lim 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include "fimc-is-sensor.h"
+#include "fimc-is.h"
+
+static char *sensor_clock_name[] = {
+   [SCLK_BAYER]= "sclk_bayer",
+   [SCLK_CAM0] = "sclk_cam0",
+   [SCLK_CAM1] = "sclk_cam1",
+};
+
+static struct fimc_is_sensor_info sensor_info[] = {
+   [SENSOR_S5K4E5] = {
+   .sensor_id = SENSOR_S5K4E5,
+   .sensor_name = "samsung,s5k4e5",
+   .pixel_width = SENSOR_4E5_WIDTH + 16,
+   .pixel_height = SENSOR_4E5_HEIGHT + 10,
+   .active_width = SENSOR_4E5_WIDTH,
+   .active_height = SENSOR_4E5_HEIGHT,
+   .max_framerate = 30,
+   .setfile_name = "setfile_4e5.bin",
+   .ext = {
+   .actuator_con = {
+   .product_name = ACTUATOR_NAME_DW,
+   .peri_type = SE_I2C,
+   .peri_setting.i2c.channel = SENSOR_CONTROL_I2C0,
+   },
+   .flash_con = {
+   .product_name = FLADRV_NAME_KTD267,
+   .peri_type = SE_GPIO,
+   .peri_setting.gpio.first_gpio_port_no = 1,
+   .peri_setting.gpio.second_gpio_port_no = 2,
+   },
+   .from_con.product_name = FROMDRV_NAME_NOTHING,
+   .mclk = 0,
+   .mipi_lane_num = 0,
+   .mipi_speed = 0,
+   .fast_open_sensor = 0,
+   .self_calibration_mode = 0,
+   },
+
+   },
+   [SENSOR_S5K6A3] = {
+   .sensor_id = SENSOR_S5K6A3,
+   .sensor_name = "samsung,s5k6a3",
+   .pixel_width = SENSOR_6A3_WIDTH + 16,
+   .pixel_height = SENSOR_6A3_HEIGHT + 10,
+   .active_width = SENSOR_6A3_WIDTH,
+   .active_height = SENSOR_6A3_HEIGHT,
+   .max_framerate = 30,
+   .setfile_name = "setfile_6a3.bin",
+   },
+};
+
+/* Sensor supported formats */
+static struct v4l2_mbus_framefmt sensor_formats[FIMC_IS_MAX_SENSORS] = {
+   [SENSOR_S5K4E5] = {
+   .width  = SENSOR_4E5_WIDTH + 16,
+   .height = SENSOR_4E5_HEIGHT + 10,
+   .code   = V4L2_MBUS_FMT_SGRBG10_1X10,
+   .field  = V4L2_FIELD_NONE,
+   .colorspace = V4L2_COLORSPACE_SRGB,
+   },
+   [SENSOR_S5K6A3] = {
+   .width  = SENSOR_6A3_WIDTH + 16,
+   .height = SENSOR_6A3_HEIGHT + 10,
+   .code   = V4L2_MBUS_FMT_SGRBG10_1X10,
+   .field  = V4L2_FIELD_NONE,
+   .colorspace = V4L2_COLORSPACE_SRGB,
+   },
+};
+
+static struct fimc_is_sensor *sd_to_fimc_is_sensor(struct v4l2_subdev *sd)
+{
+   return container_of(sd, struct fimc_is_sensor, subdev);
+}
+
+static void sensor_clk_put(struct fimc_is_sensor *sensor)
+{
+   int i;
+
+   for (i = 0; i < SCLK_MAX_NUM; i++) {
+   if (IS_ERR_OR_NULL(sensor->clock[i]))
+   continue;
+   clk_unprepare(sensor->clock[i]);
+   clk_put(sensor->clock[i]);
+   sensor->clock[i] = NULL;
+   }
+}
+
+static int sensor_clk_init(struct fimc_is_sensor *sensor)
+{
+   int i, ret;
+
+   /* Get CAM clocks */
+   for (i = 0; i < SCLK_MAX_NUM; i++) {
+   sensor->clock[i] = clk_get(NULL, sensor_clock_name[i]);
+   if (IS_ERR(sensor->clock[i]))
+   goto err;
+   ret = clk_prepare(sensor->clock[i]);
+   

[RFC 07/12] exynos-fimc-is: Adds isp subdev

[Arun Kumar K]

fimc-is driver takes video data input from the ISP video node
which is added in this patch. This node accepts Bayer input
buffers which is given from the IS sensors.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 drivers/media/platform/exynos5-is/fimc-is-isp.c |  546 +++
 drivers/media/platform/exynos5-is/fimc-is-isp.h |   88 
 2 files changed, 634 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.c 
b/drivers/media/platform/exynos5-is/fimc-is-isp.c
new file mode 100644
index 000..e68e936
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-isp.c
@@ -0,0 +1,546 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *  Arun Kumar K 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+
+#include "fimc-is.h"
+
+static struct fimc_is_fmt formats[] = {
+   {
+   .name   = "Bayer GR-BG 8bits",
+   .fourcc = V4L2_PIX_FMT_SGRBG8,
+   .depth  = {8},
+   .num_planes = 1,
+   },
+   {
+   .name   = "Bayer GR-BG 10bits",
+   .fourcc = V4L2_PIX_FMT_SGRBG10,
+   .depth  = {10},
+   .num_planes = 1,
+   },
+   {
+   .name   = "Bayer GR-BG 12bits",
+   .fourcc = V4L2_PIX_FMT_SGRBG12,
+   .depth  = {12},
+   .num_planes = 1,
+   },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+   unsigned int i;
+
+   for (i = 0; i < NUM_FORMATS; i++) {
+   if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
+   return &formats[i];
+   }
+   return NULL;
+}
+
+static int isp_video_output_start_streaming(struct vb2_queue *vq,
+   unsigned int count)
+{
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+
+   /* Set state to RUNNING */
+   set_bit(STATE_RUNNING, &isp->output_state);
+   return 0;
+}
+
+static int isp_video_output_stop_streaming(struct vb2_queue *vq)
+{
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+
+   clear_bit(STATE_RUNNING, &isp->output_state);
+   return 0;
+}
+
+static int isp_video_output_queue_setup(struct vb2_queue *vq,
+   const struct v4l2_format *pfmt,
+   unsigned int *num_buffers, unsigned int *num_planes,
+   unsigned int sizes[], void *allocators[])
+{
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+   struct fimc_is_fmt *fmt = isp->fmt;
+   unsigned int wh, i;
+
+   if (!fmt)
+   return -EINVAL;
+
+   *num_planes = fmt->num_planes;
+   wh = isp->width * isp->height;
+
+   for (i = 0; i < *num_planes; i++) {
+   allocators[i] = isp->alloc_ctx;
+   sizes[i] = (wh * fmt->depth[i]) / 8;
+   }
+   return 0;
+}
+
+static int isp_video_output_buffer_init(struct vb2_buffer *vb)
+{
+   struct vb2_queue *vq = vb->vb2_queue;
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+   struct fimc_is_buf *buf;
+
+   buf = &isp->output_bufs[vb->v4l2_buf.index];
+   /* Initialize buffer */
+   buf->vb = vb;
+   buf->paddr[0] = vb2_dma_contig_plane_dma_addr(vb, 0);
+   isp->out_buf_cnt++;
+   return 0;
+}
+
+static void isp_video_output_buffer_queue(struct vb2_buffer *vb)
+{
+   struct vb2_queue *vq = vb->vb2_queue;
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+   struct fimc_is_buf *buf;
+
+   buf = &isp->output_bufs[vb->v4l2_buf.index];
+
+   fimc_is_pipeline_buf_lock(isp->pipeline);
+   fimc_is_isp_wait_queue_add(isp, buf);
+   fimc_is_pipeline_buf_unlock(isp->pipeline);
+
+   /* Call shot command */
+   fimc_is_pipeline_shot(isp->pipeline);
+}
+
+static void isp_lock(struct vb2_queue *vq)
+{
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+   mutex_lock(&isp->video_lock);
+}
+
+static void isp_unlock(struct vb2_queue *vq)
+{
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+   mutex_unlock(&isp->video_lock);
+}
+
+static const struct vb2_ops isp_video_output_qops = {
+   .queue_setup = isp_video_output_queue_setup,
+   .buf_init= isp_video_output_buffer_init,
+   .buf_queue   = isp_video_output_buffer_queue,
+   .wait_pre

[RFC 08/12] exynos-fimc-is: Adds scaler subdev

[Arun Kumar K]

FIMC-IS has two hardware scalers named as scaler-codec and
scaler-preview. This patch adds the common code handling the
video nodes and subdevs of both the scalers.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 drivers/media/platform/exynos5-is/fimc-is-scaler.c |  595 
 drivers/media/platform/exynos5-is/fimc-is-scaler.h |  107 
 2 files changed, 702 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-scaler.c 
b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
new file mode 100644
index 000..86ac9b8
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
@@ -0,0 +1,595 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *  Arun Kumar K 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define DEBUG
+#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
+
+#include 
+#include 
+
+#include "fimc-is.h"
+
+static struct fimc_is_fmt formats[] = {
+   {
+   .name   = "YUV 4:2:0 3p MultiPlanar",
+   .fourcc = V4L2_PIX_FMT_YUV420M,
+   .depth  = {8, 2, 2},
+   .num_planes = 3,
+   },
+   {
+   .name   = "YUV 4:2:0 2p MultiPlanar",
+   .fourcc = V4L2_PIX_FMT_NV12M,
+   .depth  = {8, 4},
+   .num_planes = 2,
+   },
+   {
+   .name   = "YUV 4:2:2 1p MultiPlanar",
+   .fourcc = V4L2_PIX_FMT_NV16,
+   .depth  = {16},
+   .num_planes = 1,
+   },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+   unsigned int i;
+
+   for (i = 0; i < NUM_FORMATS; i++) {
+   if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
+   return &formats[i];
+   }
+   return NULL;
+}
+
+static int scaler_video_capture_start_streaming(struct vb2_queue *vq,
+   unsigned int count)
+{
+   struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+   int ret;
+
+   /* Scaler start */
+   ret = fimc_is_pipeline_scaler_start(ctx->pipeline,
+   ctx->scaler_id,
+   (unsigned int **)ctx->buf_paddr,
+   ctx->num_buffers,
+   ctx->fmt->num_planes);
+   if (ret) {
+   is_err("Scaler start failed.\n");
+   return -EINVAL;
+   }
+
+   set_bit(STATE_RUNNING, &ctx->capture_state);
+   return 0;
+}
+
+static int scaler_video_capture_stop_streaming(struct vb2_queue *vq)
+{
+   struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+   int ret;
+
+   /* Scaler stop */
+   ret = fimc_is_pipeline_scaler_stop(ctx->pipeline, ctx->scaler_id);
+   if (ret)
+   is_dbg(3, "Scaler already stopped.\n");
+
+   clear_bit(STATE_RUNNING, &ctx->capture_state);
+   return 0;
+}
+
+static int scaler_video_capture_queue_setup(struct vb2_queue *vq,
+   const struct v4l2_format *pfmt,
+   unsigned int *num_buffers, unsigned int *num_planes,
+   unsigned int sizes[], void *allocators[])
+{
+   struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+   struct fimc_is_fmt *fmt = ctx->fmt;
+   unsigned int wh;
+   int i;
+
+   if (!fmt)
+   return -EINVAL;
+
+   *num_planes = fmt->num_planes;
+   wh = ctx->width * ctx->height;
+
+   for (i = 0; i < *num_planes; i++) {
+   allocators[i] = ctx->alloc_ctx;
+   sizes[i] = (wh * fmt->depth[i]) / 8;
+   }
+   return 0;
+}
+
+static int scaler_video_capture_buffer_init(struct vb2_buffer *vb)
+{
+   struct vb2_queue *vq = vb->vb2_queue;
+   struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+   struct fimc_is_buf *buf;
+   struct fimc_is_fmt *fmt;
+   int i;
+
+   buf = &ctx->capture_bufs[vb->v4l2_buf.index];
+   /* Initialize buffer */
+   buf->vb = vb;
+   fmt = ctx->fmt;
+   for (i = 0; i < fmt->num_planes; i++)
+   buf->paddr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
+
+   ctx->cap_buf_cnt++;
+   return 0;
+}
+
+static void scaler_video_capture_buffer_queue(struct vb2_buffer *vb)
+{
+   struct vb2_queue *vq = vb->vb2_queue;
+   struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+  

[RFC 10/12] exynos-fimc-is: Adds the hardware interface module

[Arun Kumar K]

The hardware interface module finally sends the commands to the
FIMC-IS firmware and runs the interrupt handler for getting the
responses.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 .../media/platform/exynos5-is/fimc-is-interface.c  | 1003 
 .../media/platform/exynos5-is/fimc-is-interface.h  |  130 +++
 2 files changed, 1133 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-interface.c 
b/drivers/media/platform/exynos5-is/fimc-is-interface.c
new file mode 100644
index 000..2537220
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-interface.c
@@ -0,0 +1,1003 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Kil-yeon Lim 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "fimc-is.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-regs.h"
+
+#define init_request_barrier(itf) mutex_init(&itf->request_barrier)
+#define enter_request_barrier(itf) mutex_lock(&itf->request_barrier)
+#define exit_request_barrier(itf) mutex_unlock(&itf->request_barrier)
+
+static inline void itf_get_cmd(struct fimc_is_interface *itf,
+   struct fimc_is_msg *msg, unsigned int index)
+{
+   struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+   switch (index) {
+   case INTR_GENERAL:
+   msg->id = 0;
+   msg->command = com_regs->ihcmd;
+   msg->instance = com_regs->ihc_sensorid;
+   msg->parameter1 = com_regs->ihc_param1;
+   msg->parameter2 = com_regs->ihc_param2;
+   msg->parameter3 = com_regs->ihc_param3;
+   msg->parameter4 = com_regs->ihc_param4;
+   break;
+   case INTR_SCC_FDONE:
+   msg->id = 0;
+   msg->command = IHC_FRAME_DONE;
+   msg->instance = com_regs->scc_sensor_id;
+   msg->parameter1 = com_regs->scc_param1;
+   msg->parameter2 = com_regs->scc_param2;
+   msg->parameter3 = com_regs->scc_param3;
+   msg->parameter4 = 0;
+   break;
+   case INTR_SCP_FDONE:
+   msg->id = 0;
+   msg->command = IHC_FRAME_DONE;
+   msg->instance = com_regs->scp_sensor_id;
+   msg->parameter1 = com_regs->scp_param1;
+   msg->parameter2 = com_regs->scp_param2;
+   msg->parameter3 = com_regs->scp_param3;
+   msg->parameter4 = 0;
+   break;
+   case INTR_META_DONE:
+   msg->id = 0;
+   msg->command = IHC_FRAME_DONE;
+   msg->instance = com_regs->meta_sensor_id;
+   msg->parameter1 = com_regs->meta_param1;
+   msg->parameter2 = 0;
+   msg->parameter3 = 0;
+   msg->parameter4 = 0;
+   break;
+   case INTR_SHOT_DONE:
+   msg->id = 0;
+   msg->command = IHC_FRAME_DONE;
+   msg->instance = com_regs->shot_sensor_id;
+   msg->parameter1 = com_regs->shot_param1;
+   msg->parameter2 = com_regs->shot_param2;
+   msg->parameter3 = 0;
+   msg->parameter4 = 0;
+   break;
+   default:
+   msg->id = 0;
+   msg->command = 0;
+   msg->instance = 0;
+   msg->parameter1 = 0;
+   msg->parameter2 = 0;
+   msg->parameter3 = 0;
+   msg->parameter4 = 0;
+   is_err("unknown command getting\n");
+   break;
+   }
+}
+
+static inline unsigned int itf_get_intr(struct fimc_is_interface *itf)
+{
+   unsigned int status;
+   struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+   status = readl(itf->regs + INTMSR1) | com_regs->ihcmd_iflag |
+   com_regs->scc_iflag |
+   com_regs->scp_iflag |
+   com_regs->meta_iflag |
+   com_regs->shot_iflag;
+
+   return status;
+}
+
+static void itf_set_state(struct fimc_is_interface *itf,
+   unsigned long state)
+{
+   unsigned long flags;
+   spin_lock_irqsave(&itf->slock_state, flags);
+   set_bit(state, &itf->state);
+   spin_unlock_irqrestore(&itf->slock_state, flags);
+}
+
+static void itf_clr_state(struct fimc_is_interface *itf,
+   unsigned long state)
+{
+   uns

[RFC 11/12] exynos-fimc-is: Adds the Kconfig and Makefile

[Arun Kumar K]

Modifies the exynos5-is Makefile and Kconfig to include the new
fimc-is driver.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 drivers/media/platform/exynos5-is/Kconfig  |   12 
 drivers/media/platform/exynos5-is/Makefile |3 +++
 2 files changed, 15 insertions(+)

diff --git a/drivers/media/platform/exynos5-is/Kconfig 
b/drivers/media/platform/exynos5-is/Kconfig
index 7aacf3b..588103e 100644
--- a/drivers/media/platform/exynos5-is/Kconfig
+++ b/drivers/media/platform/exynos5-is/Kconfig
@@ -5,3 +5,15 @@ config VIDEO_SAMSUNG_EXYNOS5_MDEV
  This is a v4l2 based media controller driver for
  Exynos5 SoC.
 
+if VIDEO_SAMSUNG_EXYNOS5_MDEV
+
+config VIDEO_SAMSUNG_EXYNOS5_FIMC_IS
+   tristate "Samsung Exynos5 SoC FIMC-IS driver"
+   depends on VIDEO_V4L2_SUBDEV_API
+   depends on VIDEO_SAMSUNG_EXYNOS5_MDEV
+   select VIDEOBUF2_DMA_CONTIG
+   help
+ This is a v4l2 driver for Samsung Exynos5 SoC series Imaging
+ subsystem known as FIMC-IS.
+
+endif #VIDEO_SAMSUNG_EXYNOS5_MDEV
diff --git a/drivers/media/platform/exynos5-is/Makefile 
b/drivers/media/platform/exynos5-is/Makefile
index 472d8e1..e5003d0 100644
--- a/drivers/media/platform/exynos5-is/Makefile
+++ b/drivers/media/platform/exynos5-is/Makefile
@@ -1,4 +1,7 @@
 ccflags-y += -Idrivers/media/platform/s5p-fimc
+exynos5-fimc-is-objs := fimc-is-core.o fimc-is-isp.o fimc-is-scaler.o 
fimc-is-sensor.o
+exynos5-fimc-is-objs += fimc-is-pipeline.o fimc-is-interface.o
 exynos-mdevice-objs := exynos5-mdev.o
 
+obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_FIMC_IS) += exynos5-fimc-is.o
 obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_MDEV) += exynos-mdevice.o
-- 
1.7.9.5

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[RFC 12/12] mipi-csis: Enable all interrupts for fimc-is usage

[Arun Kumar K]

FIMC-IS firmware needs all the MIPI-CSIS interrupts to be enabled.
This patch enables all those MIPI interrupts.

Signed-off-by: Arun Kumar K 
---
 drivers/media/platform/s5p-fimc/mipi-csis.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/media/platform/s5p-fimc/mipi-csis.c 
b/drivers/media/platform/s5p-fimc/mipi-csis.c
index debda7c..11eef67 100644
--- a/drivers/media/platform/s5p-fimc/mipi-csis.c
+++ b/drivers/media/platform/s5p-fimc/mipi-csis.c
@@ -64,7 +64,7 @@ MODULE_PARM_DESC(debug, "Debug level (0-2)");
 
 /* Interrupt mask */
 #define S5PCSIS_INTMSK 0x10
-#define S5PCSIS_INTMSK_EN_ALL  0xf000103f
+#define S5PCSIS_INTMSK_EN_ALL  0xfc00103f
 #define S5PCSIS_INTMSK_EVEN_BEFORE (1 << 31)
 #define S5PCSIS_INTMSK_EVEN_AFTER  (1 << 30)
 #define S5PCSIS_INTMSK_ODD_BEFORE  (1 << 29)
-- 
1.7.9.5

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Re: [RFC 12/12] mipi-csis: Enable all interrupts for fimc-is usage

[Arun Kumar K]

Hi Sylwester,

>>
>>  /* Interrupt mask */
>>  #define S5PCSIS_INTMSK   0x10
>> -#define S5PCSIS_INTMSK_EN_ALL0xf000103f
>> +#define S5PCSIS_INTMSK_EN_ALL0xfc00103f
>
> Do you know what interrupts are assigned to the CSIS_INTMSK
> bits 26, 27 ? In the documentation I have they are marked
> as reserved. I have tested this patch on Exynos4x12, it seems
> OK but you might want to merge it to the patch adding compatible
> property for exynos5.

The bits 26 and 27 are for Frame start and Frame end interrupts.
Yes this change can be merged with the MIPI-CSIS support for Exynos5.
Shaik will pick it up and merge it along with his patch series in v2.

>
> It would be good to know what these bits are for. And how
> enabling the interrupts actually help without modifying the
> interrupt handler ? Is it enough to just acknowledge those
> interrupts ? Or how it works ?
>

These interrupts are used by the FIMC-IS firmware possibly to check if the
sensor is working. Without enabling these, I get the error from firmware
on Sensor Open command.

Regards
Arun
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[PATCH] Add MFC device tree support

[Arun Kumar K]

This patch incorporates device tree support for the video codec
IP (MFC) present in Exynos series SoCs.
The driver side support for this will be posted as a separate
patch in the linux-media mailing list.

Naveen Krishna Chatradhi (1):
  ARM: EXYNOS: Add MFC device tree support

 .../devicetree/bindings/media/s5p-mfc.txt  |   24 
 arch/arm/boot/dts/exynos4210.dtsi  |   10 
 arch/arm/boot/dts/exynos5250.dtsi  |   10 
 arch/arm/mach-exynos/clock-exynos5.c   |2 +-
 arch/arm/mach-exynos/mach-exynos4-dt.c |   22 ++
 arch/arm/mach-exynos/mach-exynos5-dt.c |   22 ++
 6 files changed, 89 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt

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[PATCH] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

From: Naveen Krishna Chatradhi 

This patch adds device tree entry for MFC in the Exynos
machines. Exynos4 SoCs support MFC v5 version and Exynos5 has
MFC v6.x version. So making the required changes in the clock
files and adds MFC to the DT device list.

Signed-off-by: Naveen Krishna Chatradhi 
Signed-off-by: Arun Kumar K 
---
 .../devicetree/bindings/media/s5p-mfc.txt  |   24 
 arch/arm/boot/dts/exynos4210.dtsi  |   10 
 arch/arm/boot/dts/exynos5250.dtsi  |   10 
 arch/arm/mach-exynos/clock-exynos5.c   |2 +-
 arch/arm/mach-exynos/mach-exynos4-dt.c |   22 ++
 arch/arm/mach-exynos/mach-exynos5-dt.c |   22 ++
 6 files changed, 89 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt

diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt 
b/Documentation/devicetree/bindings/media/s5p-mfc.txt
new file mode 100644
index 000..b9bd266
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -0,0 +1,24 @@
+* Samsung Multi Format Codec (MFC)
+
+Mult Format Codec (MFC) is the IP present in Samsung SoCs which
+supports high resolution decoding and encoding functionalities.
+
+Required properties:
+  - compatible : value should be either one among the following
+   (a) "samsung,s5p-mfc-v5" for MFC v5 present in Exynos4 SoCs
+   (b) "samsung,s5p-mfc-v6" for MFC v6.x present in Exynos5 SoCs
+
+  - reg : Physical base address of the IP registers and length of memory
+ mapped region.
+
+  - interrupts : MFC interupt number to the CPU.
+
+  - samsung,mfc-r : Base address of the first memory bank used by MFC
+   for DMA contiguous memory allocation.
+
+  - samsung,mfc-r-size : Size of the first memory bank.
+
+  - samsung,mfc-l : Base address of the second memory bank used by MFC
+   for DMA contiguous memory allocation.
+
+  - samsung,mfc-l-size : Size of the second memory bank.
diff --git a/arch/arm/boot/dts/exynos4210.dtsi 
b/arch/arm/boot/dts/exynos4210.dtsi
index 02891fe..b5ee43d 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -56,6 +56,16 @@
interrupts = <0 43 0>;
};
 
+   mfc {
+   compatible = "samsung,s5p-mfc";
+   reg = <0x1340 0x1>;
+   interrupts = <0 94 0>;
+   samsung,mfc-r = <0x4300>;
+   samsung,mfc-r-size = <8388608>;
+   samsung,mfc-l = <0x5100>;
+   samsung,mfc-l-size = <8388608>;
+   };
+
rtc@1007 {
compatible = "samsung,s3c6410-rtc";
reg = <0x1007 0x100>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 004aaa8..3c762a4 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,6 +58,16 @@
interrupts = <0 42 0>;
};
 
+   mfc {
+   compatible = "samsung,s5p-mfc-v6";
+   reg = <0x1100 0x1>;
+   interrupts = <0 96 0>;
+   samsung,mfc-r = <0x4300>;
+   samsung,mfc-r-size = <8388608>;
+   samsung,mfc-l = <0x5100>;
+   samsung,mfc-l-size = <8388608>;
+   };
+
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E 0x100>;
diff --git a/arch/arm/mach-exynos/clock-exynos5.c 
b/arch/arm/mach-exynos/clock-exynos5.c
index 3b00e29..c85e7b2 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -607,7 +607,7 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit= (1 << 25),
}, {
.name   = "mfc",
-   .devname= "s5p-mfc",
+   .devname= "s5p-mfc-v6",
.enable = exynos5_clk_ip_mfc_ctrl,
.ctrlbit= (1 << 0),
}, {
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c 
b/arch/arm/mach-exynos/mach-exynos4-dt.c
index b2b5d5f..c4a0e16 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -13,6 +13,7 @@
 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -63,6 +64,7 @@ static const struct of_dev_auxdata 
exynos4210_auxdata_lookup[] __initconst = {
"exynos4210-spi.2", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
+   OF_DEV_AUXDATA("samsung,s5p-m

Re: [PATCH] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

Hi Thomas,
Thank you for the comments.
Please find my response inline.

--- Original Message ---
Sender : Thomas Abraham 
Date   : Aug 16, 2012 17:12 (GMT+05:30)
Title  : Re: [PATCH] ARM: EXYNOS: Add MFC device tree support

On 16 August 2012 18:01, Arun Kumar K  wrote:
> From: Naveen Krishna Chatradhi 
>
> This patch adds device tree entry for MFC in the Exynos
> machines. Exynos4 SoCs support MFC v5 version and Exynos5 has
> MFC v6.x version. So making the required changes in the clock
> files and adds MFC to the DT device list.
>
> Signed-off-by: Naveen Krishna Chatradhi 
> Signed-off-by: Arun Kumar K 
> ---
>  .../devicetree/bindings/media/s5p-mfc.txt  |   24 
> 
>  arch/arm/boot/dts/exynos4210.dtsi  |   10 
>  arch/arm/boot/dts/exynos5250.dtsi  |   10 
>  arch/arm/mach-exynos/clock-exynos5.c   |2 +-
>  arch/arm/mach-exynos/mach-exynos4-dt.c |   22 ++
>  arch/arm/mach-exynos/mach-exynos5-dt.c |   22 ++
>  6 files changed, 89 insertions(+), 1 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt
>
> diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt 
> b/Documentation/devicetree/bindings/media/s5p-mfc.txt
> new file mode 100644
> index 000..b9bd266
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
> @@ -0,0 +1,24 @@
> +* Samsung Multi Format Codec (MFC)
> +
> +Mult Format Codec (MFC) is the IP present in Samsung SoCs which
> +supports high resolution decoding and encoding functionalities.
>
> In addition to this, specifying that mfc is used for video
> encode/decode would be informative.

Ok. I will make it more descriptive.

> +
> +Required properties:
> +  - compatible : value should be either one among the following
> +   (a) "samsung,s5p-mfc-v5" for MFC v5 present in Exynos4 SoCs
> +   (b) "samsung,s5p-mfc-v6" for MFC v6.x present in Exynos5 SoCs
>
> "s5p" should be dropped from the compatible values. For example, it
> should be "samsung,mfc-v5", which is sufficient to identify the
> version of the mfc controller.

Ok will remove s5p.

> +
> +  - reg : Physical base address of the IP registers and length of memory
> + mapped region.
> +
> +  - interrupts : MFC interupt number to the CPU.
> +
> +  - samsung,mfc-r : Base address of the first memory bank used by MFC
> +   for DMA contiguous memory allocation.
> +
> +  - samsung,mfc-r-size : Size of the first memory bank.
>
> It is not allowed to pass buffer base address and size from device
> tree. Device tree node should describe only the MFC controller
> hardware. Any memory management related information should be handled
> outside of device tree. This helps the bindings to be reusable across
> multiple operating systems.

The mfc-l and mfc-r base address and size is board specific info which has to
be passed to the driver. This is used for DMA contiguous allocation by driver 
and this value
can change on a different board. 
So in that case, i will pass it as platform data to the driver from 
mach-exynos5-dt.c file.
I hope that would be ok.

> +
> +  - samsung,mfc-l : Base address of the second memory bank used by MFC
> +   for DMA contiguous memory allocation.
> +
> +  - samsung,mfc-l-size : Size of the second memory bank.
>
> Same comment as above. And the bindings documentation is usually
> included in the same patch that adds device tree support for the
> driver.

Ok

> diff --git a/arch/arm/boot/dts/exynos4210.dtsi 
> b/arch/arm/boot/dts/exynos4210.dtsi
> index 02891fe..b5ee43d 100644
> --- a/arch/arm/boot/dts/exynos4210.dtsi
> +++ b/arch/arm/boot/dts/exynos4210.dtsi
> @@ -56,6 +56,16 @@
> interrupts = <0 43 0>;
> };
>
> +   mfc {
> +   compatible = "samsung,s5p-mfc";
> +   reg = <0x1340 0x1>;
> +   interrupts = <0 94 0>;
> +   samsung,mfc-r = <0x4300>;
> +   samsung,mfc-r-size = <8388608>;
> +   samsung,mfc-l = <0x5100>;
> +   samsung,mfc-l-size = <8388608>;
> +   };
> +
> rtc@1007 {
> compatible = "samsung,s3c6410-rtc";
> reg = <0x1007 0x100>;
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
> b/arch/arm/boot/dts/exynos5250.dtsi
> index 004aaa8..3c762a4 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -58,6 +58,16 @@
> 

RE: [PATCH] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

Hi Kgene,
Thank you for the review comments.
Please find my response inline.

On Thu, Aug 23, 2012 at 1:46 PM, Kukjin Kim  wrote:
> Arun Kumar K wrote:
>>
>> Hi Thomas,
>> Thank you for the comments.
>> Please find my response inline.
>>
>> --- Original Message ---
>> Sender : Thomas Abraham
>> Date   : Aug 16, 2012 17:12 (GMT+05:30)
>> Title  : Re: [PATCH] ARM: EXYNOS: Add MFC device tree support
>>
>> On 16 August 2012 18:01, Arun Kumar K  wrote:
>> > From: Naveen Krishna Chatradhi 
>> >
>> > This patch adds device tree entry for MFC in the Exynos
>> > machines. Exynos4 SoCs support MFC v5 version and Exynos5 has
>> > MFC v6.x version. So making the required changes in the clock
>
> Since v6.1 is not used anywhere so just MFC v6 should be ok.
>

Ok.

>> > files and adds MFC to the DT device list.
>> >
>> > Signed-off-by: Naveen Krishna Chatradhi 
>> > Signed-off-by: Arun Kumar K 
>> > ---
>> >  .../devicetree/bindings/media/s5p-mfc.txt  |   24
>> 
>> >  arch/arm/boot/dts/exynos4210.dtsi  |   10 
>> >  arch/arm/boot/dts/exynos5250.dtsi  |   10 
>> >  arch/arm/mach-exynos/clock-exynos5.c   |2 +-
>> >  arch/arm/mach-exynos/mach-exynos4-dt.c |   22
>> ++
>> >  arch/arm/mach-exynos/mach-exynos5-dt.c |   22
>> ++
>> >  6 files changed, 89 insertions(+), 1 deletions(-)
>> >  create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt
>> >
>> > diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt
>> b/Documentation/devicetree/bindings/media/s5p-mfc.txt
>> > new file mode 100644
>> > index 000..b9bd266
>> > --- /dev/null
>> > +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
>> > @@ -0,0 +1,24 @@
>> > +* Samsung Multi Format Codec (MFC)
>> > +
>> > +Mult Format Codec (MFC) is the IP present in Samsung SoCs which
>> > +supports high resolution decoding and encoding functionalities.
>> >
>> > In addition to this, specifying that mfc is used for video
>> > encode/decode would be informative.
>>
>> Ok. I will make it more descriptive.
>>
>> > +
>> > +Required properties:
>> > +  - compatible : value should be either one among the following
>> > +   (a) "samsung,s5p-mfc-v5" for MFC v5 present in Exynos4 SoCs
>> > +   (b) "samsung,s5p-mfc-v6" for MFC v6.x present in Exynos5 SoCs
>> >
>> > "s5p" should be dropped from the compatible values. For example, it
>> > should be "samsung,mfc-v5", which is sufficient to identify the
>> > version of the mfc controller.
>>
>> Ok will remove s5p.
>>
> Yeah, I agree, just 'mfc-vX' is enough.
>

Ok. Will change it.

>> > +
>> > +  - reg : Physical base address of the IP registers and length of
>> memory
>> > + mapped region.
>> > +
>> > +  - interrupts : MFC interupt number to the CPU.
>> > +
>> > +  - samsung,mfc-r : Base address of the first memory bank used by MFC
>> > +   for DMA contiguous memory allocation.
>> > +
>> > +  - samsung,mfc-r-size : Size of the first memory bank.
>> >
>> > It is not allowed to pass buffer base address and size from device
>> > tree. Device tree node should describe only the MFC controller
>> > hardware. Any memory management related information should be handled
>> > outside of device tree. This helps the bindings to be reusable across
>> > multiple operating systems.
>>
>> The mfc-l and mfc-r base address and size is board specific info which has
>> to
>> be passed to the driver. This is used for DMA contiguous allocation by
>> driver and this value
>> can change on a different board.
>> So in that case, i will pass it as platform data to the driver from mach-
>> exynos5-dt.c file.
>> I hope that would be ok.
>>
> I don't think so. The mach-exynos5-dt is for all EXYNOS5 SoCs not
> platform_data. As I know, the addresses and sizes for buffer passed via
> platform data before, so it can be passed via device tree for board(.dtsi)?
> not SoC. In addition, it depends on board.
>

Ok. So as suggested the best option would be to move the mfc-l and r 
base address and size information to board dts file 
(exynos5250-smdk5250.dts) from exynos5250.dtsi. Hope th

Re: [PATCH] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

Hi Karol,
Thanks for your comments. 
Please find my response inline.

On Mon, Aug 20, 2012 at 11:47 AM, Karol Lewandowski  
wrote:
> On 08/16/2012 08:42 PM, Thomas Abraham wrote:
>> On 16 August 2012 18:01, Arun Kumar K  wrote:
>
>>> +  - interrupts : MFC interupt number to the CPU.
>>> +
>>> +  - samsung,mfc-r : Base address of the first memory bank used by MFC
>>> +   for DMA contiguous memory allocation.
>>> +
>>> +  - samsung,mfc-r-size : Size of the first memory bank.
>>
>> It is not allowed to pass buffer base address and size from device
>> tree. Device tree node should describe only the MFC controller
>> hardware. Any memory management related information should be handled
>> outside of device tree. This helps the bindings to be reusable across
>> multiple operating systems.
>
> The question is where elsewhere this should be described as this is strictly
> board-dependent option (number and size of RAM banks are important here).
>
> I agree that base addresses are bad, but I'm not aware of any functionality
> that would allow driver (actually, its platform dependent part in
> exynosN_reserve() function) to enumerate available memory banks and grab
> memory chunks from two distinct banks.
>
> My (lack of) knowledge ARM might be to blame here but I simply don't know
> how to achieve this. Any suggestions?
>

As suggested by kgene, I will pass it from the board specific dts file.

>
> On 08/16/2012 09:31 PM, Arun Kumar K wrote:
>
>> +static void s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
>> + phys_addr_t lbase, unsigned int lsize) {
>> +
>> + if (memblock_remove(lbase, lsize)) {
>> + pr_err("Failed to reserve bank1 memory for MFC device\n");
>> + WARN_ON(1);
>> + }
>> +
>> + if (memblock_remove(rbase, rsize)) {
>> + pr_err("Failed to reserve bank2 memory for MFC device\n");
>> + WARN_ON(1);
>> + }
>> +}
>
>
> non-static function with the same name is already defined in
> arch/arm/plat-samsung/s5p-dev-mfc.c. Please don't duplicate it,
> especially that you seem to be trying to do that twice!
>

Ok, I will use the existing function.

>
>> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c 
>> b/arch/arm/mach-exynos/mach-exynos5-dt.c
>
>> index ef770bc..898d2de 100644
>> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
>> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> ...
>> +static void s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
>> + phys_addr_t lbase, unsigned int lsize) {
>> +
>> + if (memblock_remove(lbase, lsize)) {
>> + pr_err("Failed to reserve bank1 memory for MFC device\n");
>> + WARN_ON(1);
>> + }
>> +
>> + if (memblock_remove(rbase, rsize)) {
>> + pr_err("Failed to reserve bank2 memory for MFC device\n");
>> + WARN_ON(1);
>> + }
>> +}
>
>
> See above.
>
>> +
>> +static void __init exynos5_reserve(void)
>> +{
>> + s5p_mfc_reserve_mem(0x4300, 8 << 20, 0x5100, 8 << 20);
>
>
> I think it would make sense to make this memory reservation dependent
> on "mfc*" node being present in DTS.  It's to early to use of_* functions
> (because tree is not populated at this stage) but fdt_* family of functions
> work just fine.
>

As I can see the fdt_* functions are not used in any of the ARM based SoC
init codes. Though I can see some references in powerpc.
The implementation and includes are present in arch/arm/boot/compressed/
which I think cannot be used directly in mach-exynos unless we make some
comon makefile changes. 
Please clarify whether its ok to use fdt_* functions to parse the dts in 
exynos machine init or please point me to some sample implementations
which I can refer to.

Regards
Arun

Regards
Arun

[PATCH v1 0/2] Add MFC device tree support

[Arun Kumar K]

This patchset adds device tree support for s5p-mfc driver.
The first patch adds DT support for both Exynos4 and 5 SoCs
which has different versions of MFC. The second patch which
adds DT support for the driver has to be applied over the 
patchset [1] which adds the MFCv6 support.

Changelog:
- Moved board specific DT information to different dtsi file
- Changed compatible name for the device
- Addressed other review comments

[1] http://www.mail-archive.com/linux-media@vger.kernel.org/msg51284.html

Arun Kumar K (1):
  [media] s5p-mfc: Add device tree support

Naveen Krishna Chatradhi (1):
  ARM: EXYNOS: Add MFC device tree support

 .../devicetree/bindings/media/s5p-mfc.txt  |   27 +
 arch/arm/boot/dts/exynos4210-origen.dts|7 ++
 arch/arm/boot/dts/exynos4210.dtsi  |6 +
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |7 ++
 arch/arm/boot/dts/exynos5250.dtsi  |6 +
 arch/arm/mach-exynos/Kconfig   |2 +
 arch/arm/mach-exynos/clock-exynos5.c   |2 +-
 arch/arm/mach-exynos/mach-exynos4-dt.c |9 ++
 arch/arm/mach-exynos/mach-exynos5-dt.c |9 ++
 drivers/media/platform/s5p-mfc/s5p_mfc.c   |  104 +---
 10 files changed, 162 insertions(+), 17 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt

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[PATCH v1 1/2] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

From: Naveen Krishna Chatradhi 

This patch adds device tree entry for MFC in the Exynos
machines. Exynos4 SoCs support MFC v5 version and Exynos5 has
MFC v6 version. So making the required changes in the clock
files and adds MFC to the DT device list.

Signed-off-by: Naveen Krishna Chatradhi 
Signed-off-by: Arun Kumar K 
---
 arch/arm/boot/dts/exynos4210-origen.dts   |7 +++
 arch/arm/boot/dts/exynos4210.dtsi |6 ++
 arch/arm/boot/dts/exynos5250-smdk5250.dts |7 +++
 arch/arm/boot/dts/exynos5250.dtsi |6 ++
 arch/arm/mach-exynos/Kconfig  |2 ++
 arch/arm/mach-exynos/clock-exynos5.c  |2 +-
 arch/arm/mach-exynos/mach-exynos4-dt.c|9 +
 arch/arm/mach-exynos/mach-exynos5-dt.c|9 +
 8 files changed, 47 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4210-origen.dts 
b/arch/arm/boot/dts/exynos4210-origen.dts
index 0c49caa..5cf9e93 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -146,4 +146,11 @@
spi_2: spi@1394 {
status = "disabled";
};
+
+   mfc {
+   samsung,mfc-r = <0x4300>;
+   samsung,mfc-r-size = <8388608>;
+   samsung,mfc-l = <0x5100>;
+   samsung,mfc-l-size = <8388608>;
+   };
 };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi 
b/arch/arm/boot/dts/exynos4210.dtsi
index 02891fe..5d57348 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -56,6 +56,12 @@
interrupts = <0 43 0>;
};
 
+   mfc {
+   compatible = "samsung,mfc-v5";
+   reg = <0x1340 0x1>;
+   interrupts = <0 94 0>;
+   };
+
rtc@1007 {
compatible = "samsung,s3c6410-rtc";
reg = <0x1007 0x100>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts 
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348..5824c97 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -109,4 +109,11 @@
spi_2: spi@12d4 {
status = "disabled";
};
+
+   mfc {
+   samsung,mfc-r = <0x4300>;
+   samsung,mfc-r-size = <8388608>;
+   samsung,mfc-l = <0x5100>;
+   samsung,mfc-l-size = <8388608>;
+   };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 004aaa8..d727b8b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,6 +58,12 @@
interrupts = <0 42 0>;
};
 
+   mfc {
+   compatible = "samsung,mfc-v6";
+   reg = <0x1100 0x1>;
+   interrupts = <0 96 0>;
+   };
+
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E 0x100>;
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index b5b4c8c..19e8313 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -36,6 +36,7 @@ config CPU_EXYNOS4210
select S5P_PM if PM
select S5P_SLEEP if PM
select PM_GENERIC_DOMAINS
+   select S5P_DEV_MFC
help
  Enable EXYNOS4210 CPU support
 
@@ -64,6 +65,7 @@ config SOC_EXYNOS5250
select SAMSUNG_DMADEV
select S5P_PM if PM
select S5P_SLEEP if PM
+   select S5P_DEV_MFC
help
  Enable EXYNOS5250 SoC support
 
diff --git a/arch/arm/mach-exynos/clock-exynos5.c 
b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c..480c251 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -612,7 +612,7 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit= (1 << 25),
}, {
.name   = "mfc",
-   .devname= "s5p-mfc",
+   .devname= "s5p-mfc-v6",
.enable = exynos5_clk_ip_mfc_ctrl,
.ctrlbit= (1 << 0),
}, {
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c 
b/arch/arm/mach-exynos/mach-exynos4-dt.c
index b2b5d5f..44bcfa4 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -13,6 +13,7 @@
 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -20,6 +21,7 @@
 
 #include 
 #include 
+#include 
 
 #include "common.h"
 
@@ -63,6 +65,7 @@ static const struct of_dev_auxdata 
exynos4210_auxdata_lookup[] __initconst = {
"exynos4210-spi.2", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0

[PATCH v1 2/2] [media] s5p-mfc: Add device tree support

[Arun Kumar K]

This patch will add the device tree support for MFC driver.

Signed-off-by: Arun Kumar K 
---
 .../devicetree/bindings/media/s5p-mfc.txt  |   27 +
 drivers/media/platform/s5p-mfc/s5p_mfc.c   |  104 +---
 2 files changed, 115 insertions(+), 16 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt

diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt 
b/Documentation/devicetree/bindings/media/s5p-mfc.txt
new file mode 100644
index 000..9a74d09
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -0,0 +1,27 @@
+* Samsung Multi Format Codec (MFC)
+
+Mult Format Codec (MFC) is the IP present in Samsung SoCs which
+supports high resolution decoding and encoding functionalities.
+The MFC device driver is a v4l2 driver which can encode/decode
+video raw/elementary streams and has support for all popular
+video codecs.
+
+Required properties:
+  - compatible : value should be either one among the following
+   (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
+   (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
+
+  - reg : Physical base address of the IP registers and length of memory
+ mapped region.
+
+  - interrupts : MFC interupt number to the CPU.
+
+  - samsung,mfc-r : Base address of the first memory bank used by MFC
+   for DMA contiguous memory allocation.
+
+  - samsung,mfc-r-size : Size of the first memory bank.
+
+  - samsung,mfc-l : Base address of the second memory bank used by MFC
+   for DMA contiguous memory allocation.
+
+  - samsung,mfc-l-size : Size of the second memory bank.
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c 
b/drivers/media/platform/s5p-mfc/s5p_mfc.c
index 80f0555..365b6f5 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
@@ -957,6 +957,8 @@ static int match_child(struct device *dev, void *data)
return !strcmp(dev_name(dev), (char *)data);
 }
 
+static void *mfc_get_drv_data(struct platform_device *pdev);
+
 /* MFC probe function */
 static int s5p_mfc_probe(struct platform_device *pdev)
 {
@@ -964,6 +966,8 @@ static int s5p_mfc_probe(struct platform_device *pdev)
struct video_device *vfd;
struct resource *res;
int ret;
+   unsigned int base_addr;
+   unsigned int bank_size;
 
pr_debug("%s++\n", __func__);
dev = devm_kzalloc(&pdev->dev, sizeof *dev, GFP_KERNEL);
@@ -980,8 +984,7 @@ static int s5p_mfc_probe(struct platform_device *pdev)
return -ENODEV;
}
 
-   dev->variant = (struct s5p_mfc_variant *)
-   platform_get_device_id(pdev)->driver_data;
+   dev->variant = mfc_get_drv_data(pdev);
 
ret = s5p_mfc_init_pm(dev);
if (ret < 0) {
@@ -1011,20 +1014,59 @@ static int s5p_mfc_probe(struct platform_device *pdev)
goto err_res;
}
 
-   dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, "s5p-mfc-l",
-  match_child);
-   if (!dev->mem_dev_l) {
-   mfc_err("Mem child (L) device get failed\n");
-   ret = -ENODEV;
-   goto err_res;
-   }
+   if (pdev->dev.of_node) {
+   dev->mem_dev_l = kzalloc(sizeof(struct device), GFP_KERNEL);
+   if (!dev->mem_dev_l) {
+   mfc_err("Not enough memory\n");
+   ret = -ENOMEM;
+   goto err_res;
+   }
+   of_property_read_u32(pdev->dev.of_node, "samsung,mfc-l",
+   &base_addr);
+   of_property_read_u32(pdev->dev.of_node, "samsung,mfc-l-size",
+   &bank_size);
+   if (dma_declare_coherent_memory(dev->mem_dev_l, base_addr,
+   base_addr, bank_size,
+   DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
+   mfc_err("Failed to declare coherent memory for\n"
+   "MFC device\n");
+   ret = -ENOMEM;
+   goto err_res;
+   }
 
-   dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, "s5p-mfc-r",
-  match_child);
-   if (!dev->mem_dev_r) {
-   mfc_err("Mem child (R) device get failed\n");
-   ret = -ENODEV;
-   goto err_res;
+   dev->mem_dev_r = kzalloc(sizeof(struct device), GFP_KERNEL);
+   if (!dev->mem_dev_r) {
+   mfc_err("Not enough memory\n");
+   ret = -ENOMEM;
+   goto err_res

Re: [PATCH] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

Hi Karol,
Thank you very much for the detailed explanation.
Its indeed very well explained and seems like a great approach 
to remove the hard codings.
I will go ahead with this implementation and post the updated patch.

Regards
Arun

On Wed, Sep 5, 2012 at 8:12 AM, Karol Lewandowski  
wrote:
> On 08/28/2012 07:08 PM, Arun Kumar K wrote:
>
>> Hi Karol,
>> Thanks for your comments.
>> Please find my response inline.
>
> Hi... and sorry for so much delayed response.
>
>>>> +
>>>> +static void __init exynos5_reserve(void)
>>>> +{
>>>> + s5p_mfc_reserve_mem(0x4300, 8 << 20, 0x5100, 8 << 20);
>>>
>>>
>>> I think it would make sense to make this memory reservation dependent
>>> on "mfc*" node being present in DTS.  It's to early to use of_* functions
>>> (because tree is not populated at this stage) but fdt_* family of functions
>>> work just fine.
>>>
>>
>> As I can see the fdt_* functions are not used in any of the ARM based SoC
>> init codes. Though I can see some references in powerpc.
>> The implementation and includes are present in arch/arm/boot/compressed/
>> which I think cannot be used directly in mach-exynos unless we make some
>> comon makefile changes.
>
>
> It looks like I was writing from memory, and I actually mixed things
> up.  To be clear this time - we can't use regular device tree handling
> functions in reserve() as it's too early.  Namely, flattened device tree
> is not yet converted to kernel's-natural representation.  However,
> I think we can scan fdt just fine.  To do so one just needs to use
> functions declared here
>
>   #include 
>
> Actual architecture-independent code is in drivers/of/fdt.c.  This
> provides of_fdt_ family of functions. Please see below for example.
>
>
>> Please clarify whether its ok to use fdt_* functions to parse the dts in
>> exynos machine init or please point me to some sample implementations
>> which I can refer to.
>
>
> It should be ok to use anything that works on flattened device tree
> rather than its uncompressed version.  I've experimented a bit and
> something like this worked for me just fine (it was around 3.3-kernel
> timeframe, but I don't think that fdt api has changed):
>
> [mach-exynos4-dt.c]
>
> #include 
>
> int fdt_find_compat(unsigned long node, const char *uname, int depth, void 
> *data)
> {
> if (of_flat_dt_is_compatible(node, (char *)data))
> return 1;
>
> return 0;
> }
>
> static void __init exynos4210_dt_reserve(void)
> {
> /* Reserve memory for MFC only if it's available */
> if (of_scan_flat_dt(fdt_find_compat, "samsung,s5pv210-mfc")) {
> printk(KERN_NOTICE "exynos4-dt: mfc device node found - 
> setting up memory area for dma\n");
> s5p_mfc_reserve_mem(0x4300, 8 << 20, 0x5100, 8 << 20);
> }
> }
>
> [.dts]
>
>  codec@some-addr {
>   compatible = "samsung,s5pv210-mfc";
>  };
>
>
> So, in above code fragment I just check if mfc was defined in dts.
> This could probably stay as it is.
>
> Then I allocate _predefined_ region - and this part should be fixed.
>
> If you have nodes like "mfc-r-size"/offset, then you could just get
> this information directly from (f)dt rather than hardcoding it in the code.
> Precisely, after we find compatible node we could do something like
> following (untested):
>
> unsigned long lsize, loff, rsize, roff len;
> __be32 *prop;
>
> prop = of_get_flat_dt_prop(node, "samsung,mfc-l-size", &len);
> if (!prop)
>return;
> lsize = of_read_ulong(prop, len/4);
> ...
>
> Regards,
> --
> Karol Lewandowski | Samsung Poland R&D Center | Linux/Platform
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" 
> in
> the body of a message to majord...@vger.kernel.org
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[PATCH v2] Add MFC device tree support

[Arun Kumar K]

This patch adds the device tree entries for MFC on Exynos5.
It incorporates the comment from Karol Lewandowski [1] to parse the
dt file during machine init.
This is rebased to the linux-samsung for-next branch.

[1] http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/12430

Changelog v2
- Use fdt functions to parse dtsi file for mfc memory info

Changelog v1
- Moved board specific DT information to different dtsi file
- Changed compatible name for the device
- Addressed other review comments

Arun Kumar K (1):
  ARM: EXYNOS: Add MFC device tree support

 .../devicetree/bindings/media/s5p-mfc.txt  |   27 +
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |7 +++
 arch/arm/boot/dts/exynos5250.dtsi  |6 ++
 arch/arm/mach-exynos/Kconfig   |1 +
 arch/arm/mach-exynos/clock-exynos5.c   |2 +-
 arch/arm/mach-exynos/mach-exynos5-dt.c |   56 
 6 files changed, 98 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt

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[PATCH v2] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

This patch adds device tree entry for MFC v6 in the Exynos5
SoC. Makes the required changes in the clock files and adds
MFC to the DT device list.

Signed-off-by: Naveen Krishna Chatradhi 
Signed-off-by: Arun Kumar K 
---
 .../devicetree/bindings/media/s5p-mfc.txt  |   27 +
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |7 +++
 arch/arm/boot/dts/exynos5250.dtsi  |6 ++
 arch/arm/mach-exynos/Kconfig   |1 +
 arch/arm/mach-exynos/clock-exynos5.c   |2 +-
 arch/arm/mach-exynos/mach-exynos5-dt.c |   56 
 6 files changed, 98 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt

diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt 
b/Documentation/devicetree/bindings/media/s5p-mfc.txt
new file mode 100644
index 000..9a74d09
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -0,0 +1,27 @@
+* Samsung Multi Format Codec (MFC)
+
+Mult Format Codec (MFC) is the IP present in Samsung SoCs which
+supports high resolution decoding and encoding functionalities.
+The MFC device driver is a v4l2 driver which can encode/decode
+video raw/elementary streams and has support for all popular
+video codecs.
+
+Required properties:
+  - compatible : value should be either one among the following
+   (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
+   (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
+
+  - reg : Physical base address of the IP registers and length of memory
+ mapped region.
+
+  - interrupts : MFC interupt number to the CPU.
+
+  - samsung,mfc-r : Base address of the first memory bank used by MFC
+   for DMA contiguous memory allocation.
+
+  - samsung,mfc-r-size : Size of the first memory bank.
+
+  - samsung,mfc-l : Base address of the second memory bank used by MFC
+   for DMA contiguous memory allocation.
+
+  - samsung,mfc-l-size : Size of the second memory bank.
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts 
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348..5824c97 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -109,4 +109,11 @@
spi_2: spi@12d4 {
status = "disabled";
};
+
+   mfc {
+   samsung,mfc-r = <0x4300>;
+   samsung,mfc-r-size = <8388608>;
+   samsung,mfc-l = <0x5100>;
+   samsung,mfc-l-size = <8388608>;
+   };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index b55794b..5df2f99 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -62,6 +62,12 @@
interrupts = <0 42 0>;
};
 
+   mfc {
+   compatible = "samsung,mfc-v6";
+   reg = <0x1100 0x1>;
+   interrupts = <0 96 0>;
+   };
+
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E 0x100>;
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 195b50e..8ddc26a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -64,6 +64,7 @@ config SOC_EXYNOS5250
select SAMSUNG_DMADEV
select S5P_PM if PM
select S5P_SLEEP if PM
+   select S5P_DEV_MFC
help
  Enable EXYNOS5250 SoC support
 
diff --git a/arch/arm/mach-exynos/clock-exynos5.c 
b/arch/arm/mach-exynos/clock-exynos5.c
index eb3f4fc..461a721 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -669,7 +669,7 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit= (1 << 25),
}, {
.name   = "mfc",
-   .devname= "s5p-mfc",
+   .devname= "s5p-mfc-v6",
.enable = exynos5_clk_ip_mfc_ctrl,
.ctrlbit= (1 << 0),
}, {
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c 
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index e707eb1..0f131da 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,6 +11,8 @@
 
 #include 
 #include 
+#include 
+#include 
 
 #include 
 #include 
@@ -18,6 +20,7 @@
 
 #include 
 #include 
+#include 
 
 #include "common.h"
 
@@ -64,6 +67,7 @@ static const struct of_dev_auxdata 
exynos5250_auxdata_lookup[] __initconst = {
"exynos-gsc.2", NULL),
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
"exynos-gsc.3", NULL),
+   OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000

Re: [PATCH v2] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

Hi Sylwester,
Thank you for the comments.
Will make the necessary changes.

Regards
Arun

On Thu, Sep 13, 2012 at 1:54 AM, Sylwester Nawrocki 
 wrote:
> Just a few small comments...
>
>
> On 09/12/2012 03:34 PM, Arun Kumar K wrote:
>>
>> This patch adds device tree entry for MFC v6 in the Exynos5
>> SoC. Makes the required changes in the clock files and adds
>> MFC to the DT device list.
>>
>> Signed-off-by: Naveen Krishna Chatradhi
>> Signed-off-by: Arun Kumar K
>> ---
>
> ...
>>
>> diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt
>> b/Documentation/devicetree/bindings/media/s5p-mfc.txt
>>
>> new file mode 100644
>> index 000..9a74d09
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
>> @@ -0,0 +1,27 @@
>> +* Samsung Multi Format Codec (MFC)
>> +
>> +Mult Format Codec (MFC) is the IP present in Samsung SoCs which
>
>
> Mult -> Multi
>
>
>> +supports high resolution decoding and encoding functionalities.
>> +The MFC device driver is a v4l2 driver which can encode/decode
>> +video raw/elementary streams and has support for all popular
>> +video codecs.
>> +
>> +Required properties:
>> +  - compatible : value should be either one among the following
>> +   (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
>> +   (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
>> +
>> +  - reg : Physical base address of the IP registers and length of memory
>> + mapped region.
>> +
>> +  - interrupts : MFC interupt number to the CPU.
>
>
> interupt -> interrupt
>
>
>> +
>> +  - samsung,mfc-r : Base address of the first memory bank used by MFC
>> +   for DMA contiguous memory allocation.
>> +
>> +  - samsung,mfc-r-size : Size of the first memory bank.
>> +
>> +  - samsung,mfc-l : Base address of the second memory bank used by MFC
>> +   for DMA contiguous memory allocation.
>> +
>
> ...
>
>> +struct mfc_dt_meminfo {
>> +   unsigned long loff;
>> +   unsigned long lsize;
>> +   unsigned long roff;
>> +   unsigned long rsize;
>> +};
>> +
>> +int fdt_find_mfc_mem(unsigned long node, const char *uname, int depth,
>> +   void *data)
>> +{
>> +   __be32 *prop;
>> +   unsigned long len;
>> +   struct mfc_dt_meminfo *mfc_mem = (struct mfc_dt_meminfo *)data;
>
>
> No need for explicit cast from void *.
>
>
>> +   if (of_flat_dt_is_compatible(node, "samsung,mfc-v6")) {
>
>
> Might be worth to change it to
>
> if (!of_flat_dt_is_compatible(node, "samsung,mfc-v6"))
> return 0;
>
> and avoid indentation.
>
>> +   prop = of_get_flat_dt_prop(node, "samsung,mfc-l",&len);
>> +   if (!prop)
>> +   return 0;
>> +   mfc_mem->loff = of_read_ulong(prop, len/4);
>> +
>> +   prop = of_get_flat_dt_prop(node,
>> "samsung,mfc-l-size",&len);
>> +   if (!prop)
>> +   return 0;
>> +   mfc_mem->lsize = of_read_ulong(prop, len/4);
>> +
>> +   prop = of_get_flat_dt_prop(node, "samsung,mfc-r",&len);
>> +   if (!prop)
>> +   return 0;
>> +   mfc_mem->roff = of_read_ulong(prop, len/4);
>> +
>> +   prop = of_get_flat_dt_prop(node,
>> "samsung,mfc-r-size",&len);
>> +   if (!prop)
>> +   return 0;
>> +   mfc_mem->rsize = of_read_ulong(prop, len/4);
>> +
>> +   return 1;
>> +   }
>> +   return 0;
>> +}
>
>
> --
> Regards,
> Sylwester
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at  
> http://vger.kernel.org/majordomo-info.htmlN‹§²æìr¸›yúèšØb²X¬¶Ç§vØ^–)Þº{.nÇ+‰·¥Š{±±©¬ºx,¡È§¶›¡Ü¨}©ž²Æ zÚ&j:+v‰¨¾«‘êçzZ+€Ê+zf£¢·hšˆ§~†­†Ûiÿûàz¹®w¥¢¸?™¨è­Ú&¢)ߢf

[PATCH v3] Add MFC device tree support

[Arun Kumar K]

This patch adds the device tree entries for MFC on Exynos5.
This is rebased to the linux-samsung for-next branch.

Changelog v3
- Addressed review comments given by Sylwester Nawrocki
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg12340.html

Changelog v2
- Use fdt functions to parse dtsi file for mfc memory info

Changelog v1
- Moved board specific DT information to different dtsi file
- Changed compatible name for the device
- Addressed other review comments

Arun Kumar K (1):
  ARM: EXYNOS: Add MFC device tree support

 .../devicetree/bindings/media/s5p-mfc.txt  |   27 ++
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |7 +++
 arch/arm/boot/dts/exynos5250.dtsi  |6 ++
 arch/arm/mach-exynos/Kconfig   |1 +
 arch/arm/mach-exynos/clock-exynos5.c   |2 +-
 arch/arm/mach-exynos/mach-exynos5-dt.c |   55 
 6 files changed, 97 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt

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[PATCH v3] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

This patch adds device tree entry for MFC v6 in the Exynos5
SoC. Makes the required changes in the clock files and adds
MFC to the DT device list.

Signed-off-by: Naveen Krishna Chatradhi 
Signed-off-by: Arun Kumar K 
---
 .../devicetree/bindings/media/s5p-mfc.txt  |   27 ++
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |7 +++
 arch/arm/boot/dts/exynos5250.dtsi  |6 ++
 arch/arm/mach-exynos/Kconfig   |1 +
 arch/arm/mach-exynos/clock-exynos5.c   |2 +-
 arch/arm/mach-exynos/mach-exynos5-dt.c |   55 
 6 files changed, 97 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt

diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt 
b/Documentation/devicetree/bindings/media/s5p-mfc.txt
new file mode 100644
index 000..f95e775
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -0,0 +1,27 @@
+* Samsung Multi Format Codec (MFC)
+
+Multi Format Codec (MFC) is the IP present in Samsung SoCs which
+supports high resolution decoding and encoding functionalities.
+The MFC device driver is a v4l2 driver which can encode/decode
+video raw/elementary streams and has support for all popular
+video codecs.
+
+Required properties:
+  - compatible : value should be either one among the following
+   (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
+   (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
+
+  - reg : Physical base address of the IP registers and length of memory
+ mapped region.
+
+  - interrupts : MFC interrupt number to the CPU.
+
+  - samsung,mfc-r : Base address of the first memory bank used by MFC
+   for DMA contiguous memory allocation.
+
+  - samsung,mfc-r-size : Size of the first memory bank.
+
+  - samsung,mfc-l : Base address of the second memory bank used by MFC
+   for DMA contiguous memory allocation.
+
+  - samsung,mfc-l-size : Size of the second memory bank.
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts 
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348..5824c97 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -109,4 +109,11 @@
spi_2: spi@12d4 {
status = "disabled";
};
+
+   mfc {
+   samsung,mfc-r = <0x4300>;
+   samsung,mfc-r-size = <8388608>;
+   samsung,mfc-l = <0x5100>;
+   samsung,mfc-l-size = <8388608>;
+   };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index b55794b..5df2f99 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -62,6 +62,12 @@
interrupts = <0 42 0>;
};
 
+   mfc {
+   compatible = "samsung,mfc-v6";
+   reg = <0x1100 0x1>;
+   interrupts = <0 96 0>;
+   };
+
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E 0x100>;
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 195b50e..8ddc26a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -64,6 +64,7 @@ config SOC_EXYNOS5250
select SAMSUNG_DMADEV
select S5P_PM if PM
select S5P_SLEEP if PM
+   select S5P_DEV_MFC
help
  Enable EXYNOS5250 SoC support
 
diff --git a/arch/arm/mach-exynos/clock-exynos5.c 
b/arch/arm/mach-exynos/clock-exynos5.c
index eb3f4fc..461a721 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -669,7 +669,7 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit= (1 << 25),
}, {
.name   = "mfc",
-   .devname= "s5p-mfc",
+   .devname= "s5p-mfc-v6",
.enable = exynos5_clk_ip_mfc_ctrl,
.ctrlbit= (1 << 0),
}, {
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c 
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index e707eb1..243ba63 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,6 +11,8 @@
 
 #include 
 #include 
+#include 
+#include 
 
 #include 
 #include 
@@ -18,6 +20,7 @@
 
 #include 
 #include 
+#include 
 
 #include "common.h"
 
@@ -64,6 +67,7 @@ static const struct of_dev_auxdata 
exynos5250_auxdata_lookup[] __initconst = {
"exynos-gsc.2", NULL),
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
"exynos-gsc.3", NULL),
+   OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000

Re: [PATCH v3] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

Hi Karol,
Thank you for the review.
Please find my comments inline.

On Wed, Sep 19, 2012 at 3:08 PM, Karol Lewandowski  
wrote:
> On 09/14/2012 05:38 PM, Arun Kumar K wrote:
>
>> This patch adds device tree entry for MFC v6 in the Exynos5
>> SoC. Makes the required changes in the clock files and adds
>> MFC to the DT device list.
>
>
> Hi!
>
> Thanks for working on this patch. Please allow me to add few
> comments.
>
>
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
>> b/arch/arm/boot/dts/exynos5250.dtsi
>> index b55794b..5df2f99 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -62,6 +62,12 @@
>>   interrupts = <0 42 0>;
>>   };
>>
>> + mfc {
>
>
> Nitpick - shouldn't node names be generic?  MFC is strictly
> samsung specific, something like "codec"/"video-codec" would make
> more sense (IMVHO). I would prefer to see address too (e.g.
> codec@0x1100).
>
> However, I do see that rtc below doesn't specify address in node too,
> so maybe I'm missing something here.
>

Yes codec makes it more generic.
I too dont see the addresses used everywhere in node names.
If somebody can please suggest which one is better
mfc OR codec OR codec@0x1100 as node name.


>
>>
>> +struct mfc_dt_meminfo {
>> + unsigned long loff;
>> + unsigned long lsize;
>> + unsigned long roff;
>> + unsigned long rsize;
>
>
>   char *compatible;
>
>> +};
>> +
>> +int fdt_find_mfc_mem(unsigned long node, const char *uname, int depth,
>> + void *data)
>> +{
>> + __be32 *prop;
>> + unsigned long len;
>> + struct mfc_dt_meminfo *mfc_mem = data;
>> +
>> + if (!of_flat_dt_is_compatible(node, "samsung,mfc-v6"))
>> + return 0;
>
>
>   if (!of_flat_dt_is_compatible(node, mfc_mem->compatible))
> return 0;
>
>> +
>> + prop = of_get_flat_dt_prop(node, "samsung,mfc-l", &len);
>> + if (!prop)
>> + return 0;
>> + mfc_mem->loff = of_read_ulong(prop, len/4);
>> +
>> + prop = of_get_flat_dt_prop(node, "samsung,mfc-l-size", &len);
>> + if (!prop)
>> + return 0;
>> + mfc_mem->lsize = of_read_ulong(prop, len/4);
>> +
>> + prop = of_get_flat_dt_prop(node, "samsung,mfc-r", &len);
>> + if (!prop)
>> + return 0;
>> + mfc_mem->roff = of_read_ulong(prop, len/4);
>> +
>> + prop = of_get_flat_dt_prop(node, "samsung,mfc-r-size", &len);
>> + if (!prop)
>> + return 0;
>> + mfc_mem->rsize = of_read_ulong(prop, len/4);
>> +
>> + return 1;
>> +}
>
>
> Above function could be reused for mfc-v5 (exynos4-dt.c) if compatible
> string weren't hardcoded. Thus, please consider changing that and
> moving this function to some common(.c?) file - you can see one possible
> solution inline.
>

Yes I can move it to common.c file and the structure definition to common.h
file for function reusability. Will make this change.

>> +
>> +static void __init exynos5_reserve(void)
>> +{
>> + struct mfc_dt_meminfo mfc_mem;
>
>
> mfc_mem.compatible = "samsung,mfc-v6";
>
>> +
>> + /* Reserve memory for MFC only if it's available */
>> + if (of_scan_flat_dt(fdt_find_mfc_mem, &mfc_mem))
>> + s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
>> + mfc_mem.lsize);
>> +}
>> +
>>  DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
>>   /* Maintainer: Kukjin Kim  */
>>   .init_irq   = exynos5_init_irq,
>> @@ -94,4 +148,5 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened 
>> Device Tree)")
>>   .timer  = &exynos4_timer,
>>   .dt_compat  = exynos5250_dt_compat,
>>   .restart= exynos5_restart,
>> + .reserve= exynos5_reserve,
>>  MACHINE_END
>
>
> Regards,
> --
> Karol Lewandowski | Samsung Poland R&D Center | Linux/Platform
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" 
> in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v4] Add MFC device tree support

[Arun Kumar K]

This patch adds the device tree entries for MFC on Exynos5.
This is rebased to the linux-samsung for-next branch.

Changelog v4
- Addressed review comments from Karol Lewandowski
http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/12703

Changelog v3
- Addressed review comments given by Sylwester Nawrocki
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg12340.html

Changelog v2
- Use fdt functions to parse dtsi file for mfc memory info

Changelog v1
- Moved board specific DT information to different dtsi file
- Changed compatible name for the device
- Addressed other review comments

Arun Kumar K (1):
  ARM: EXYNOS: Add MFC device tree support

 .../devicetree/bindings/media/s5p-mfc.txt  |   27 ++
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |7 
 arch/arm/boot/dts/exynos5250.dtsi  |6 +++
 arch/arm/mach-exynos/Kconfig   |1 +
 arch/arm/mach-exynos/clock-exynos5.c   |2 +-
 arch/arm/mach-exynos/common.c  |   37 
 arch/arm/mach-exynos/common.h  |   10 +
 arch/arm/mach-exynos/mach-exynos5-dt.c |   16 
 8 files changed, 105 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt

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[PATCH v4] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

This patch adds device tree entry for MFC v6 in the Exynos5
SoC. Makes the required changes in the clock files and adds
MFC to the DT device list.

Signed-off-by: Naveen Krishna Chatradhi 
Signed-off-by: Arun Kumar K 
---
 .../devicetree/bindings/media/s5p-mfc.txt  |   27 ++
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |7 
 arch/arm/boot/dts/exynos5250.dtsi  |6 +++
 arch/arm/mach-exynos/Kconfig   |1 +
 arch/arm/mach-exynos/clock-exynos5.c   |2 +-
 arch/arm/mach-exynos/common.c  |   37 
 arch/arm/mach-exynos/common.h  |   10 +
 arch/arm/mach-exynos/mach-exynos5-dt.c |   16 
 8 files changed, 105 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt

diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt 
b/Documentation/devicetree/bindings/media/s5p-mfc.txt
new file mode 100644
index 000..f95e775
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -0,0 +1,27 @@
+* Samsung Multi Format Codec (MFC)
+
+Multi Format Codec (MFC) is the IP present in Samsung SoCs which
+supports high resolution decoding and encoding functionalities.
+The MFC device driver is a v4l2 driver which can encode/decode
+video raw/elementary streams and has support for all popular
+video codecs.
+
+Required properties:
+  - compatible : value should be either one among the following
+   (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
+   (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
+
+  - reg : Physical base address of the IP registers and length of memory
+ mapped region.
+
+  - interrupts : MFC interrupt number to the CPU.
+
+  - samsung,mfc-r : Base address of the first memory bank used by MFC
+   for DMA contiguous memory allocation.
+
+  - samsung,mfc-r-size : Size of the first memory bank.
+
+  - samsung,mfc-l : Base address of the second memory bank used by MFC
+   for DMA contiguous memory allocation.
+
+  - samsung,mfc-l-size : Size of the second memory bank.
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts 
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348..99890ec 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -109,4 +109,11 @@
spi_2: spi@12d4 {
status = "disabled";
};
+
+   codec@1100 {
+   samsung,mfc-r = <0x4300>;
+   samsung,mfc-r-size = <8388608>;
+   samsung,mfc-l = <0x5100>;
+   samsung,mfc-l-size = <8388608>;
+   };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index b55794b..d2ae4ff 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -62,6 +62,12 @@
interrupts = <0 42 0>;
};
 
+   codec@1100 {
+   compatible = "samsung,mfc-v6";
+   reg = <0x1100 0x1>;
+   interrupts = <0 96 0>;
+   };
+
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E 0x100>;
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4372075..a0677f6 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -64,6 +64,7 @@ config SOC_EXYNOS5250
select SAMSUNG_DMADEV
select S5P_PM if PM
select S5P_SLEEP if PM
+   select S5P_DEV_MFC
help
  Enable EXYNOS5250 SoC support
 
diff --git a/arch/arm/mach-exynos/clock-exynos5.c 
b/arch/arm/mach-exynos/clock-exynos5.c
index f3171c3..452316b 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -669,7 +669,7 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit= (1 << 25),
}, {
.name   = "mfc",
-   .devname= "s5p-mfc",
+   .devname= "s5p-mfc-v6",
.enable = exynos5_clk_ip_mfc_ctrl,
.ctrlbit= (1 << 0),
}, {
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 715b690..90e484e 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -22,6 +22,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -1043,3 +1044,39 @@ static int __init exynos_init_irq_eint(void)
return 0;
 }
 arch_initcall(exynos_init_irq_eint);
+
+int exynos_fdt_find_mfc_mem(unsigned long node, const char *uname,
+   int depth, void *data)
+{
+   __be32 *prop;
+   unsigned long len;
+   struct mfc_dt_meminfo *mfc_mem = dat

RE: [PATCH v4] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

Hi Kukjin,

As suggested by you, the function exynos_fdt_find_mfc_mem() can be moved to 
plat-samsung.
I feel plat-samsung/s5p-dev-mfc.c would be a good place. Hope it is ok?
Also I will wrap it with #ifdef CONFIG_OF for non-dt mode.
I will post the updated patch with the suggested changes.

Regards
Arun

On Wed, Sep 26, 2012 at 7:42 AM, Kukjin Kim  wrote:
> Karol Lewandowski wrote:
>>
>> On 09/22/2012 08:07 PM, Arun Kumar K wrote:
>>
>> > This patch adds device tree entry for MFC v6 in the Exynos5
>> > SoC. Makes the required changes in the clock files and adds
>> > MFC to the DT device list.
>> >
>> > Signed-off-by: Naveen Krishna Chatradhi 
>> > Signed-off-by: Arun Kumar K 
>>
>>
>> Looks good for me. FWIW, I could probably add
>>
>> Acked-by: Karol Lewandowski 
>>
> Happens following build error with exynos4_defconfig because of non-DT ?
>
> arch/arm/mach-exynos/common.c: In function 'exynos_fdt_find_mfc_mem':
> arch/arm/mach-exynos/common.c:1058: error: implicit declaration of function 
> 'of_flat_dt_is_compatible'
> arch/arm/mach-exynos/common.c:1061: error: implicit declaration of function 
> 'of_get_flat_dt_prop'
> arch/arm/mach-exynos/common.c:1061: warning: assignment makes pointer from 
> integer without a cast
> arch/arm/mach-exynos/common.c:1064: error: implicit declaration of function 
> 'of_read_ulong'
> arch/arm/mach-exynos/common.c:1066: warning: assignment makes pointer from 
> integer without a cast
> arch/arm/mach-exynos/common.c:1071: warning: assignment makes pointer from 
> integer without a cast
> arch/arm/mach-exynos/common.c:1076: warning: assignment makes pointer from 
> integer without a cast
> make[1]: *** [arch/arm/mach-exynos/common.o] Error 1
>
> And I think, firstly we could move the function exynos_fdt_find_mfc_mem() 
> into plat-samsung/ for using on other Samsung stuff such as s5pv210 and need 
> to enclose '#ifdef CONFIG_OF" for non-DT?
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim , Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" 
> in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at  
> http://vger.kernel.org/majordomo-info.htmlN‹§²æìr¸›yúèšØb²X¬¶Ç§vØ^–)Þº{.nÇ+‰·¥Š{±±©¬ºx,¡È§¶›¡Ü¨}©ž²Æ zÚ&j:+v‰¨¾«‘êçzZ+€Ê+zf£¢·hšˆ§~†­†Ûiÿûàz¹®w¥¢¸?™¨è­Ú&¢)ߢf

Re: [PATCH v4] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

Hi Tomasz,

> Maybe the base address and size could be merged into one property with two
> values, as it is done with the reg property? What do you think?
>
>> + codec@1100 {
>> + samsung,mfc-r = <0x4300>;
>> + samsung,mfc-r-size = <8388608>;
>> + samsung,mfc-l = <0x5100>;
>> + samsung,mfc-l-size = <8388608>;
>
> It would look like this:
>
> samsung-mfc-r = <0x4300 0x80>;
> samsung-mfc-l = <0x5100 0x80>;
>

Thanks for the suggestion. It sure looks better this way.
I will include this change and post updated patch.

Regards
ArunN‹§²æìr¸›yúèšØb²X¬¶Ç§vØ^–)Þº{.nÇ+‰·¥Š{±±©¬ºx,¡È§¶›¡Ü¨}©ž²Æ zÚ&j:+v‰¨¾«‘êçzZ+€Ê+zf£¢·hšˆ§~†­†Ûiÿûàz¹®w¥¢¸?™¨è­Ú&¢)ߢf

[PATCH v5] Add MFC device tree support

[Arun Kumar K]

This patch adds the device tree entries for MFC on Exynos5.
This is rebased to the linux-samsung for-next branch.

Changelog v5
- Fixed non-DT compile issue
- Moved fdt mfc parsing function to plat-samsung as suggested by Kukjin Kim
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg12647.html
- Use single property for both base address and size for mfc memory banks
  as suggested by Tomasz Figa
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg12650.html

Changelog v4
- Addressed review comments from Karol Lewandowski
http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/12703

Changelog v3
- Addressed review comments given by Sylwester Nawrocki
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg12340.html

Changelog v2
- Use fdt functions to parse dtsi file for mfc memory info

Changelog v1
- Moved board specific DT information to different dtsi file
- Changed compatible name for the device
- Addressed other review comments

Arun Kumar K (1):
  ARM: EXYNOS: Add MFC device tree support

 .../devicetree/bindings/media/s5p-mfc.txt  |   23 +
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |5 +++
 arch/arm/boot/dts/exynos5250.dtsi  |6 +++
 arch/arm/mach-exynos/Kconfig   |1 +
 arch/arm/mach-exynos/clock-exynos5.c   |2 +-
 arch/arm/mach-exynos/mach-exynos5-dt.c |   16 +
 arch/arm/plat-samsung/devs.c   |1 +
 arch/arm/plat-samsung/include/plat/mfc.h   |   11 ++
 arch/arm/plat-samsung/s5p-dev-mfc.c|   34 
 9 files changed, 98 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt

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[PATCH v5] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

This patch adds device tree entry for MFC v6 in the Exynos5
SoC. Makes the required changes in the clock files and adds
MFC to the DT device list.

Signed-off-by: Naveen Krishna Chatradhi 
Signed-off-by: Arun Kumar K 
---
 .../devicetree/bindings/media/s5p-mfc.txt  |   23 +
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |5 +++
 arch/arm/boot/dts/exynos5250.dtsi  |6 +++
 arch/arm/mach-exynos/Kconfig   |1 +
 arch/arm/mach-exynos/clock-exynos5.c   |2 +-
 arch/arm/mach-exynos/mach-exynos5-dt.c |   16 +
 arch/arm/plat-samsung/devs.c   |1 +
 arch/arm/plat-samsung/include/plat/mfc.h   |   11 ++
 arch/arm/plat-samsung/s5p-dev-mfc.c|   34 
 9 files changed, 98 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt

diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt 
b/Documentation/devicetree/bindings/media/s5p-mfc.txt
new file mode 100644
index 000..67ec3d4
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -0,0 +1,23 @@
+* Samsung Multi Format Codec (MFC)
+
+Multi Format Codec (MFC) is the IP present in Samsung SoCs which
+supports high resolution decoding and encoding functionalities.
+The MFC device driver is a v4l2 driver which can encode/decode
+video raw/elementary streams and has support for all popular
+video codecs.
+
+Required properties:
+  - compatible : value should be either one among the following
+   (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
+   (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
+
+  - reg : Physical base address of the IP registers and length of memory
+ mapped region.
+
+  - interrupts : MFC interrupt number to the CPU.
+
+  - samsung,mfc-r : Base address of the first memory bank used by MFC
+   for DMA contiguous memory allocation and its size.
+
+  - samsung,mfc-l : Base address of the second memory bank used by MFC
+   for DMA contiguous memory allocation and its size.
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts 
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index a352df4..21d4ccd 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -166,4 +166,9 @@
spi_2: spi@12d4 {
status = "disabled";
};
+
+   codec@1100 {
+   samsung,mfc-r = <0x4300 0x80>;
+   samsung,mfc-l = <0x5100 0x80>;
+   };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index dddfd6e..49546bc 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -62,6 +62,12 @@
interrupts = <0 42 0>;
};
 
+   codec@1100 {
+   compatible = "samsung,mfc-v6";
+   reg = <0x1100 0x1>;
+   interrupts = <0 96 0>;
+   };
+
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E 0x100>;
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4372075..a0677f6 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -64,6 +64,7 @@ config SOC_EXYNOS5250
select SAMSUNG_DMADEV
select S5P_PM if PM
select S5P_SLEEP if PM
+   select S5P_DEV_MFC
help
  Enable EXYNOS5250 SoC support
 
diff --git a/arch/arm/mach-exynos/clock-exynos5.c 
b/arch/arm/mach-exynos/clock-exynos5.c
index bab6140..46dfea6 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -664,7 +664,7 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit= (1 << 25),
}, {
.name   = "mfc",
-   .devname= "s5p-mfc",
+   .devname= "s5p-mfc-v6",
.enable = exynos5_clk_ip_mfc_ctrl,
.ctrlbit= (1 << 0),
}, {
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c 
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index fee9dcd..b4ed43a 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,6 +11,8 @@
 
 #include 
 #include 
+#include 
+#include 
 
 #include 
 #include 
@@ -18,6 +20,7 @@
 
 #include 
 #include 
+#include 
 
 #include "common.h"
 
@@ -72,6 +75,7 @@ static const struct of_dev_auxdata 
exynos5250_auxdata_lookup[] __initconst = {
"exynos-gsc.2", NULL),
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
"exynos-gsc.3", NULL),
+   OF_DEV_AUXDATA(&qu

Re: [PATCH v5] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

Hi all,
Any comments / acks on this?

Regards
Arun

On Thu, Sep 27, 2012 at 10:39 PM, Arun Kumar K  wrote:
> This patch adds device tree entry for MFC v6 in the Exynos5
> SoC. Makes the required changes in the clock files and adds
> MFC to the DT device list.
>
> Signed-off-by: Naveen Krishna Chatradhi 
> Signed-off-by: Arun Kumar K 
> ---
>  .../devicetree/bindings/media/s5p-mfc.txt  |   23 +
>  arch/arm/boot/dts/exynos5250-smdk5250.dts  |5 +++
>  arch/arm/boot/dts/exynos5250.dtsi  |6 +++
>  arch/arm/mach-exynos/Kconfig   |1 +
>  arch/arm/mach-exynos/clock-exynos5.c   |2 +-
>  arch/arm/mach-exynos/mach-exynos5-dt.c |   16 +
>  arch/arm/plat-samsung/devs.c   |1 +
>  arch/arm/plat-samsung/include/plat/mfc.h   |   11 ++
>  arch/arm/plat-samsung/s5p-dev-mfc.c|   34 
> 
>  9 files changed, 98 insertions(+), 1 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/media/s5p-mfc.txt
>
> diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt 
> b/Documentation/devicetree/bindings/media/s5p-mfc.txt
> new file mode 100644
> index 000..67ec3d4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
> @@ -0,0 +1,23 @@
> +* Samsung Multi Format Codec (MFC)
> +
> +Multi Format Codec (MFC) is the IP present in Samsung SoCs which
> +supports high resolution decoding and encoding functionalities.
> +The MFC device driver is a v4l2 driver which can encode/decode
> +video raw/elementary streams and has support for all popular
> +video codecs.
> +
> +Required properties:
> +  - compatible : value should be either one among the following
> +   (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
> +   (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
> +
> +  - reg : Physical base address of the IP registers and length of memory
> + mapped region.
> +
> +  - interrupts : MFC interrupt number to the CPU.
> +
> +  - samsung,mfc-r : Base address of the first memory bank used by MFC
> +   for DMA contiguous memory allocation and its size.
> +
> +  - samsung,mfc-l : Base address of the second memory bank used by MFC
> +   for DMA contiguous memory allocation and its size.
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts 
> b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index a352df4..21d4ccd 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -166,4 +166,9 @@
> spi_2: spi@12d4 {
> status = "disabled";
> };
> +
> +   codec@1100 {
> +   samsung,mfc-r = <0x4300 0x80>;
> +   samsung,mfc-l = <0x5100 0x80>;
> +   };
>  };
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
> b/arch/arm/boot/dts/exynos5250.dtsi
> index dddfd6e..49546bc 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -62,6 +62,12 @@
> interrupts = <0 42 0>;
> };
>
> +   codec@1100 {
> +   compatible = "samsung,mfc-v6";
> +   reg = <0x1100 0x1>;
> +   interrupts = <0 96 0>;
> +   };
> +
> rtc {
> compatible = "samsung,s3c6410-rtc";
> reg = <0x101E 0x100>;
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index 4372075..a0677f6 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -64,6 +64,7 @@ config SOC_EXYNOS5250
> select SAMSUNG_DMADEV
> select S5P_PM if PM
> select S5P_SLEEP if PM
> +   select S5P_DEV_MFC
> help
>   Enable EXYNOS5250 SoC support
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c 
> b/arch/arm/mach-exynos/clock-exynos5.c
> index bab6140..46dfea6 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -664,7 +664,7 @@ static struct clk exynos5_init_clocks_off[] = {
> .ctrlbit= (1 << 25),
> }, {
> .name   = "mfc",
> -   .devname= "s5p-mfc",
> +   .devname= "s5p-mfc-v6",
> .enable = exynos5_clk_ip_mfc_ctrl,
> .ctrlbit= (1 << 0),
> }, {
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c

Re: [PATCH v5] ARM: EXYNOS: Add MFC device tree support

[Arun Kumar K]

Hi Seungwoo Kim,

Thank you for the review.

>> +
>> + /* Reserve memory for MFC only if it's available */
>> + mfc_mem.compatible = "samsung,mfc-v6";
>> + if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
>
> of_scan_flat_dt() is called but it does not have __init on its
> definition. So this causes section mismatch.
>

The function of_scan_flat_dt is having __init in its definition.
I hope you meant the function s5p_fdt_find_mfc_mem which is not
defined with __init and causing section mismatch.
I will correct this and post an updated patch.

Regards
Arun
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Re: [RFC 01/12] exynos-fimc-is: Adding device tree nodes

[Arun Kumar K]

Hi Sylwester,

Thank you for the review.


>> +Sensor sub-nodes:
>> +
>> +FIMC-IS IP supports custom built sensors to be controlled exclusively by
>> +the FIMC-IS firmware. These sensor properties are to be defined here.
>

[snip]

>
> Defining image sensor nodes in a standard way as ISP I2C bus controller
> nodes has an disadvantage that we need dummy I2C bus controller driver,
> at least this is how I have written the driver for Exynos4x12. In some
> version of it I had sensor nodes put in a isp-i2c fimc-is sub-node, but
> then there was an issue that this was not a fully specified I2C bus
> controller node.
>
> You can refer to my exynos4 fimc-is patch series for details on how this
> is now implemented.
>
> Handling the image sensor in a standard way, as regular I2C client devices
> has an advantage that we can put pinctrl properties in relevant device
> nodes,
> where available, which more closely describes the hardware structure.
>
> I'm not really sure in 100% if all this complication is required. It would
> allow to use same DT blob for different Imaging Subsystem SW architecture.
> For example some parts of functionality handled currently by FIMC-IS (ARM
> Cortex-A5) could be moved to host CPU, without any change in the device
> tree structure. The kernel could decide e.g. if it uses image sensor driver
> implemented in the ISP firmware, or a driver run on the host CPU.
>
> What do you think ?
>

I have seen your Exynos4 FIMC-IS patchset and you have made a dummy
I2C sensor driver there.
That mode would work fine in Exynos4 since the sensor and ISP will be used
by the same media controller pipeline. So the ISP component in the pipeline
will ensure that the HW is initialized and sensor is working.

But in Exynos5, we are using sensor in pipeline0 and ISP in pipeline1.
So there is a possibility of using sensor subdev independently
without using pipeline1 ISP components.

So with the driver I sent, the pipeline0 can still work like this -->

ISP sensor ---> MIPI-CSIS ---> FIMC-LITE ---> Memory

This cannot be done if a dummy I2C driver is made for ISP sensor.
What is your suggestion on this?

Regards
Arun
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Re: [RFC 01/12] exynos-fimc-is: Adding device tree nodes

[Arun Kumar K]

On Wed, Mar 27, 2013 at 4:21 AM, Sylwester Nawrocki
 wrote:
> On 03/26/2013 01:17 PM, Arun Kumar K wrote:
>>>>
>>>> +Sensor sub-nodes:
>>>> +
>>>> +FIMC-IS IP supports custom built sensors to be controlled exclusively
>>>> by
>>>> +the FIMC-IS firmware. These sensor properties are to be defined here.
>>
>>
>> [snip]
>>
>>> Defining image sensor nodes in a standard way as ISP I2C bus controller
>>> nodes has an disadvantage that we need dummy I2C bus controller driver,
>>> at least this is how I have written the driver for Exynos4x12. In some
>>> version of it I had sensor nodes put in a isp-i2c fimc-is sub-node, but
>>> then there was an issue that this was not a fully specified I2C bus
>>> controller node.
>>>
>>> You can refer to my exynos4 fimc-is patch series for details on how this
>>> is now implemented.
>>>
>>> Handling the image sensor in a standard way, as regular I2C client
>>> devices
>>> has an advantage that we can put pinctrl properties in relevant device
>>> nodes,
>>> where available, which more closely describes the hardware structure.
>>>
>>> I'm not really sure in 100% if all this complication is required. It
>>> would
>>> allow to use same DT blob for different Imaging Subsystem SW
>>> architecture.
>>> For example some parts of functionality handled currently by FIMC-IS (ARM
>>> Cortex-A5) could be moved to host CPU, without any change in the device
>>> tree structure. The kernel could decide e.g. if it uses image sensor
>>> driver
>>> implemented in the ISP firmware, or a driver run on the host CPU.
>>>
>>> What do you think ?
>>
>>
>> I have seen your Exynos4 FIMC-IS patchset and you have made a dummy
>> I2C sensor driver there.
>> That mode would work fine in Exynos4 since the sensor and ISP will be used
>> by the same media controller pipeline. So the ISP component in the
>> pipeline
>> will ensure that the HW is initialized and sensor is working.
>>
>> But in Exynos5, we are using sensor in pipeline0 and ISP in pipeline1.
>> So there is a possibility of using sensor subdev independently
>> without using pipeline1 ISP components.
>>
>> So with the driver I sent, the pipeline0 can still work like this -->
>>
>> ISP sensor --->  MIPI-CSIS --->  FIMC-LITE --->  Memory
>>
>> This cannot be done if a dummy I2C driver is made for ISP sensor.
>
>
> Why not ? I'm not sure what the problem is here.
>
> I realize that describing image sensors in DT as standard I2C slave devices
> is not helpful with current firmware architecture. It adds some unnecessary
> complication, OTOH it could simplify the sensors registration and media
> graph
> initialization code, by unifying it for the firmware based ISP specific
> sensors and the external ones with a built-in ISP. Also we could avoid
> having
> the bindings defined by current architecture of the driver.
>
> Nevertheless, coming back to your question, the I2C controller driver would
> be in same module as the FIMC-IS driver. From user space perspective nothing
> changes when you add I2C bus driver and register the sensor in a standard
> way.
> What exactly couldn't be done in the kernel ?


Only issue is with the context sharing.
Right now you can see that the fimc-is context is shared between all
the subdevs.
As all of them are part of the same driver, it is possible.
If sensor is made as an independent i2c device, a separate probe will
be called for it.
For ISP sensor subdev to work independently, it needs to call the
fimc_is_pipeline_* calls
for FW initialization and other configurations for which it needs the
fimc-is main context.

Now there is a workaround here by calling a get_context() macro in
sensor's probe
to get the fimc-is context. This will cause the same context to be
shared and updated by
2 drivers though both are part of fimc-is.
Is this acceptable? Or am I missing some other simple solution of implementing
it in a better way?

Regards
Arun
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Re: [RFC 01/12] exynos-fimc-is: Adding device tree nodes

[Arun Kumar K]

On Wed, Mar 27, 2013 at 7:17 PM, Sylwester Nawrocki
 wrote:
> On 03/27/2013 05:31 AM, Arun Kumar K wrote:
>> On Wed, Mar 27, 2013 at 4:21 AM, Sylwester Nawrocki
>>  wrote:
>>> On 03/26/2013 01:17 PM, Arun Kumar K wrote:
> [...]
>> Only issue is with the context sharing.
>> Right now you can see that the fimc-is context is shared between all
>> the subdevs.
>> As all of them are part of the same driver, it is possible.
>> If sensor is made as an independent i2c device, a separate probe will
>> be called for it.
>> For ISP sensor subdev to work independently, it needs to call the
>> fimc_is_pipeline_* calls
>> for FW initialization and other configurations for which it needs the
>> fimc-is main context.
>>
>> Now there is a workaround here by calling a get_context() macro in
>> sensor's probe
>> to get the fimc-is context. This will cause the same context to be
>> shared and updated by
>> 2 drivers though both are part of fimc-is.
>> Is this acceptable? Or am I missing some other simple solution of 
>> implementing
>> it in a better way?
>
> OK, thanks for the explanation.
>
> I can think of at least one possible way to get hold of the fimc-is
> context in the subdev. For instance, in subdev's .registered callback
> you get a pointer to struct v4l2_device, which is normally embedded
> in a top level driver's private data. Then with container_of()
> you could get hold of required data at the fimc-is driver.

But as per current implementation, it is not the fimc-is driver that is
registering the ISP subdevs. It will be registered from the
media controller driver. So fimc-is context cannot be obtained by
just using container_of().

>
> But... to make the subdev drivers reuse possible subdevs should
> normally not be required to know the internals of a host driver they
> are registered to. And it looks a bit unusual to have fimc_pipeline_*
> calls in the sensor's operation handlers.

fimc_pipeline_* I mentioned is not the media controller pipeline.
In the fimc-is driver, all the subdevs just implement the interface part.
All the core functionalities happen in fimc-is-pipeline.c and
fimc-is-interface.c.
Since these ISP subdevs (sensor, isp, scc, scp) are not independent
devices, all are controlled by the ISP firmware whose configuration and
interface is done from the fimc_is_pipeline_* and fimc_is_itf_* functions.
So all the ISP subdevs including sensor need to call these functions.

>
> I thought that the subdevs could provide basic methods and it would
> be the top level media driver that would resolve any dependencies
> in calling required subdev ops, according to media graph configuration
> done by the user on /dev/media?.
>

In case of ISP subdevs (isp, scc and scp), there is not much configuration
that the media device can do. Only control possible is to turn on/off
specific scaler DMA outputs which can be done via the video node ioctls.
The role of media device here is mostly to convey the pipeline structure
to the user. For eg. it is not possible to directly connect isp (sd)
--> scp (sd).
In the media controller pipeline1 implementation, we were planning to
put immutable links between these subdevs. Is that acceptable?


> The media driver has a list of media entities (subdevices and video
> nodes) and I though it could coordinate any requests involving whole
> video/image processing pipeline originating from /dev/video ioctls/fops.
>
> So for instance if /dev/video in this pipeline is opened
>
> sensor (sd) -> mipi-csis (sd) -> fimc-lite (sd) -> memory (/dev/video)
>
> it would call s_power operation on the above subdevs and additionally
> on e.g. the isp subdev (or any other we choose as a main subdev
> implementing the FIMC-IS slave interface).
>
> Then couldn't it be done that video node ioctls invoke pipeline
> operations, and the media device resolves any dependencies/calls
> order, as in case of the exynos4 driver ?

On Exynos4 subdevs, it is well and good since all the subdevs are
independent IPs. Here in ISP since the same IP can take one input and
provide multiple outputs, we designed them as separate subdevs. So
here we cannot make the subdevs independent of each other where only
the sequence / dependencies is controlled from the media device.

Regards
Arun
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Re: [RFC 01/12] exynos-fimc-is: Adding device tree nodes

[Arun Kumar K]

Hi Sylwester,

Sorry for the late reply.

>>>
>>> OK, thanks for the explanation.
>>>
>>> I can think of at least one possible way to get hold of the fimc-is
>>> context in the subdev. For instance, in subdev's .registered callback
>>> you get a pointer to struct v4l2_device, which is normally embedded
>>> in a top level driver's private data. Then with container_of()
>>> you could get hold of required data at the fimc-is driver.
>>
>>
>> But as per current implementation, it is not the fimc-is driver that is
>> registering the ISP subdevs. It will be registered from the
>> media controller driver. So fimc-is context cannot be obtained by
>> just using container_of().
>
>
> I guess best option would be to have a function to get the IS slave
> interface driver context at the sensor subdev exported by the IS driver
> module, as you suggested previously.

Ok I will make the sensor as i2c device and check what is the best
way to get the IS context in sensor subdev.

>
> You still could obtain the fimc-is object from the media device private
> data structure, since the media device has normally a list of its all
> entities in one form or the other. But the sensor would need to know
> details of the media device, which makes it a bit pointless.
>
> Nevertheless, my main concern is the DT binding. Sharing the sensor
> subdev driver might not be that important at the moment, we are talking
> about 300..500 lines of code per ISP driver currently anyway.
>
> More important is to have the hardware described in a standard way, so
> when the firmware changes there is no need to change the DT bindings.
>

Yes that's right. Need to define the hardware in a generic way regardless
of what the firmware is doing.


>>>
>>
>> In case of ISP subdevs (isp, scc and scp), there is not much configuration
>> that the media device can do. Only control possible is to turn on/off
>> specific scaler DMA outputs which can be done via the video node ioctls.
>> The role of media device here is mostly to convey the pipeline structure
>> to the user. For eg. it is not possible to directly connect isp (sd)
>> -->  scp (sd).
>> In the media controller pipeline1 implementation, we were planning to
>> put immutable links between these subdevs. Is that acceptable?
>
>
> Not sure I understand which links you mean exactly. Could you post the
> media graph generated by media-ctl (--print-dot) ?
>
> If you're talking about the on-the-fly (FIFO) links, then it probably
> makes sense. The media device driver should respond to the link_notify
> events and not to allow data links unsupported in the hardware. If you
> create immutable OTF links, then how would you switch between DMA and
> OTF interfaces ? Or can all processing blocks of the ISP chain work
> simultaneously with the DMA and OTF ? The FD block, for instance, can fed
> data from memory _or_ from previous processing block in the chain, right ?
> You will need a user interface to control which input is used and the
> links configuration seems most natural here.

Yes I agree to that. Though in the current driver, there are no subdevs which
can change between DMA <-> OTF inputs, in future versions we might add it.
So link configuration option will be provided.


>
>
>>> The media driver has a list of media entities (subdevices and video
>>> nodes) and I though it could coordinate any requests involving whole
>>> video/image processing pipeline originating from /dev/video ioctls/fops.
>>>
>>> So for instance if /dev/video in this pipeline is opened
>>>
>>> sensor (sd) ->  mipi-csis (sd) ->  fimc-lite (sd) ->  memory (/dev/video)
>>>
>>> it would call s_power operation on the above subdevs and additionally
>>> on e.g. the isp subdev (or any other we choose as a main subdev
>>> implementing the FIMC-IS slave interface).
>>>
>>> Then couldn't it be done that video node ioctls invoke pipeline
>>> operations, and the media device resolves any dependencies/calls
>>> order, as in case of the exynos4 driver ?
>>
>>
>> On Exynos4 subdevs, it is well and good since all the subdevs are
>> independent IPs. Here in ISP since the same IP can take one input and
>
>
> Not really, there are going to be 2 subdevs exposed by the fimc-is: ISP
> and FD. However FD is still not supported in my last patch series. I was
> planning this for a subsequent kernel release.
>
>
>> provide multiple outputs, we designed them as separate subdevs. So
>> here we cannot make the subdevs independent of each other where only
>> the sequence / dependencies is controlled from the media device.
>
>
> I'm not asking you to make the FIMC-IS subdevs more self-contained,
> it's of course perfectly fine to have multiple (logical) subdevs exposed
> by a complex device like that. I have been thinking only about the
> sensor driver, since the sensors are normally shared across ISPs from
> various chip manufacturers. But let us leave this topic for now.
>
> BTW, in my interpretation FIMC-IS is a collection of IPs/peripheral
> devices, not a sing

[PATCH] clk: Exynos5250: Fix HDMI clock number in documentation

[Arun Kumar K]

This patch corrects the HDMI clock number given wrongly
in the documentation.

Signed-off-by: Arun Kumar K 
---
 Documentation/devicetree/bindings/clock/exynos5250-clock.txt |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt 
b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 781a627..1a05761 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -154,7 +154,7 @@ clock which they consume.
   dsim0341
   dp   342
   mixer343
-  hdmi 345
+  hdmi 344
 
 Example 1: An example of a clock controller node is listed below.
 
-- 
1.7.10.4

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[PATCH] clk: Exynos5250: Add clocks for G3D

[Arun Kumar K]

This patch adds the required clocks for ARM Mali IP
in Exynos5250.

Signed-off-by: Arun Kumar K 
---
 .../devicetree/bindings/clock/exynos5250-clock.txt |2 ++
 drivers/clk/samsung/clk-exynos5250.c   |   12 +++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt 
b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 1a05761..5b93637 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -155,6 +155,8 @@ clock which they consume.
   dp   342
   mixer343
   hdmi 344
+  g3d  345
+  aclk_400_g3d 346
 
 Example 1: An example of a clock controller node is listed below.
 
diff --git a/drivers/clk/samsung/clk-exynos5250.c 
b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..7d87500 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -23,6 +23,7 @@
 #define DIV_CPU0   0x500
 #define SRC_CORE1  0x4204
 #define SRC_TOP0   0x10210
+#define SRC_TOP1   0x10214
 #define SRC_TOP2   0x10218
 #define SRC_GSCL   0x10220
 #define SRC_DISP1_00x1022c
@@ -55,6 +56,7 @@
 #define DIV_PERIC5 0x1056c
 #define GATE_IP_GSCL   0x10920
 #define GATE_IP_MFC0x1092c
+#define GATE_IP_G3D0x10930
 #define GATE_IP_GEN0x10934
 #define GATE_IP_FSYS   0x10944
 #define GATE_IP_PERIC  0x10950
@@ -98,7 +100,7 @@ enum exynos5250_clks {
spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
-   wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
+   wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g3d, aclk_400_g3d,
 
nr_clks,
 };
@@ -112,6 +114,7 @@ static __initdata unsigned long exynos5250_clk_regs[] = {
DIV_CPU0,
SRC_CORE1,
SRC_TOP0,
+   SRC_TOP1,
SRC_TOP2,
SRC_GSCL,
SRC_DISP1_0,
@@ -164,10 +167,12 @@ PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
 PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
 PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
 PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
+PNAME(mout_gpll_p) = { "fin_pll", "fout_gpll" };
 PNAME(mout_mpll_user_p)= { "fin_pll", "sclk_mpll" };
 PNAME(mout_bpll_user_p)= { "fin_pll", "sclk_bpll" };
 PNAME(mout_aclk166_p)  = { "sclk_cpll", "sclk_mpll_user" };
 PNAME(mout_aclk200_p)  = { "sclk_mpll_user", "sclk_bpll_user" };
+PNAME(mout_aclk400_p)  = { "aclk_400_g3d_mid", "sclk_gpll" };
 PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
 PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" };
 PNAME(mout_group1_p)   = { "fin_pll", "fin_pll", "sclk_hdmi27m",
@@ -223,6 +228,9 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = 
{
MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
+   MUX(none, "aclk_400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
+   MUX(none, "sclk_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
+   MUX(none, "mout_aclk400", mout_aclk400_p, SRC_TOP1, 28, 1),
MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
@@ -262,6 +270,7 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = 
{
DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+   DIV(aclk_400_g3d, "aclk_400_g3d", "mout_aclk400", DIV_TOP0, 24, 3),
DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
@@ -462,6 +471,7 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata 
= {
GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
+   GATE(g3d, "g3d", "aclk_400_g3d", GATE_IP_G3D, 0, 0, 0),
 };
 
 static __initdata struct of_device_id ext_clk_match[] = {
-- 
1.7.10.4

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Re: [PATCH] clk: exynos5250: Added MUX, DIV and GATE clocks for Gscaler and MFC

[Arun Kumar K]

NAK

In testing we have seen that, when sysmmu of mfc/gscl is used,
the respective IP clock has to be ON, or else it was malfunctioning.
So for smmu_mfcl and smmu_mfcr, the parent should be mfc
so that we make sure the parent is turned on every time sysmmu is accessed.
Same thing applies to gscl also.

Regards
Arun Kumar

On Tue, Mar 26, 2013 at 9:56 AM, Prasanna Kumar  wrote:
> From: Prasanna Kumar 
>
> Gscaler :
>
>   1. For "aclk_300_gscl",following clocks are added
>   Mux clocks
> mout_aclk_300_gscl_mid,
> mout_aclk_300_gscl_mid1,
> mout_aclk_300_gscl
>   Divider clock
> div_aclk300_gscl
>   Sub-Mux clock ( driven from output of divider clock)
> mout_sub_aclk300
>   2. For "aclk_266_gscl",
>Sub-Mux clock "mout_sub_aclk266" added
>Divider clock has been modified to refer Sub-Mux clock
>
> MFC :
>For "aclk_333"
> Sub-Mux clock "mout_sub_aclk333" added
>Divider clock has been modified to refer Sub-Mux clock
> Signed-off-by: Prasanna Kumar 
> ---
>  drivers/clk/samsung/clk-exynos5250.c |   57 +
>  1 files changed, 43 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5250.c 
> b/drivers/clk/samsung/clk-exynos5250.c
> index e40d6af..40dff9d 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -24,7 +24,9 @@
>  #define DIV_CPU0   0x500
>  #define SRC_CORE1  0x4204
>  #define SRC_TOP0   0x10210
> +#define SRC_TOP1   0x10214
>  #define SRC_TOP2   0x10218
> +#define SRC_TOP3   0x1021C
>  #define SRC_GSCL   0x10220
>  #define SRC_DISP1_00x1022c
>  #define SRC_MAU0x10240
> @@ -112,7 +114,9 @@ static __initdata unsigned long exynos5250_clk_regs[] = {
> DIV_CPU0,
> SRC_CORE1,
> SRC_TOP0,
> +   SRC_TOP1,
> SRC_TOP2,
> +   SRC_TOP3,
> SRC_GSCL,
> SRC_DISP1_0,
> SRC_MAU,
> @@ -167,6 +171,13 @@ PNAME(mout_mpll_user_p)= { "fin_pll", "sclk_mpll" };
>  PNAME(mout_bpll_user_p)= { "fin_pll", "sclk_bpll" };
>  PNAME(mout_aclk166_p)  = { "sclk_cpll", "sclk_mpll_user" };
>  PNAME(mout_aclk200_p)  = { "sclk_mpll_user", "sclk_bpll_user" };
> +PNAME(mout_sub_aclk266_p) = { "fin_pll", "div_aclk266" };
> +PNAME(mout_aclk_300_gscl_mid_p) = { "sclk_mpll_user", "sclk_bpll_user"};
> +PNAME(mout_aclk_300_gscl_mid1_p) = { "sclk_vpll", "sclk_cpll"};
> +PNAME(mout_aclk_300_gscl_p) = { "mout_aclk_300_gscl_mid",
> +   "mout_aclk_300_gscl_mid1" };
> +PNAME(mout_sub_aclk300_p) = { "fin_pll", "div_aclk300_gscl" };
> +PNAME(mout_sub_aclk333_p) = { "fin_pll", "div_aclk333" };
>  PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
>  PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" };
>  PNAME(mout_group1_p)   = { "fin_pll", "fin_pll", "sclk_hdmi27m",
> @@ -220,8 +231,20 @@ struct samsung_mux_clock exynos5250_mux_clks[] 
> __initdata = {
> MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
> MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
> MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
> -   MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
> MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
> +   MUX_A(none, "mout_sub_aclk266", mout_sub_aclk266_p,
> +   SRC_TOP3, 8, 1, "m_sub_aclk266"),
> +   MUX(none, "mout_aclk_300_gscl", mout_aclk_300_gscl_p,
> +   SRC_TOP0, 25, 1),
> +   MUX(none, "mout_aclk_300_gscl_mid", mout_aclk_300_gscl_mid_p,
> +   SRC_TOP0, 24, 1),
> +   MUX(none, "mout_aclk_300_gscl_mid1", mout_aclk_300_gscl_mid1_p,
> +   SRC_TOP1, 12, 1),
> +   MUX_A(none, "mout_sub_aclk300", mout_sub_aclk300_p,
> +   SRC_TOP3, 10, 1, "m_sub_aclk300"),
> +   MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
> +   MUX_A(none, "mout_sub_aclk333", mout_sub_aclk333_p,
> +   SRC_TOP3, 24, 1, "m_sub_aclk333"),
> MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
> MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
> MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
> @@ -257,10 +280,12 @@ struct samsung_div_clock exynos5250_div_clks[] 
> __initdata = {
> DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
> DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
> DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
> -   DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3),
> DIV(none, "aclk166", "

Re: [PATCH] clk: Exynos5250: Add clocks for G3D

[Arun Kumar K]

Hi Tomasz,

Thanks for your review.

>> + DIV(aclk_400_g3d, "aclk_400_g3d", "mout_aclk400", DIV_TOP0, 24,
> 3),
>
> Do you need to export this div clock? If it's a parent of a gate clock,
> then you can simply add CLK_SET_RATE_PARENT flag to the gate clock and
> calling set_rate on it will reconfigure the divider.
>

Yes this clock doesnt need to exported. But the current driver gets this clock
and will fail if its not exported. So that will need some changes from the
driver side also.


>>   DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
>>   DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
>>   DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
>> @@ -462,6 +471,7 @@ struct samsung_gate_clock exynos5250_gate_clks[]
>> __initdata = { GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
>>   GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
>>   GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
>> + GATE(g3d, "g3d", "aclk_400_g3d", GATE_IP_G3D, 0, 0, 0),
>
> This would be then:
>
> GATE(g3d, "g3d", "aclk_400_g3d", GATE_IP_G3D, 0,
> CLK_SET_RATE_PARENT, 0),
>

Yes this would work. I will change it accordingly.

Thanks
Arun
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Re: clk: Exynos5250: Add clocks for G3D

[Arun Kumar K]

Hi Doug,

Thanks for the review.
But as per Tomasz Figa's comment, I will remove the exporting of aclk_400_g3d
to the driver.

Regards
Arun

On Wed, May 22, 2013 at 4:13 AM, Doug Anderson  wrote:
> Arun,
>
> On Tue, May 21, 2013 at 5:36 AM, Arun Kumar K  wrote:
>> @@ -262,6 +270,7 @@ struct samsung_div_clock exynos5250_div_clks[] 
>> __initdata = {
>> DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
>> DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
>> DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
>> +   DIV(aclk_400_g3d, "aclk_400_g3d", "mout_aclk400", DIV_TOP0, 24, 3),
>
> Doh!  I looked at this more and it looks like I missed something.
> You've added this clock to the range assigned for "[Peripheral Clock
> Gates]".  This is not a gate clock but is a div clock.
>
> Perhaps it should be in a different range?  Could make IDs that start
> at 512 or something?
>
> -Doug
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[PATCH v2] clk: Exynos5250: Add clocks for G3D

[Arun Kumar K]

This patch adds the required clocks for ARM Mali IP
in Exynos5250.

Signed-off-by: Arun Kumar K 
---
Changes from v1
- Removed exporting of parent DIV clock for g3d
  as per Tomsz Figa's comment.
---
 .../devicetree/bindings/clock/exynos5250-clock.txt |1 +
 drivers/clk/samsung/clk-exynos5250.c   |   12 +++-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt 
b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 1a05761..b3700cf 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -155,6 +155,7 @@ clock which they consume.
   dp   342
   mixer343
   hdmi 344
+  g3d  345
 
 Example 1: An example of a clock controller node is listed below.
 
diff --git a/drivers/clk/samsung/clk-exynos5250.c 
b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..0d52c19 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -23,6 +23,7 @@
 #define DIV_CPU0   0x500
 #define SRC_CORE1  0x4204
 #define SRC_TOP0   0x10210
+#define SRC_TOP1   0x10214
 #define SRC_TOP2   0x10218
 #define SRC_GSCL   0x10220
 #define SRC_DISP1_00x1022c
@@ -55,6 +56,7 @@
 #define DIV_PERIC5 0x1056c
 #define GATE_IP_GSCL   0x10920
 #define GATE_IP_MFC0x1092c
+#define GATE_IP_G3D0x10930
 #define GATE_IP_GEN0x10934
 #define GATE_IP_FSYS   0x10944
 #define GATE_IP_PERIC  0x10950
@@ -98,7 +100,7 @@ enum exynos5250_clks {
spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
-   wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
+   wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g3d,
 
nr_clks,
 };
@@ -112,6 +114,7 @@ static __initdata unsigned long exynos5250_clk_regs[] = {
DIV_CPU0,
SRC_CORE1,
SRC_TOP0,
+   SRC_TOP1,
SRC_TOP2,
SRC_GSCL,
SRC_DISP1_0,
@@ -164,10 +167,12 @@ PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
 PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
 PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
 PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
+PNAME(mout_gpll_p) = { "fin_pll", "fout_gpll" };
 PNAME(mout_mpll_user_p)= { "fin_pll", "sclk_mpll" };
 PNAME(mout_bpll_user_p)= { "fin_pll", "sclk_bpll" };
 PNAME(mout_aclk166_p)  = { "sclk_cpll", "sclk_mpll_user" };
 PNAME(mout_aclk200_p)  = { "sclk_mpll_user", "sclk_bpll_user" };
+PNAME(mout_aclk400_p)  = { "aclk_400_g3d_mid", "sclk_gpll" };
 PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
 PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" };
 PNAME(mout_group1_p)   = { "fin_pll", "fin_pll", "sclk_hdmi27m",
@@ -223,6 +228,9 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = 
{
MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
+   MUX(none, "aclk_400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
+   MUX(none, "sclk_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
+   MUX(none, "mout_aclk400", mout_aclk400_p, SRC_TOP1, 28, 1),
MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
@@ -262,6 +270,7 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = 
{
DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+   DIV(none, "aclk_400_g3d", "mout_aclk400", DIV_TOP0, 24, 3),
DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
@@ -462,6 +471,7 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata 
= {
 

Re: [PATCH 0/5] clk/exynos5250: add clocks for hdmi subsystem

[Arun Kumar K]

Hi,
Tested this series on snow board and is working fine.

Tested-by: Arun Kumar K 

Regards
Arun

On Mon, Jun 10, 2013 at 4:30 PM, Rahul Sharma  wrote:
> Add clock changes for hdmi subsystem for exynos5250 SoC. These
> include addition of new clocks like mout_hdmi and smmu_tv, associating
> ID to clk_hdmiphy and some essential corrections.
>
> This set is based on kukjin's for-next branch at
> http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git.
>
> Arun Kumar K (1):
>   clk/exynos5250: Fix HDMI clock number in documentation
>
> Rahul Sharma (4):
>   clk/exynos5250: add mout_hdmi mux clock for hdmi
>   clk/exynos5250: add sclk_hdmiphy in the list of special clocks
>   clk/exynos5250: add clock for tv sysmmu
>   clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystem
>
>  .../devicetree/bindings/clock/exynos5250-clock.txt   |   12 +++-
>  drivers/clk/samsung/clk-exynos5250.c |   18 
> +-
>  2 files changed, 24 insertions(+), 6 deletions(-)
>
> --
> 1.7.10.4
>
> --
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> in
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[PATCH 2/3] ARM: dts: Add MFC node for exynos 5420

[Arun Kumar K]

The patch adds MFC nodes for exynos 5420 and for
smdk 5420 board.

Signed-off-by: Arun Kumar K 
---
 arch/arm/boot/dts/exynos5420-smdk5420.dts |5 +
 arch/arm/boot/dts/exynos5420.dtsi |8 
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 08607df..682532c 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -30,4 +30,9 @@
clock-frequency = <2400>;
};
};
+
+   codec@1100 {
+   samsung,mfc-r = <0x4300 0x80>;
+   samsung,mfc-l = <0x5100 0x80>;
+   };
 };
diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 8474d63..cb74356 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -100,4 +100,12 @@
clocks = <&clock 260>, <&clock 131>;
clock-names = "uart", "clk_uart_baud0";
};
+
+   codec@1100 {
+   compatible = "samsung,mfc-v7";
+   reg = <0x1100 0x1>;
+   interrupts = <0 96 0>;
+   clocks = <&clock 401>;
+   clock-names = "mfc";
+   };
 };
-- 
1.7.9.5

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[PATCH 3/3] ARM: EXYNOS: Add mfc-v7 to memory reserve

[Arun Kumar K]

The patch updates the exynos5 memory reservation to reserve
memory for mfc-v7 also in addition to v6.

Signed-off-by: Arun Kumar K 
---
 arch/arm/mach-exynos/mach-exynos5-dt.c |   14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c 
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index f874b77..fdb6181 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -60,13 +60,17 @@ static char const *exynos5_dt_compat[] __initdata = {
 static void __init exynos5_reserve(void)
 {
 #ifdef CONFIG_S5P_DEV_MFC
-   struct s5p_mfc_dt_meminfo mfc_mem;
+   int i;
+   struct s5p_mfc_dt_meminfo mfc_mem[] = {
+   {.compatible = "samsung,mfc-v6"},
+   {.compatible = "samsung,mfc-v7"},
+   };
 
/* Reserve memory for MFC only if it's available */
-   mfc_mem.compatible = "samsung,mfc-v6";
-   if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
-   s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
-   mfc_mem.lsize);
+   for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
+   if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem[i]))
+   s5p_mfc_reserve_mem(mfc_mem[i].roff, mfc_mem[i].rsize,
+   mfc_mem[i].loff, mfc_mem[i].lsize);
 #endif
 }
 
-- 
1.7.9.5

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[PATCH 1/3] ARM: dts: Add MFC clock entry for 5250

[Arun Kumar K]

The patch adds the MFC clock entry for the 5250 SoC

Signed-off-by: Arun Kumar K 
---
 arch/arm/boot/dts/exynos5250.dtsi |2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index d04ab0a..9c6cda6 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -168,6 +168,8 @@
reg = <0x1100 0x1>;
interrupts = <0 96 0>;
samsung,power-domain = <&pd_mfc>;
+   clocks = <&clock 266>;
+   clock-names = "mfc";
};
 
rtc {
-- 
1.7.9.5

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Re: [PATCH 2/3] ARM: dts: Add MFC node for exynos 5420

[Arun Kumar K]

Hi Sachin,

On Wed, Jun 19, 2013 at 2:54 PM, Sachin Kamat  wrote:
> On 19 June 2013 14:22, Arun Kumar K  wrote:
>> The patch adds MFC nodes for exynos 5420 and for
>> smdk 5420 board.
>>
>> Signed-off-by: Arun Kumar K 
>> ---
>>  arch/arm/boot/dts/exynos5420-smdk5420.dts |5 +
>>  arch/arm/boot/dts/exynos5420.dtsi |8 
>>  2 files changed, 13 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
>> b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> index 08607df..682532c 100644
>> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> @@ -30,4 +30,9 @@
>> clock-frequency = <2400>;
>> };
>> };
>> +
>> +   codec@1100 {
>> +   samsung,mfc-r = <0x4300 0x80>;
>> +   samsung,mfc-l = <0x5100 0x80>;
>> +   };
>>  };
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
>> b/arch/arm/boot/dts/exynos5420.dtsi
>> index 8474d63..cb74356 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -100,4 +100,12 @@
>> clocks = <&clock 260>, <&clock 131>;
>> clock-names = "uart", "clk_uart_baud0";
>> };
>> +
>> +   codec@1100 {
>> +   compatible = "samsung,mfc-v7";
>> +   reg = <0x1100 0x1>;
>> +   interrupts = <0 96 0>;
>> +   clocks = <&clock 401>;
>> +   clock-names = "mfc";
>> +   };
>
> I think it is better if we disable the IPs in dtsi file and enbale
> them in respective board files as was followed for Exynos4.
>

Right. Will change it.

Regards
Arun
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Re: [PATCH 2/3] ARM: dts: Add MFC node for exynos 5420

[Arun Kumar K]

Hi Chander,

On Wed, Jun 19, 2013 at 5:34 PM, Chander Kashyap
 wrote:
> On 19 June 2013 14:22, Arun Kumar K  wrote:
>> The patch adds MFC nodes for exynos 5420 and for
>> smdk 5420 board.
>>
>> Signed-off-by: Arun Kumar K 
>> ---
>>  arch/arm/boot/dts/exynos5420-smdk5420.dts |5 +
>>  arch/arm/boot/dts/exynos5420.dtsi |8 
>>  2 files changed, 13 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
>> b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> index 08607df..682532c 100644
>> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> @@ -30,4 +30,9 @@
>> clock-frequency = <2400>;
>> };
>> };
>> +
>> +   codec@1100 {
>> +   samsung,mfc-r = <0x4300 0x80>;
>> +   samsung,mfc-l = <0x5100 0x80>;
>> +   };
>>  };
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
>> b/arch/arm/boot/dts/exynos5420.dtsi
>> index 8474d63..cb74356 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -100,4 +100,12 @@
>> clocks = <&clock 260>, <&clock 131>;
>> clock-names = "uart", "clk_uart_baud0";
>> };
>> +
>> +   codec@1100 {
>> +   compatible = "samsung,mfc-v7";
>> +   reg = <0x1100 0x1>;
>> +   interrupts = <0 96 0>;
>> +   clocks = <&clock 401>;
>> +   clock-names = "mfc";
>> +   };
> Is it not possible to move the common part of this node to common
> exynos5.dtsi? As exynos5250 is using same property values.

Yes that can be done. I have kept it separate as the IP is different
and compatible is also changing. But the reg and interrupt remains same
and hopefully that can be moved to common exynos5.dtsi.

Regards
Arun
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[PATCH v2 1/5] ARM: dts: Update clocks entry in MFC binding documentation

[Arun Kumar K]

MFC driver is updated to use only one clock instead of
two. Correcting this in the binding documentation.

Signed-off-by: Arun Kumar K 
---
 .../devicetree/bindings/media/s5p-mfc.txt  |   10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt 
b/Documentation/devicetree/bindings/media/s5p-mfc.txt
index df37b02..d75c3e5 100644
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -15,9 +15,9 @@ Required properties:
  mapped region.
 
   - interrupts : MFC interrupt number to the CPU.
-  - clocks : from common clock binding: handle to mfc clocks.
-  - clock-names : from common clock binding: must contain "sclk_mfc" and "mfc",
- corresponding to entries in the clocks property.
+  - clocks : from common clock binding: handle to mfc clock.
+  - clock-names : from common clock binding: must contain "mfc",
+ corresponding to entry in the clocks property.
 
   - samsung,mfc-r : Base address of the first memory bank used by MFC
for DMA contiguous memory allocation and its size.
@@ -37,8 +37,8 @@ mfc: codec@1340 {
reg = <0x1340 0x1>;
interrupts = <0 94 0>;
samsung,power-domain = <&pd_mfc>;
-   clocks = <&clock 170>, <&clock 273>;
-   clock-names = "sclk_mfc", "mfc";
+   clocks = <&clock 273>;
+   clock-names = "mfc";
 };
 
 Board specific DT entry:
-- 
1.7.9.5

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[PATCH v2 4/5] ARM: dts: Add MFC node for exynos 5420

[Arun Kumar K]

The patch adds MFC nodes for exynos 5420 and for
smdk 5420 board.

Signed-off-by: Arun Kumar K 
---
 arch/arm/boot/dts/exynos5420-smdk5420.dts |6 ++
 arch/arm/boot/dts/exynos5420.dtsi |7 +++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 08607df..09ebecf 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -30,4 +30,10 @@
clock-frequency = <2400>;
};
};
+
+   codec@1100 {
+   samsung,mfc-r = <0x4300 0x80>;
+   samsung,mfc-l = <0x5100 0x80>;
+   status = "okay";
+   };
 };
diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 8474d63..3ef604d 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -100,4 +100,11 @@
clocks = <&clock 260>, <&clock 131>;
clock-names = "uart", "clk_uart_baud0";
};
+
+   codec@1100 {
+   compatible = "samsung,mfc-v7";
+   clocks = <&clock 401>;
+   clock-names = "mfc";
+   status = "disabled";
+   };
 };
-- 
1.7.9.5

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[PATCH v2 5/5] ARM: EXYNOS: Add mfc-v7 to memory reserve

[Arun Kumar K]

The patch updates the exynos5 memory reservation to reserve
memory for mfc-v7 also in addition to v6.

Signed-off-by: Arun Kumar K 
---
 arch/arm/mach-exynos/mach-exynos5-dt.c |   14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c 
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index f874b77..fdb6181 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -60,13 +60,17 @@ static char const *exynos5_dt_compat[] __initdata = {
 static void __init exynos5_reserve(void)
 {
 #ifdef CONFIG_S5P_DEV_MFC
-   struct s5p_mfc_dt_meminfo mfc_mem;
+   int i;
+   struct s5p_mfc_dt_meminfo mfc_mem[] = {
+   {.compatible = "samsung,mfc-v6"},
+   {.compatible = "samsung,mfc-v7"},
+   };
 
/* Reserve memory for MFC only if it's available */
-   mfc_mem.compatible = "samsung,mfc-v6";
-   if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
-   s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
-   mfc_mem.lsize);
+   for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
+   if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem[i]))
+   s5p_mfc_reserve_mem(mfc_mem[i].roff, mfc_mem[i].rsize,
+   mfc_mem[i].loff, mfc_mem[i].lsize);
 #endif
 }
 
-- 
1.7.9.5

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[PATCH v2 2/5] ARM: dts: Remove unsused MFC clock from exynos4

[Arun Kumar K]

Removes the unused sclk_mfc from exynos4 dtsi file.

Signed-off-by: Arun Kumar K 
---
 arch/arm/boot/dts/exynos4.dtsi |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 3f94fe8..0f213a3 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -160,8 +160,8 @@
reg = <0x1340 0x1>;
interrupts = <0 94 0>;
samsung,power-domain = <&pd_mfc>;
-   clocks = <&clock 170>, <&clock 273>;
-   clock-names = "sclk_mfc", "mfc";
+   clocks = <&clock 273>;
+   clock-names = "mfc";
status = "disabled";
};
 
-- 
1.7.9.5

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[PATCH v2 3/5] ARM: dts: Update 5250 MFC node

[Arun Kumar K]

The patch adds the MFC clock entry for the 5250 SoC and
also moves the common params to newly added exynos5.dtsi.

Signed-off-by: Arun Kumar K 
---
 arch/arm/boot/dts/exynos5.dtsi|5 +
 arch/arm/boot/dts/exynos5250.dtsi |4 ++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index f65e124..7966a10 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -108,4 +108,9 @@
interrupts = <0 42 0>;
status = "disabled";
};
+
+   codec@1100 {
+   reg = <0x1100 0x1>;
+   interrupts = <0 96 0>;
+   };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index d04ab0a..5ffdae9 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -165,9 +165,9 @@
 
codec@1100 {
compatible = "samsung,mfc-v6";
-   reg = <0x1100 0x1>;
-   interrupts = <0 96 0>;
samsung,power-domain = <&pd_mfc>;
+   clocks = <&clock 266>;
+   clock-names = "mfc";
};
 
rtc {
-- 
1.7.9.5

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[PATCH v2 0/5] DT/ARCH updates for MFC

[Arun Kumar K]

The patch series updates the DT nodes of MFC in Exynos4,
Exynos 5250 and creates node in 5420. Also updates the
memory reserve in exynos5 for mfc-v7.

Changes from v1:
- Made status disabled in dtsi and enable in dts
  as suggested by Sachin Kamat.
- Moved common properties to exynos5.dtsi as
  suggested by Chander.
- Updated binding documentation for special clk removal
- Updated exynos4 dtsi

Arun Kumar K (5):
  ARM: dts: Update clocks entry in MFC binding documentation
  ARM: dts: Remove unsused MFC clock from exynos4
  ARM: dts: Update 5250 MFC node
  ARM: dts: Add MFC node for exynos 5420
  ARM: EXYNOS: Add mfc-v7 to memory reserve

 .../devicetree/bindings/media/s5p-mfc.txt  |   10 +-
 arch/arm/boot/dts/exynos4.dtsi |4 ++--
 arch/arm/boot/dts/exynos5.dtsi |5 +
 arch/arm/boot/dts/exynos5250.dtsi  |4 ++--
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |6 ++
 arch/arm/boot/dts/exynos5420.dtsi  |7 +++
 arch/arm/mach-exynos/mach-exynos5-dt.c |   14 +-
 7 files changed, 36 insertions(+), 14 deletions(-)

-- 
1.7.9.5

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Re: [RFC v2 03/10] exynos5-fimc-is: Adds common driver header files

[Arun Kumar K]

Hi Sylwester,

On Fri, Jun 21, 2013 at 4:16 AM, Sylwester Nawrocki
 wrote:
> Guys, I was wondering how difficult would be to make a common driver
> for the Exynos4 and Exynos5 FIMC-IS ? My feeling is that it would allow
> to save significant amount of code, since the hardware has many
> similarities. I imagine it would be a lot of work, and testing would have
> been a bit difficult. But would it really to troublesome to make a common
> driver ? Could you list some arguments against it ? For the MFC we have
> same driver, handling different firmware versions. Similarly for the other
> media IPs. Only the FIMC-IS subsystems would have separate drivers.
> My intentions is really only to reduce the amount of code we would have
> to merge with this new driver, nothing else. But I'm not going to push
> for the common driver if this is too much trouble.

We have thought about it while starting the development and major
arguments against common driver are :

- FIMC-IS IP has significantly changed from Exynos4.
In Exynos4, it has sub-components ISP, DRC and FD where as in exynos5,
it has ISP, DRC, SCC, ODC, DIS. 3DNR, SCP and FD.

- The FW design has changed considerably to make use of camera2 api
interface. Most of the code in the new driver is for this FW interface
which are done in fimc_is_pipeline.* and fimc_is_interface.*. This is the
major reason against a common driver as the new FW expects each
input frame to be passed along with the controls in a SHOT command.
It is a request-response mode handled per-frame by the FW which is
a major design philosophy change from exynos4.

- Two scalers introduced in the pipeline capable of DMA out which
again changes the pipeline design considerably compared to exynos4.

- The only common part of code between exynos 4 and 5 now is in
the fimc-isp.c and fimc-is-sensor.c and some control structures
in header files. If re-used, only some user controls part can be
re-used and most of the code will still be different.
>From the exynos5 driver, still the fimc-is-scaler.*, fimc-is-pipeline.*,
fimc-is-interface.* has to be retained which constitutes majority of the LOC.

Regards
Arun
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Re: [RFC v2 01/10] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation

[Arun Kumar K]

Hi Sylwester,

Thank you for the review and sorry for the delayed response.

On Fri, Jun 21, 2013 at 4:15 AM, Sylwester Nawrocki
 wrote:
> Hi Arun,
>
> On 05/31/2013 03:03 PM, Arun Kumar K wrote:
>
> Please add at least one sentence here. All in all this patch
> adds DT binding documentation for a fairly complex subsystem.
>
> And please Cc devicetree-disc...@lists.ozlabs.org next time.
>

Ok will do that.

>
>> Signed-off-by: Arun Kumar K
>> ---
>>   .../devicetree/bindings/media/exynos5-fimc-is.txt  |   41
>> 
>>   1 file changed, 41 insertions(+)
>>   create mode 100644
>> Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>>
>> diff --git a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>> b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>> new file mode 100644
>> index 000..9fd4646
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>> @@ -0,0 +1,41 @@
>> +Samsung EXYNOS SoC Camera Subsystem
>
>
> Shouldn't it be, e.g.:
>
> Samsung EXYNOS5 SoC series Imaging Subsystem (FIMC-IS)
>
> Or do you intend this file to be describing also the other sub-devices,
> like GScaler ?
>

Probably not. WIll change it to Imaging subsystem.

>
>> +---
>> +
>> +The camera subsystem on Samsung Exynos5 SoC has some changes relative
>> +to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
>> +FIMC-LITE IPs but has a much improved version of FIMC-IS which can
>> +handle sensor controls and camera post-processing operations. The
>> +Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many
>> +post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two
>> +dedicated scalers (SCC and SCP).
>> +
>> +fimc-is node
>> +
>> +
>> +Required properties:
>> +
>> +- compatible: must be "samsung,exynos5250-fimc-is"
>> +- reg   : physical base address and size of the memory mapped
>> +  registers
>> +- interrupt-parent  : Parent interrupt controller
>> +- interrupts: fimc-is interrupt to the parent combiner
>> +- clocks: list of clock specifiers, corresponding to entries
>> in
>> +  clock-names property;
>> +- clock-names   : must contain "isp", "mcu_isp", "isp_div0",
>> "isp_div1",
>> +  "isp_divmpwm", "mcu_isp_div0", "mcu_isp_div1"
>> entries,
>> +  matching entries in the clocks property.
>> +
>> +
>> +Board specific properties:
>> +
>> +- pinctrl-names: pinctrl names for camera port pinmux control, at
>> least
>> +"default" needs to be specified.
>> +- pinctrl-0...N   : pinctrl properties corresponding to
>> pinctrl-names
>
>
> What pins exactly are supposed to be covered by these properties ? For what
> devices ? Aren't the camera port pins supposed to be specified at the common
> 'camera' node ? I believe the camera ports are not specific to the FIMC-IS.
>

These are for the sensor controls (especially clock lines).
I think I should move these to the sensor node.

>
>> +pmu subnode
>> +---
>> +
>> +Required properties:
>> + - reg : should contain PMU physical base address and size of the memory
>> + mapped registers.
>
>
> What about other devices, like ISP I2C, SPI ? Don't you want to list at
> least
> the ones currently used (I2C bus controllers) ?
>

The present driver doesnt make use of the SPI bus as its used only
for sensor calibration which is not yet added.
I2C bus is used by the sensor which has its own node. May be I should
explain one of the sensor nodes over here?

Regards
Arun
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Re: [RFC v2 03/10] exynos5-fimc-is: Adds common driver header files

[Arun Kumar K]

Hi Sylwester,

Thank you for the review.

On Fri, Jun 21, 2013 at 4:16 AM, Sylwester Nawrocki
 wrote:
> On 05/31/2013 03:03 PM, Arun Kumar K wrote:
>>
>> This patch adds all the common header files used by the fimc-is
>> driver. It includes the commands for interfacing with the firmware
>> and error codes from IS firmware, metadata and command parameter
>> definitions.
>>
>> Signed-off-by: Arun Kumar K
>> Signed-off-by: Kilyeon Im
>> ---
>>   drivers/media/platform/exynos5-is/fimc-is-cmd.h|  201 
>>   drivers/media/platform/exynos5-is/fimc-is-err.h|  261 
>>   .../media/platform/exynos5-is/fimc-is-metadata.h   |  771 
>>   drivers/media/platform/exynos5-is/fimc-is-param.h  | 1259
>> 
>>   4 files changed, 2492 insertions(+)
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-cmd.h
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-err.h
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-metadata.h
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-param.h
>>
>> diff --git a/drivers/media/platform/exynos5-is/fimc-is-cmd.h
>> b/drivers/media/platform/exynos5-is/fimc-is-cmd.h
>> new file mode 100644
>> index 000..4adf832
>> --- /dev/null
>> +++ b/drivers/media/platform/exynos5-is/fimc-is-cmd.h
>> @@ -0,0 +1,201 @@
>> +/*
>> + * Samsung Exynos5 SoC series FIMC-IS driver
>> + *
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd
>> + * Kil-yeon Lim
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#ifndef FIMC_IS_CMD_H
>> +#define FIMC_IS_CMD_H
>> +
>> +#define IS_COMMAND_VER 122 /* IS COMMAND VERSION 1.22 */
>> +
>> +enum is_cmd {
>> +   /* HOST ->  IS */
>> +   HIC_PREVIEW_STILL = 0x1,
>> +   HIC_PREVIEW_VIDEO,
>> +   HIC_CAPTURE_STILL,
>> +   HIC_CAPTURE_VIDEO,
>> +   HIC_PROCESS_START,
>> +   HIC_PROCESS_STOP,
>> +   HIC_STREAM_ON,
>> +   HIC_STREAM_OFF,
>> +   HIC_SHOT,
>> +   HIC_GET_STATIC_METADATA,
>> +   HIC_SET_CAM_CONTROL,
>> +   HIC_GET_CAM_CONTROL,
>> +   HIC_SET_PARAMETER,
>> +   HIC_GET_PARAMETER,
>> +   HIC_SET_A5_MEM_ACCESS,
>> +   RESERVED2,
>> +   HIC_GET_STATUS,
>> +   /* SENSOR PART*/
>> +   HIC_OPEN_SENSOR,
>> +   HIC_CLOSE_SENSOR,
>> +   HIC_SIMMIAN_INIT,
>> +   HIC_SIMMIAN_WRITE,
>> +   HIC_SIMMIAN_READ,
>> +   HIC_POWER_DOWN,
>> +   HIC_GET_SET_FILE_ADDR,
>> +   HIC_LOAD_SET_FILE,
>> +   HIC_MSG_CONFIG,
>> +   HIC_MSG_TEST,
>> +   /* IS ->  HOST */
>> +   IHC_GET_SENSOR_NUMBER = 0x1000,
>> +   /* Parameter1 : Address of space to copy a setfile */
>> +   /* Parameter2 : Space szie */
>> +   IHC_SET_SHOT_MARK,
>> +   /* PARAM1 : a frame number */
>> +   /* PARAM2 : confidence level(smile 0~100) */
>> +   /* PARMA3 : confidence level(blink 0~100) */
>> +   IHC_SET_FACE_MARK,
>> +   /* PARAM1 : coordinate count */
>> +   /* PARAM2 : coordinate buffer address */
>> +   IHC_FRAME_DONE,
>> +   /* PARAM1 : frame start number */
>> +   /* PARAM2 : frame count */
>> +   IHC_AA_DONE,
>> +   IHC_NOT_READY,
>> +   IHC_FLASH_READY
>> +};
>> +
>> +enum is_reply {
>> +   ISR_DONE= 0x2000,
>> +   ISR_NDONE
>> +};
>> +
>> +enum is_scenario_id {
>> +   ISS_PREVIEW_STILL,
>> +   ISS_PREVIEW_VIDEO,
>> +   ISS_CAPTURE_STILL,
>> +   ISS_CAPTURE_VIDEO,
>> +   ISS_END
>> +};
>> +
>> +enum is_subscenario_id {
>> +   ISS_SUB_SCENARIO_STILL,
>> +   ISS_SUB_SCENARIO_VIDEO,
>> +   ISS_SUB_SCENARIO_SCENE1,
>> +   ISS_SUB_SCENARIO_SCENE2,
>> +   ISS_SUB_SCENARIO_SCENE3,
>> +   ISS_SUB_END
>> +};
>> +
>> +struct is_setfile_header_element {
>> +   u32 binary_addr;
>> +   u32 binary_size;
>> +};
>> +
>> +struct is_setfile_header {
>> +   struct is_setfile_header_element isp[ISS_END];
>> +   struct is_setfile_header_element drc[ISS_END];
>> +   struct is_setfile_header_element fd[ISS_END];
>> +};
>> +
>> +struct is_common_reg {
&g

Re: [RFC v2 06/10] exynos5-fimc-is: Adds isp subdev

[Arun Kumar K]

Hi Sylwester,

On Fri, Jun 21, 2013 at 4:55 AM, Sylwester Nawrocki
 wrote:
> On 05/31/2013 03:03 PM, Arun Kumar K wrote:
>>
>> fimc-is driver takes video data input from the ISP video node
>> which is added in this patch. This node accepts Bayer input
>> buffers which is given from the IS sensors.
>>
>> Signed-off-by: Arun Kumar K
>> Signed-off-by: Kilyeon Im
>> ---
>>   drivers/media/platform/exynos5-is/fimc-is-isp.c |  438
>> +++
>>   drivers/media/platform/exynos5-is/fimc-is-isp.h |   89 +
>>   2 files changed, 527 insertions(+)
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h
>>
>> diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.c
>> b/drivers/media/platform/exynos5-is/fimc-is-isp.c
>> new file mode 100644
>> index 000..2890f17
>> --- /dev/null
>> +++ b/drivers/media/platform/exynos5-is/fimc-is-isp.c
>> @@ -0,0 +1,438 @@
>> +/*
>> + * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
>> + *
>> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
>> + *  Arun Kumar K
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include
>> +#include
>> +
>> +#include "fimc-is.h"
>> +
>> +#define ISP_DRV_NAME "fimc-is-isp"
>> +
>> +static const struct fimc_is_fmt formats[] = {
>> +   {
>> +   .name   = "Bayer GR-BG 8bits",
>> +   .fourcc = V4L2_PIX_FMT_SGRBG8,
>> +   .depth  = {8},
>
>
> Please add spaces betwen {} and the number.
>

Ok

>
>> +   .num_planes = 1,
>> +   },
>> +   {
>> +   .name   = "Bayer GR-BG 10bits",
>> +   .fourcc = V4L2_PIX_FMT_SGRBG10,
>> +   .depth  = {10},
>> +   .num_planes = 1,
>> +   },
>> +   {
>> +   .name   = "Bayer GR-BG 12bits",
>> +   .fourcc = V4L2_PIX_FMT_SGRBG12,
>> +   .depth  = {12},
>> +   .num_planes = 1,
>> +   },
>> +};
>> +#define NUM_FORMATS ARRAY_SIZE(formats)
>> +
>> +static struct fimc_is_fmt *find_format(struct v4l2_format *f)
>
>
> Make the return value 'const'...
>

Ok

>
>> +{
>> +   unsigned int i;
>> +
>> +   for (i = 0; i<  NUM_FORMATS; i++) {
>> +   if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
>> +   return (struct fimc_is_fmt *)&formats[i];
>
>
> and drop the casting here.
>

Ok

>
>> +   }
>> +   return NULL;
>> +}
>> +
>> +static int isp_video_output_start_streaming(struct vb2_queue *vq,
>> +   unsigned int count)
>> +{
>> +   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
>> +
>> +   /* Set state to RUNNING */
>
>
> This comment doesn't add any value.
>

Yes :) will remove.

>> +   set_bit(STATE_RUNNING,&isp->output_state);
>>
>> +   return 0;
>> +}
>> +
>> +static int isp_video_output_stop_streaming(struct vb2_queue *vq)
>> +{
>> +   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
>> +
>> +   clear_bit(STATE_RUNNING,&isp->output_state);
>>
>> +   return 0;
>> +}
>> +
>> +static int isp_video_output_queue_setup(struct vb2_queue *vq,
>> +   const struct v4l2_format *pfmt,
>> +   unsigned int *num_buffers, unsigned int
>> *num_planes,
>> +   unsigned int sizes[], void *allocators[])
>> +{
>> +   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
>> +   struct fimc_is_fmt *fmt = isp->fmt;
>> +   unsigned int wh, i;
>> +
>> +   if (!fmt)
>> +   return -EINVAL;
>> +
>> +   *num_planes = fmt->num_planes;
>> +   wh = isp->width * isp->height;
>> +
>> +   for (i = 0; i<  *num_planes; i++) {
>> +   allocators[i] = isp->alloc_ctx;
>> +   sizes[i] = (wh * fmt->depth[i]) / 8;
>> +   }
>> +   return 0;
>> +}

Re: [RFC v2 05/10] exynos5-fimc-is: Adds the sensor subdev

[Arun Kumar K]

Hi Sylwester,

Thank you for the review.

On Fri, Jun 21, 2013 at 4:34 AM, Sylwester Nawrocki
 wrote:
> On 05/31/2013 03:03 PM, Arun Kumar K wrote:
>>
>> FIMC-IS uses certain sensors which are exclusively controlled
>> from the IS firmware. This patch adds the sensor subdev for the
>> fimc-is sensors.
>>
>> Signed-off-by: Arun Kumar K
>> Signed-off-by: Kilyeon Im
>> ---
>>   drivers/media/platform/exynos5-is/fimc-is-sensor.c |  463
>> 
>>   drivers/media/platform/exynos5-is/fimc-is-sensor.h |  168 +++
>>   2 files changed, 631 insertions(+)
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.c
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.h
>>
>> diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.c
>> b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
>> new file mode 100644
>> index 000..b8fb834
>> --- /dev/null
>> +++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
>> @@ -0,0 +1,463 @@
>> +/*
>> + * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
>> + *
>> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
>> + * Arun Kumar K
>> + * Kil-yeon Lim
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include "fimc-is-sensor.h"
>> +#include "fimc-is.h"
>> +
>> +#define DRIVER_NAME "fimc-is-sensor"
>> +
>> +static char *sensor_clock_name[] = {
>> +   [SCLK_BAYER]= "sclk_bayer",
>> +   [SCLK_CAM0] = "sclk_cam0",
>> +   [SCLK_CAM1] = "sclk_cam1",
>> +};
>> +
>> +/* Sensor supported formats */
>> +static struct v4l2_mbus_framefmt sensor_formats[FIMC_IS_MAX_SENSORS] = {
>> +   [SENSOR_S5K4E5] = {
>> +   .width  = SENSOR_4E5_WIDTH + 16,
>> +   .height = SENSOR_4E5_HEIGHT + 10,
>> +   .code   = V4L2_MBUS_FMT_SGRBG10_1X10,
>> +   .field  = V4L2_FIELD_NONE,
>> +   .colorspace = V4L2_COLORSPACE_SRGB,
>> +   },
>> +   [SENSOR_S5K6A3] = {
>> +   .width  = SENSOR_6A3_WIDTH + 16,
>> +   .height = SENSOR_6A3_HEIGHT + 10,
>> +   .code   = V4L2_MBUS_FMT_SGRBG10_1X10,
>> +   .field  = V4L2_FIELD_NONE,
>> +   .colorspace = V4L2_COLORSPACE_SRGB,
>> +   },
>> +};
>> +
>> +static struct fimc_is_sensor *sd_to_fimc_is_sensor(struct v4l2_subdev
>> *sd)
>> +{
>> +   return container_of(sd, struct fimc_is_sensor, subdev);
>> +}
>> +
>> +static void sensor_clk_put(struct fimc_is_sensor *sensor)
>> +{
>> +   int i;
>> +
>> +   for (i = 0; i<  SCLK_MAX_NUM; i++) {
>> +   if (IS_ERR(sensor->clock[i]))
>> +   continue;
>> +   clk_unprepare(sensor->clock[i]);
>> +   clk_put(sensor->clock[i]);
>> +   sensor->clock[i] = ERR_PTR(-EINVAL);
>> +   }
>> +}
>> +
>> +static int sensor_clk_init(struct fimc_is_sensor *sensor)
>> +{
>> +   int i, ret;
>> +
>> +   /* Get CAM clocks */
>> +   for (i = 0; i<  SCLK_MAX_NUM; i++) {
>> +   sensor->clock[i] = clk_get(NULL, sensor_clock_name[i]);
>> +   if (IS_ERR(sensor->clock[i]))
>> +   goto err;
>> +   ret = clk_prepare(sensor->clock[i]);
>> +   if (ret<  0) {
>> +   clk_put(sensor->clock[i]);
>> +   sensor->clock[i] = ERR_PTR(-EINVAL);
>> +   goto err;
>> +   }
>> +   }
>> +
>> +   /* Set clock rates */
>> +   ret = clk_set_rate(sensor->clock[SCLK_CAM0], 24 * 100);
>> +   ret |= clk_set_rate(sensor->clock[SCLK_BAYER], 24 * 100);
>
>
> Please don't obfuscate the return value.
>
>

Ok

>> +   if (ret) {
>> +   pr_err("Failed to set cam clock rates\n");
>> +   goto err;
>> +   }
>> +   return 0;
>> +err:
>> +   sensor_clk_put(se

Re: [RFC v2 01/10] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation

[Arun Kumar K]

Hi Sylwester,

On Wed, Jul 17, 2013 at 2:53 AM, Sylwester Nawrocki
 wrote:
> Hi Arun,
>
>
> On 07/09/2013 01:08 PM, Arun Kumar K wrote:
>>
>> On Fri, Jun 21, 2013 at 4:15 AM, Sylwester Nawrocki
>>   wrote:
>>>
>>> On 05/31/2013 03:03 PM, Arun Kumar K wrote:
>
> [...]
>
>>>> Signed-off-by: Arun Kumar K
>>>> ---
>>>>.../devicetree/bindings/media/exynos5-fimc-is.txt  |   41
>>>> 
>>>>1 file changed, 41 insertions(+)
>>>>create mode 100644
>>>> Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>>>> b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>>>> new file mode 100644
>>>> index 000..9fd4646
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>>>> @@ -0,0 +1,41 @@
>
> [...]
>
>>>> +---
>>>> +
>>>> +The camera subsystem on Samsung Exynos5 SoC has some changes relative
>>>> +to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
>>>> +FIMC-LITE IPs but has a much improved version of FIMC-IS which can
>>>> +handle sensor controls and camera post-processing operations. The
>>>> +Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many
>>>> +post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two
>>>> +dedicated scalers (SCC and SCP).
>>>> +
>>>> +fimc-is node
>>>> +
>>>> +
>>>> +Required properties:
>>>> +
>>>> +- compatible: must be "samsung,exynos5250-fimc-is"
>>>> +- reg   : physical base address and size of the memory
>>>> mapped
>>>> +  registers
>>>> +- interrupt-parent  : Parent interrupt controller
>>>> +- interrupts: fimc-is interrupt to the parent combiner
>>>> +- clocks: list of clock specifiers, corresponding to
>>>> entries
>>>> in
>>>> +  clock-names property;
>>>> +- clock-names   : must contain "isp", "mcu_isp", "isp_div0",
>>>> "isp_div1",
>>>> +  "isp_divmpwm", "mcu_isp_div0", "mcu_isp_div1"
>>>> entries,
>>>> +  matching entries in the clocks property.
>>>> +
>>>> +
>>>> +Board specific properties:
>>>> +
>>>> +- pinctrl-names: pinctrl names for camera port pinmux control, at
>>>> least
>>>> +"default" needs to be specified.
>>>> +- pinctrl-0...N   : pinctrl properties corresponding to
>>>> pinctrl-names
>>>
>>>
>>>
>>> What pins exactly are supposed to be covered by these properties ? For
>>> what
>>> devices ? Aren't the camera port pins supposed to be specified at the
>>> common
>>> 'camera' node ? I believe the camera ports are not specific to the
>>> FIMC-IS.
>>
>>
>> These are for the sensor controls (especially clock lines).
>> I think I should move these to the sensor node.
>
>
> This doesn't sound right either. These pins are not a property of an
> external
> image sensor device, they are specific to the AP SoC. So IMO these pinctrl
> properties belong to some SoC's internal device node.
>

Ok. Time being I will move it to the camera node pinctrl properties.

> I think we could add a clock provider for the sclk_cam clocks and then the
> pinmux of those clock outputs could be configurable from with the clock ops.
> E.g. we set the pinumx into CAM_?_CLKOUT function only when a clock is
> enabled.
> Disabling a clock would put CLKOUT pin pinmux e.g. into input with pull down
> state. This would ensure proper CLKOUT pin configuration when image sensor
> is
> suspended or entirely powered off. I'm working on something like this for
> exynos4.
>

Ok that would be great. I will refer your exynos4 implementation for doing this.

>
>>>> +pmu subnode
>>>> +---
>>>> +
>>>> +Required properties:
>>>> + - reg : should contain PMU physical base address and size of the
>>>> memory
>>>> + mapped registers.
>>>
>>&g

Re: [RFC v2 06/10] exynos5-fimc-is: Adds isp subdev

[Arun Kumar K]

Hi Sylwester,

On Wed, Jul 17, 2013 at 3:41 AM, Sylwester Nawrocki
 wrote:
> On 07/09/2013 01:42 PM, Arun Kumar K wrote:
>>>>
>>>> +   /* Check if same as sensor width&   height */
>>>> >>
>>>> >>  +   sensor_width = p->sensor->drvdata->pixel_width;
>>>> >>  +   sensor_height = p->sensor->drvdata->pixel_height;
>>>> >>  +   if ((sensor_width != f->fmt.pix_mp.width) ||
>>>> >>  +   (sensor_height != f->fmt.pix_mp.height)) {
>>>
>>> >
>>> >
>>> >  What's the point of this check ?
>>> >
>>
>> Check was added to ensure ISP input width and height is
>> set same as the sensor output or not.
>> But yes this cannot be extended to generic (non-IS controlled) sensors.
>> Will drop this check and let media controller take care.
>>
>>> >
>>>>
>>>> >>  +   f->fmt.pix_mp.width = sensor_width;
>>>> >>  +   f->fmt.pix_mp.height = sensor_height;
>>>> >>  +   }
>
>
> I meant that you could do the assignment unconditionally, since you
> always end up with sensor_width/height assigned to pix_mp.width/height.
> Indeed, this should be handled by subdev ioctls, and any discrepancies
> should be detected while starting streaming and reported to user space.
>

Ok I got it. Will modify accordingly

Thanks & Regards
Arun
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[PATCH] [media] exynos-gsc: Register v4l2 device

[Arun Kumar K]

Gscaler video device registration was happening without
reference to a parent v4l2_dev causing probe to fail.
The patch creates a parent v4l2 device and uses it for
gsc m2m video device registration.

Signed-off-by: Arun Kumar K 
---
 drivers/media/platform/exynos-gsc/gsc-core.c |9 -
 drivers/media/platform/exynos-gsc/gsc-core.h |1 +
 drivers/media/platform/exynos-gsc/gsc-m2m.c  |1 +
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/media/platform/exynos-gsc/gsc-core.c 
b/drivers/media/platform/exynos-gsc/gsc-core.c
index 559fab2..1ec60264 100644
--- a/drivers/media/platform/exynos-gsc/gsc-core.c
+++ b/drivers/media/platform/exynos-gsc/gsc-core.c
@@ -1122,10 +1122,14 @@ static int gsc_probe(struct platform_device *pdev)
goto err_clk;
}
 
-   ret = gsc_register_m2m_device(gsc);
+   ret = v4l2_device_register(dev, &gsc->v4l2_dev);
if (ret)
goto err_clk;
 
+   ret = gsc_register_m2m_device(gsc);
+   if (ret)
+   goto err_v4l2;
+
platform_set_drvdata(pdev, gsc);
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(&pdev->dev);
@@ -1147,6 +1151,8 @@ err_pm:
pm_runtime_put(dev);
 err_m2m:
gsc_unregister_m2m_device(gsc);
+err_v4l2:
+   v4l2_device_unregister(&gsc->v4l2_dev);
 err_clk:
gsc_clk_put(gsc);
return ret;
@@ -1157,6 +1163,7 @@ static int gsc_remove(struct platform_device *pdev)
struct gsc_dev *gsc = platform_get_drvdata(pdev);
 
gsc_unregister_m2m_device(gsc);
+   v4l2_device_unregister(&gsc->v4l2_dev);
 
vb2_dma_contig_cleanup_ctx(gsc->alloc_ctx);
pm_runtime_disable(&pdev->dev);
diff --git a/drivers/media/platform/exynos-gsc/gsc-core.h 
b/drivers/media/platform/exynos-gsc/gsc-core.h
index cc19bba..76435d3 100644
--- a/drivers/media/platform/exynos-gsc/gsc-core.h
+++ b/drivers/media/platform/exynos-gsc/gsc-core.h
@@ -343,6 +343,7 @@ struct gsc_dev {
unsigned long   state;
struct vb2_alloc_ctx*alloc_ctx;
struct video_device vdev;
+   struct v4l2_device  v4l2_dev;
 };
 
 /**
diff --git a/drivers/media/platform/exynos-gsc/gsc-m2m.c 
b/drivers/media/platform/exynos-gsc/gsc-m2m.c
index 40a73f7..e576ff2 100644
--- a/drivers/media/platform/exynos-gsc/gsc-m2m.c
+++ b/drivers/media/platform/exynos-gsc/gsc-m2m.c
@@ -751,6 +751,7 @@ int gsc_register_m2m_device(struct gsc_dev *gsc)
gsc->vdev.release   = video_device_release_empty;
gsc->vdev.lock  = &gsc->lock;
gsc->vdev.vfl_dir   = VFL_DIR_M2M;
+   gsc->vdev.v4l2_dev  = &gsc->v4l2_dev;
snprintf(gsc->vdev.name, sizeof(gsc->vdev.name), "%s.%d:m2m",
GSC_MODULE_NAME, gsc->id);
 
-- 
1.7.9.5

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Re: [REVIEW PATCH 0/6] exynos4-is: Asynchronous subdev registration support

[Arun Kumar K]

Hi Sylwester,

On Wed, Jul 24, 2013 at 12:09 AM, Sylwester Nawrocki
 wrote:
> This patch series is a refactoring of the exynos4-is driver to get rid
> of the common fimc-is-sensor driver and to adapt it to use "standard"
> sensor subdev drivers, one per each image sensor type.
> Then a clock provider is added to the exynos4-is driver and the s5k6a3
> subdev is modified to use one of the clocks registered by exynos4-is.
>
> Arun, I think you could reuse the s5k6a3 sensor for your work on the
> Exynos5 FIMC-IS driver. One advantage of separate sensor drivers is
> that the power on/off sequences can be written specifically for each
> sensor. We are probably going to need such sequences per board in
> future. Also having the clock control inside the sensor subdev allows
> to better match the hardware power on/off sequence requirements,
> however the S5K6A3 sensor can have active clock signal on its clock
> input pin even when all its power supplies are turned off.
>
> I'm posting this series before having a proper implementation for
> clk_unregister() in the clock framework, so you are not blocked with
> your Exynos5 FIMC-IS works.
>


Thank you for the patches. I am modifying exynos5-is based on
the same design.

Thanks & Regards
Arun
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Re: [REVIEW PATCH 4/6] exynos4-is: Add clock provider for the external clocks

[Arun Kumar K]

Hi Sylwester,

On Wed, Jul 24, 2013 at 12:09 AM, Sylwester Nawrocki
 wrote:
> This patch adds clock provider to expose the sclk_cam0/1 clocks
> for image sensor subdevs.
>
> Signed-off-by: Sylwester Nawrocki 
> Signed-off-by: Kyungmin Park 
> ---
>  .../devicetree/bindings/media/samsung-fimc.txt |   17 +++-
>  drivers/media/platform/exynos4-is/media-dev.c  |   92 
> 
>  drivers/media/platform/exynos4-is/media-dev.h  |   19 +++-
>  3 files changed, 125 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/samsung-fimc.txt 
> b/Documentation/devicetree/bindings/media/samsung-fimc.txt
> index 96312f6..04a2b87 100644
> --- a/Documentation/devicetree/bindings/media/samsung-fimc.txt
> +++ b/Documentation/devicetree/bindings/media/samsung-fimc.txt
> @@ -91,6 +91,15 @@ Optional properties
>  - samsung,camclk-out : specifies clock output for remote sensor,
>0 - CAM_A_CLKOUT, 1 - CAM_B_CLKOUT;
>
> +'clock-controller' node (optional)
> +--
> +
> +The purpose of this node is to define a clock provider for external image
> +sensors and link any of the CAM_?_CLKOUT clock outputs with related external
> +clock consumer device. Properties specific to this node are described in
> +../clock/clock-bindings.txt.
> +
> +
>  Image sensor nodes
>  --
>
> @@ -114,7 +123,7 @@ Example:
> vddio-supply = <...>;
>
> clock-frequency = <2400>;
> -   clocks = <...>;
> +   clocks = <&camclk 1>;
> clock-names = "mclk";
>
> port {
> @@ -135,7 +144,7 @@ Example:
> vddio-supply = <...>;
>
> clock-frequency = <2400>;
> -   clocks = <...>;
> +   clocks = <&camclk 0>;
> clock-names = "mclk";
>
> port {
> @@ -156,6 +165,10 @@ Example:
> pinctrl-names = "default";
> pinctrl-0 = <&cam_port_a_clk_active>;
>
> +   camclk: clock-controller {
> +  #clock-cells = 1;

Isn't it
  #clock-cells = <1>;
?

> +   };
> +


Regards
Arun
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Re: [RFC v2 06/10] exynos5-fimc-is: Adds isp subdev

[Arun Kumar K]

Hi Sylwester,

On Fri, Jun 21, 2013 at 4:55 AM, Sylwester Nawrocki
 wrote:
> On 05/31/2013 03:03 PM, Arun Kumar K wrote:
>>
>> fimc-is driver takes video data input from the ISP video node
>> which is added in this patch. This node accepts Bayer input
>> buffers which is given from the IS sensors.
>>
>> Signed-off-by: Arun Kumar K
>> Signed-off-by: Kilyeon Im
>> ---
>>   drivers/media/platform/exynos5-is/fimc-is-isp.c |  438
>> +++
>>   drivers/media/platform/exynos5-is/fimc-is-isp.h |   89 +
>>   2 files changed, 527 insertions(+)
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h
>>

[snip]

>> + * Video node ioctl operations
>> + */
>> +static int isp_querycap_output(struct file *file, void *priv,
>> +   struct v4l2_capability *cap)
>> +{
>> +   strncpy(cap->driver, ISP_DRV_NAME, sizeof(cap->driver) - 1);
>> +   strncpy(cap->card, ISP_DRV_NAME, sizeof(cap->card) - 1);
>> +   strncpy(cap->bus_info, ISP_DRV_NAME, sizeof(cap->bus_info) - 1);
>> +   cap->capabilities = V4L2_CAP_STREAMING |
>> V4L2_CAP_VIDEO_OUTPUT_MPLANE;
>> +   cap->device_caps = V4L2_CAP_STREAMING |
>> V4L2_CAP_VIDEO_OUTPUT_MPLANE;
>
>
> cap->capabilities = V4L2_CAP_STREAMING;
>
> cap->device_caps = V4L2_CAP_STREAMING |
> V4L2_CAP_VIDEO_OUTPUT_MPLANE;
>
> This should be:
>
> cap->device_caps = V4L2_CAP_STREAMING;
> cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
>
> Media Controller device nodes must not use V4L2_CAP_VIDEO_{OUTPUT,
> CAPTURE}_(_MPLANE)
> capability flags.
>

If I dont provide any video capabilities, the v4l2-compliance tool
gives a fail :

 fail: v4l2-compliance.cpp(298) : node->is_video && !(dcaps & video_caps)
test VIDIOC_QUERYCAP: FAIL

This error doesn't come if I give V4L2_CAP_VIDEO_OUTPUT_MPLANE capability.

One more related error compliance tool gives is :

   fail: v4l2-test-formats.cpp(286): Video Output Multiplanar cap not
set, but Video Output Multiplanar formats defined
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: FAIL

Shall these errors be ignored?

Regards
Arun
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[RFC v3 01/13] [media] exynos5-is: Adding media device driver for exynos5

[Arun Kumar K]

From: Shaik Ameer Basha 

This patch adds support for media device for EXYNOS5 SoCs.
The current media device supports the following ips to connect
through the media controller framework.

* MIPI-CSIS
  Support interconnection(subdev interface) between devices

* FIMC-LITE
  Support capture interface from device(Sensor, MIPI-CSIS) to memory
  Support interconnection(subdev interface) between devices

* FIMC-IS
  Camera post-processing IP having multiple sub-nodes.

G-Scaler will be added later to the current media device.

The media device creates two kinds of pipelines for connecting
the above mentioned IPs.
The pipeline0 is uses Sensor, MIPI-CSIS and FIMC-LITE which captures
image data and dumps to memory.
Pipeline1 uses FIMC-IS components for doing post-processing
operations on the captured image and give scaled YUV output.

Pipeline0
  ++ +---+ +---+ ++
  | Sensor | --> | MIPI-CSIS | --> | FIMC-LITE | --> | Memory |
  ++ +---+ +---+ ++

Pipeline1
 ++  ++ +---+ +---+
 | Memory | -->  |  ISP   | --> |SCC| --> |SCP|
 ++  ++ +---+ +---+

Signed-off-by: Shaik Ameer Basha 
Signed-off-by: Arun Kumar K 
---
 .../devicetree/bindings/media/exynos5-mdev.txt |  153 ++
 drivers/media/platform/exynos5-is/exynos5-mdev.c   | 1471 
 drivers/media/platform/exynos5-is/exynos5-mdev.h   |  199 +++
 3 files changed, 1823 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/exynos5-mdev.txt
 create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.c
 create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.h

diff --git a/Documentation/devicetree/bindings/media/exynos5-mdev.txt 
b/Documentation/devicetree/bindings/media/exynos5-mdev.txt
new file mode 100644
index 000..d7d419b
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos5-mdev.txt
@@ -0,0 +1,153 @@
+Samsung EXYNOS5 SoC Camera Subsystem (FIMC)
+--
+
+The Exynos5 SoC Camera subsystem comprises of multiple sub-devices
+represented by separate device tree nodes. Currently this includes: FIMC-LITE,
+MIPI CSIS and FIMC-IS.
+
+The sub-subdevices are defined as child nodes of the common 'camera' node which
+also includes common properties of the whole subsystem not really specific to
+any single sub-device, like common camera port pins or the CAMCLK clock outputs
+for external image sensors attached to an SoC.
+
+Common 'camera' node
+
+
+Required properties:
+
+- compatible   : must be "samsung,exynos5-fimc", "simple-bus"
+- clocks   : list of clock specifiers, corresponding to entries in
+ the clock-names property;
+- clock-names  : must contain "sclk_cam0", "sclk_cam1" entries,
+ matching entries in the clocks property.
+
+The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used
+to define a required pinctrl state named "default" and optional pinctrl states:
+"idle", "active-a", active-b". These optional states can be used to switch the
+camera port pinmux at runtime. The "idle" state should configure both the 
camera
+ports A and B into high impedance state, especially the CAMCLK clock output
+should be inactive. For the "active-a" state the camera port A must be 
activated
+and the port B deactivated and for the state "active-b" it should be the other
+way around.
+
+The 'camera' node must include at least one 'fimc-lite' child node.
+
+'parallel-ports' node
+-
+
+This node should contain child 'port' nodes specifying active parallel video
+input ports. It includes camera A and camera B inputs. 'reg' property in the
+port nodes specifies data input - 0, 1 indicates input A, B respectively.
+
+Optional properties
+
+- samsung,camclk-out : specifies clock output for remote sensor,
+  0 - CAM_A_CLKOUT, 1 - CAM_B_CLKOUT;
+
+Image sensor nodes
+--
+
+The sensor device nodes should be added to their control bus controller (e.g.
+I2C0) nodes and linked to a port node in the csis or the parallel-ports node,
+using the common video interfaces bindings, defined in video-interfaces.txt.
+The implementation of this bindings requires clock-frequency property to be
+present in the sensor device nodes.
+
+Example:
+
+   aliases {
+   fimc-lite0 = &fimc_lite_0
+   };
+
+   /* Parallel bus IF sensor */
+   i2c_0: i2c@1386 {
+   s5k6aa: sensor@3c {
+   compatible = "samsung,s5k6aafx";
+   reg = <0x3c>;
+   vddio-supply = <...>

[RFC v3 03/13] [media] exynos5-fimc-is: Add driver core files

[Arun Kumar K]

This driver is for the FIMC-IS IP available in Samsung Exynos5
SoC onwards. This patch adds the core files for the new driver.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 drivers/media/platform/exynos5-is/fimc-is-core.c |  394 ++
 drivers/media/platform/exynos5-is/fimc-is-core.h |  122 +++
 2 files changed, 516 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c 
b/drivers/media/platform/exynos5-is/fimc-is-core.c
new file mode 100644
index 000..7b7762b
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
@@ -0,0 +1,394 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "fimc-is.h"
+#include "fimc-is-i2c.h"
+
+#define CLK_MCU_ISP_DIV0_FREQ  (200 * 100)
+#define CLK_MCU_ISP_DIV1_FREQ  (100 * 100)
+#define CLK_ISP_DIV0_FREQ  (134 * 100)
+#define CLK_ISP_DIV1_FREQ  (68 * 100)
+#define CLK_ISP_DIVMPWM_FREQ   (34 * 100)
+
+static char *fimc_is_clock_name[] = {
+   [IS_CLK_ISP]= "isp",
+   [IS_CLK_MCU_ISP]= "mcu_isp",
+   [IS_CLK_ISP_DIV0]   = "isp_div0",
+   [IS_CLK_ISP_DIV1]   = "isp_div1",
+   [IS_CLK_ISP_DIVMPWM]= "isp_divmpwm",
+   [IS_CLK_MCU_ISP_DIV0]   = "mcu_isp_div0",
+   [IS_CLK_MCU_ISP_DIV1]   = "mcu_isp_div1",
+};
+
+static void fimc_is_put_clocks(struct fimc_is *is)
+{
+   int i;
+
+   for (i = 0; i < IS_CLK_MAX_NUM; i++) {
+   if (IS_ERR(is->clock[i]))
+   continue;
+   clk_unprepare(is->clock[i]);
+   clk_put(is->clock[i]);
+   is->clock[i] = NULL;
+   }
+}
+
+static int fimc_is_get_clocks(struct fimc_is *is)
+{
+   struct device *dev = &is->pdev->dev;
+   int i, ret;
+
+   for (i = 0; i < IS_CLK_MAX_NUM; i++) {
+   is->clock[i] = clk_get(dev, fimc_is_clock_name[i]);
+   if (IS_ERR(is->clock[i]))
+   goto err;
+   ret = clk_prepare(is->clock[i]);
+   if (ret < 0) {
+   clk_put(is->clock[i]);
+   is->clock[i] = ERR_PTR(-EINVAL);
+   goto err;
+   }
+   }
+   return 0;
+err:
+   fimc_is_put_clocks(is);
+   pr_err("Failed to get clock: %s\n", fimc_is_clock_name[i]);
+   return -ENXIO;
+}
+
+static int fimc_is_configure_clocks(struct fimc_is *is)
+{
+   int i, ret;
+
+   for (i = 0; i < IS_CLK_MAX_NUM; i++)
+   is->clock[i] = ERR_PTR(-EINVAL);
+
+   ret = fimc_is_get_clocks(is);
+   if (ret)
+   return ret;
+
+   /* Set rates */
+   ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV0],
+   CLK_MCU_ISP_DIV0_FREQ);
+   if (ret)
+   return ret;
+   ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV1],
+   CLK_MCU_ISP_DIV1_FREQ);
+   if (ret)
+   return ret;
+   ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV0], CLK_ISP_DIV0_FREQ);
+   if (ret)
+   return ret;
+   ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV1], CLK_ISP_DIV1_FREQ);
+   if (ret)
+   return ret;
+   ret = clk_set_rate(is->clock[IS_CLK_ISP_DIVMPWM],
+   CLK_ISP_DIVMPWM_FREQ);
+   return ret;
+}
+
+static void fimc_is_pipelines_destroy(struct fimc_is *is)
+{
+   int i;
+
+   for (i = 0; i < is->num_instance; i++)
+   fimc_is_pipeline_destroy(&is->pipeline[i]);
+}
+
+static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
+   struct device_node *node)
+{
+   struct fimc_is_sensor *sensor = &is->sensor[index];
+   u32 tmp = 0;
+   int ret;
+
+   sensor->drvdata = exynos5_is_sensor_get_drvdata(node);
+   if (!sensor->drvdata) {
+   dev_err(&is->pdev->dev, "no driver data found for: %s\n",
+node->fu

[RFC v3 00/13] Exynos5 IS driver

[Arun Kumar K]

The patch series add support for Exynos5 camera subsystem. It
re-uses mipi-csis and fimc-lite from exynos4-is and adds a new
media device and fimc-is device drivers for exynos5.
The media device supports asynchronos subdev registration for the
fimc-is sensors and is based on the patch series from Sylwester
for exynos4-is [1].

[1] http://www.mail-archive.com/linux-media@vger.kernel.org/msg64653.html

Changes from v2
---
- Added exynos5 media device driver from Shaik to this series
- Added ISP pipeline support in media device driver
- Based on Sylwester's latest exynos4-is development
- Asynchronos registration of sensor subdevs
- Made independent IS-sensor support
- Add s5k4e5 sensor driver
- Addressed review comments from Sylwester, Hans, Andrzej, Sachin

Changes from v1
---
- Addressed all review comments from Sylwester
- Made sensor subdevs as independent i2c devices
- Lots of cleanup
- Debugfs support added
- Removed PMU global register access

Arun Kumar K (12):
  [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings
documentation
  [media] exynos5-fimc-is: Add driver core files
  [media] exynos5-fimc-is: Add common driver header files
  [media] exynos5-fimc-is: Add register definition and context header
  [media] exynos5-fimc-is: Add isp subdev
  [media] exynos5-fimc-is: Add scaler subdev
  [media] exynos5-fimc-is: Add sensor interface
  [media] exynos5-fimc-is: Add the hardware pipeline control
  [media] exynos5-fimc-is: Add the hardware interface module
  [media] exynos5-is: Add Kconfig and Makefile
  V4L: s5k6a3: Change sensor min/max resolutions
  V4L: Add driver for s5k4e5 image sensor

Shaik Ameer Basha (1):
  [media] exynos5-is: Adding media device driver for exynos5

 .../devicetree/bindings/media/exynos5-fimc-is.txt  |   52 +
 .../devicetree/bindings/media/exynos5-mdev.txt |  153 ++
 drivers/media/i2c/Kconfig  |8 +
 drivers/media/i2c/Makefile |1 +
 drivers/media/i2c/s5k4e5.c |  362 
 drivers/media/i2c/s5k6a3.c |   14 +-
 drivers/media/platform/Kconfig |1 +
 drivers/media/platform/Makefile|1 +
 drivers/media/platform/exynos5-is/Kconfig  |   19 +
 drivers/media/platform/exynos5-is/Makefile |7 +
 drivers/media/platform/exynos5-is/exynos5-mdev.c   | 1471 +++
 drivers/media/platform/exynos5-is/exynos5-mdev.h   |  199 ++
 drivers/media/platform/exynos5-is/fimc-is-cmd.h|  187 ++
 drivers/media/platform/exynos5-is/fimc-is-core.c   |  394 
 drivers/media/platform/exynos5-is/fimc-is-core.h   |  122 ++
 drivers/media/platform/exynos5-is/fimc-is-err.h|  257 +++
 .../media/platform/exynos5-is/fimc-is-interface.c  |  861 +
 .../media/platform/exynos5-is/fimc-is-interface.h  |  128 ++
 drivers/media/platform/exynos5-is/fimc-is-isp.c|  509 +
 drivers/media/platform/exynos5-is/fimc-is-isp.h|   93 +
 .../media/platform/exynos5-is/fimc-is-metadata.h   |  767 
 drivers/media/platform/exynos5-is/fimc-is-param.h  | 1212 
 .../media/platform/exynos5-is/fimc-is-pipeline.c   | 1961 
 .../media/platform/exynos5-is/fimc-is-pipeline.h   |  129 ++
 drivers/media/platform/exynos5-is/fimc-is-regs.h   |  105 ++
 drivers/media/platform/exynos5-is/fimc-is-scaler.c |  458 +
 drivers/media/platform/exynos5-is/fimc-is-scaler.h |  112 ++
 drivers/media/platform/exynos5-is/fimc-is-sensor.c |   46 +
 drivers/media/platform/exynos5-is/fimc-is-sensor.h |   69 +
 drivers/media/platform/exynos5-is/fimc-is.h|  153 ++
 30 files changed, 9847 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
 create mode 100644 Documentation/devicetree/bindings/media/exynos5-mdev.txt
 create mode 100644 drivers/media/i2c/s5k4e5.c
 create mode 100644 drivers/media/platform/exynos5-is/Kconfig
 create mode 100644 drivers/media/platform/exynos5-is/Makefile
 create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.c
 create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-cmd.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-err.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-metadata.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-param.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.c
 create mode 100644 drivers/

[RFC v3 05/13] [media] exynos5-fimc-is: Add register definition and context header

[Arun Kumar K]

This patch adds the register definition file for the fimc-is driver
and also the header file containing the main context for the driver.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 drivers/media/platform/exynos5-is/fimc-is-regs.h |  105 +++
 drivers/media/platform/exynos5-is/fimc-is.h  |  153 ++
 2 files changed, 258 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-regs.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-regs.h 
b/drivers/media/platform/exynos5-is/fimc-is-regs.h
new file mode 100644
index 000..06aa466
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-regs.h
@@ -0,0 +1,105 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd
+ * Arun Kumar K 
+ * Kil-yeon Lim 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_REGS_H
+#define FIMC_IS_REGS_H
+
+/* WDT_ISP register */
+#define WDT0x0017
+/* MCUCTL register */
+#define MCUCTL 0x0018
+/* MCU Controller Register */
+#define MCUCTLR(MCUCTL+0x00)
+#define MCUCTLR_AXI_ISPX_AWCACHE(x)((x) << 16)
+#define MCUCTLR_AXI_ISPX_ARCACHE(x)((x) << 12)
+#define MCUCTLR_MSWRST (1 << 0)
+/* Boot Base OFfset Address Register */
+#define BBOAR  (MCUCTL+0x04)
+#define BBOAR_BBOA(x)  ((x) << 0)
+
+/* Interrupt Generation Register 0 from Host CPU to VIC */
+#define INTGR0 (MCUCTL+0x08)
+#define INTGR0_INTGC(n)(1 << ((n) + 16))
+#define INTGR0_INTGD(n)(1 << (n))
+
+/* Interrupt Clear Register 0 from Host CPU to VIC */
+#define INTCR0 (MCUCTL+0x0c)
+#define INTCR0_INTCC(n)(1 << ((n) + 16))
+#define INTCR0_INTCD(n)(1 << (n))
+
+/* Interrupt Mask Register 0 from Host CPU to VIC */
+#define INTMR0 (MCUCTL+0x10)
+#define INTMR0_INTMC(n)(1 << ((n) + 16))
+#define INTMR0_INTMD(n)(1 << (n))
+
+/* Interrupt Status Register 0 from Host CPU to VIC */
+#define INTSR0 (MCUCTL+0x14)
+#define INTSR0_GET_INTSD(n, x) (((x) >> (n)) & 0x1)
+#define INTSR0_GET_INTSC(n, x) (((x) >> ((n) + 16)) & 0x1)
+
+/* Interrupt Mask Status Register 0 from Host CPU to VIC */
+#define INTMSR0(MCUCTL+0x18)
+#define INTMSR0_GET_INTMSD(n, x)   (((x) >> (n)) & 0x1)
+#define INTMSR0_GET_INTMSC(n, x)   (((x) >> ((n) + 16)) & 0x1)
+
+/* Interrupt Generation Register 1 from ISP CPU to Host IC */
+#define INTGR1 (MCUCTL+0x1c)
+#define INTGR1_INTGC(n)(1 << (n))
+
+/* Interrupt Clear Register 1 from ISP CPU to Host IC */
+#define INTCR1 (MCUCTL+0x20)
+#define INTCR1_INTCC(n)(1 << (n))
+
+/* Interrupt Mask Register 1 from ISP CPU to Host IC */
+#define INTMR1 (MCUCTL+0x24)
+#define INTMR1_INTMC(n)(1 << (n))
+
+/* Interrupt Status Register 1 from ISP CPU to Host IC */
+#define INTSR1 (MCUCTL+0x28)
+/* Interrupt Mask Status Register 1 from ISP CPU to Host IC */
+#define INTMSR1(MCUCTL+0x2c)
+/* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */
+#define INTCR2 (MCUCTL+0x30)
+#define INTCR2_INTCC(n)(1 << (n))
+
+/* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */
+#define INTMR2 (MCUCTL+0x34)
+#define INTMR2_INTMCIS(n)  (1 << (n))
+
+/* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */
+#define INTSR2 (MCUCTL+0x38)
+/* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */
+#define INTMSR2(MCUCTL+0x3c)
+/* General Purpose Output Control Register (0~17) */
+#define GPOCTLR(MCUCTL+0x40)
+#define GPOCTLR_GPOG(n, x) ((x) << (n))
+
+/* General Purpose Pad Output Enable Register (0~17) */
+#define GPOENCTLR  (MCUCTL+0x44)
+#define GPOENCTLR_GPOEN0(n, x) ((x) << (n))
+
+/* General Purpose Input Control Register (0~17) */
+#define GPICTLR(MCUCTL+0x48)
+
+/* IS Shared Registers between ISP CPU and HOST CPU */
+#define ISSR(n)(M

[RFC v3 02/13] [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation

[Arun Kumar K]

The patch adds the DT binding documentation for Samsung
Exynos5 SoC series imaging subsystem (FIMC-IS).

Signed-off-by: Arun Kumar K 
---
 .../devicetree/bindings/media/exynos5-fimc-is.txt  |   52 
 1 file changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/exynos5-fimc-is.txt

diff --git a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt 
b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
new file mode 100644
index 000..49a373a
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
@@ -0,0 +1,52 @@
+Samsung EXYNOS5 SoC series Imaging Subsystem (FIMC-IS)
+--
+
+The camera subsystem on Samsung Exynos5 SoC has some changes relative
+to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
+FIMC-LITE IPs but has a much improved version of FIMC-IS which can
+handle sensor controls and camera post-processing operations. The
+Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many
+post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two
+dedicated scalers (SCC and SCP).
+
+fimc-is node
+
+
+Required properties:
+
+- compatible: must be "samsung,exynos5250-fimc-is"
+- reg   : physical base address and size of the memory mapped
+  registers
+- interrupt-parent  : Parent interrupt controller
+- interrupts: fimc-is interrupt to the parent combiner
+- clocks: list of clock specifiers, corresponding to entries in
+  clock-names property;
+- clock-names   : must contain "isp", "mcu_isp", "isp_div0", "isp_div1",
+  "isp_divmpwm", "mcu_isp_div0", "mcu_isp_div1" entries,
+  matching entries in the clocks property.
+
+pmu subnode
+---
+
+Required properties:
+ - reg : should contain PMU physical base address and size of the memory
+ mapped registers.
+
+i2c-isp (ISP I2C bus controller) nodes
+--
+
+Required properties:
+
+- compatible   : should be "samsung,exynos4212-i2c-isp" for Exynos4212,
+ Exynos4412 and Exynos5250 SoCs;
+- reg  : physical base address and length of the registers set;
+- clocks   : must contain gate clock specifier for this controller;
+- clock-names  : must contain "i2c_isp" entry.
+
+For the above nodes it is required to specify a pinctrl state named "default",
+according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt.
+
+Device tree nodes of the image sensors' controlled directly by the FIMC-IS
+firmware must be child nodes of their corresponding ISP I2C bus controller 
node.
+The data link of these image sensors must be specified using the common video
+interfaces bindings, defined in video-interfaces.txt.
-- 
1.7.9.5

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[RFC v3 07/13] [media] exynos5-fimc-is: Add scaler subdev

[Arun Kumar K]

FIMC-IS has two hardware scalers named as scaler-codec and
scaler-preview. This patch adds the common code handling the
video nodes and subdevs of both the scalers.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 drivers/media/platform/exynos5-is/fimc-is-scaler.c |  458 
 drivers/media/platform/exynos5-is/fimc-is-scaler.h |  112 +
 2 files changed, 570 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-scaler.c 
b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
new file mode 100644
index 000..7cff186
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
@@ -0,0 +1,458 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *  Arun Kumar K 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+
+#include "fimc-is.h"
+
+#define IS_SCALER_DRV_NAME "fimc-is-scaler"
+
+static const struct fimc_is_fmt formats[] = {
+   {
+   .name   = "YUV 4:2:0 3p MultiPlanar",
+   .fourcc = V4L2_PIX_FMT_YUV420M,
+   .depth  = {8, 2, 2},
+   .num_planes = 3,
+   },
+   {
+   .name   = "YUV 4:2:0 2p MultiPlanar",
+   .fourcc = V4L2_PIX_FMT_NV12M,
+   .depth  = {8, 4},
+   .num_planes = 2,
+   },
+   {
+   .name   = "YUV 4:2:2 1p MultiPlanar",
+   .fourcc = V4L2_PIX_FMT_NV16,
+   .depth  = {16},
+   .num_planes = 1,
+   },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static const struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+   unsigned int i;
+
+   for (i = 0; i < NUM_FORMATS; i++) {
+   if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
+   return &formats[i];
+   }
+   return NULL;
+}
+
+static int scaler_video_capture_start_streaming(struct vb2_queue *vq,
+   unsigned int count)
+{
+   struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+   int ret;
+
+   /* Scaler start */
+   ret = fimc_is_pipeline_scaler_start(ctx->pipeline,
+   ctx->scaler_id,
+   (unsigned int **)ctx->buf_paddr,
+   vq->num_buffers,
+   ctx->fmt->num_planes);
+   if (ret) {
+   pr_err("Scaler start failed.\n");
+   return -EINVAL;
+   }
+
+   set_bit(STATE_RUNNING, &ctx->capture_state);
+   return 0;
+}
+
+static int scaler_video_capture_stop_streaming(struct vb2_queue *vq)
+{
+   struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+   int ret;
+
+   /* Scaler stop */
+   ret = fimc_is_pipeline_scaler_stop(ctx->pipeline, ctx->scaler_id);
+   if (ret)
+   pr_debug("Scaler already stopped.\n");
+
+   clear_bit(STATE_RUNNING, &ctx->capture_state);
+   return 0;
+}
+
+static int scaler_video_capture_queue_setup(struct vb2_queue *vq,
+   const struct v4l2_format *pfmt,
+   unsigned int *num_buffers, unsigned int *num_planes,
+   unsigned int sizes[], void *allocators[])
+{
+   struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+   const struct fimc_is_fmt *fmt = ctx->fmt;
+   unsigned int wh;
+   int i;
+
+   if (!fmt)
+   return -EINVAL;
+
+   *num_planes = fmt->num_planes;
+   wh = ctx->width * ctx->height;
+
+   for (i = 0; i < *num_planes; i++) {
+   allocators[i] = ctx->alloc_ctx;
+   sizes[i] = (wh * fmt->depth[i]) / 8;
+   }
+   return 0;
+}
+
+static int scaler_video_capture_buffer_init(struct vb2_buffer *vb)
+{
+   struct vb2_queue *vq = vb->vb2_queue;
+   struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+   struct fimc_is_buf *buf;
+   const struct fimc_is_fmt *fmt;
+   int i;
+
+   buf = &ctx->capture_bufs[vb->v4l2_buf.index];
+   /* Initialize buffer */
+   buf->vb = vb;
+   fmt = ctx->fmt;
+   for (i = 0; i < fmt->num_planes; i++)
+   buf->paddr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
+
+   ctx->cap_buf_cnt++;
+   return 0;
+}
+
+static void scaler_video_capture_buffer_queue(struct vb2_buffer *vb)
+{
+   struct vb2_queue *vq = vb->vb2_queue;
+   struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+

[RFC v3 08/13] [media] exynos5-fimc-is: Add sensor interface

[Arun Kumar K]

Some sensors to be used with fimc-is are exclusively controlled
by the fimc-is firmware. This minimal sensor driver provides
the required info for the firmware to configure the sensors
sitting on I2C bus.

Signed-off-by: Arun Kumar K 
---
 drivers/media/platform/exynos5-is/fimc-is-sensor.c |   46 +
 drivers/media/platform/exynos5-is/fimc-is-sensor.h |   69 
 2 files changed, 115 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.c 
b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
new file mode 100644
index 000..3e4aae9
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
@@ -0,0 +1,46 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Authors:  Sylwester Nawrocki 
+ *   Arun Kumar K 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "fimc-is-sensor.h"
+
+static const struct sensor_drv_data s5k6a3_drvdata = {
+   .id = FIMC_IS_SENSOR_ID_S5K6A3,
+   .open_timeout   = S5K6A3_OPEN_TIMEOUT,
+   .setfile_name   = "setfile_6a3.bin",
+};
+
+static const struct sensor_drv_data s5k4e5_drvdata = {
+   .id = FIMC_IS_SENSOR_ID_S5K4E5,
+   .open_timeout   = S5K4E5_OPEN_TIMEOUT,
+   .setfile_name   = "setfile_4e5.bin",
+};
+
+static const struct of_device_id fimc_is_sensor_of_ids[] = {
+   {
+   .compatible = "samsung,s5k6a3",
+   .data   = &s5k6a3_drvdata,
+   },
+   {
+   .compatible = "samsung,s5k4e5",
+   .data   = &s5k4e5_drvdata,
+   },
+   {  }
+};
+
+const struct sensor_drv_data *exynos5_is_sensor_get_drvdata(
+   struct device_node *node)
+{
+   const struct of_device_id *of_id;
+
+   of_id = of_match_node(fimc_is_sensor_of_ids, node);
+   return of_id ? of_id->data : NULL;
+}
diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.h 
b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
new file mode 100644
index 000..51e18ea
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
@@ -0,0 +1,69 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *
+ * Authors:  Sylwester Nawrocki 
+ *  Younghwan Joo 
+ *  Arun Kumar K 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_SENSOR_H_
+#define FIMC_IS_SENSOR_H_
+
+#include 
+#include 
+
+#define S5K6A3_OPEN_TIMEOUT2000 /* ms */
+#define S5K6A3_SENSOR_WIDTH1392
+#define S5K6A3_SENSOR_HEIGHT   1392
+
+#define S5K4E5_OPEN_TIMEOUT2000 /* ms */
+#define S5K4E5_SENSOR_WIDTH2560
+#define S5K4E5_SENSOR_HEIGHT   1920
+
+#define SENSOR_WIDTH_PADDING   16
+#define SENSOR_HEIGHT_PADDING  10
+
+enum fimc_is_sensor_id {
+   FIMC_IS_SENSOR_ID_S5K3H2 = 1,
+   FIMC_IS_SENSOR_ID_S5K6A3,
+   FIMC_IS_SENSOR_ID_S5K4E5,
+   FIMC_IS_SENSOR_ID_S5K3H7,
+   FIMC_IS_SENSOR_ID_CUSTOM,
+   FIMC_IS_SENSOR_ID_END
+};
+
+#define IS_SENSOR_CTRL_BUS_I2C00
+#define IS_SENSOR_CTRL_BUS_I2C11
+
+struct sensor_drv_data {
+   enum fimc_is_sensor_id id;
+   /* sensor open timeout in ms */
+   unsigned short open_timeout;
+   char *setfile_name;
+};
+
+/**
+ * struct fimc_is_sensor - fimc-is sensor data structure
+ * @drvdata: a pointer to the sensor's parameters data structure
+ * @i2c_bus: ISP I2C bus index (0...1)
+ * @test_pattern: true to enable video test pattern
+ */
+struct fimc_is_sensor {
+   const struct sensor_drv_data *drvdata;
+   unsigned int i2c_bus;
+   unsigned int width;
+   unsigned int height;
+   unsigned int pixel_width;
+   unsigned int pixel_height;
+   u8 test_pattern;
+};
+
+const struct sensor_drv_data *exynos5_is_sensor_get_drvdata(
+   struct device_node *node);
+
+#endif /* FIMC_IS_SENSOR_H_ */
-- 
1.7.9.5

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[RFC v3 06/13] [media] exynos5-fimc-is: Add isp subdev

[Arun Kumar K]

fimc-is driver takes video data input from the ISP video node
which is added in this patch. This node accepts Bayer input
buffers which is given from the IS sensors.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 drivers/media/platform/exynos5-is/fimc-is-isp.c |  509 +++
 drivers/media/platform/exynos5-is/fimc-is-isp.h |   93 +
 2 files changed, 602 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.c 
b/drivers/media/platform/exynos5-is/fimc-is-isp.c
new file mode 100644
index 000..e97e473
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-isp.c
@@ -0,0 +1,509 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *  Arun Kumar K 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+
+#include "fimc-is.h"
+
+#define ISP_DRV_NAME "fimc-is-isp"
+
+static const struct fimc_is_fmt formats[] = {
+   {
+   .name   = "Bayer GR-BG 8bits",
+   .fourcc = V4L2_PIX_FMT_SGRBG8,
+   .depth  = { 8 },
+   .num_planes = 1,
+   },
+   {
+   .name   = "Bayer GR-BG 10bits",
+   .fourcc = V4L2_PIX_FMT_SGRBG10,
+   .depth  = { 16 },
+   .num_planes = 1,
+   },
+   {
+   .name   = "Bayer GR-BG 12bits",
+   .fourcc = V4L2_PIX_FMT_SGRBG12,
+   .depth  = { 16 },
+   .num_planes = 1,
+   },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static const struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+   unsigned int i;
+
+   for (i = 0; i < NUM_FORMATS; i++) {
+   if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
+   return &formats[i];
+   }
+   return NULL;
+}
+
+static int isp_video_output_start_streaming(struct vb2_queue *vq,
+   unsigned int count)
+{
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+
+   set_bit(STATE_RUNNING, &isp->output_state);
+   return 0;
+}
+
+static int isp_video_output_stop_streaming(struct vb2_queue *vq)
+{
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+
+   clear_bit(STATE_RUNNING, &isp->output_state);
+   return 0;
+}
+
+static int isp_video_output_queue_setup(struct vb2_queue *vq,
+   const struct v4l2_format *pfmt,
+   unsigned int *num_buffers, unsigned int *num_planes,
+   unsigned int sizes[], void *allocators[])
+{
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+   const struct fimc_is_fmt *fmt = isp->fmt;
+   unsigned int wh, i;
+
+   if (!fmt)
+   return -EINVAL;
+
+   *num_planes = fmt->num_planes;
+   wh = isp->width * isp->height;
+
+   for (i = 0; i < *num_planes; i++) {
+   allocators[i] = isp->alloc_ctx;
+   sizes[i] = (wh * fmt->depth[i]) / 8;
+   }
+   return 0;
+}
+
+static int isp_video_output_buffer_init(struct vb2_buffer *vb)
+{
+   struct vb2_queue *vq = vb->vb2_queue;
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+   struct fimc_is_buf *buf;
+
+   buf = &isp->output_bufs[vb->v4l2_buf.index];
+   /* Initialize buffer */
+   buf->vb = vb;
+   buf->paddr[0] = vb2_dma_contig_plane_dma_addr(vb, 0);
+   isp->out_buf_cnt++;
+   return 0;
+}
+
+static void isp_video_output_buffer_queue(struct vb2_buffer *vb)
+{
+   struct vb2_queue *vq = vb->vb2_queue;
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+   struct fimc_is_buf *buf;
+
+   buf = &isp->output_bufs[vb->v4l2_buf.index];
+
+   fimc_is_pipeline_buf_lock(isp->pipeline);
+   fimc_is_isp_wait_queue_add(isp, buf);
+   fimc_is_pipeline_buf_unlock(isp->pipeline);
+
+   /* Call shot command */
+   fimc_is_pipeline_shot(isp->pipeline);
+}
+
+static const struct vb2_ops isp_video_output_qops = {
+   .queue_setup = isp_video_output_queue_setup,
+   .buf_init= isp_video_output_buffer_init,
+   .buf_queue   = isp_video_output_buffer_queue,
+   .wait_prepare= vb2_ops_wait_prepare,
+   .wait_finish = vb2_ops_wait_finish,
+   .start_streaming = isp_video_output_start_streaming,
+   .stop_streaming  = isp_video_output_stop_streaming,
+};
+
+static const struct v4l2_file_operations isp_video_output_fops 

[RFC v3 10/13] [media] exynos5-fimc-is: Add the hardware interface module

[Arun Kumar K]

The hardware interface module finally sends the commands to the
FIMC-IS firmware and runs the interrupt handler for getting the
responses.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 .../media/platform/exynos5-is/fimc-is-interface.c  |  861 
 .../media/platform/exynos5-is/fimc-is-interface.h  |  128 +++
 2 files changed, 989 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-interface.c 
b/drivers/media/platform/exynos5-is/fimc-is-interface.c
new file mode 100644
index 000..12073be
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-interface.c
@@ -0,0 +1,861 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Kil-yeon Lim 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include "fimc-is.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-regs.h"
+
+#define init_request_barrier(itf) mutex_init(&itf->request_barrier)
+#define enter_request_barrier(itf) mutex_lock(&itf->request_barrier)
+#define exit_request_barrier(itf) mutex_unlock(&itf->request_barrier)
+
+static inline void itf_get_cmd(struct fimc_is_interface *itf,
+   struct fimc_is_msg *msg, unsigned int index)
+{
+   struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+   memset(msg, 0, sizeof(*msg));
+
+   switch (index) {
+   case INTR_GENERAL:
+   msg->command = com_regs->ihcmd;
+   msg->instance = com_regs->ihc_sensorid;
+   msg->param[0] = com_regs->ihc_param[0];
+   msg->param[1] = com_regs->ihc_param[1];
+   msg->param[2] = com_regs->ihc_param[2];
+   msg->param[3] = com_regs->ihc_param[3];
+   break;
+   case INTR_SCC_FDONE:
+   msg->command = IHC_FRAME_DONE;
+   msg->instance = com_regs->scc_sensor_id;
+   msg->param[0] = com_regs->scc_param[0];
+   msg->param[1] = com_regs->scc_param[1];
+   msg->param[2] = com_regs->scc_param[2];
+   break;
+   case INTR_SCP_FDONE:
+   msg->command = IHC_FRAME_DONE;
+   msg->instance = com_regs->scp_sensor_id;
+   msg->param[0] = com_regs->scp_param[0];
+   msg->param[1] = com_regs->scp_param[1];
+   msg->param[2] = com_regs->scp_param[2];
+   break;
+   case INTR_META_DONE:
+   msg->command = IHC_FRAME_DONE;
+   msg->instance = com_regs->meta_sensor_id;
+   msg->param[0] = com_regs->meta_param1;
+   break;
+   case INTR_SHOT_DONE:
+   msg->command = IHC_FRAME_DONE;
+   msg->instance = com_regs->shot_sensor_id;
+   msg->param[0] = com_regs->shot_param[0];
+   msg->param[1] = com_regs->shot_param[1];
+   break;
+   default:
+   pr_err("unknown command getting\n");
+   break;
+   }
+}
+
+static inline unsigned int itf_get_intr(struct fimc_is_interface *itf)
+{
+   unsigned int status;
+   struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+   status = readl(itf->regs + INTMSR1) | com_regs->ihcmd_iflag |
+   com_regs->scc_iflag |
+   com_regs->scp_iflag |
+   com_regs->meta_iflag |
+   com_regs->shot_iflag;
+
+   return status;
+}
+
+static void itf_set_state(struct fimc_is_interface *itf,
+   unsigned long state)
+{
+   unsigned long flags;
+   spin_lock_irqsave(&itf->slock_state, flags);
+   __set_bit(state, &itf->state);
+   spin_unlock_irqrestore(&itf->slock_state, flags);
+}
+
+static void itf_clr_state(struct fimc_is_interface *itf,
+   unsigned long state)
+{
+   unsigned long flags;
+   spin_lock_irqsave(&itf->slock_state, flags);
+   __clear_bit(state, &itf->state);
+   spin_unlock_irqrestore(&itf->slock_state, flags);
+}
+
+static int itf_get_state(struct fimc_is_interface *itf,
+   unsigned long state)
+{
+   int ret = 0;
+   unsigned long flags;
+
+   spin_lock_irqsave(&itf->slock_state, flags);
+   ret = test_bit(state, &itf->state);
+   spin_unlock_irqrestore(&itf->slock_state, flags);
+   return ret;
+}
+
+static void itf_init_wakeup(struct fimc_is_interface *itf)
+{
+   itf_set_state(itf, IS_IF_STATE_INI

[RFC v3 12/13] V4L: s5k6a3: Change sensor min/max resolutions

[Arun Kumar K]

s5k6a3 sensor has actual pixel resolution of 1408x1402 against
the active resolution 1392x1392. The real resolution is needed
when raw sensor SRGB data is dumped to memory by fimc-lite.

Signed-off-by: Arun Kumar K 
---
 drivers/media/i2c/s5k6a3.c |   14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/media/i2c/s5k6a3.c b/drivers/media/i2c/s5k6a3.c
index ccbb4fc..d81638d 100644
--- a/drivers/media/i2c/s5k6a3.c
+++ b/drivers/media/i2c/s5k6a3.c
@@ -30,6 +30,9 @@
 #define S5K6A3_SENSOR_MIN_WIDTH32
 #define S5K6A3_SENSOR_MIN_HEIGHT   32
 
+#define S5K6A3_WIDTH_PADDING   16
+#define S5K6A3_HEIGHT_PADDING  10
+
 #define S5K6A3_DEF_PIX_WIDTH   1296
 #define S5K6A3_DEF_PIX_HEIGHT  732
 
@@ -107,10 +110,13 @@ static void s5k6a3_try_format(struct v4l2_mbus_framefmt 
*mf)
 
fmt = find_sensor_format(mf);
mf->code = fmt->code;
-   v4l_bound_align_image(&mf->width, S5K6A3_SENSOR_MIN_WIDTH,
- S5K6A3_SENSOR_MAX_WIDTH, 0,
- &mf->height, S5K6A3_SENSOR_MIN_HEIGHT,
- S5K6A3_SENSOR_MAX_HEIGHT, 0, 0);
+   v4l_bound_align_image(&mf->width,
+   S5K6A3_SENSOR_MIN_WIDTH + S5K6A3_WIDTH_PADDING,
+   S5K6A3_SENSOR_MAX_WIDTH + S5K6A3_WIDTH_PADDING, 0,
+   &mf->height,
+   S5K6A3_SENSOR_MIN_HEIGHT + S5K6A3_HEIGHT_PADDING,
+   S5K6A3_SENSOR_MAX_HEIGHT + S5K6A3_HEIGHT_PADDING, 0,
+   0);
 }
 
 static struct v4l2_mbus_framefmt *__s5k6a3_get_format(
-- 
1.7.9.5

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[RFC v3 13/13] V4L: Add driver for s5k4e5 image sensor

[Arun Kumar K]

This patch adds subdev driver for Samsung S5K4E5 raw image sensor.
Like s5k6a3, it is also another fimc-is firmware controlled
sensor. This minimal sensor driver doesn't do any I2C communications
as its done by ISP firmware. It can be updated if needed to a
regular sensor driver by adding the I2C communication.

Signed-off-by: Arun Kumar K 
---
 drivers/media/i2c/Kconfig  |8 +
 drivers/media/i2c/Makefile |1 +
 drivers/media/i2c/s5k4e5.c |  362 
 3 files changed, 371 insertions(+)
 create mode 100644 drivers/media/i2c/s5k4e5.c

diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index f7e9147..271028b 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -572,6 +572,14 @@ config VIDEO_S5K6A3
  This is a V4L2 sensor-level driver for Samsung S5K6A3 raw
  camera sensor.
 
+config VIDEO_S5K4E5
+   tristate "Samsung S5K4E5 sensor support"
+   depends on MEDIA_CAMERA_SUPPORT
+   depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && OF
+   ---help---
+ This is a V4L2 sensor-level driver for Samsung S5K4E5 raw
+ camera sensor.
+
 config VIDEO_S5K4ECGX
 tristate "Samsung S5K4ECGX sensor support"
 depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index cf3cf03..0aeed8e 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_VIDEO_SR030PC30) += sr030pc30.o
 obj-$(CONFIG_VIDEO_NOON010PC30)+= noon010pc30.o
 obj-$(CONFIG_VIDEO_S5K6AA) += s5k6aa.o
 obj-$(CONFIG_VIDEO_S5K6A3) += s5k6a3.o
+obj-$(CONFIG_VIDEO_S5K4E5) += s5k4e5.o
 obj-$(CONFIG_VIDEO_S5K4ECGX)   += s5k4ecgx.o
 obj-$(CONFIG_VIDEO_S5C73M3)+= s5c73m3/
 obj-$(CONFIG_VIDEO_ADP1653)+= adp1653.o
diff --git a/drivers/media/i2c/s5k4e5.c b/drivers/media/i2c/s5k4e5.c
new file mode 100644
index 000..a713c6a
--- /dev/null
+++ b/drivers/media/i2c/s5k4e5.c
@@ -0,0 +1,362 @@
+/*
+ * Samsung S5K4E5 image sensor driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define S5K4E5_SENSOR_MAX_WIDTH2560
+#define S5K4E5_SENSOR_MAX_HEIGHT   1920
+#define S5K4E5_SENSOR_MIN_WIDTH32
+#define S5K4E5_SENSOR_MIN_HEIGHT   32
+
+#define S5K4E5_WIDTH_PADDING   16
+#define S5K4E5_HEIGHT_PADDING  10
+
+#define S5K4E5_DEF_PIX_WIDTH   1296
+#define S5K4E5_DEF_PIX_HEIGHT  732
+
+#define S5K4E5_DRV_NAME"S5K4E5"
+#define S5K4E5_CLK_NAME"mclk"
+
+#define S5K4E5_NUM_SUPPLIES2
+
+/**
+ * struct s5k4e5 - fimc-is sensor data structure
+ * @dev: pointer to this I2C client device structure
+ * @subdev: the image sensor's v4l2 subdev
+ * @pad: subdev media source pad
+ * @supplies: image sensor's voltage regulator supplies
+ * @gpio_reset: GPIO connected to the sensor's reset pin
+ * @lock: mutex protecting the structure's members below
+ * @format: media bus format at the sensor's source pad
+ */
+struct s5k4e5 {
+   struct device *dev;
+   struct v4l2_subdev subdev;
+   struct media_pad pad;
+   struct regulator_bulk_data supplies[S5K4E5_NUM_SUPPLIES];
+   int gpio_reset;
+   struct mutex lock;
+   struct v4l2_mbus_framefmt format;
+   struct clk *clock;
+   u32 clock_frequency;
+};
+
+static const char * const s5k4e5_supply_names[] = {
+   "svdda",
+   "svddio"
+};
+
+static inline struct s5k4e5 *sd_to_s5k4e5(struct v4l2_subdev *sd)
+{
+   return container_of(sd, struct s5k4e5, subdev);
+}
+
+static const struct v4l2_mbus_framefmt s5k4e5_formats[] = {
+   {
+   .code = V4L2_MBUS_FMT_SGRBG10_1X10,
+   .colorspace = V4L2_COLORSPACE_SRGB,
+   .field = V4L2_FIELD_NONE,
+   }
+};
+
+static const struct v4l2_mbus_framefmt *find_sensor_format(
+   struct v4l2_mbus_framefmt *mf)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(s5k4e5_formats); i++)
+   if (mf->code == s5k4e5_formats[i].code)
+   return &s5k4e5_formats[i];
+
+   return &s5k4e5_formats[0];
+}
+
+static int s5k4e5_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+   if (code->index >= ARRAY_SIZE(s5k4e5_fo

[RFC v3 11/13] [media] exynos5-is: Add Kconfig and Makefile

[Arun Kumar K]

Adds Kconfig and Makefile for exynos5-is driver files.

Signed-off-by: Shaik Ameer Basha 
Signed-off-by: Kilyeon Im 
Signed-off-by: Arun Kumar K 
---
 drivers/media/platform/Kconfig |1 +
 drivers/media/platform/Makefile|1 +
 drivers/media/platform/exynos5-is/Kconfig  |   19 +++
 drivers/media/platform/exynos5-is/Makefile |7 +++
 4 files changed, 28 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/Kconfig
 create mode 100644 drivers/media/platform/exynos5-is/Makefile

diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 08de865..4b0475e 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -123,6 +123,7 @@ config VIDEO_S3C_CAMIF
 
 source "drivers/media/platform/soc_camera/Kconfig"
 source "drivers/media/platform/exynos4-is/Kconfig"
+source "drivers/media/platform/exynos5-is/Kconfig"
 source "drivers/media/platform/s5p-tv/Kconfig"
 
 endif # V4L_PLATFORM_DRIVERS
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index eee28dd..b1225e5 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_TV)+= s5p-tv/
 
 obj-$(CONFIG_VIDEO_SAMSUNG_S5P_G2D)+= s5p-g2d/
 obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC) += exynos-gsc/
+obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_MDEV)   += exynos5-is/
 
 obj-$(CONFIG_BLACKFIN)  += blackfin/
 
diff --git a/drivers/media/platform/exynos5-is/Kconfig 
b/drivers/media/platform/exynos5-is/Kconfig
new file mode 100644
index 000..99d5edf
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/Kconfig
@@ -0,0 +1,19 @@
+config VIDEO_SAMSUNG_EXYNOS5_MDEV
+   bool "Samsung Exynos5 Media Device driver"
+   depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && PM_RUNTIME && 
VIDEO_SAMSUNG_EXYNOS4_IS
+   help
+ This is a v4l2 based media controller driver for
+ Exynos5 SoC.
+
+if VIDEO_SAMSUNG_EXYNOS5_MDEV
+
+config VIDEO_SAMSUNG_EXYNOS5_FIMC_IS
+   tristate "Samsung Exynos5 SoC FIMC-IS driver"
+   depends on I2C && OF
+   depends on VIDEO_EXYNOS4_FIMC_IS
+   select VIDEOBUF2_DMA_CONTIG
+   help
+ This is a V4L2 driver for Samsung Exynos5 SoC series Imaging
+ Subsystem known as FIMC-IS.
+
+endif #VIDEO_SAMSUNG_EXYNOS5_MDEV
diff --git a/drivers/media/platform/exynos5-is/Makefile 
b/drivers/media/platform/exynos5-is/Makefile
new file mode 100644
index 000..c4e37e0
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/Makefile
@@ -0,0 +1,7 @@
+ccflags-y += -Idrivers/media/platform/exynos4-is
+exynos5-fimc-is-objs := fimc-is-core.o fimc-is-isp.o fimc-is-scaler.o
+exynos5-fimc-is-objs += fimc-is-pipeline.o fimc-is-interface.o fimc-is-sensor.o
+exynos-mdevice-objs := exynos5-mdev.o
+
+obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_FIMC_IS) += exynos5-fimc-is.o
+obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_MDEV) += exynos-mdevice.o
-- 
1.7.9.5

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Re: [RFC v3 00/13] Exynos5 IS driver

[Arun Kumar K]

Hi Sylwester,

On Sun, Aug 4, 2013 at 3:10 AM, Sylwester Nawrocki
 wrote:
> Hi Arun,
>
>
> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>
>> The patch series add support for Exynos5 camera subsystem. It
>> re-uses mipi-csis and fimc-lite from exynos4-is and adds a new
>> media device and fimc-is device drivers for exynos5.
>> The media device supports asynchronos subdev registration for the
>> fimc-is sensors and is based on the patch series from Sylwester
>> for exynos4-is [1].
>>
>> [1]http://www.mail-archive.com/linux-media@vger.kernel.org/msg64653.html
>>
>> Changes from v2
>> ---
>> - Added exynos5 media device driver from Shaik to this series
>> - Added ISP pipeline support in media device driver
>> - Based on Sylwester's latest exynos4-is development
>> - Asynchronos registration of sensor subdevs
>> - Made independent IS-sensor support
>> - Add s5k4e5 sensor driver
>> - Addressed review comments from Sylwester, Hans, Andrzej, Sachin
>
>
> This is starting to look pretty good to me, I hope we can merge this
> patch set for v3.12. Let use coming two weeks for one or two review/
> corrections round.

Sure. I will address the review comments quickly and send v4 version.

> In the meantime I've done numerous fixes to the patch series [1],
> especially the clock provider code was pretty buggy on the clean up
> paths. Let's go through the patches and see what can be improved yet.
>

Ok. Is the updated version available in your git repository
git://linuxtv.org/snawrocki/samsung.git?

Regards
Arun
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Re: [RFC v3 01/13] [media] exynos5-is: Adding media device driver for exynos5

[Arun Kumar K]

Hi Sylwester,

Thank you for the review.
Will address all your review comments.
Some responses below:

[snip]
>> +
>> +static int fimc_md_register_sensor_entities(struct fimc_md *fmd)
>> +{
>> +   struct device_node *of_node = fmd->pdev->dev.of_node;
>> +   int ret;
>> +
>> +   /*
>> +* Runtime resume one of the FIMC entities to make sure
>> +* the sclk_cam clocks are not globally disabled.
>
>
> It's a bit mysterious to me, is this requirement still valid on Exynos5 ?
> I glanced over the Exynos5250 datasheet and there seem to be no sclk_cam?
> clocks dependency on any of GScaler clocks. Maybe you don't need a clock
> provider in this driver, perhaps sensor drivers could use sclk_cam clocks
> directly, assigned through dts ?
>

Yes these clocks can be directly exposed via dt.
I will drop clock provider from this driver.

[snip]

>> +/*
>> + * The peripheral sensor clock management.
>> + */
>> +static void fimc_md_put_clocks(struct fimc_md *fmd)
>> +{
>> +   int i = FIMC_MAX_CAMCLKS;
>> +
>> +   while (--i>= 0) {
>> +   if (IS_ERR(fmd->camclk[i].clock))
>> +   continue;
>> +   clk_put(fmd->camclk[i].clock);
>> +   fmd->camclk[i].clock = ERR_PTR(-EINVAL);
>> +   }
>
>
> Please double check if you need this sclk_cam clocks handling. We could
> simply add a requirement that this driver supports only sensor subdevs
> through the v4l2-async API and which controls their clock themselves.
>

sclk_cam* handling can be removed and be done from respective
sensors. But I think the sclk_bayer handling needs to be retained in the
media driver.

>> +}
>> +
>> +static int fimc_md_get_clocks(struct fimc_md *fmd)
>> +{
>> +   struct device *dev = NULL;
>> +   char clk_name[32];
>> +   struct clk *clock;
>> +   int i, ret = 0;
>> +
>> +   for (i = 0; i<  FIMC_MAX_CAMCLKS; i++)
>> +   fmd->camclk[i].clock = ERR_PTR(-EINVAL);
>> +
>> +   if (fmd->pdev->dev.of_node)
>> +   dev =&fmd->pdev->dev;
>> +
>> +   for (i = 0; i<  SCLK_BAYER; i++) {
>> +   snprintf(clk_name, sizeof(clk_name), "sclk_cam%u", i);
>> +   clock = clk_get(dev, clk_name);
>> +
>> +   if (IS_ERR(clock)) {
>> +   dev_err(&fmd->pdev->dev, "Failed to get clock:
>> %s\n",
>> +   clk_name);
>> +   ret = PTR_ERR(clock);
>> +   break;
>> +   }
>> +   fmd->camclk[i].clock = clock;
>> +   }
>> +   if (ret)
>> +   fimc_md_put_clocks(fmd);
>> +
>> +   /* Prepare bayer clk */
>> +   clock = clk_get(dev, "sclk_bayer");
>> +
>> +   if (IS_ERR(clock)) {
>> +   dev_err(&fmd->pdev->dev, "Failed to get clock: %s\n",
>> +   clk_name);
>
>
> Wrong error message.
>
>> +   ret = PTR_ERR(clock);
>> +   goto err_exit;
>> +   }
>> +   ret = clk_prepare(clock);
>> +   if (ret<  0) {
>> +   clk_put(clock);
>> +   fmd->camclk[SCLK_BAYER].clock = ERR_PTR(-EINVAL);
>> +   goto err_exit;
>> +   }
>> +   fmd->camclk[SCLK_BAYER].clock = clock;
>
>
> Could you explain a bit how is this SCLK_BAYER clock used ? Is it routed
> to external image sensor, or is it used only inside an SoC ?
>

It is not defined properly in the manual, but I suppose its the bus clock
for the bayer rgb data bus. So for proper sensor functionality, we need this
sclk_bayer in addition to the external sensor clks (sclk_cam*). Isn't
exynos5 media driver is the best place to handle such clocks?

>> +   return 0;
>> +err_exit:
>> +   fimc_md_put_clocks(fmd);
>> +   return ret;
>> +}
>> +

Regards
Arun
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Re: [RFC v3 01/13] [media] exynos5-is: Adding media device driver for exynos5

[Arun Kumar K]

Hi Sachin,

Thank you for the review.

On Mon, Aug 5, 2013 at 10:51 AM, Sachin Kamat  wrote:
> On 2 August 2013 20:32, Arun Kumar K  wrote:
>> From: Shaik Ameer Basha 
>>
>> This patch adds support for media device for EXYNOS5 SoCs.
>> The current media device supports the following ips to connect
>> through the media controller framework.
>>
>> * MIPI-CSIS
>>   Support interconnection(subdev interface) between devices
>>
>> * FIMC-LITE
>>   Support capture interface from device(Sensor, MIPI-CSIS) to memory
>>   Support interconnection(subdev interface) between devices
>>
>> * FIMC-IS
>>   Camera post-processing IP having multiple sub-nodes.
>>
>> G-Scaler will be added later to the current media device.
>>
>> The media device creates two kinds of pipelines for connecting
>> the above mentioned IPs.
>> The pipeline0 is uses Sensor, MIPI-CSIS and FIMC-LITE which captures
>> image data and dumps to memory.
>> Pipeline1 uses FIMC-IS components for doing post-processing
>> operations on the captured image and give scaled YUV output.
>>
>> Pipeline0
>>   ++ +---+ +---+ ++
>>   | Sensor | --> | MIPI-CSIS | --> | FIMC-LITE | --> | Memory |
>>   ++ +---+ +---+ ++
>>
>> Pipeline1
>>  ++  ++ +---+ +---+
>>  | Memory | -->  |  ISP   | --> |SCC| --> |SCP|
>>  ++  ++ +---+ +---+
>>
>> Signed-off-by: Shaik Ameer Basha 
>> Signed-off-by: Arun Kumar K 
>
> [snip]
>
>> +
>> +Common 'camera' node
>> +
>> +
>> +Required properties:
>> +
>> +- compatible   : must be "samsung,exynos5-fimc", "simple-bus"
>
> I am not sure if this point was discusssed during the previous
> versions. "samsung,exynos5-fimc" seems a bit generic.
> The compatible string should generally point to a specific SoC (the
> first one to have this IP), something like "samsung,exynos5250-fimc".
>

Yes will make it samsung,exynos5250-fimc

>> +- clocks   : list of clock specifiers, corresponding to entries in
>> + the clock-names property;
>> +- clock-names  : must contain "sclk_cam0", "sclk_cam1" entries,
>> + matching entries in the clocks property.
>> +
>
> [snip]
>
>> +Example:
>> +
>> +   aliases {
>> +   fimc-lite0 = &fimc_lite_0
>> +   };
>> +
>> +   /* Parallel bus IF sensor */
>> +   i2c_0: i2c@1386 {
>> +   s5k6aa: sensor@3c {
>> +   compatible = "samsung,s5k6aafx";
>> +   reg = <0x3c>;
>> +   vddio-supply = <...>;
>> +
>> +   clock-frequency = <2400>;
>> +   clocks = <...>;
>> +   clock-names = "mclk";
>> +
>> +   port {
>> +   s5k6aa_ep: endpoint {
>> +   remote-endpoint = <&fimc0_ep>;
>> +   bus-width = <8>;
>> +   hsync-active = <0>;
>> +   vsync-active = <1>;
>> +   pclk-sample = <1>;
>> +   };
>> +   };
>> +   };
>> +   };
>> +
>> +   /* MIPI CSI-2 bus IF sensor */
>> +   s5c73m3: sensor@0x1a {
>
> 0x not needed.
>

Ok.

Regards
Arun
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Re: [RFC v3 03/13] [media] exynos5-fimc-is: Add driver core files

[Arun Kumar K]

Hi Sylwester,

On Sun, Aug 4, 2013 at 3:12 AM, Sylwester Nawrocki
 wrote:
> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>
>> This driver is for the FIMC-IS IP available in Samsung Exynos5
>> SoC onwards. This patch adds the core files for the new driver.
>>
>> Signed-off-by: Arun Kumar K
>> Signed-off-by: Kilyeon Im
>> ---
>>   drivers/media/platform/exynos5-is/fimc-is-core.c |  394
>> ++
>>   drivers/media/platform/exynos5-is/fimc-is-core.h |  122 +++
>>   2 files changed, 516 insertions(+)
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h
>>
>> diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c
>> b/drivers/media/platform/exynos5-is/fimc-is-core.c
>> new file mode 100644
>> index 000..7b7762b
>> --- /dev/null
>> +++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
>> @@ -0,0 +1,394 @@
>> +/*
>> + * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
>> +*
>> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
>> + * Arun Kumar K
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "fimc-is.h"
>> +#include "fimc-is-i2c.h"
>> +
>> +#define CLK_MCU_ISP_DIV0_FREQ  (200 * 100)
>> +#define CLK_MCU_ISP_DIV1_FREQ  (100 * 100)
>> +#define CLK_ISP_DIV0_FREQ  (134 * 100)
>> +#define CLK_ISP_DIV1_FREQ  (68 * 100)
>> +#define CLK_ISP_DIVMPWM_FREQ   (34 * 100)
>> +
>> +static char *fimc_is_clock_name[] = {
>> +   [IS_CLK_ISP]= "isp",
>> +   [IS_CLK_MCU_ISP]= "mcu_isp",
>> +   [IS_CLK_ISP_DIV0]   = "isp_div0",
>> +   [IS_CLK_ISP_DIV1]   = "isp_div1",
>> +   [IS_CLK_ISP_DIVMPWM]= "isp_divmpwm",
>> +   [IS_CLK_MCU_ISP_DIV0]   = "mcu_isp_div0",
>> +   [IS_CLK_MCU_ISP_DIV1]   = "mcu_isp_div1",
>> +};
>> +
>> +static void fimc_is_put_clocks(struct fimc_is *is)
>> +{
>> +   int i;
>> +
>> +   for (i = 0; i<  IS_CLK_MAX_NUM; i++) {
>> +   if (IS_ERR(is->clock[i]))
>> +   continue;
>> +   clk_unprepare(is->clock[i]);
>> +   clk_put(is->clock[i]);
>> +   is->clock[i] = NULL;
>> +   }
>> +}
>> +
>> +static int fimc_is_get_clocks(struct fimc_is *is)
>> +{
>> +   struct device *dev =&is->pdev->dev;
>>
>> +   int i, ret;
>> +
>> +   for (i = 0; i<  IS_CLK_MAX_NUM; i++) {
>> +   is->clock[i] = clk_get(dev, fimc_is_clock_name[i]);
>> +   if (IS_ERR(is->clock[i]))
>> +   goto err;
>> +   ret = clk_prepare(is->clock[i]);
>> +   if (ret<  0) {
>> +   clk_put(is->clock[i]);
>> +   is->clock[i] = ERR_PTR(-EINVAL);
>> +   goto err;
>> +   }
>> +   }
>> +   return 0;
>> +err:
>> +   fimc_is_put_clocks(is);
>> +   pr_err("Failed to get clock: %s\n", fimc_is_clock_name[i]);
>> +   return -ENXIO;
>> +}
>> +
>> +static int fimc_is_configure_clocks(struct fimc_is *is)
>> +{
>> +   int i, ret;
>> +
>> +   for (i = 0; i<  IS_CLK_MAX_NUM; i++)
>> +   is->clock[i] = ERR_PTR(-EINVAL);
>> +
>> +   ret = fimc_is_get_clocks(is);
>> +   if (ret)
>> +   return ret;
>> +
>> +   /* Set rates */
>> +   ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV0],
>> +   CLK_MCU_ISP_DIV0_FREQ);
>>

Re: [RFC v3 04/13] [media] exynos5-fimc-is: Add common driver header files

[Arun Kumar K]

Hi Sylwester,

On Sun, Aug 4, 2013 at 3:13 AM, Sylwester Nawrocki
 wrote:
> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>
>> This patch adds all the common header files used by the fimc-is
>> driver. It includes the commands for interfacing with the firmware
>> and error codes from IS firmware, metadata and command parameter
>> definitions.
>>
>> Signed-off-by: Arun Kumar K
>> Signed-off-by: Kilyeon Im
>> ---
>>   drivers/media/platform/exynos5-is/fimc-is-cmd.h|  187 +++
>>   drivers/media/platform/exynos5-is/fimc-is-err.h|  257 +
>>   .../media/platform/exynos5-is/fimc-is-metadata.h   |  767 +
>>   drivers/media/platform/exynos5-is/fimc-is-param.h  | 1212
>> 
>>   4 files changed, 2423 insertions(+)
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-cmd.h
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-err.h
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-metadata.h
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-param.h
>>

[snip]

>> +
>> +struct camera2_tonemap_dm {
>> +   enum tonemap_mode   mode;
>> +   /* assuming maxCurvePoints = 64 */
>> +   float   curve_red[64];
>> +   float   curve_green[64];
>> +   float   curve_blue[64];
>
>
> So all those floating point numbers are now not really used in
> the driver but we need them for proper data structures/offsets
> declarations of the firmware interface ?
>

Yes. Same floats are used in firmware internal data structures
also and the driver should assign these values when these parameters
are to be changed.

>> +};
>> +

[snip]

>> +/* --  Effect
>> --- */
>> +enum isp_imageeffect_command {
>> +   ISP_IMAGE_EFFECT_DISABLE= 0,
>> +   ISP_IMAGE_EFFECT_MONOCHROME = 1,
>> +   ISP_IMAGE_EFFECT_NEGATIVE_MONO  = 2,
>> +   ISP_IMAGE_EFFECT_NEGATIVE_COLOR = 3,
>> +   ISP_IMAGE_EFFECT_SEPIA  = 4,
>> +   ISP_IMAGE_EFFECT_AQUA   = 5,
>> +   ISP_IMAGE_EFFECT_EMBOSS = 6,
>> +   ISP_IMAGE_EFFECT_EMBOSS_MONO= 7,
>> +   ISP_IMAGE_EFFECT_SKETCH = 8,
>> +   ISP_IMAGE_EFFECT_RED_YELLOW_POINT   = 9,
>> +   ISP_IMAGE_EFFECT_GREEN_POINT= 10,
>> +   ISP_IMAGE_EFFECT_BLUE_POINT = 11,
>> +   ISP_IMAGE_EFFECT_MAGENTA_POINT  = 12,
>> +   ISP_IMAGE_EFFECT_WARM_VINTAGE   = 13,
>> +   ISP_IMAGE_EFFECT_COLD_VINTAGE   = 14,
>> +   ISP_IMAGE_EFFECT_POSTERIZE  = 15,
>> +   ISP_IMAGE_EFFECT_SOLARIZE   = 16,
>> +   ISP_IMAGE_EFFECT_WASHED = 17,
>> +   ISP_IMAGE_EFFECT_CCM= 18,
>> +};
>
>
> Hmm, I guess we will need a private v4l2 control for those.
>

Yes. I am planning to add the controls after the basic support
gets merged.

Regards
Arun
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Re: [RFC v3 09/13] [media] exynos5-fimc-is: Add the hardware pipeline control

[Arun Kumar K]

Hi Sylwester,

On Sun, Aug 4, 2013 at 8:30 PM, Sylwester Nawrocki
 wrote:
> Hi Arun,
>
> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>
>> This patch adds the crucial hardware pipeline control for the
>> fimc-is driver. All the subdev nodes will call this pipeline
>> interfaces to reach the hardware. Responsibilities of this module
>> involves configuring and maintaining the hardware pipeline involving
>> multiple sub-ips like ISP, DRC, Scalers, ODC, 3DNR, FD etc.
>>
>> Signed-off-by: Arun Kumar K
>> Signed-off-by: Kilyeon Im
>> ---

[snip]


>> +static int fimc_is_pipeline_isp_setparams(struct fimc_is_pipeline
>> *pipeline,
>> +   unsigned int enable)
>> +{
>> +   struct isp_param *isp_param =&pipeline->is_region->parameter.isp;
>> +   struct fimc_is *is = pipeline->is;
>> +   unsigned int indexes, lindex, hindex;
>> +   unsigned int sensor_width, sensor_height, scc_width, scc_height;
>> +   unsigned int crop_x, crop_y, isp_width, isp_height;
>> +   unsigned int sensor_ratio, output_ratio;
>> +   int ret;
>> +
>> +   /* Crop calculation */
>> +   sensor_width = pipeline->sensor_width;
>> +   sensor_height = pipeline->sensor_height;
>> +   scc_width = pipeline->scaler_width[SCALER_SCC];
>> +   scc_height = pipeline->scaler_height[SCALER_SCC];
>> +   isp_width = sensor_width;
>> +   isp_height = sensor_height;
>> +   crop_x = crop_y = 0;
>> +
>> +   sensor_ratio = sensor_width * 1000 / sensor_height;
>> +   output_ratio = scc_width * 1000 / scc_height;
>> +
>> +   if (sensor_ratio == output_ratio) {
>> +   isp_width = sensor_width;
>> +   isp_height = sensor_height;
>> +   } else if (sensor_ratio<  output_ratio) {
>> +   isp_height = (sensor_width * scc_height) / scc_width;
>> +   isp_height = ALIGN(isp_height, 2);
>> +   crop_y = ((sensor_height - isp_height)>>  1)&  0xFFFE;
>
>
> nit: Use ~1U instead of 0xFFFE.
>
>
>> +   } else {
>> +   isp_width = (sensor_height * scc_width) / scc_height;
>> +   isp_width = ALIGN(isp_width, 4);
>> +   crop_x =  ((sensor_width - isp_width)>>  1)&  0xFFFE;
>
>
> Ditto.
>
>> +   }
>> +   pipeline->isp_width = isp_width;
>> +   pipeline->isp_height = isp_height;
>> +
>> +   indexes = hindex = lindex = 0;
>> +
>> +   isp_param->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
>> +   isp_param->otf_output.width = pipeline->sensor_width;
>> +   isp_param->otf_output.height = pipeline->sensor_height;
>> +   isp_param->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
>> +   isp_param->otf_output.bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT;
>> +   isp_param->otf_output.order = OTF_INPUT_ORDER_BAYER_GR_BG;
>> +   lindex |= LOWBIT_OF(PARAM_ISP_OTF_OUTPUT);
>> +   hindex |= HIGHBIT_OF(PARAM_ISP_OTF_OUTPUT);
>> +   indexes++;
>
>
> All right, let's stop this hindex/lindex/indexes madness. I've already
> commented on that IIRC. Nevertheless, this should be replaced with proper
> bitmap operations. A similar issue has been fixed in commit
>
>
>> +   isp_param->dma1_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
>> +   lindex |= LOWBIT_OF(PARAM_ISP_DMA1_OUTPUT);
>> +   hindex |= HIGHBIT_OF(PARAM_ISP_DMA1_OUTPUT);
>> +   indexes++;
>> +
>> +   isp_param->dma2_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
>> +   lindex |= LOWBIT_OF(PARAM_ISP_DMA2_OUTPUT);
>> +   hindex |= HIGHBIT_OF(PARAM_ISP_DMA2_OUTPUT);
>> +   indexes++;
>> +
>> +   if (enable)
>> +   isp_param->control.bypass = CONTROL_BYPASS_DISABLE;
>> +   else
>> +   isp_param->control.bypass = CONTROL_BYPASS_ENABLE;
>> +   isp_param->control.cmd = CONTROL_COMMAND_START;
>> +   isp_param->control.run_mode = 1;
>> +   lindex |= LOWBIT_OF(PARAM_ISP_CONTROL);
>> +   hindex |= HIGHBIT_OF(PARAM_ISP_CONTROL);
>> +   indexes++;
>> +
>> +   isp_param->dma1_input.cmd = DMA_INPUT_COMMAND_BUF_MNGR;
>> +   isp_param->dma1_input.width = sensor_width;
>> +   isp_param->dma1_input.height = sensor_height;
>> +   isp_param->dma1_input.dma_crop_offset_x = crop_x;
>> +   isp_param->dma1_input.dma_crop_offset_y = crop_y;
>> +   

Re: [RFC v3 10/13] [media] exynos5-fimc-is: Add the hardware interface module

[Arun Kumar K]

Hi Sylwester,

On Sun, Aug 4, 2013 at 8:33 PM, Sylwester Nawrocki
 wrote:
> Hi Arun,
>
>
> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>
>> The hardware interface module finally sends the commands to the
>> FIMC-IS firmware and runs the interrupt handler for getting the
>> responses.
>>
>> Signed-off-by: Arun Kumar K
>> Signed-off-by: Kilyeon Im
>> ---

[snip]

>> +static int itf_get_state(struct fimc_is_interface *itf,
>> +   unsigned long state)
>> +{
>> +   int ret = 0;
>> +   unsigned long flags;
>> +
>> +   spin_lock_irqsave(&itf->slock_state, flags);
>> +   ret = test_bit(state,&itf->state);
>
>
> Shouldn't it be __test_bit() ?
>

__test_bit() is not availble !
In file include/asm-generic/bitops/non-atomic.h, all other ops
are prefixed with __xxx(), but its just test_bit().

Regards
Arun
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[PATCH v4 00/13] Exynos5 IS driver

[Arun Kumar K]

The patch series add support for Exynos5 camera subsystem. It
re-uses mipi-csis and fimc-lite from exynos4-is and adds a new
media device and fimc-is device drivers for exynos5.
The media device supports asynchronos subdev registration for the
fimc-is sensors and is based on the patch series from Sylwester
for exynos4-is [1].

[1] http://www.mail-archive.com/linux-media@vger.kernel.org/msg64653.html

Changes from v3
---
- Dropped the RFC tag
- Addressed all review comments from Sylwester and Sachin
- Removed clock provider for media dev
- Added s5k4e5 sensor devicetree binding doc

Changes from v2
---
- Added exynos5 media device driver from Shaik to this series
- Added ISP pipeline support in media device driver
- Based on Sylwester's latest exynos4-is development
- Asynchronos registration of sensor subdevs
- Made independent IS-sensor support
- Add s5k4e5 sensor driver
- Addressed review comments from Sylwester, Hans, Andrzej, Sachin

Changes from v1
---
- Addressed all review comments from Sylwester
- Made sensor subdevs as independent i2c devices
- Lots of cleanup
- Debugfs support added
- Removed PMU global register access

Arun Kumar K (12):
  [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings
documentation
  [media] exynos5-fimc-is: Add driver core files
  [media] exynos5-fimc-is: Add common driver header files
  [media] exynos5-fimc-is: Add register definition and context header
  [media] exynos5-fimc-is: Add isp subdev
  [media] exynos5-fimc-is: Add scaler subdev
  [media] exynos5-fimc-is: Add sensor interface
  [media] exynos5-fimc-is: Add the hardware pipeline control
  [media] exynos5-fimc-is: Add the hardware interface module
  [media] exynos5-is: Add Kconfig and Makefile
  V4L: s5k6a3: Change sensor min/max resolutions
  V4L: Add driver for s5k4e5 image sensor

Shaik Ameer Basha (1):
  [media] exynos5-is: Adding media device driver for exynos5

 .../devicetree/bindings/media/exynos5-fimc-is.txt  |   52 +
 .../devicetree/bindings/media/exynos5-mdev.txt |  148 ++
 .../devicetree/bindings/media/i2c/s5k4e5.txt   |   44 +
 drivers/media/i2c/Kconfig  |8 +
 drivers/media/i2c/Makefile |1 +
 drivers/media/i2c/s5k4e5.c |  361 +
 drivers/media/i2c/s5k6a3.c |   21 +-
 drivers/media/platform/Kconfig |1 +
 drivers/media/platform/Makefile|1 +
 drivers/media/platform/exynos5-is/Kconfig  |   20 +
 drivers/media/platform/exynos5-is/Makefile |7 +
 drivers/media/platform/exynos5-is/exynos5-mdev.c   | 1189 ++
 drivers/media/platform/exynos5-is/exynos5-mdev.h   |  164 ++
 drivers/media/platform/exynos5-is/fimc-is-cmd.h|  187 +++
 drivers/media/platform/exynos5-is/fimc-is-core.c   |  413 +
 drivers/media/platform/exynos5-is/fimc-is-core.h   |  134 ++
 drivers/media/platform/exynos5-is/fimc-is-err.h|  257 +++
 .../media/platform/exynos5-is/fimc-is-interface.c  |  810 ++
 .../media/platform/exynos5-is/fimc-is-interface.h  |  125 ++
 drivers/media/platform/exynos5-is/fimc-is-isp.c|  516 ++
 drivers/media/platform/exynos5-is/fimc-is-isp.h|   90 ++
 .../media/platform/exynos5-is/fimc-is-metadata.h   |  767 +
 drivers/media/platform/exynos5-is/fimc-is-param.h  | 1160 ++
 .../media/platform/exynos5-is/fimc-is-pipeline.c   | 1691 
 .../media/platform/exynos5-is/fimc-is-pipeline.h   |  127 ++
 drivers/media/platform/exynos5-is/fimc-is-regs.h   |  105 ++
 drivers/media/platform/exynos5-is/fimc-is-scaler.c |  449 ++
 drivers/media/platform/exynos5-is/fimc-is-scaler.h |  106 ++
 drivers/media/platform/exynos5-is/fimc-is-sensor.c |   45 +
 drivers/media/platform/exynos5-is/fimc-is-sensor.h |   66 +
 drivers/media/platform/exynos5-is/fimc-is.h|  160 ++
 31 files changed, 9217 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
 create mode 100644 Documentation/devicetree/bindings/media/exynos5-mdev.txt
 create mode 100644 Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
 create mode 100644 drivers/media/i2c/s5k4e5.c
 create mode 100644 drivers/media/platform/exynos5-is/Kconfig
 create mode 100644 drivers/media/platform/exynos5-is/Makefile
 create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.c
 create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-cmd.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-err.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.h
 create mode 100644 drivers/media/pla

[PATCH v4 02/13] [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation

[Arun Kumar K]

The patch adds the DT binding documentation for Samsung
Exynos5 SoC series imaging subsystem (FIMC-IS).

Signed-off-by: Arun Kumar K 
Reviewed-by: Sylwester Nawrocki 
---
 .../devicetree/bindings/media/exynos5-fimc-is.txt  |   52 
 1 file changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/exynos5-fimc-is.txt

diff --git a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt 
b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
new file mode 100644
index 000..5e6dee6
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
@@ -0,0 +1,52 @@
+Samsung EXYNOS5 SoC series Imaging Subsystem (FIMC-IS)
+--
+
+The camera subsystem on Samsung Exynos5 SoC has some changes relative
+to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
+FIMC-LITE IPs but has a much improved version of FIMC-IS which can
+handle sensor controls and camera post-processing operations. The
+Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many
+post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two
+dedicated scalers (SCC and SCP).
+
+fimc-is node
+
+
+Required properties:
+
+- compatible: must be "samsung,exynos5250-fimc-is"
+- reg   : physical base address and size of the memory mapped
+  registers
+- interrupt-parent  : parent interrupt controller
+- interrupts: fimc-is interrupt to the parent combiner
+- clocks: list of clock specifiers, corresponding to entries in
+  clock-names property;
+- clock-names   : must contain "isp", "mcu_isp", "isp_div0", "isp_div1",
+  "isp_divmpwm", "mcu_isp_div0", "mcu_isp_div1" entries,
+  matching entries in the clocks property.
+
+pmu subnode
+---
+
+Required properties:
+ - reg : should contain PMU physical base address and size of the memory
+ mapped registers.
+
+i2c-isp (ISP I2C bus controller) nodes
+--
+
+Required properties:
+
+- compatible   : should be "samsung,exynos4212-i2c-isp" for Exynos4212,
+ Exynos4412 and Exynos5250 SoCs;
+- reg  : physical base address and length of the registers set;
+- clocks   : must contain gate clock specifier for this controller;
+- clock-names  : must contain "i2c_isp" entry.
+
+For the i2c-isp node, it is required to specify a pinctrl state named 
"default",
+according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt.
+
+Device tree nodes of the image sensors' controlled directly by the FIMC-IS
+firmware must be child nodes of their corresponding ISP I2C bus controller 
node.
+The data link of these image sensors must be specified using the common video
+interfaces bindings, defined in video-interfaces.txt.
-- 
1.7.9.5

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[PATCH v4 01/13] [media] exynos5-is: Adding media device driver for exynos5

[Arun Kumar K]

From: Shaik Ameer Basha 

This patch adds support for media device for EXYNOS5 SoCs.
The current media device supports the following ips to connect
through the media controller framework.

* MIPI-CSIS
  Support interconnection(subdev interface) between devices

* FIMC-LITE
  Support capture interface from device(Sensor, MIPI-CSIS) to memory
  Support interconnection(subdev interface) between devices

* FIMC-IS
  Camera post-processing IP having multiple sub-nodes.

G-Scaler will be added later to the current media device.

The media device creates two kinds of pipelines for connecting
the above mentioned IPs.
The pipeline0 is uses Sensor, MIPI-CSIS and FIMC-LITE which captures
image data and dumps to memory.
Pipeline1 uses FIMC-IS components for doing post-processing
operations on the captured image and give scaled YUV output.

Pipeline0
  ++ +---+ +---+ ++
  | Sensor | --> | MIPI-CSIS | --> | FIMC-LITE | --> | Memory |
  ++ +---+ +---+ ++

Pipeline1
 ++  ++ +---+ +---+
 | Memory | -->  |  ISP   | --> |SCC| --> |SCP|
 ++  ++ +---+ +---+

Signed-off-by: Shaik Ameer Basha 
Signed-off-by: Arun Kumar K 
---
 .../devicetree/bindings/media/exynos5-mdev.txt |  148 +++
 drivers/media/platform/exynos5-is/exynos5-mdev.c   | 1189 
 drivers/media/platform/exynos5-is/exynos5-mdev.h   |  164 +++
 3 files changed, 1501 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/exynos5-mdev.txt
 create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.c
 create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.h

diff --git a/Documentation/devicetree/bindings/media/exynos5-mdev.txt 
b/Documentation/devicetree/bindings/media/exynos5-mdev.txt
new file mode 100644
index 000..8b2ffb9
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos5-mdev.txt
@@ -0,0 +1,148 @@
+Samsung EXYNOS5 SoC Camera Subsystem
+
+
+The Exynos5 SoC Camera subsystem comprises of multiple sub-devices
+represented by separate device tree nodes. Currently this includes: FIMC-LITE,
+MIPI CSIS and FIMC-IS.
+
+The sub-subdevices are defined as child nodes of the common 'camera' node which
+also includes common properties of the whole subsystem not really specific to
+any single sub-device, like common camera port pins or the CAMCLK clock outputs
+for external image sensors attached to an SoC.
+
+Common 'camera' node
+
+
+Required properties:
+
+- compatible   : must be "samsung,exynos5-fimc", "simple-bus"
+- clocks   : list of clock specifiers, corresponding to entries in
+ the clock-names property;
+- clock-names  : must contain "sclk_bayer" entry and matching clock property
+  entry
+
+The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used
+to define a required pinctrl state named "default" and optional pinctrl states:
+"idle", "active-a", active-b". These optional states can be used to switch the
+camera port pinmux at runtime. The "idle" state should configure both the 
camera
+ports A and B into high impedance state, especially the CAMCLK clock output
+should be inactive. For the "active-a" state the camera port A must be 
activated
+and the port B deactivated and for the state "active-b" it should be the other
+way around.
+
+The 'camera' node must include at least one 'fimc-lite' child node.
+
+'parallel-ports' node
+-
+
+This node should contain child 'port' nodes specifying active parallel video
+input ports. It includes camera A and camera B inputs. 'reg' property in the
+port nodes specifies data input - 0, 1 indicates input A, B respectively.
+
+Image sensor nodes
+--
+
+The sensor device nodes should be added to their control bus controller (e.g.
+I2C0) nodes and linked to a port node in the csis or the parallel-ports node,
+using the common video interfaces bindings, defined in video-interfaces.txt.
+The implementation of this bindings requires clock-frequency property to be
+present in the sensor device nodes.
+
+Example:
+
+   aliases {
+   fimc-lite0 = &fimc_lite_0
+   };
+
+   /* Parallel bus IF sensor */
+   i2c_0: i2c@1386 {
+   s5k6aa: sensor@3c {
+   compatible = "samsung,s5k6aafx";
+   reg = <0x3c>;
+   vddio-supply = <...>;
+
+   clock-frequency = <2400>;
+   clocks = <...>;
+   clock-names = "mclk";
+
+   por

[PATCH v4 05/13] [media] exynos5-fimc-is: Add register definition and context header

[Arun Kumar K]

This patch adds the register definition file for the fimc-is driver
and also the header file containing the main context for the driver.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 drivers/media/platform/exynos5-is/fimc-is-regs.h |  105 ++
 drivers/media/platform/exynos5-is/fimc-is.h  |  160 ++
 2 files changed, 265 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-regs.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-regs.h 
b/drivers/media/platform/exynos5-is/fimc-is-regs.h
new file mode 100644
index 000..06aa466
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-regs.h
@@ -0,0 +1,105 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd
+ * Arun Kumar K 
+ * Kil-yeon Lim 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_REGS_H
+#define FIMC_IS_REGS_H
+
+/* WDT_ISP register */
+#define WDT0x0017
+/* MCUCTL register */
+#define MCUCTL 0x0018
+/* MCU Controller Register */
+#define MCUCTLR(MCUCTL+0x00)
+#define MCUCTLR_AXI_ISPX_AWCACHE(x)((x) << 16)
+#define MCUCTLR_AXI_ISPX_ARCACHE(x)((x) << 12)
+#define MCUCTLR_MSWRST (1 << 0)
+/* Boot Base OFfset Address Register */
+#define BBOAR  (MCUCTL+0x04)
+#define BBOAR_BBOA(x)  ((x) << 0)
+
+/* Interrupt Generation Register 0 from Host CPU to VIC */
+#define INTGR0 (MCUCTL+0x08)
+#define INTGR0_INTGC(n)(1 << ((n) + 16))
+#define INTGR0_INTGD(n)(1 << (n))
+
+/* Interrupt Clear Register 0 from Host CPU to VIC */
+#define INTCR0 (MCUCTL+0x0c)
+#define INTCR0_INTCC(n)(1 << ((n) + 16))
+#define INTCR0_INTCD(n)(1 << (n))
+
+/* Interrupt Mask Register 0 from Host CPU to VIC */
+#define INTMR0 (MCUCTL+0x10)
+#define INTMR0_INTMC(n)(1 << ((n) + 16))
+#define INTMR0_INTMD(n)(1 << (n))
+
+/* Interrupt Status Register 0 from Host CPU to VIC */
+#define INTSR0 (MCUCTL+0x14)
+#define INTSR0_GET_INTSD(n, x) (((x) >> (n)) & 0x1)
+#define INTSR0_GET_INTSC(n, x) (((x) >> ((n) + 16)) & 0x1)
+
+/* Interrupt Mask Status Register 0 from Host CPU to VIC */
+#define INTMSR0(MCUCTL+0x18)
+#define INTMSR0_GET_INTMSD(n, x)   (((x) >> (n)) & 0x1)
+#define INTMSR0_GET_INTMSC(n, x)   (((x) >> ((n) + 16)) & 0x1)
+
+/* Interrupt Generation Register 1 from ISP CPU to Host IC */
+#define INTGR1 (MCUCTL+0x1c)
+#define INTGR1_INTGC(n)(1 << (n))
+
+/* Interrupt Clear Register 1 from ISP CPU to Host IC */
+#define INTCR1 (MCUCTL+0x20)
+#define INTCR1_INTCC(n)(1 << (n))
+
+/* Interrupt Mask Register 1 from ISP CPU to Host IC */
+#define INTMR1 (MCUCTL+0x24)
+#define INTMR1_INTMC(n)(1 << (n))
+
+/* Interrupt Status Register 1 from ISP CPU to Host IC */
+#define INTSR1 (MCUCTL+0x28)
+/* Interrupt Mask Status Register 1 from ISP CPU to Host IC */
+#define INTMSR1(MCUCTL+0x2c)
+/* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */
+#define INTCR2 (MCUCTL+0x30)
+#define INTCR2_INTCC(n)(1 << (n))
+
+/* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */
+#define INTMR2 (MCUCTL+0x34)
+#define INTMR2_INTMCIS(n)  (1 << (n))
+
+/* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */
+#define INTSR2 (MCUCTL+0x38)
+/* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */
+#define INTMSR2(MCUCTL+0x3c)
+/* General Purpose Output Control Register (0~17) */
+#define GPOCTLR(MCUCTL+0x40)
+#define GPOCTLR_GPOG(n, x) ((x) << (n))
+
+/* General Purpose Pad Output Enable Register (0~17) */
+#define GPOENCTLR  (MCUCTL+0x44)
+#define GPOENCTLR_GPOEN0(n, x) ((x) << (n))
+
+/* General Purpose Input Control Register (0~17) */
+#define GPICTLR(MCUCTL+0x48)
+
+/* IS Shared Registers between ISP CPU and HOST CPU */
+#define ISSR(n)(M

[PATCH v4 03/13] [media] exynos5-fimc-is: Add driver core files

[Arun Kumar K]

This driver is for the FIMC-IS IP available in Samsung Exynos5
SoC onwards. This patch adds the core files for the new driver.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 drivers/media/platform/exynos5-is/fimc-is-core.c |  413 ++
 drivers/media/platform/exynos5-is/fimc-is-core.h |  134 +++
 2 files changed, 547 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c 
b/drivers/media/platform/exynos5-is/fimc-is-core.c
new file mode 100644
index 000..067dea6
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
@@ -0,0 +1,413 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "fimc-is.h"
+#include "fimc-is-i2c.h"
+
+#define CLK_MCU_ISP_DIV0_FREQ  (200 * 100)
+#define CLK_MCU_ISP_DIV1_FREQ  (100 * 100)
+#define CLK_ISP_DIV0_FREQ  (134 * 100)
+#define CLK_ISP_DIV1_FREQ  (68 * 100)
+#define CLK_ISP_DIVMPWM_FREQ   (34 * 100)
+
+static char *fimc_is_clock_name[] = {
+   [IS_CLK_ISP]= "isp",
+   [IS_CLK_MCU_ISP]= "mcu_isp",
+   [IS_CLK_ISP_DIV0]   = "isp_div0",
+   [IS_CLK_ISP_DIV1]   = "isp_div1",
+   [IS_CLK_ISP_DIVMPWM]= "isp_divmpwm",
+   [IS_CLK_MCU_ISP_DIV0]   = "mcu_isp_div0",
+   [IS_CLK_MCU_ISP_DIV1]   = "mcu_isp_div1",
+};
+
+static void fimc_is_put_clocks(struct fimc_is *is)
+{
+   int i;
+
+   for (i = 0; i < IS_CLK_MAX_NUM; i++) {
+   if (IS_ERR(is->clock[i]))
+   continue;
+   clk_unprepare(is->clock[i]);
+   clk_put(is->clock[i]);
+   is->clock[i] = NULL;
+   }
+}
+
+static int fimc_is_get_clocks(struct fimc_is *is)
+{
+   struct device *dev = &is->pdev->dev;
+   int i, ret;
+
+   for (i = 0; i < IS_CLK_MAX_NUM; i++) {
+   is->clock[i] = clk_get(dev, fimc_is_clock_name[i]);
+   if (IS_ERR(is->clock[i]))
+   goto err;
+   ret = clk_prepare(is->clock[i]);
+   if (ret < 0) {
+   clk_put(is->clock[i]);
+   is->clock[i] = ERR_PTR(-EINVAL);
+   goto err;
+   }
+   }
+   return 0;
+err:
+   fimc_is_put_clocks(is);
+   pr_err("Failed to get clock: %s\n", fimc_is_clock_name[i]);
+   return -ENXIO;
+}
+
+static int fimc_is_configure_clocks(struct fimc_is *is)
+{
+   int i, ret;
+
+   for (i = 0; i < IS_CLK_MAX_NUM; i++)
+   is->clock[i] = ERR_PTR(-EINVAL);
+
+   ret = fimc_is_get_clocks(is);
+   if (ret)
+   return ret;
+
+   /* Set rates */
+   ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV0],
+   CLK_MCU_ISP_DIV0_FREQ);
+   if (ret)
+   return ret;
+   ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV1],
+   CLK_MCU_ISP_DIV1_FREQ);
+   if (ret)
+   return ret;
+   ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV0], CLK_ISP_DIV0_FREQ);
+   if (ret)
+   return ret;
+   ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV1], CLK_ISP_DIV1_FREQ);
+   if (ret)
+   return ret;
+   ret = clk_set_rate(is->clock[IS_CLK_ISP_DIVMPWM],
+   CLK_ISP_DIVMPWM_FREQ);
+   return ret;
+}
+
+static void fimc_is_pipelines_destroy(struct fimc_is *is)
+{
+   int i;
+
+   for (i = 0; i < is->drvdata->num_instance; i++)
+   fimc_is_pipeline_destroy(&is->pipeline[i]);
+}
+
+static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
+   struct device_node *node)
+{
+   struct fimc_is_sensor *sensor = &is->sensor[index];
+   u32 tmp = 0;
+   int ret;
+
+   sensor->drvdata = exynos5_is_sensor_get_drvdata(node);
+   if (!sensor->drvdata) {
+   dev_err(&is->pdev->dev, "no driver data found for: %s\n",
+   

[PATCH v4 08/13] [media] exynos5-fimc-is: Add sensor interface

[Arun Kumar K]

Some sensors to be used with fimc-is are exclusively controlled
by the fimc-is firmware. This minimal sensor driver provides
the required info for the firmware to configure the sensors
sitting on I2C bus.

Signed-off-by: Arun Kumar K 
---
 drivers/media/platform/exynos5-is/fimc-is-sensor.c |   45 +
 drivers/media/platform/exynos5-is/fimc-is-sensor.h |   66 
 2 files changed, 111 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.c 
b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
new file mode 100644
index 000..7df2b11
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
@@ -0,0 +1,45 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "fimc-is-sensor.h"
+
+static const struct sensor_drv_data s5k6a3_drvdata = {
+   .id = FIMC_IS_SENSOR_ID_S5K6A3,
+   .open_timeout   = S5K6A3_OPEN_TIMEOUT,
+   .setfile_name   = "setfile_6a3.bin",
+};
+
+static const struct sensor_drv_data s5k4e5_drvdata = {
+   .id = FIMC_IS_SENSOR_ID_S5K4E5,
+   .open_timeout   = S5K4E5_OPEN_TIMEOUT,
+   .setfile_name   = "setfile_4e5.bin",
+};
+
+static const struct of_device_id fimc_is_sensor_of_ids[] = {
+   {
+   .compatible = "samsung,s5k6a3",
+   .data   = &s5k6a3_drvdata,
+   },
+   {
+   .compatible = "samsung,s5k4e5",
+   .data   = &s5k4e5_drvdata,
+   },
+   {  }
+};
+
+const struct sensor_drv_data *exynos5_is_sensor_get_drvdata(
+   struct device_node *node)
+{
+   const struct of_device_id *of_id;
+
+   of_id = of_match_node(fimc_is_sensor_of_ids, node);
+   return of_id ? of_id->data : NULL;
+}
diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.h 
b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
new file mode 100644
index 000..736ef16
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
@@ -0,0 +1,66 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *
+ * Author: Arun Kumar K 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_SENSOR_H_
+#define FIMC_IS_SENSOR_H_
+
+#include 
+#include 
+
+#define S5K6A3_OPEN_TIMEOUT2000 /* ms */
+#define S5K6A3_SENSOR_WIDTH1392
+#define S5K6A3_SENSOR_HEIGHT   1392
+
+#define S5K4E5_OPEN_TIMEOUT2000 /* ms */
+#define S5K4E5_SENSOR_WIDTH2560
+#define S5K4E5_SENSOR_HEIGHT   1920
+
+#define SENSOR_WIDTH_PADDING   16
+#define SENSOR_HEIGHT_PADDING  10
+
+enum fimc_is_sensor_id {
+   FIMC_IS_SENSOR_ID_S5K3H2 = 1,
+   FIMC_IS_SENSOR_ID_S5K6A3,
+   FIMC_IS_SENSOR_ID_S5K4E5,
+   FIMC_IS_SENSOR_ID_S5K3H7,
+   FIMC_IS_SENSOR_ID_CUSTOM,
+   FIMC_IS_SENSOR_ID_END
+};
+
+struct sensor_drv_data {
+   enum fimc_is_sensor_id id;
+   /* sensor open timeout in ms */
+   unsigned short open_timeout;
+   char *setfile_name;
+};
+
+/**
+ * struct fimc_is_sensor - fimc-is sensor data structure
+ * @drvdata: a pointer to the sensor's parameters data structure
+ * @i2c_bus: ISP I2C bus index (0...1)
+ * @width: sensor active width
+ * @height: sensor active height
+ * @pixel_width: sensor effective pixel width (width + padding)
+ * @pixel_height: sensor effective pixel height (height + padding)
+ */
+struct fimc_is_sensor {
+   const struct sensor_drv_data *drvdata;
+   unsigned int i2c_bus;
+   unsigned int width;
+   unsigned int height;
+   unsigned int pixel_width;
+   unsigned int pixel_height;
+};
+
+const struct sensor_drv_data *exynos5_is_sensor_get_drvdata(
+   struct device_node *node);
+
+#endif /* FIMC_IS_SENSOR_H_ */
-- 
1.7.9.5

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[PATCH v4 06/13] [media] exynos5-fimc-is: Add isp subdev

[Arun Kumar K]

fimc-is driver takes video data input from the ISP video node
which is added in this patch. This node accepts Bayer input
buffers which is given from the IS sensors.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 drivers/media/platform/exynos5-is/fimc-is-isp.c |  516 +++
 drivers/media/platform/exynos5-is/fimc-is-isp.h |   90 
 2 files changed, 606 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.c 
b/drivers/media/platform/exynos5-is/fimc-is-isp.c
new file mode 100644
index 000..afbf4a2
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-isp.c
@@ -0,0 +1,516 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *  Arun Kumar K 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+
+#include "fimc-is.h"
+
+#define ISP_DRV_NAME "fimc-is-isp"
+
+static const struct fimc_is_fmt formats[] = {
+   {
+   .name   = "Bayer GR-BG 8bits",
+   .fourcc = V4L2_PIX_FMT_SGRBG8,
+   .depth  = { 8 },
+   .num_planes = 1,
+   },
+   {
+   .name   = "Bayer GR-BG 10bits",
+   .fourcc = V4L2_PIX_FMT_SGRBG10,
+   .depth  = { 16 },
+   .num_planes = 1,
+   },
+   {
+   .name   = "Bayer GR-BG 12bits",
+   .fourcc = V4L2_PIX_FMT_SGRBG12,
+   .depth  = { 16 },
+   .num_planes = 1,
+   },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static const struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+   unsigned int i;
+
+   for (i = 0; i < NUM_FORMATS; i++)
+   if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
+   return &formats[i];
+   return NULL;
+}
+
+static int isp_video_output_start_streaming(struct vb2_queue *vq,
+   unsigned int count)
+{
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+
+   set_bit(STATE_RUNNING, &isp->output_state);
+   return 0;
+}
+
+static int isp_video_output_stop_streaming(struct vb2_queue *vq)
+{
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+   struct fimc_is_buf *buf;
+
+   /* Release un-used buffers */
+   while (!list_empty(&isp->wait_queue)) {
+   buf = fimc_is_isp_wait_queue_get(isp);
+   vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
+   }
+   while (!list_empty(&isp->run_queue)) {
+   buf = fimc_is_isp_run_queue_get(isp);
+   vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
+   }
+
+   clear_bit(STATE_RUNNING, &isp->output_state);
+   return 0;
+}
+
+static int isp_video_output_queue_setup(struct vb2_queue *vq,
+   const struct v4l2_format *pfmt,
+   unsigned int *num_buffers, unsigned int *num_planes,
+   unsigned int sizes[], void *allocators[])
+{
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+   const struct fimc_is_fmt *fmt = isp->fmt;
+   unsigned int wh, i;
+
+   if (!fmt)
+   return -EINVAL;
+
+   *num_planes = fmt->num_planes;
+   wh = isp->width * isp->height;
+
+   for (i = 0; i < *num_planes; i++) {
+   allocators[i] = isp->alloc_ctx;
+   sizes[i] = (wh * fmt->depth[i]) / 8;
+   }
+   return 0;
+}
+
+static int isp_video_output_buffer_init(struct vb2_buffer *vb)
+{
+   struct fimc_is_buf *buf = container_of(vb, struct fimc_is_buf, vb);
+
+   buf->paddr[0] = vb2_dma_contig_plane_dma_addr(vb, 0);
+   return 0;
+}
+
+static void isp_video_output_buffer_queue(struct vb2_buffer *vb)
+{
+   struct vb2_queue *vq = vb->vb2_queue;
+   struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+   struct fimc_is_buf *buf = container_of(vb, struct fimc_is_buf, vb);
+
+   fimc_is_pipeline_buf_lock(isp->pipeline);
+   fimc_is_isp_wait_queue_add(isp, buf);
+   fimc_is_pipeline_buf_unlock(isp->pipeline);
+
+   /* Call shot command */
+   fimc_is_pipeline_shot(isp->pipeline);
+}
+
+static const struct vb2_ops isp_video_output_qops = {
+   .queue_setup = isp_video_output_queue_setup,
+   .buf_init= isp_video_output_buffer_init,
+   .buf_queue   = isp_video_output_buffer_queue,
+   .wait_prepare= vb2_ops_wait_prepare,
+   .wait_finish = vb2_ops_wait_finish,
+ 

[PATCH v4 07/13] [media] exynos5-fimc-is: Add scaler subdev

[Arun Kumar K]

FIMC-IS has two hardware scalers named as scaler-codec and
scaler-preview. This patch adds the common code handling the
video nodes and subdevs of both the scalers.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 drivers/media/platform/exynos5-is/fimc-is-scaler.c |  449 
 drivers/media/platform/exynos5-is/fimc-is-scaler.h |  106 +
 2 files changed, 555 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-scaler.c 
b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
new file mode 100644
index 000..c9bd07b
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
@@ -0,0 +1,449 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *  Arun Kumar K 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+
+#include "fimc-is.h"
+
+#define IS_SCALER_DRV_NAME "fimc-is-scaler"
+
+static const struct fimc_is_fmt formats[] = {
+   {
+   .name   = "YUV 4:2:0 3p MultiPlanar",
+   .fourcc = V4L2_PIX_FMT_YUV420M,
+   .depth  = {8, 2, 2},
+   .num_planes = 3,
+   },
+   {
+   .name   = "YUV 4:2:0 2p MultiPlanar",
+   .fourcc = V4L2_PIX_FMT_NV12M,
+   .depth  = {8, 4},
+   .num_planes = 2,
+   },
+   {
+   .name   = "YUV 4:2:2 1p MultiPlanar",
+   .fourcc = V4L2_PIX_FMT_NV16,
+   .depth  = {16},
+   .num_planes = 1,
+   },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static const struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+   unsigned int i;
+
+   for (i = 0; i < NUM_FORMATS; i++) {
+   if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
+   return &formats[i];
+   }
+   return NULL;
+}
+
+static int scaler_video_capture_start_streaming(struct vb2_queue *vq,
+   unsigned int count)
+{
+   struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+   int ret;
+
+   ret = fimc_is_pipeline_scaler_start(ctx->pipeline,
+   ctx->scaler_id,
+   vq->num_buffers,
+   ctx->fmt->num_planes);
+   if (ret) {
+   v4l2_err(&ctx->subdev, "Scaler start failed.\n");
+   return -EINVAL;
+   }
+
+   set_bit(STATE_RUNNING, &ctx->capture_state);
+   return 0;
+}
+
+static int scaler_video_capture_stop_streaming(struct vb2_queue *vq)
+{
+   struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+   struct fimc_is_buf *buf;
+   int ret;
+
+   ret = fimc_is_pipeline_scaler_stop(ctx->pipeline, ctx->scaler_id);
+   if (ret)
+   v4l2_info(&ctx->subdev, "Scaler already stopped.\n");
+
+   /* Release un-used buffers */
+   while (!list_empty(&ctx->wait_queue)) {
+   buf = fimc_is_scaler_wait_queue_get(ctx);
+   vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
+   }
+   while (!list_empty(&ctx->run_queue)) {
+   buf = fimc_is_scaler_run_queue_get(ctx);
+   vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
+   }
+
+   clear_bit(STATE_RUNNING, &ctx->capture_state);
+   return 0;
+}
+
+static int scaler_video_capture_queue_setup(struct vb2_queue *vq,
+   const struct v4l2_format *pfmt,
+   unsigned int *num_buffers, unsigned int *num_planes,
+   unsigned int sizes[], void *allocators[])
+{
+   struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+   const struct fimc_is_fmt *fmt = ctx->fmt;
+   unsigned int wh;
+   int i;
+
+   if (!fmt)
+   return -EINVAL;
+
+   *num_planes = fmt->num_planes;
+   wh = ctx->width * ctx->height;
+
+   for (i = 0; i < *num_planes; i++) {
+   allocators[i] = ctx->alloc_ctx;
+   sizes[i] = (wh * fmt->depth[i]) / 8;
+   }
+   return 0;
+}
+
+static int scaler_video_capture_buffer_init(struct vb2_buffer *vb)
+{
+   struct vb2_queue *vq = vb->vb2_queue;
+   struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+   struct fimc_is_buf *buf = container_of(vb, struct fimc_is_buf, vb);
+   const struct fimc_is_fmt *fmt;
+   int i;
+
+   fmt = ctx->fmt;
+   for (i = 0; i < fmt->num_planes; i++)
+ 

[PATCH v4 10/13] [media] exynos5-fimc-is: Add the hardware interface module

[Arun Kumar K]

The hardware interface module finally sends the commands to the
FIMC-IS firmware and runs the interrupt handler for getting the
responses.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 .../media/platform/exynos5-is/fimc-is-interface.c  |  810 
 .../media/platform/exynos5-is/fimc-is-interface.h  |  125 +++
 2 files changed, 935 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-interface.c 
b/drivers/media/platform/exynos5-is/fimc-is-interface.c
new file mode 100644
index 000..9fcf89d
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-interface.c
@@ -0,0 +1,810 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Kil-yeon Lim 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include "fimc-is.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-regs.h"
+
+#define init_request_barrier(itf) mutex_init(&itf->request_barrier)
+#define enter_request_barrier(itf) mutex_lock(&itf->request_barrier)
+#define exit_request_barrier(itf) mutex_unlock(&itf->request_barrier)
+
+static inline void itf_get_cmd(struct fimc_is_interface *itf,
+   struct fimc_is_msg *msg, unsigned int index)
+{
+   struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+   memset(msg, 0, sizeof(*msg));
+
+   switch (index) {
+   case INTR_GENERAL:
+   msg->command = com_regs->ihcmd;
+   msg->instance = com_regs->ihc_sensorid;
+   memcpy(msg->param, com_regs->ihc_param,
+   4 * sizeof(msg->param[0]));
+   break;
+   case INTR_SCC_FDONE:
+   msg->command = IHC_FRAME_DONE;
+   msg->instance = com_regs->scc_sensor_id;
+   memcpy(msg->param, com_regs->scc_param,
+   3 * sizeof(msg->param[0]));
+   break;
+   case INTR_SCP_FDONE:
+   msg->command = IHC_FRAME_DONE;
+   msg->instance = com_regs->scp_sensor_id;
+   memcpy(msg->param, com_regs->scp_param,
+   3 * sizeof(msg->param[0]));
+   break;
+   case INTR_META_DONE:
+   msg->command = IHC_FRAME_DONE;
+   msg->instance = com_regs->meta_sensor_id;
+   msg->param[0] = com_regs->meta_param1;
+   break;
+   case INTR_SHOT_DONE:
+   msg->command = IHC_FRAME_DONE;
+   msg->instance = com_regs->shot_sensor_id;
+   memcpy(msg->param, com_regs->shot_param,
+   2 * sizeof(msg->param[0]));
+   break;
+   default:
+   dev_err(itf->dev, "%s Unknown command\n", __func__);
+   break;
+   }
+}
+
+static inline unsigned int itf_get_intr(struct fimc_is_interface *itf)
+{
+   unsigned int status;
+   struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+   status = readl(itf->regs + INTMSR1) | com_regs->ihcmd_iflag |
+   com_regs->scc_iflag |
+   com_regs->scp_iflag |
+   com_regs->meta_iflag |
+   com_regs->shot_iflag;
+
+   return status;
+}
+
+static void itf_set_state(struct fimc_is_interface *itf,
+   unsigned long state)
+{
+   unsigned long flags;
+   spin_lock_irqsave(&itf->slock_state, flags);
+   __set_bit(state, &itf->state);
+   spin_unlock_irqrestore(&itf->slock_state, flags);
+}
+
+static void itf_clr_state(struct fimc_is_interface *itf,
+   unsigned long state)
+{
+   unsigned long flags;
+   spin_lock_irqsave(&itf->slock_state, flags);
+   __clear_bit(state, &itf->state);
+   spin_unlock_irqrestore(&itf->slock_state, flags);
+}
+
+static int itf_get_state(struct fimc_is_interface *itf,
+   unsigned long state)
+{
+   int ret = 0;
+   unsigned long flags;
+
+   spin_lock_irqsave(&itf->slock_state, flags);
+   ret = test_bit(state, &itf->state);
+   spin_unlock_irqrestore(&itf->slock_state, flags);
+   return ret;
+}
+
+static void itf_init_wakeup(struct fimc_is_interface *itf)
+{
+   itf_set_state(itf, IS_IF_STATE_INIT);
+   wake_up(&itf->irq_queue);
+}
+
+void itf_busy_wakeup(struct fimc_is_interface *itf)
+{
+   itf_clr_state(itf, IS_IF_STATE_BUSY);
+   wake_up(&itf->irq_queue);
+}
+
+static int itf_wait_hw_re

[PATCH v4 12/13] V4L: s5k6a3: Change sensor min/max resolutions

[Arun Kumar K]

s5k6a3 sensor has actual pixel resolution of 1408x1402 against
the active resolution 1392x1392. The real resolution is needed
when raw sensor SRGB data is dumped to memory by fimc-lite.

Signed-off-by: Arun Kumar K 
---
 drivers/media/i2c/s5k6a3.c |   21 +
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/media/i2c/s5k6a3.c b/drivers/media/i2c/s5k6a3.c
index ccbb4fc..6dec2ec 100644
--- a/drivers/media/i2c/s5k6a3.c
+++ b/drivers/media/i2c/s5k6a3.c
@@ -25,10 +25,14 @@
 #include 
 #include 
 
-#define S5K6A3_SENSOR_MAX_WIDTH1392
-#define S5K6A3_SENSOR_MAX_HEIGHT   1392
-#define S5K6A3_SENSOR_MIN_WIDTH32
-#define S5K6A3_SENSOR_MIN_HEIGHT   32
+#define S5K6A3_SENSOR_MAX_WIDTH1408
+#define S5K6A3_SENSOR_MAX_HEIGHT   1408
+
+#define S5K6A3_SENSOR_ACTIVE_WIDTH 1392
+#define S5K6A3_SENSOR_ACTIVE_HEIGHT1392
+
+#define S5K6A3_SENSOR_MIN_WIDTH(32 + 16)
+#define S5K6A3_SENSOR_MIN_HEIGHT   (32 + 10)
 
 #define S5K6A3_DEF_PIX_WIDTH   1296
 #define S5K6A3_DEF_PIX_HEIGHT  732
@@ -107,10 +111,11 @@ static void s5k6a3_try_format(struct v4l2_mbus_framefmt 
*mf)
 
fmt = find_sensor_format(mf);
mf->code = fmt->code;
-   v4l_bound_align_image(&mf->width, S5K6A3_SENSOR_MIN_WIDTH,
- S5K6A3_SENSOR_MAX_WIDTH, 0,
- &mf->height, S5K6A3_SENSOR_MIN_HEIGHT,
- S5K6A3_SENSOR_MAX_HEIGHT, 0, 0);
+   v4l_bound_align_image(&mf->width,
+   S5K6A3_SENSOR_MIN_WIDTH, S5K6A3_SENSOR_MAX_WIDTH, 0,
+   &mf->height,
+   S5K6A3_SENSOR_MIN_HEIGHT, S5K6A3_SENSOR_MAX_HEIGHT, 0,
+   0);
 }
 
 static struct v4l2_mbus_framefmt *__s5k6a3_get_format(
-- 
1.7.9.5

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[PATCH v4 11/13] [media] exynos5-is: Add Kconfig and Makefile

[Arun Kumar K]

Adds Kconfig and Makefile for exynos5-is driver files.

Signed-off-by: Shaik Ameer Basha 
Signed-off-by: Kilyeon Im 
Signed-off-by: Arun Kumar K 
---
 drivers/media/platform/Kconfig |1 +
 drivers/media/platform/Makefile|1 +
 drivers/media/platform/exynos5-is/Kconfig  |   20 
 drivers/media/platform/exynos5-is/Makefile |7 +++
 4 files changed, 29 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/Kconfig
 create mode 100644 drivers/media/platform/exynos5-is/Makefile

diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 08de865..4b0475e 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -123,6 +123,7 @@ config VIDEO_S3C_CAMIF
 
 source "drivers/media/platform/soc_camera/Kconfig"
 source "drivers/media/platform/exynos4-is/Kconfig"
+source "drivers/media/platform/exynos5-is/Kconfig"
 source "drivers/media/platform/s5p-tv/Kconfig"
 
 endif # V4L_PLATFORM_DRIVERS
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index eee28dd..40bf09f 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_TV)+= s5p-tv/
 
 obj-$(CONFIG_VIDEO_SAMSUNG_S5P_G2D)+= s5p-g2d/
 obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC) += exynos-gsc/
+obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_CAMERA) += exynos5-is/
 
 obj-$(CONFIG_BLACKFIN)  += blackfin/
 
diff --git a/drivers/media/platform/exynos5-is/Kconfig 
b/drivers/media/platform/exynos5-is/Kconfig
new file mode 100644
index 000..c872757
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/Kconfig
@@ -0,0 +1,20 @@
+config VIDEO_SAMSUNG_EXYNOS5_CAMERA
+   bool "Samsung Exynos5 Media Device driver"
+   depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && PM_RUNTIME
+   depends on VIDEO_SAMSUNG_EXYNOS4_IS
+   help
+ This is a v4l2 based media controller driver for
+ Exynos5 SoC.
+
+if VIDEO_SAMSUNG_EXYNOS5_CAMERA
+
+config VIDEO_SAMSUNG_EXYNOS5_FIMC_IS
+   tristate "Samsung Exynos5 SoC FIMC-IS driver"
+   depends on I2C && OF
+   depends on VIDEO_EXYNOS4_FIMC_IS
+   select VIDEOBUF2_DMA_CONTIG
+   help
+ This is a V4L2 driver for Samsung Exynos5 SoC series Imaging
+ Subsystem known as FIMC-IS.
+
+endif #VIDEO_SAMSUNG_EXYNOS5_MDEV
diff --git a/drivers/media/platform/exynos5-is/Makefile 
b/drivers/media/platform/exynos5-is/Makefile
new file mode 100644
index 000..6cdb037
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/Makefile
@@ -0,0 +1,7 @@
+ccflags-y += -Idrivers/media/platform/exynos4-is
+exynos5-fimc-is-objs := fimc-is-core.o fimc-is-isp.o fimc-is-scaler.o
+exynos5-fimc-is-objs += fimc-is-pipeline.o fimc-is-interface.o fimc-is-sensor.o
+exynos-mdevice-objs := exynos5-mdev.o
+
+obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_FIMC_IS) += exynos5-fimc-is.o
+obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_CAMERA) += exynos-mdevice.o
-- 
1.7.9.5

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[PATCH v4 09/13] [media] exynos5-fimc-is: Add the hardware pipeline control

[Arun Kumar K]

This patch adds the crucial hardware pipeline control for the
fimc-is driver. All the subdev nodes will call this pipeline
interfaces to reach the hardware. Responsibilities of this module
involves configuring and maintaining the hardware pipeline involving
multiple sub-ips like ISP, DRC, Scalers, ODC, 3DNR, FD etc.

Signed-off-by: Arun Kumar K 
Signed-off-by: Kilyeon Im 
---
 .../media/platform/exynos5-is/fimc-is-pipeline.c   | 1691 
 .../media/platform/exynos5-is/fimc-is-pipeline.h   |  127 ++
 2 files changed, 1818 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-pipeline.c 
b/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
new file mode 100644
index 000..e37ce56
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
@@ -0,0 +1,1691 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K 
+ * Kil-yeon Lim 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "fimc-is.h"
+#include "fimc-is-pipeline.h"
+#include "fimc-is-metadata.h"
+#include "fimc-is-regs.h"
+#include "fimc-is-cmd.h"
+#include 
+#include 
+
+/* Default setting values */
+#define DEFAULT_PREVIEW_STILL_WIDTH1280
+#define DEFAULT_PREVIEW_STILL_HEIGHT   720
+#define DEFAULT_CAPTURE_VIDEO_WIDTH1920
+#define DEFAULT_CAPTURE_VIDEO_HEIGHT   1080
+#define DEFAULT_CAPTURE_STILL_WIDTH2560
+#define DEFAULT_CAPTURE_STILL_HEIGHT   1920
+#define DEFAULT_CAPTURE_STILL_CROP_WIDTH   2560
+#define DEFAULT_CAPTURE_STILL_CROP_HEIGHT  1440
+#define DEFAULT_PREVIEW_VIDEO_WIDTH640
+#define DEFAULT_PREVIEW_VIDEO_HEIGHT   480
+
+/* Init params for pipeline devices */
+static const struct sensor_param init_sensor_param = {
+   .frame_rate = {
+   .frame_rate = 30,
+   },
+};
+
+static const struct isp_param init_isp_param = {
+   .control = {
+   .cmd = CONTROL_COMMAND_START,
+   .bypass = CONTROL_BYPASS_DISABLE,
+   },
+   .otf_input = {
+   .cmd = OTF_INPUT_COMMAND_DISABLE,
+   .width = DEFAULT_CAPTURE_STILL_WIDTH,
+   .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+   .format = OTF_INPUT_FORMAT_BAYER,
+   .bitwidth = OTF_INPUT_BIT_WIDTH_10BIT,
+   .order = OTF_INPUT_ORDER_BAYER_GR_BG,
+   .frametime_max = 3,
+   },
+   .dma1_input = {
+   .cmd = DMA_INPUT_COMMAND_DISABLE,
+   },
+   .dma2_input = {
+   .cmd = DMA_INPUT_COMMAND_DISABLE,
+   },
+   .aa = {
+   .cmd = ISP_AA_COMMAND_START,
+   .target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
+   ISP_AA_TARGET_AWB,
+   .mode = ISP_AF_CONTINUOUS,
+   },
+   .flash = {
+   .cmd = ISP_FLASH_COMMAND_DISABLE,
+   .redeye = ISP_FLASH_REDEYE_DISABLE,
+   },
+   .awb = {
+   .cmd = ISP_AWB_COMMAND_AUTO,
+   },
+   .effect = {
+   .cmd = ISP_IMAGE_EFFECT_DISABLE,
+   },
+   .iso = {
+   .cmd = ISP_ISO_COMMAND_AUTO,
+   },
+   .adjust = {
+   .cmd = ISP_ADJUST_COMMAND_AUTO,
+   },
+   .metering = {
+   .cmd = ISP_METERING_COMMAND_CENTER,
+   .win_width = DEFAULT_CAPTURE_STILL_WIDTH,
+   .win_height = DEFAULT_CAPTURE_STILL_HEIGHT,
+   },
+   .afc = {
+   .cmd = ISP_AFC_COMMAND_AUTO,
+   },
+   .otf_output = {
+   .cmd = OTF_OUTPUT_COMMAND_ENABLE,
+   .width = DEFAULT_CAPTURE_STILL_WIDTH,
+   .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+   .format = OTF_OUTPUT_FORMAT_YUV444,
+   .bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT,
+   .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+   },
+   .dma1_output = {
+   .cmd = DMA_OUTPUT_COMMAND_DISABLE,
+   .width = DEFAULT_CAPTURE_STILL_WIDTH,
+   .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+   .format = DMA_INPUT_FORMAT_YUV444,
+   .bitwidth = DMA_INPUT_BIT_WIDTH_8BIT,
+   .plane = 1,
+   .order = DMA_INPUT_ORDER_YCBCR,
+   },
+   .dma2_output = {
+   .cmd = DMA_OUTPUT_COMMAND_DISABLE,
+   .width = DEFAULT_CAPTURE_STILL_WIDTH,
+   .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+   .format = DMA_OUTPUT_FORMAT_BAYER,
+   .bitwidth = DMA_OUTPUT_BIT_WIDTH_12BIT,