[PATCH] spi: s3c64xx: Remove unused platform_device_id entries

[Sylwester Nawrocki]

s5pv210 and exynos4 are now DT only platforms hence these
entries can now be safely removed from the match table.

Signed-off-by: Sylwester Nawrocki <s.nawro...@samsung.com>
---
 drivers/spi/spi-s3c64xx.c |6 --
 1 file changed, 6 deletions(-)

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 8e86e7f..ec697fe 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -1370,12 +1370,6 @@ static const struct platform_device_id 
s3c64xx_spi_driver_ids[] = {
}, {
.name   = "s3c6410-spi",
.driver_data= (kernel_ulong_t)_spi_port_config,
-   }, {
-   .name   = "s5pv210-spi",
-   .driver_data= (kernel_ulong_t)_spi_port_config,
-   }, {
-   .name   = "exynos4210-spi",
-   .driver_data= (kernel_ulong_t)_spi_port_config,
},
{ },
 };
-- 
1.7.9.5

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Re: [GIT PULL] clk/samsung updates for v4.5

[Sylwester Nawrocki]

Hello Mike,

On 22/12/15 19:38, Mike Turquette wrote:
> Pulled.
> 
> Was it necessary to base on -rc5? That required me to update my tree
> from -rc1.
> 
> This is not difficult, but it is a bit annoying when it is not strictly
> necessary just to take one PR.

Sorry about that, originally I've put some of those patches in
a branch for 4.4 fixes PR and then reused it for this one,
forgetting to change the base to the one used in clk tree.

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Re: [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL block clocks

[Sylwester Nawrocki]

Mike,

On 22/12/15 19:44, Mike Turquette wrote:
> This is superseded by the pull request found in Message-ID:
> <5671a456.9030...@samsung.com>, correct?

The two pull requests are based on same branch, first 2 commits are
tagged with for-4.5-clk-exynos5420 tag and the whole branch is tagged
as clk-samsung-4.5. I assumed it's fine to use just the below tag for
arm-soc.

>>> > > The following changes since commit 
>>> > > 9f9499ae8e6415cefc4fe0a96ad0e27864353c89:
>>> > > 
>>> > >   Linux 4.4-rc5 (2015-12-13 17:42:58 -0800)
>>> > > 
>>> > > are available in the git repository at:
>>> > > 
>>> > >   git://linuxtv.org/snawrocki/samsung.git tags/for-4.5-clk-exynos5420
>>> > > 
>>> > > for you to fetch changes up to bee4f87f01dc30fcf9e05eb55b833f89fd9bb4f4:
>>> > > 
>>> > >   clk: samsung: exynos5420: add cpu clock configuration data and 
>>> > > instantiate cpu clock (2015-12-16 16:35:26 +0100)
>>> > > 
>>> > > 
>>> > > Samsung exynos5420 SoC clk subsystem support updates:
>>> > > instantiation of the cpu clocks and addition of the GSCL
>>> > > IP parent clocks to the list of available consumer clocks.
>>> > > 
>>> > > 
>>> > > Marek Szyprowski (1):
>>> > >   clk: samsung: exynos542x: add missing parent GSCL block clocks
>>> > > 
>>> > > Thomas Abraham (1):
>>> > >   clk: samsung: exynos5420: add cpu clock configuration data and 
>>> > > instantiate cpu clock
>>> > > 
>>> > >  drivers/clk/samsung/clk-exynos5420.c   |   66 
>>> > > +---
>>> > >  include/dt-bindings/clock/exynos5420.h |4 ++
>>> > >  2 files changed, 64 insertions(+), 6 deletions(-)

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Re: [PATCH v3] clk: s3c2410: removed unneeded variable in s3c24xx_clkout_set_parent

[Sylwester Nawrocki]

On 30/11/15 11:08, Mutharaju, Prasanna (P.) wrote:
> From: Prasanna Karthik 
> 
> Remove unneeded variable used to store return value.
> 
> Signed-off-by: Prasanna Karthik 

Patch applied, thanks.
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[GIT PULL] clk/samsung updates for v4.5

[Sylwester Nawrocki]

The following changes since commit 9f9499ae8e6415cefc4fe0a96ad0e27864353c89:

  Linux 4.4-rc5 (2015-12-13 17:42:58 -0800)

are available in the git repository at:

  git://linuxtv.org/snawrocki/samsung.git tags/clk-samsung-4.5

for you to fetch changes up to c5e949c1c24d67ae2813afdf02408a9b0c6fe55c:

  clk: s3c2410: removed unneeded variable in s3c24xx_clkout_set_parent 
(2015-12-16 16:36:04 +0100)


drivers/clk/samsung updates (mostly bug fixes):
 - instantiation of the cpu clocks and addition of the GSCL
   IP parent clocks to the list of available consumer clocks
   for exynos542x SoCs;
 - MFC IP parent clock fix for exynos542x;
 - fix of locking bug in samsung/clk-cpu.c which caused
   system crashes with cpufreq enabled;
 - minor cleanup for s3c2410.


Bartlomiej Zolnierkiewicz (1):
  clk: samsung: exynos542x/5800: fix cpu clock configuration data

Marek Szyprowski (3):
  clk: samsung: exynos542x: add missing parent GSCL block clocks
  clk: samsung: exynos542x: fix MFC clock hierarchy parent
  clk: exynos: use irqsave version of spin_lock to avoid deadlock with irqs

Prasanna Karthik (1):
  clk: s3c2410: removed unneeded variable in s3c24xx_clkout_set_parent

Thomas Abraham (1):
  clk: samsung: exynos5420: add cpu clock configuration data and 
instantiate cpu clock

 drivers/clk/samsung/clk-cpu.c  |   10 ++--
 drivers/clk/samsung/clk-exynos5420.c   |   98 +---
 drivers/clk/samsung/clk-s3c2410-dclk.c |3 +-
 include/dt-bindings/clock/exynos5420.h |4 ++
 4 files changed, 102 insertions(+), 13 deletions(-)

-- 
Thanks,
Sylwester
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Re: [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL block clocks

[Sylwester Nawrocki]

Krzysztof,

On 09/12/15 14:36, Krzysztof Kozlowski wrote:
> W dniu 09.12.2015 o 19:14, Sylwester Nawrocki pisze:
>> > Adding Stephen and linux-clk at Cc.
>> > 
>> > On 09/12/15 05:49, Krzysztof Kozlowski wrote:
>>> >> On 08.12.2015 22:46, Marek Szyprowski wrote:
>>>>> >>>> This patch adds clocks, which are required for preserving parent 
>>>>> >>>> clock
>>>>> >>>> configuration on GSCL power domain on/off.
>>>>> >>>>
>>>>> >>>> Signed-off-by: Marek Szyprowski <m.szyprow...@samsung.com>
>>>>> >>>> ---
>>>>> >>>>  drivers/clk/samsung/clk-exynos5420.c   | 8 
>>>>> >>>>  include/dt-bindings/clock/exynos5420.h | 2 ++
>>>>> >>>>  2 files changed, 6 insertions(+), 4 deletions(-)
>>> >>
>>> >> I suppose that, with ack from clock folks, this can go through 
>>> >> samsung-soc?
>> > 
>> > I guess it makes more sense that making a stable branch with just
>> > this patch to be pulled into arm-soc and clk tree. I'm fine with
>> > applying this patch through arm-soc, but I think we also need
>> > Mike's or Stephen ack for this.
>> > 
>> > Acked-by: Sylwester Nawrocki <s.nawro...@samsung.com>
>
> I am fine with the branch approach (actually in such cases I make them
> anyway just in case).
> 
> As you suggested I'll wait for Mike's or Stepen's acks.

I've put the $subject patch and the other exynos5420 patch which 
was a dependency for dts patches (both touching include/dt-bindings/
clock/exynos5420.h) onto a stable branch. Below are details if 
you need to pull.


The following changes since commit 9f9499ae8e6415cefc4fe0a96ad0e27864353c89:

  Linux 4.4-rc5 (2015-12-13 17:42:58 -0800)

are available in the git repository at:

  git://linuxtv.org/snawrocki/samsung.git tags/for-4.5-clk-exynos5420

for you to fetch changes up to bee4f87f01dc30fcf9e05eb55b833f89fd9bb4f4:

  clk: samsung: exynos5420: add cpu clock configuration data and instantiate 
cpu clock (2015-12-16 16:35:26 +0100)


Samsung exynos5420 SoC clk subsystem support updates:
instantiation of the cpu clocks and addition of the GSCL
IP parent clocks to the list of available consumer clocks.


Marek Szyprowski (1):
  clk: samsung: exynos542x: add missing parent GSCL block clocks

Thomas Abraham (1):
  clk: samsung: exynos5420: add cpu clock configuration data and 
instantiate cpu clock

 drivers/clk/samsung/clk-exynos5420.c   |   66 +---
 include/dt-bindings/clock/exynos5420.h |4 ++
 2 files changed, 64 insertions(+), 6 deletions(-)

-- 
Thanks
Sylwester
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Re: [PATCH] clk: exynos: use irqsave version of spin_lock to avoid deadlock with irqs

[Sylwester Nawrocki]

On 11/12/15 15:38, Marek Szyprowski wrote:
> It is allowed to enable/disable clocks from interrupts, so common Exynos
> ARM clock management code for CPUfreq should use 'irqsave' version of
> spin_lock calls to avoid potential deadlock caused by spin_lock recursion.
> The same spin_lock is used by gate/mux clocks during enable/disable calls.
> 
> This deadlock, can be reproduced by enabling CPUfreq (ondemand or
> userspace) and decoding video with s5p-mfc driver.

> Signed-off-by: Marek Szyprowski <m.szyprow...@samsung.com>
> CC: sta...@vger.kernel.org  # v4.2+

Acked-by: Sylwester Nawrocki <s.nawro...@samsung.com>

Mike, Stephen, could you apply this patch directly?
It would be nice to have it in 4.4 as the bug fixed here causes
some of exynos boards in mainline to fail booting with default
config. I could resend the patch directly to you if needed.

Thanks,
Sylwester

> ---
>  drivers/clk/samsung/clk-cpu.c | 10 ++
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
> index 2fe37f708dc7..813003d6ce09 100644
> --- a/drivers/clk/samsung/clk-cpu.c
> +++ b/drivers/clk/samsung/clk-cpu.c
> @@ -148,6 +148,7 @@ static int exynos_cpuclk_pre_rate_change(struct 
> clk_notifier_data *ndata,
>   unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent);
>   unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
>   unsigned long div0, div1 = 0, mux_reg;
> + unsigned long flags;
>  
>   /* find out the divider values to use for clock data */
>   while ((cfg_data->prate * 1000) != ndata->new_rate) {
> @@ -156,7 +157,7 @@ static int exynos_cpuclk_pre_rate_change(struct 
> clk_notifier_data *ndata,
>   cfg_data++;
>   }
>  
> - spin_lock(cpuclk->lock);
> + spin_lock_irqsave(cpuclk->lock, flags);
>  
>   /*
>* For the selected PLL clock frequency, get the pre-defined divider
> @@ -212,7 +213,7 @@ static int exynos_cpuclk_pre_rate_change(struct 
> clk_notifier_data *ndata,
>   DIV_MASK_ALL);
>   }
>  
> - spin_unlock(cpuclk->lock);
> + spin_unlock_irqrestore(cpuclk->lock, flags);
>   return 0;
>  }
>  
> @@ -223,6 +224,7 @@ static int exynos_cpuclk_post_rate_change(struct 
> clk_notifier_data *ndata,
>   const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
>   unsigned long div = 0, div_mask = DIV_MASK;
>   unsigned long mux_reg;
> + unsigned long flags;
>  
>   /* find out the divider values to use for clock data */
>   if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
> @@ -233,7 +235,7 @@ static int exynos_cpuclk_post_rate_change(struct 
> clk_notifier_data *ndata,
>   }
>   }
>  
> - spin_lock(cpuclk->lock);
> + spin_lock_irqsave(cpuclk->lock, flags);
>  
>   /* select mout_apll as the alternate parent */
>   mux_reg = readl(base + E4210_SRC_CPU);
> @@ -246,7 +248,7 @@ static int exynos_cpuclk_post_rate_change(struct 
> clk_notifier_data *ndata,
>   }
>  
>   exynos_set_safe_div(base, div, div_mask);
> - spin_unlock(cpuclk->lock);
> + spin_unlock_irqrestore(cpuclk->lock, flags);
>   return 0;
>  }
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Re: [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL block clocks

[Sylwester Nawrocki]

Adding Stephen and linux-clk at Cc.

On 09/12/15 05:49, Krzysztof Kozlowski wrote:
> On 08.12.2015 22:46, Marek Szyprowski wrote:
>> > This patch adds clocks, which are required for preserving parent clock
>> > configuration on GSCL power domain on/off.
>> > 
>> > Signed-off-by: Marek Szyprowski <m.szyprow...@samsung.com>
>> > ---
>> >  drivers/clk/samsung/clk-exynos5420.c   | 8 
>> >  include/dt-bindings/clock/exynos5420.h | 2 ++
>> >  2 files changed, 6 insertions(+), 4 deletions(-)
>
> I suppose that, with ack from clock folks, this can go through samsung-soc?

I guess it makes more sense that making a stable branch with just
this patch to be pulled into arm-soc and clk tree. I'm fine with
applying this patch through arm-soc, but I think we also need
Mike's or Stephen ack for this.

Acked-by: Sylwester Nawrocki <s.nawro...@samsung.com>

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Re: [PATCH v3 06/10] clk: samsung: exynos5800: fix cpu clock configuration data

[Sylwester Nawrocki]

On 04/12/15 18:30, Bartlomiej Zolnierkiewicz wrote:
> Fix cpu clock configuration data for Exynos5800 (it uses
> higher PCLK_DBG divider values than Exynos5420 and supports
> additional frequencies).
> 
> Based on Hardkernel's kernel for ODROID-XU3 board.
> 
> Cc: Tomasz Figa <tomasz.f...@gmail.com>
> Cc: Mike Turquette <mturque...@linaro.org>
> Cc: Javier Martinez Canillas <jav...@osg.samsung.com>
> Cc: Thomas Abraham <thomas...@samsung.com>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnier...@samsung.com>

Acked-by: Sylwester Nawrocki <s.nawro...@samsung.com>

-- 
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Re: [PATCH v3 03/10] clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock

[Sylwester Nawrocki]

On 04/12/15 18:30, Bartlomiej Zolnierkiewicz wrote:
> From: Thomas Abraham <thomas...@samsung.com>
> 
> With the addition of the new Samsung specific cpu-clock type, the
> arm clock can be represented as a cpu-clock type. Add the CPU clock
> configuration data and instantiate the CPU clock type for Exynos5420.
> 
> Changes by Bartlomiej:
> - split Exynos5420 support from the original patches
> - moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
> 
> Cc: Tomasz Figa <tomasz.f...@gmail.com>
> Cc: Mike Turquette <mturque...@linaro.org>
> Cc: Javier Martinez Canillas <jav...@osg.samsung.com>
> Signed-off-by: Thomas Abraham <thomas...@samsung.com>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnier...@samsung.com>

Acked-by: Sylwester Nawrocki <s.nawro...@samsung.com>

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Re: [PATCH 1/2] clk: samsung: Don't build ARMv8 clock drivers on ARMv7

[Sylwester Nawrocki]

On 19/11/15 10:16, Tomasz Figa wrote:
> 2015-11-19 13:51 GMT+09:00 Krzysztof Kozlowski :
>> > On 19.11.2015 13:18, Tomasz Figa wrote:
>>> >> However, I don't think we can disable compilation of particular
>>> >> 64-bit SoCs, so maybe there isn't much sense in splitting their 
>>> >> clock drivers into separate symbols?
>> >
>> > To me it does not really matter. Indeed as you said one cannot 
>> > disable building of one particular Exynos SoCs.
>> >
>> > However we could still want not build some parts of such SoCs (like
>> > clock, pinctrl etc). I don't see much benefit for such case except
>> > when someone would like to drastically reduce the size of kernel 
>> > image (for whatever reasons he has.).
>
> Can we really build a kernel that support selected Exynos SoC without
> its clock driver? Actually I don't think we even allow deselecting
> clock drivers currently, because they are not visible in menuconfig.
> Unless there is a clear goal to separate ARCH level Kconfig symbol for
> particular ARM64-based Exynos SoCs, I don't think it makes any sense
> to keep the clock-related symbols separate.
> 
>> >
>> > On the other hand having separate symbols causes duplication and
>> > obfuscates a little the Kconfig/Makefile. I like keeping things 
>> > simple so one symbol for all ARM64 Exynos clocks sounds good.
>> >
>> > Sylwester preferred current approach. You and Pankaj seem to prefer
>> > one symbol-way.
>
> Hmm, I read Sylwester's post as a reply to your original message and
> not Pankaj's. Sylwester, could you clarify?

OK, let's just use a common clk Kconfig symbol for Exynos ARM64.

What I tried to say is that with addition of support for few more
of those SoCs the kernel image size can easily grow by 1MB order,
due to just clk drivers inclusion. Perhaps it's not a big issue
with current hardware configuration.
Maybe in long term we should think about splitting CMU drivers
into a built-in critical clocks part and the rest in loadable
modules.

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Re: [PATCH 1/2] clk: samsung: Don't build ARMv8 clock drivers on ARMv7

[Sylwester Nawrocki]

On 17/11/15 05:39, Krzysztof Kozlowski wrote:
> On 17.11.2015 13:31, pankaj.dubey wrote:
>> On Monday 16 November 2015 07:06 AM, Krzysztof Kozlowski wrote:
>>> Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS
>>> so it is built also on ARMv7. This does not bring any kind of benefit.
>>> There won't be a single kernel image for ARMv7 and ARMv8 SoCs (like
>>> multi_v7 for ARMv7).
>>>
>>> Instead build clock drivers only for respective SoC's architecture.
>>>
>>> Signed-off-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
>>> ---
>>>  drivers/clk/samsung/Kconfig  | 13 +
>>>  drivers/clk/samsung/Makefile |  4 ++--
>>>  2 files changed, 15 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
>>> index 84196ecdaa12..5f138fc4d84d 100644
>>> --- a/drivers/clk/samsung/Kconfig
>>> +++ b/drivers/clk/samsung/Kconfig
>>> @@ -2,6 +2,7 @@ config COMMON_CLK_SAMSUNG
>>> bool
>>> select COMMON_CLK
>>>  
>>> +# ARMv7 SoCs:
>>>  config S3C2410_COMMON_CLK
>>> bool
>>> select COMMON_CLK_SAMSUNG
>>> @@ -24,3 +25,15 @@ config S3C2443_COMMON_CLK
>>> bool
>>> select COMMON_CLK_SAMSUNG
>>>  
>>> +# ARMv8 SoCs:
>>> +config EXYNOS5433_COMMON_CLK
>>> +   bool
>>> +   depends on ARM64 || COMPILE_TEST
>>> +   default ARCH_EXYNOS
>>> +   select COMMON_CLK_SAMSUNG
>>> +
>>> +config EXYNOS7_COMMON_CLK
>>> +   bool
>>> +   depends on ARM64 || COMPILE_TEST
>>> +   default ARCH_EXYNOS
>>> +   select COMMON_CLK_SAMSUNG
>>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>>> index 5f6833ea355d..a31332a24ef4 100644
>>> --- a/drivers/clk/samsung/Makefile
>>> +++ b/drivers/clk/samsung/Makefile
>>> @@ -10,11 +10,11 @@ obj-$(CONFIG_SOC_EXYNOS5250)+= clk-exynos5250.o
>>>  obj-$(CONFIG_SOC_EXYNOS5260)   += clk-exynos5260.o
>>>  obj-$(CONFIG_SOC_EXYNOS5410)   += clk-exynos5410.o
>>>  obj-$(CONFIG_SOC_EXYNOS5420)   += clk-exynos5420.o
>>> -obj-$(CONFIG_ARCH_EXYNOS)  += clk-exynos5433.o
>>> +obj-$(CONFIG_EXYNOS5433_COMMON_CLK)+= clk-exynos5433.o
>>>  obj-$(CONFIG_SOC_EXYNOS5440)   += clk-exynos5440.o
>>>  obj-$(CONFIG_ARCH_EXYNOS)  += clk-exynos-audss.o
>>>  obj-$(CONFIG_ARCH_EXYNOS)  += clk-exynos-clkout.o
>>> -obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o
>>> +obj-$(CONFIG_EXYNOS7_COMMON_CLK)   += clk-exynos7.o
>>>  obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
>>>  obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
>>>  obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
>>>
>>
>> So in this approach we need to add separate config for clock support of
>> each ARM64 Exynos64 SoC. Is this fine?
>>
>> Can we club compilation of each ARM64 Exynos SoC clock file under
>> EXYNOS7_COMMON_CLK? As for all ARM64 SoC there is single defconfig and
>> binary.
> 
> Yes, it can be one config symbol for all clocks of ARMv8 Exynos SoCs.
> From my point of view both has some advantages and disadvantages (kernel
> size, granularity, number of Kconfig symbols etc.) and I don't mind
> choosing different than I selected before.
> 
> Any opinion from Samsung clock maintainers? Which do you prefer?

It would have been a bit unfortunate to not be able to exclude
the unneeded clk drivers from build.  From my side both patches
look like a step in right direction.

For the $subject patch:

Acked-by: Sylwester Nawrocki <s.nawro...@samsung.com>

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Re: [PATCH 01/10] clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks

[Sylwester Nawrocki]

On 20/10/15 12:34, Michael Turquette wrote:
>> diff --git a/include/dt-bindings/clock/exynos5433.h 
>> b/include/dt-bindings/clock/exynos5433.h
>> > index 5bd80d5..4f0d566 100644
>> > --- a/include/dt-bindings/clock/exynos5433.h
>> > +++ b/include/dt-bindings/clock/exynos5433.h
>> > @@ -765,7 +765,10 @@
>> >  #define CLK_SCLK_RGB_VCLK  109
>> >  #define CLK_SCLK_RGB_TV_VCLK   110
>> >  
>> > -#define DISP_NR_CLK111
>> > +#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY  111
>> > +#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY   112
>> > +
>> > +#define DISP_NR_CLK113
>
> Why break compatibility with older DTBs?

I used to be resistant to changing those _NR_CLK defines
in the past but then realized they are not part of the DT ABI.
These defines are used only in drivers and affect only size
of the provider's allocated clock array. The confusion may be
caused by the fact that the whole header is shared by the kernel
source and dts.

$ git grep -l _NR_CLK arch/arm/boot/dts drivers/clk/samsung/
drivers/clk/samsung/clk-exynos-clkout.c
drivers/clk/samsung/clk-exynos3250.c
drivers/clk/samsung/clk-exynos4.c
drivers/clk/samsung/clk-exynos4415.c
drivers/clk/samsung/clk-exynos5250.c
drivers/clk/samsung/clk-exynos5260.c
drivers/clk/samsung/clk-exynos5410.c
drivers/clk/samsung/clk-exynos5420.c
drivers/clk/samsung/clk-exynos5433.c
drivers/clk/samsung/clk-exynos5440.c
drivers/clk/samsung/clk-exynos7.c

There is no *_NR_CLK in any dts file.
New kernel will work will older DTB, the driver will just
register more clocks, which will not be dereferenced anywhere
in older dtb.

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Re: [PATCH 04/10] dt-bindings: video: add PCLK clock entry to exynos5433-decon

[Sylwester Nawrocki]

On 20/10/15 14:24, Krzysztof Kozlowski wrote:
> W dniu 20.10.2015 o 18:22, Andrzej Hajda pisze:
>> > DECON IP requires this clock to access configuration registers.
>> > 
>> > Signed-off-by: Andrzej Hajda 
>> > ---
>> >  Documentation/devicetree/bindings/video/exynos5433-decon.txt | 2 +-
>> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> > 
>> > diff --git a/Documentation/devicetree/bindings/video/exynos5433-decon.txt 
>> > b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
>> > index 377afbf..3dff78b 100644
>> > --- a/Documentation/devicetree/bindings/video/exynos5433-decon.txt
>> > +++ b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
>> > @@ -16,7 +16,7 @@ Required properties:
>> >  - clocks: must include clock specifiers corresponding to entries in the
>> >  clock-names property.
>> >  - clock-names: list of clock names sorted in the same order as the clocks
>> > - property. Must contain "aclk_decon", "aclk_smmu_decon0x",
>> > + property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
>
> I assume that old DTB wouldn't work at all, so there is no point in
> maintaining ABI compatibility?

As you know there is no single exynos5433 board dts that would use
the DECON IP block in mainline yet. I doubt anyone at this point
in mainline cares whether we require this additional clock or not.

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Re: [PATCH] arm: dts: Fix audio card detection on peach boards

[Sylwester Nawrocki]

On 12/10/15 08:47, Krzysztof Kozlowski wrote:
>> diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts 
>> b/arch/arm/boot/dts/exynos5420-peach-pit.dts
>> > index 8f4d76c..525a93a 100644
>> > --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
>> > +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
>> > @@ -1056,5 +1056,10 @@
>> >timeout-sec = <32>;
>> >  };
>> >  
>> > +_system_controller {
>
> Please put the node in alphabetical order.
> 
>> > +  assigned-clocks = <_system_controller 0>;
>> > +  assigned-clock-parents =  < CLK_FIN_PLL>;
>
> I might be missing something here but isn't the first clock of
> pmu_system_controller already a CLK_FIN_PLL? So you are reparenting the
> FIN_PLL to FIN_PLL?

No, it's not, the first PMU consumer clock is indeed CLK_FIN_PLL,
but pmu_system_controller is also a clock provider.  The first output
clock of pmu_system_controller is CLKOUT, it's a composite mux and
gate clock (registered in drivers/clk/samsung /clk-exynos-clkout.c).
So  the above dts change is selecting an external oscillator input of
the CLKOUT mux, i.e. it will route 24 MHz clock signal from the external
oscillator to the CLKOUT output pin, to which audio CODEC is connected
on peach-pit AFAICS.

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Re: [GIT PULL] clk/samsung updates for v4.4

[Sylwester Nawrocki]

On 02/10/15 20:37, Stephen Boyd wrote:
> On 10/02, Sylwester Nawrocki wrote:
...
> Thanks, pulled. I put this patch on top though.

Thanks for taking care of this, I'll make sure such issues
are fixed before sending any future pull requests.

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Re: [PATCH 5/7] [media] mipi-csis: make sparse happy

[Sylwester Nawrocki]

On 05/10/15 13:07, Arnd Bergmann wrote:
> On Monday 05 October 2015 12:24:40 Sylwester Nawrocki wrote:
>> > On 03/10/15 00:25, Arnd Bergmann wrote:
>>> > > On Thursday 01 October 2015 19:17:27 Mauro Carvalho Chehab wrote:
>>>>> > >> > diff --git a/drivers/media/platform/exynos4-is/mipi-csis.c 
>>>>> > >> > b/drivers/media/platform/exynos4-is/mipi-csis.c
>>>>> > >> > index d74e1bec3d86..4b85105dc159 100644
>>>>> > >> > --- a/drivers/media/platform/exynos4-is/mipi-csis.c
>>>>> > >> > +++ b/drivers/media/platform/exynos4-is/mipi-csis.c
>>>>> > >> > @@ -706,7 +706,8 @@ static irqreturn_t s5pcsis_irq_handler(int 
>>>>> > >> > irq, void *dev_id)
>>>>> > >> > else
>>>>> > >> > offset = S5PCSIS_PKTDATA_ODD;
>>>>> > >> >  
>>>>> > >> > -   memcpy(pktbuf->data, state->regs + offset, 
>>>>> > >> > pktbuf->len);
>>>>> > >> > +   memcpy(pktbuf->data, (u8 __force *)state->regs + 
>>>>> > >> > offset,
>>>>> > >> > +  pktbuf->len);
>>>>> > >> > pktbuf->data = NULL;
>>>>> > >> > 
>>> > >
>>> > > I think this is what memcpy_toio() is meant for.
>> > 
>> > Exactly memcpy_fromio().  But it's implementation is inefficient on
>> > ARCH=arm, memcpy_fromio() will be translated to a loop of readb(),
>> > only if an arm sub-architecture provides a processor instruction
>> > to access memory by byte.  Each readb() also involves a memory barrier.
>> > That's all what we wanted to avoid. AFAIR using memcpy_fromio() was
>> > causing increase of the copy operation several times comparing to
>> > memcpy(). On arm64 it looks better, but this driver is currently
>> > used only on arm32.
>> > 
>> > I would prefer to add (void __force *) instead:
>> > 
>> > memcpy(pktbuf->data, (void __force *)state->regs + offset, pktbuf->len);
>> > 
>> > Alternatively, the memset could just be replaced by a loop of
>> > u32 reads - __raw_readl();
>
> You are right for old kernels, but this was fixed in 7ddfe625cb ("ARM:
> optimize memset_io()/memcpy_fromio()/memcpy_toio()") at least for
> little-endian kernels and should be fine now on ARM just like
> everywhere else.

Indeed, I had just previously checked it in 4.0 kernel and missed those
recent further optimizations. It should be fine to replace memcpy()
with memcpy_fromio() then.

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Re: [PATCH 5/7] [media] mipi-csis: make sparse happy

[Sylwester Nawrocki]

On 03/10/15 00:25, Arnd Bergmann wrote:
> On Thursday 01 October 2015 19:17:27 Mauro Carvalho Chehab wrote:
>> > diff --git a/drivers/media/platform/exynos4-is/mipi-csis.c 
>> > b/drivers/media/platform/exynos4-is/mipi-csis.c
>> > index d74e1bec3d86..4b85105dc159 100644
>> > --- a/drivers/media/platform/exynos4-is/mipi-csis.c
>> > +++ b/drivers/media/platform/exynos4-is/mipi-csis.c
>> > @@ -706,7 +706,8 @@ static irqreturn_t s5pcsis_irq_handler(int irq, void 
>> > *dev_id)
>> > else
>> > offset = S5PCSIS_PKTDATA_ODD;
>> >  
>> > -   memcpy(pktbuf->data, state->regs + offset, pktbuf->len);
>> > +   memcpy(pktbuf->data, (u8 __force *)state->regs + offset,
>> > +  pktbuf->len);
>> > pktbuf->data = NULL;
>> > 
>
> I think this is what memcpy_toio() is meant for.

Exactly memcpy_fromio().  But it's implementation is inefficient on
ARCH=arm, memcpy_fromio() will be translated to a loop of readb(),
only if an arm sub-architecture provides a processor instruction
to access memory by byte.  Each readb() also involves a memory barrier.
That's all what we wanted to avoid. AFAIR using memcpy_fromio() was
causing increase of the copy operation several times comparing to
memcpy(). On arm64 it looks better, but this driver is currently
used only on arm32.

I would prefer to add (void __force *) instead:

memcpy(pktbuf->data, (void __force *)state->regs + offset, pktbuf->len);

Alternatively, the memset could just be replaced by a loop of
u32 reads - __raw_readl();

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[GIT PULL] clk/samsung updates for v4.4

[Sylwester Nawrocki]

The following changes since commit 6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357f:

  Linux 4.3-rc1 (2015-09-12 16:35:56 -0700)

are available in the git repository at:

  git://linuxtv.org/snawrocki/samsung.git tags/clk-samsung-4.4

for you to fetch changes up to 7993b3ebec979b23c2d7425959c9d232c452498b:

  clk: samsung: exynos7: Add required clock tree for UFS (2015-09-15 11:18:15 
+0200)


Fixes, improvements and addition of some missing features
of the exynos7 clock controller driver.


Alim Akhtar (16):
  clk: samsung: exynos7: Fix CMU TOPC block clock
  clk: samsung: exynos7: Fix CMU TOP1 block
  clk: samsung: exynos7: Correct nr_clk_ids for fsys0
  clk: samsung: exynos7: Correct nr_clk_ids for fsys1
  clk: samsung: exynos7: Change the CMU_TOPC block clock names
  clk: samsung: exynos7: Adds missing clocks gates of CMU_TOPC
  clk: samsung: exynos7: Correct CMU_TOP0 clocks names
  clk: samsung: exynos7: Correct CMU_TOP1 clocks names
  clk: samsung: exynos7: Correct CMU_CCORE clocks names
  clk: samsung: exynos7: Correct CMU_PERIC0 clocks names
  clk: samsung: exynos7: Correct CMU_PERIC1 clocks names
  clk: samsung: exynos7: Correct CMU_PERIS clocks names
  clk: samsung: exynos7: Correct CMU_FSYS0 clocks names
  clk: samsung: exynos7: Correct CMU_FSYS1 clocks names
  clk: samsung: exynos7: Add missing fixed_clks to cmu_info
  clk: samsung: exynos7: Add required clock tree for UFS

 drivers/clk/samsung/clk-exynos7.c   |  465 +--
 include/dt-bindings/clock/exynos7-clk.h |   43 ++-
 2 files changed, 357 insertions(+), 151 deletions(-)

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Re: Chromebook snow issues

[Sylwester Nawrocki]

On 29/09/15 16:42, Mauro Carvalho Chehab wrote:
> Em Tue, 29 Sep 2015 16:32:58 +0200
> Sylwester Nawrocki <s.nawro...@samsung.com> escreveu:
> 
>> > Adding linux-samsung-soc mailing list at Cc.
> 
> Never mind. My mistake: I forgot to reinstall the modules (mwifiex and mfc
> drivers were compiled as such).
> 
> It is working.
> 
> I guess the only remaining thing is to add the dependency of EXYNOS_IOMMU
> to the MFC driver.

Sounds good. The patches I pointed out are only a workaround, in general
MFC should also work without IOMMU. As the driver handles also SoCs without
a SYSMMU hardware support adding such a Kconfig entry would not be correct.

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Re: Chromebook snow issues

[Sylwester Nawrocki]

Adding linux-samsung-soc mailing list at Cc.

On 29/09/15 16:01, Mauro Carvalho Chehab wrote:
> Em Tue, 29 Sep 2015 15:37:51 +0200
> Sylwester Nawrocki <s.nawro...@samsung.com> escreveu:
> 
>> Hi Mauro,
>>
>> On 29/09/15 14:43, Mauro Carvalho Chehab wrote:
>>> Hi Sylwester,
>>>
>>> I'm c/c Javier. Javier is working with us at the Open Souce Group and he
>>> has been working on making sure that Chromebooks are supported with vanilla
>>> upstream Kernels.
>>>
>>> That's said, while testing the latest upstream Kernel (4.3-rc3) on a
>>> Chromebook snow, I noticed this error message:
>>>
>>> [  211.116975] s5p_mfc_alloc_memdevs:1045: Failed to declare coherent 
>>> memory for
>>>MFC device
>>> [  211.117039] s5p-mfc: probe of 1100.codec failed with error -12
>>>
>>> Do you have any idea about how to fix? Btw, do I need any firmware to test
>>> the MFC driver there?
>>
>> You can get v4.1 based kernel with MFC working (e.g. on Odroid XU3) here:
>>
>> https://u...@review.tizen.org/gerrit/p/platform/kernel/linux-exynos.git
>> ssh://u...@review.tizen.org:29418/platform/kernel/linux-exynos.git
>> branch: tizen
>>
>> I'm adding at Cc Marek who knows more details. AFAIU you may need patches
>> like these on top of current mainline kernel:
>>
>> https://review.tizen.org/gerrit/gitweb?p=platform/kernel/linux-exynos.git;a=commitdiff;h=dcbf130658cdd1731b8a219ecedd867af0b2670e
>>
>> https://review.tizen.org/gerrit/gitweb?p=platform/kernel/linux-exynos.git;a=commitdiff;h=b82fd3408fd58476da79996d4a3bcbbb72174961
>>
>> And Exynos IOMMU needs to be enabled in kernel config.
> 
> If this is a requirement, we should enforce it at s5p-mfc Kconfig entry,
> like:
> 
>   depends on EXYNOS_IOMMU if !COMPILE_TEST

In general s5p-mfc doesn't depend on IOMMU, some SoC revisions don't
even have SYSMMU. Thus we can't add such constraint.

> Just enabled Exynos IOMMU here to see what would happen:
> 
> [   19.461839] [ cut here ]
> [   19.464264] kernel BUG at net/core/dev.c:6513!
> [   19.466648] Internal error: Oops - BUG: 0 [#2] PREEMPT SMP ARM
> [   19.469039] Modules linked in: mwifiex_sdio mwifiex exynos_gsc(+) 
> v4l2_mem2mem s5p_mfc(+) videobuf2_dma_contig videobuf2_memops videobuf2_core 
> v4l2_common videodev media
> [   19.474158] CPU: 1 PID: 1390 Comm: kworker/1:2 Tainted: G  D 
> 4.3.0-rc3-00492-g397ead8befa9 #10
> [   19.476753] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
> [   19.479326] Workqueue: events request_firmware_work_func
> [   19.481887] task: edb06d00 ti: ee18a000 task.ti: ee18a000
> [   19.484445] PC is at register_netdevice+0x23c/0x41c
> [   19.487013] LR is at register_netdevice+0x28/0x41c
> [   19.489572] pc : []lr : []psr: 60010013
> [   19.489572] sp : ee18be00  ip : 000e  fp : ed4629a0
> [   19.494692] r10: bf102940  r9 :   r8 : ed462000
> [   19.497218] r7 : 0002  r6 : ed462000  r5 : edbee000  r4 : ed738000
> [   19.499741] r3 :   r2 : 0146  r1 : 03e8  r0 : 0001
> [   19.502253] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment 
> none
> [   19.504768] Control: 10c5387d  Table: 6d5bc06a  DAC: 0051
> [   19.507247] Process kworker/1:2 (pid: 1390, stack limit = 0xee18a210)
> [   19.509717] Stack: (0xee18be00 to 0xee18c000)
> [   19.512150] be00:  0001   ed4629a0 ed738000 
> edbee000 ed462000
> [   19.514615] be20: 0002 ed7392fc ed739000 bf0fab4c 0004 0001 
> edbef000 
> [   19.517072] be40: c086697c edbee000 bf10b400 edbef000 bf12d784  
>  ed9a4800
> [   19.519518] be60: ee7b58c0 bf0d95b0     
> f1694000 0006fd7c
> [   19.521959] be80:  ec118e00 ec118dc0 c02f711c f1694000 0006fd7c 
> ed43a390 ec118d40
> [   19.524396] bea0: 0003 ee18bee4 edbbf208 c0834674 ec118dc0 c08ba8bc 
> 0002 ec118d80
> [   19.526827] bec0: ed9a4800 ec118d80
> 
> Unfortunately, the serial console didn't got everything. It _seems_ that the
> bug happens during a mwifiex kthread, when it calls mwifiex_add_virtual_intf,
> but even at the device's screen the message is truncated.

Unfortunately this doesn't ring any bells here, we don't work with Chromebooks
in general and I'm not sure how to address this issue. Maybe someone subscribed
to the mailing list can help.

> I didn't apply those two patches you pointed from Tizen.org. Not sure if
> this is related or not.

It's possible the issue is caused by some other device (driver) that also
has a sysmmu assigned to it, like display controller, et

Re: [PATCH 4/4] ARM64: dts: exynos5433: add jpeg node

[Sylwester Nawrocki]

Hi Mauro,

On 21/09/15 13:41, Mauro Carvalho Chehab wrote:
> Btw, I just got a Samsung TM1 device, with seems to be using an arm64
> SoC. Is this driver providing support for its camera?

The TM1 device (Z3) is based on a Qualcomm 64-bit SoC. The $subject
patch adds support for a standalone JPEG codec IP block of Samsung
Exynos5433 SoC, which can be found for instance in Galaxy Note4.
Perhaps someone else can provide more details regarding the TM1's camera
status.

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Re: [PATCH 5/7] [media] use v4l2_get_timestamp where possible

[Sylwester Nawrocki]

On 15/09/15 17:49, Arnd Bergmann wrote:
> This is a preparation for a change to the type of v4l2 timestamps.
> v4l2_get_timestamp() is a helper function that reads the monotonic
> time and stores it into a 'struct timeval'. Multiple drivers implement
> the same thing themselves for historic reasons.
> 
> Changing them all to use v4l2_get_timestamp() is more consistent
> and reduces the amount of code duplication, and most importantly
> simplifies the following changes.
> 
> If desired, this patch can easily be split up into one patch per
> driver.
> 
> Signed-off-by: Arnd Bergmann <a...@arndb.de>
> ---
For:

  drivers/media/platform/exynos4-is/fimc-lite.c
  drivers/media/platform/s3c-camif/camif-capture.c

Acked-by: Sylwester Nawrocki <s.nawro...@samsung.com>
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Re: [PATCH 4/7] [media] exynos4-is: use monotonic timestamps as advertized

[Sylwester Nawrocki]

On 15/09/15 17:49, Arnd Bergmann wrote:
> The exynos4 fimc capture driver claims to use monotonic
> timestamps but calls ktime_get_real_ts(). This is both
> an incorrect API use, and a bad idea because of the y2038
> problem and the fact that the wall clock time is not reliable
> for timestamps across suspend or settimeofday().
> 
> This changes the driver to use the normal v4l2_get_timestamp()
> function like all other drivers.
> 
> Signed-off-by: Arnd Bergmann <a...@arndb.de>

Acked-by: Sylwester Nawrocki <s.nawro...@samsung.com>
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Re: [PATCH v2 0/4] Improvements on exynos7 clock

[Sylwester Nawrocki]

On 26/08/15 05:30, Alim Akhtar wrote:
> This patch series are minor improvement over the current
> exynos7 clock file. This fix some bugs and update the clock
> bits as per user manual.

That one applied as well, thanks.
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Re: [PATCH v2 00/12] clk: samsung: exynos7: Cleanup of clock file

[Sylwester Nawrocki]

On 10/09/15 10:44, Alim Akhtar wrote:
> Currently there are lots of ambiguity between clock names in clock file
> and in user manual, which leads to lots of confusion for the reviewers.
> This series attempts to cleanup the exynos7 clock file as per
> user manual naming convention.
> This also adds some of the missing Gate clocks which are needed
> to complete the clock tree.

The whole series applied, thanks.
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Re: [PATCH] clk: samsung: fix cpu clock's flags checking

[Sylwester Nawrocki]

On 29/06/15 19:29, Bartlomiej Zolnierkiewicz wrote:
 CLK_CPU_HAS_DIV1 and CLK_CPU_NEEDS_DEBUG_ALT_DIV masks were
 incorrectly used as a bit numbers.  Fix it.
 
 Tested on Exynos4210 based Origen board and on Exynos5250 based
 Arndale board.
 
 Cc: Tomasz Figa tomasz.f...@gmail.com
 Cc: Michael Turquette mturque...@baylibre.com
 Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
 Cc: Thomas Abraham thomas...@samsung.com
 Reported-by: Dan Carpenter dan.carpen...@oracle.com
 Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com

Acked-by: Sylwester Nawrocki s.nawro...@samsung.com

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Re: [PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[Sylwester Nawrocki]

On 07/22/2015 08:41 AM, Krzysztof Kozlowski wrote:

On 22.07.2015 07:42, Stephen Boyd wrote:

On 06/12, Krzysztof Kozlowski wrote:

[...]

Signed-off-by: Krzysztof Kozlowskik.kozlow...@samsung.com
Cc:sta...@vger.kernel.org
Fixes: c63c57433003 (ARM: dts: Add ADC's dt data to read raw data for 
exynos4x12)
Link:https://lkml.org/lkml/2015/6/11/85


Did you want clk maintainers to apply this? The To: list is not
helping so I'm not sure what's going on and it seems to have
slipped through the cracks.



Thank you for being proactive! I appreciate this.
Some time ago Sylwester replied that he took care about this patch so I
think this will go through Samsung clock tree.

Sylwester, are you planning to send this as fix for 4.2-rc?


I think it qualifies for 4.3, it's not a new regression and will be
backported to -stable anyway.
I would prefer clk maintainers have applied this, otherwise I would
need to make a (questionable) pull request with only one patch, since
all patches except this one after the last merge window were part
of bigger series touching multiple subsystems and applied through
the samsung soc tree.

Thanks,
Sylwester



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Re: [PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[Sylwester Nawrocki]

On 12/06/15 03:53, Krzysztof Kozlowski wrote:
 The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
 However TSADC is present only on Exynos4210 so on Trats2 board (with
 Exynos4412 SoC) the exynos-adc driver could not be probed:
ERROR: could not get clock /adc@126C:adc(0)
exynos-adc 126c.adc: failed getting clock, err = -2
exynos-adc: probe of 126c.adc failed with error -2
 
 Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
 Converter is located in different register and it is named in datasheet
 as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
 is the same as purpose of TSADC from Exynos4210.
 
 The patch adds gate clock for Exynos4x12 using the proper register so
 backward compatibility is preserved. This fixes the probe of exynos-adc
 driver on Exynos4x12 boards and allows accessing sensors connected to it
 on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).
 
 Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
 Cc: sta...@vger.kernel.org
 Fixes: c63c57433003 (ARM: dts: Add ADC's dt data to read raw data for 
 exynos4x12)
 Link: https://lkml.org/lkml/2015/6/11/85

Mike, could you apply this patch directly? I can't seem to find any
more independent patches for clk/samsung pull request.
Alternatively here is a branch you could cherry-pick it from with
all Acked/Reviewed tags:

git://linuxtv.org/snawrocki/samsung.git for-v4.2/clk/fixes-1

--
Regards,
Sylwester

 Changes since v1:
 1. After discussion on LKML this solution was chosen because it smaller,
simpler, self-contained (one patch to fix issue) and maintains backward
compatibility. Thanks to Javier Martinez Canillas and Tomasz Figa for
valuable comments.
 2. Dropped patch 2/2 because now it is not needed. The clock id TSADC
will be used on all Exynos4 boards.
 3. Added CC-stable.
 ---
  drivers/clk/samsung/clk-exynos4.c | 2 ++
  1 file changed, 2 insertions(+)
 
 diff --git a/drivers/clk/samsung/clk-exynos4.c 
 b/drivers/clk/samsung/clk-exynos4.c
 index 714d6ba782c8..f7890bf652e6 100644
 --- a/drivers/clk/samsung/clk-exynos4.c
 +++ b/drivers/clk/samsung/clk-exynos4.c
 @@ -85,6 +85,7 @@
  #define DIV_PERIL4   0xc560
  #define DIV_PERIL5   0xc564
  #define E4X12_DIV_CAM1   0xc568
 +#define E4X12_GATE_BUS_FSYS1 0xc744
  #define GATE_SCLK_CAM0xc820
  #define GATE_IP_CAM  0xc920
  #define GATE_IP_TV   0xc924
 @@ -1095,6 +1096,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] 
 __initdata = {
   0),
   GATE(CLK_PPMUIMAGE, ppmuimage, aclk200, E4X12_GATE_IP_IMAGE, 9, 0,
   0),
 + GATE(CLK_TSADC, tsadc, aclk133, E4X12_GATE_BUS_FSYS1, 16, 0, 0),
   GATE(CLK_MIPI_HSI, mipi_hsi, aclk133, GATE_IP_FSYS, 10, 0, 0),
   GATE(CLK_CHIPID, chipid, aclk100, E4X12_GATE_IP_PERIR, 0, 0, 0),
   GATE(CLK_SYSREG, sysreg, aclk100, E4X12_GATE_IP_PERIR, 1,
 


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Re: [PATCH v2 4/7] clk: samsung: exynos4x12: add cpu clock configuration data and instantiate cpu clock

[Sylwester nawrocki]

On 07/10/2015 12:43 AM, Bartlomiej Zolnierkiewicz wrote:

With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4x12.

Based on the earlier work by Thomas Abraham.

Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Michael Turquette mturque...@baylibre.com
Cc: Javier Martinez Canillas jav...@dowhile0.org
Cc: Thomas Abraham thomas...@samsung.com
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
  drivers/clk/samsung/clk-exynos4.c | 50 +++
  1 file changed, 50 insertions(+)


I guess you prefer to have this whole series applied through one,
e.g samsung-soc tree? If so, here is my ack.

Acked-by: Sylwester Nawrocki s.nawro...@samsung.com
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Re: [PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[Sylwester Nawrocki]

On 09/07/15 02:23, Krzysztof Kozlowski wrote:
  drivers/clk/samsung/clk-exynos4.c | 2 ++
   1 file changed, 2 insertions(+)
 
 
  Patch looks good to me.
 
  Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
 
  Hi Tomasz and Sylwester,
 
  Any comments on this version of patch?
  Tomasz, you gave me comments on previous version. Are their satisfied?
 
  Acked-by: Tomasz Figa tomasz.f...@gmail.com
 Thanks for ack.
 
 Sylwester, are you gonna to pick it up or this should go through other tree?

I've taken care of this citizen, thanks for the reminder and reviews.

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Re: [GIT PULL] clk/samsung updates for 4.2

[Sylwester Nawrocki]

On 04/06/15 01:05, Michael Turquette wrote:
 One small thing: clk-next isn't considered stable.  I had some stuff in
 there (Stephen's amba assigned-clock-rates patch) which I had to pull
 out (no ACK from maintainer) and it crept back in because this PR was
 based on top of it. No big deal because I caught it when it happened
 (this time).
 
 In the future I am always happy to take PRs based on -rc1 (or any -rc
 that is already present in clk-next). Of course if you have a dependency
 on stuff already merged in clk-next then just let me know.

All right, sorry for the trouble. I'll keep that in mind and will use
stable tags for future pull request.

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[GIT PULL] clk/samsung updates for 4.2

[Sylwester Nawrocki]

The following changes since commit 20db7092e478c33a2bf5254063c51f5db6443959:

  Merge branch 'clk-next-hi6220' into clk-next (2015-05-27 22:06:42 -0700)

are available in the git repository at:


  git://linuxtv.org/snawrocki/samsung.git tags/clk-samsung-for-4.2

for you to fetch changes up to e5c6fc4f271a27d5b236b5f4929bf0f2dab80a7d:

  clk: exynos5433: Add CLK_IGNORE_UNUSED flag to clocks for SMC (2015-06-02
14:52:12 +0200)


Updates of the exynos5433 clock definitions for proper support of SMC,
DVFS of GPU and CPU big.LITTLE cores and a fix for system suspend adding
one of the clock controller's registers to save/restore list.


Chanwoo Choi (1):
  clk: exynos5433: Add CLK_SET_RATE_PARENT to support DVFS for big.LITTLE 
core

Hyungwon Hwang (1):
  clk: exynos5433: Add DIV_CPIF to the list of stored registers on suspend

Jonghwa Lee (1):
  clk: exynos5433: Add CLK_IGNORE_UNUSED flag to clocks for SMC

Joonyoung Shim (1):
  clk: exynos5433: Add clock flag to support the DVFS of GPU

 drivers/clk/samsung/clk-exynos5433.c |   81 +-
 1 file changed, 40 insertions(+), 41 deletions(-)

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Re: [PATCHv3 1/4] phy: phy-core: Make GENERIC_PHY an invisible option

[Sylwester Nawrocki]

On 29/05/15 14:37, Kishon Vijay Abraham I wrote:
 Tejun, Maxime, Sylwester, Kyungmin
 
 On Thursday 23 April 2015 04:34 AM, Arun Ramamurthy wrote:
 Most of the phy providers use select to enable GENERIC_PHY. Since select
 is only recommended when the config is not visible, GENERIC_PHY is changed
 an invisible option. To maintain consistency, all phy providers are changed
 to select GENERIC_PHY and all non-phy drivers use depends on when the
 phy framework is explicity required. USB_MUSB_OMAP2PLUS has a cyclic
 dependency, so it is left as select.

 Signed-off-by: Arun Ramamurthy arun.ramamur...@broadcom.com
 
 Need your ACK for this patch.

For
drivers/media/platform/exynos4-is/Kconfig
drivers/video/fbdev/exynos/Kconfig

Acked-by: Sylwester Nawrocki s.nawro...@samsung.com

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Re: [PATCH] clk: make several parent names const

[Sylwester Nawrocki]

On 28/05/15 10:45, Uwe Kleine-König wrote:
 Since commit 2893c379461a (clk: make strings in parent name arrays
 const) the name of parent clocks can be const. So add more const in
 several clock drivers.
 
 Signed-off-by: Uwe Kleine-König u.kleine-koe...@pengutronix.de

Thanks for the patch,
Acked-by: Sylwester Nawrocki s.nawro...@samsung.com

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Re: [PATCH v3 10/10] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to prevent the hang for suspend-to-ram

[Sylwester Nawrocki]

Hi Chanwoo,

On 27/04/15 13:36, Chanwoo Choi wrote:
 From: Jonghwa Lee jonghwa3@samsung.com
 
 Some clocks are required being unmasked for suspend-to-ram. Otherwise,
 PMU (Power Management Unit) will stick and power line never down.
 
 Signed-off-by: Jonghwa Lee jonghwa3@samsung.com
 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
 ---

 @@ -1718,11 +1722,14 @@ static struct samsung_gate_clock peric_gate_clks[] 
 __initdata = {
   GATE(CLK_SCLK_SPI0, sclk_spi0, sclk_spi0_peric, ENABLE_SCLK_PERIC,
   3, CLK_SET_RATE_PARENT, 0),
   GATE(CLK_SCLK_UART2, sclk_uart2, sclk_uart2_peric,
 - ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 + ENABLE_SCLK_PERIC, 2,
 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
   GATE(CLK_SCLK_UART1, sclk_uart1, sclk_uart1_peric,
 - ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
 + ENABLE_SCLK_PERIC, 1,
 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
   GATE(CLK_SCLK_UART0, sclk_uart0, sclk_uart0_peric,
 - ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
 + ENABLE_SCLK_PERIC, 0,
 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
  };
  
  static struct samsung_cmu_info peric_cmu_info __initdata = {
 @@ -3025,7 +3032,7 @@ static struct samsung_gate_clock aud_gate_clks[] 
 __initdata = {
  
   /* ENABLE_SCLK_AUD0 */
   GATE(CLK_ATCLK_AUD, atclk_aud, div_atclk_aud, ENABLE_SCLK_AUD0,
 - 2, 0, 0),
 + 2, CLK_IGNORE_UNUSED, 0),
   GATE(CLK_PCLK_DBG_AUD, pclk_dbg_aud, div_pclk_dbg_aud,
   ENABLE_SCLK_AUD0, 1, 0, 0),
   GATE(CLK_SCLK_AUD_CA5, sclk_aud_ca5, div_aud_ca5, ENABLE_SCLK_AUD0,
 @@ -3425,9 +3432,11 @@ static struct samsung_gate_clock gscl_gate_clks[] 
 __initdata = {
   GATE(CLK_ACLK_GSCLNP_111, aclk_gsclnp_111, mout_aclk_gscl_111_user,
   ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
   GATE(CLK_ACLK_GSCLRTND_333, aclk_gsclrtnd_333,
 - mout_aclk_gscl_333_user, ENABLE_ACLK_GSCL, 5, 0, 0),
 + mout_aclk_gscl_333_user, ENABLE_ACLK_GSCL, 5,
 + CLK_IGNORE_UNUSED, 0),
   GATE(CLK_ACLK_GSCLBEND_333, aclk_gsclbend_333,
 - mout_aclk_gscl_333_user, ENABLE_ACLK_GSCL, 4, 0, 0),
 + mout_aclk_gscl_333_user, ENABLE_ACLK_GSCL, 4,
 + CLK_IGNORE_UNUSED, 0),

Some of the clocks you are adding CLK_IGNORE_UNUSED flag for here are
or will be handled be the related IP drivers, thus can be gated regardless
of the changes done in this patch. I would suggest to register suspend/
resume syscore ops like exynos5420_clk_syscore_ops and enable some of
clocks you're touching in this patch explicitly in the suspend() callback
and restore the registers state from before suspend() call in resume().

I've picked up patches 01/10...09/10.
In future please also copy linux-...@vger.kernel.org on clk related patches.

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Re: ARCH_EXYNOS5433 missing in Kconfig

[Sylwester Nawrocki]

Hello,

On 28/04/15 11:25, Chanwoo Choi wrote:
 Hi Valentin,
 
 On Mon, Apr 27, 2015 at 3:31 PM, Valentin Rothberg
 valentinrothb...@gmail.com wrote:
  Hi Chanwoo,
 
  this is a kind reminder that the issue mentioned below is still
  present and made its way to v4.1-rc1.

 I sent the patch[1] to fix it. And Sylwester said that he will pick
 this patchset on patch[2].
 [1] https://lkml.org/lkml/2015/4/27/237
 [2] https://lkml.org/lkml/2015/4/28/117
 
 Hi Sylwester,
 Could you apply a patch[1] on 4.2-rc2 to fix build warning?

Sure, I plan to send a pull request this week.

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Re: [PATCH] i2c: s3c2410: Don't enable PM runtime on the adapter device

[Sylwester Nawrocki]

On 16/04/15 12:10, Charles Keepax wrote:
 Commit 523c5b89640e (i2c: Remove support for legacy PM) removed the PM
 ops from the bus type, which causes the pm operations on the s3c2410
 adapter device to fail (-ENOSUPP in rpm_callback). The adapter device
 doesn't get bound to a driver and as such can't have its own pm_runtime
 callbacks. Previously this was fine as the bus callbacks would have been
 used, but now this can cause devices which use PM runtime and are
 attached over I2C to fail to resume.
 
 This commit fixes this issue by just doing the PM operations directly on
 the I2C device, rather than the adapter device in the driver and adding
 some stub callbacks for runtime suspend and resume.
 
 Signed-off-by: Charles Keepax ckee...@opensource.wolfsonmicro.com
 ---
  drivers/i2c/busses/i2c-s3c2410.c |   21 -
  1 files changed, 16 insertions(+), 5 deletions(-)

 @@ -1253,7 +1253,6 @@ static int s3c24xx_i2c_probe(struct platform_device 
 *pdev)
   platform_set_drvdata(pdev, i2c);
  

Wouldn't adding

pm_runtime_no_callbacks(pdev-dev);

here let us avoid the runtime resume/suspend stubs?

   pm_runtime_enable(pdev-dev);
 - pm_runtime_enable(i2c-adap.dev);
  
   dev_info(pdev-dev, %s: S3C I2C adapter\n, dev_name(i2c-adap.dev));
   return 0;
 @@ -1270,7 +1269,6 @@ static int s3c24xx_i2c_remove(struct platform_device 
 *pdev)
  
   clk_unprepare(i2c-clk);
  
 - pm_runtime_disable(i2c-adap.dev);
   pm_runtime_disable(pdev-dev);
  
   s3c24xx_i2c_deregister_cpufreq(i2c);
 @@ -1318,6 +1316,16 @@ static int s3c24xx_i2c_resume_noirq(struct device *dev)
  #endif
  
  #ifdef CONFIG_PM
 +static int s3c24xx_runtime_resume(struct device *dev)
 +{
 + return 0;
 +}
 +
 +static int s3c24xx_runtime_suspend(struct device *dev)
 +{
 + return 0;
 +}

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Re: [PATCH 1/1] clk: exynos5420: Restore GATE_BUS_TOP on suspend

[Sylwester Nawrocki]

Hello,

On 08/04/15 07:34, Javier Martinez Canillas wrote:
 Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
 Management support v12) added pm support for the pl330 dma driver but
 it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
 during suspend and this in turn makes its parent clock aclk266_g2d to
 be gated. But the clock needs to be ungated prior suspend to allow the
 system to be suspend and resumed correctly.
 
 Add GATE_BUS_TOP register to the list of registers to be restored when
 the system enters into a suspend state so aclk266_g2d will be ungated.
 
 Thanks to Abhilash Kesavan for figuring out that this was the issue.
 
 Fixes: ae43b32 (ARM: 8202/1: dmaengine: pl330: Add runtime Power Management 
 support v12)
 Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
 Tested-by: Kevin Hilman khil...@linaro.org
 Tested-by: Abhilash Kesavan a.kesa...@samsung.com
 Acked-by: Tomasz Figa tomasz.f...@gmail.com
 ---
  drivers/clk/samsung/clk-exynos5420.c | 1 +
  1 file changed, 1 insertion(+)
 
 diff --git a/drivers/clk/samsung/clk-exynos5420.c 
 b/drivers/clk/samsung/clk-exynos5420.c
 index 07d666cc6a29..bea4a173eef5 100644
 --- a/drivers/clk/samsung/clk-exynos5420.c
 +++ b/drivers/clk/samsung/clk-exynos5420.c
 @@ -271,6 +271,7 @@ static const struct samsung_clk_reg_dump 
 exynos5420_set_clksrc[] = {
   { .offset = SRC_MASK_PERIC0,.value = 0x1110, },
   { .offset = SRC_MASK_PERIC1,.value = 0x1100, },
   { .offset = SRC_MASK_ISP,   .value = 0x1000, },
 + { .offset = GATE_BUS_TOP,   .value = 0x, },
   { .offset = GATE_BUS_DISP1, .value = 0x, },
   { .offset = GATE_IP_PERIC,  .value = 0x, },
  };

I'm going to tag this patch for inclusion in the stable tree and send
it to Mike or Stephen with other clk/samsung fixes after v4.1-rc1 is
released.

Mike/Stephen, if you're willing to take this patch earlier here is my:

Acked-by: Sylwester Nawrocki s.nawro...@samsung.com

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Re: [RFC PATCH v3 2/2] clk: exynos5420: Make sure MDMA0 clock is enabled during suspend

[Sylwester Nawrocki]

Hello,

On 31/03/15 22:00, Javier Martinez Canillas wrote:
 On 03/31/2015 04:38 PM, Abhilash Kesavan wrote:
 javier.marti...@collabora.co.uk wrote:

 Unfortunately I don't fully understand why this clock needs to be
 enabled. It would be good if someone at Samsung can explain in
 more detail what the real problem really is.


 I had a look at this some more today. The problem actually occurs when the
 mdma0 clock's parent - aclk266_g2d gets disabled. The run-time pm support
 in the dma driver disables mdma0 and in turn aclk266_g2d which causes the
 issue.
 From the User Manual, it appears that aclk266_g2d should be gated only when
 certain bits in the clock gating status register are 0. I cannot say for
 certain, but our gating the aclk266_g2d clock without the CG_STATUS bits
 being 0 could be a cause of the suspend failure.

 
 Thanks a lot for the explanation. I see the NOTE at the bottom of section
 7.9.1.159 CLK_GATE_BUS_TOP that mentions that. I'll add this information
 to the commit message when posting as a proper patch instead of a RFC.
 
 I confirmed that changing the patch to prevent aclk266_g2d to be gated
 instead of mdm0 also makes the system to resume correctly from suspend
 so I'll change that on the patch as well.
 
 I see that many of the Exynos5420 clocks (including aclk266_g2d) use the
 CLK_IGNORE_UNUSED flag but AFAIU it only prevents the common clock framework
 to disable the clocks on init but doesn't prevent the clocks to be disabled
 if all the clock childs are gated so the parent is gated as well.
 
 As the CG_STATUS bits are not being checked anywhere in the kernel I think
 aclk266_g2d (and others in GATE_BUS_TOP) should not be gated. I am OK with
 
 For now I'll just add aclk266_g2d but later if needed all the GATE_BUS_TOP
 clocks (and others) that should only be gated when CG_STATUS is 0 can be
 added. My patch iterates over a list of clocks to be kept during suspend even
 when there is only one for now so adding more later if needed will be trivial.

It's not clear what subsystems affect state of the CG_STATUSx registers, it
would be good if we could get more information on that. They are in the PMU
block and are related to LPI (Low Power Interface handshaking), but what
subsystems/peripheral blocks exactly are associated with them it's not clear
from the documentation.

I think it's essential to understand what triggers changes in CG_STATUSx
registers, before we start checking their value in the clock driver.

Also it might be that there are indeed some clocks which must stay enabled
over suspend/resume cycle, then the approach with enabling/disabling clocks
in the clock driver might not be such a hack as it looks at first sight.

 Or do you think that I should add all the GATE_BUS_TOP clocks now?

No, please don't do that. That includes many important clocks and we should
be certain what we are doing. I don't think it is expected to touch those
clocks in that way, it would likely cause more issues.


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Re: [RFC PATCH v3 2/2] clk: exynos5420: Make sure MDMA0 clock is enabled during suspend

[Sylwester Nawrocki]

Hello Javier,

On 01/04/15 13:44, Javier Martinez Canillas wrote:
 On 04/01/2015 01:03 PM, Sylwester Nawrocki wrote:
 On 31/03/15 22:00, Javier Martinez Canillas wrote:
 On 03/31/2015 04:38 PM, Abhilash Kesavan wrote:
 javier.marti...@collabora.co.uk wrote:
 I had a look at this some more today. The problem actually occurs when the
 mdma0 clock's parent - aclk266_g2d gets disabled. The run-time pm support
 in the dma driver disables mdma0 and in turn aclk266_g2d which causes the
 issue.
 From the User Manual, it appears that aclk266_g2d should be gated only when
 certain bits in the clock gating status register are 0. I cannot say for
 certain, but our gating the aclk266_g2d clock without the CG_STATUS bits
 being 0 could be a cause of the suspend failure.


 Thanks a lot for the explanation. I see the NOTE at the bottom of section
 7.9.1.159 CLK_GATE_BUS_TOP that mentions that. I'll add this information
 to the commit message when posting as a proper patch instead of a RFC.

 I confirmed that changing the patch to prevent aclk266_g2d to be gated
 instead of mdm0 also makes the system to resume correctly from suspend
 so I'll change that on the patch as well.

 I see that many of the Exynos5420 clocks (including aclk266_g2d) use the
 CLK_IGNORE_UNUSED flag but AFAIU it only prevents the common clock framework
 to disable the clocks on init but doesn't prevent the clocks to be disabled
 if all the clock childs are gated so the parent is gated as well.

 As the CG_STATUS bits are not being checked anywhere in the kernel I think
 aclk266_g2d (and others in GATE_BUS_TOP) should not be gated. I am OK with

 For now I'll just add aclk266_g2d but later if needed all the GATE_BUS_TOP
 clocks (and others) that should only be gated when CG_STATUS is 0 can be
 added. My patch iterates over a list of clocks to be kept during suspend 
 even
 when there is only one for now so adding more later if needed will be 
 trivial.

 It's not clear what subsystems affect state of the CG_STATUSx registers, it
 would be good if we could get more information on that. They are in the PMU
 block and are related to LPI (Low Power Interface handshaking), but what
 subsystems/peripheral blocks exactly are associated with them it's not clear
 from the documentation.
 
 Yes, I've been looking at the docs again and found out a couple of things:
 
 * Each GC_STATUSx register bit is associated with an IP hw block
 * Some LPI_MASKx registers maps exactly with the GC_STATUSx (i.e: 0 and 1)
   and others maps only partially (i.e: LPI_MASK2 and GC_STATUS2)

The CG_STATUSx and LPI_MASKx bits meaning is not matching according to
documentation I have. I guess you've got something newer than REV0.00?

 So it is related to LPI as you said and both LPI_MASKx and GC_STATUSx are
 part of the PMU register address space.
 
 In the particular case of aclk266_g2d, the doc says that the clock can only
 be gated when CG_STATUS0[20] and CG_STATUS0[21] are 0. These are associated
 with the SSS and SSS_SLIM respectively which AFAIU are crypto h/w modules.

In my Exynos5420 UM ACLK_266_G2D is associated with CG_STATUS0 register
bits 22, 21, which in turn correspond to NR3D and DIS IP blocks, i.e.
the camera subsystem. Such a dependency would be rather surprising.

 I think it's essential to understand what triggers changes in CG_STATUSx
 registers, before we start checking their value in the clock driver.

 
 Indeed, we should really understand what the status on these registers
 means. Also is not clear from the docs how much time should be waited,
 how long until giving up, etc.

Exactly, I checked some kernels from http://opensource.samsung.com
(e.g. SM-N900_JB_Opensource.zip) for CG_STATUSx, but I didn't find anything
related to these registers yet, except the address macro definitions
and debug traces in the power domains driver.

 Also it might be that there are indeed some clocks which must stay enabled
 over suspend/resume cycle, then the approach with enabling/disabling clocks
 in the clock driver might not be such a hack as it looks at first sight.

 
 Having a clock driver to both a provider and consumer feels hacky to me as
 well but I didn't find a better way to solve this issue... another option
 is to have this workaround to solve the S2R issue while we figure out what
 the the state in the CG_STATUSx really mean.

Let's try to diagnose the issue best we can, then we would choose the most
accurate bug fix.

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Re: [RFC PATCH 2/2] ARM: EXYNOS: Make sure that the Exynos5420 MDMA0 clock is enabled during suspend

[Sylwester Nawrocki]

Hello Javier,

On 27/03/15 15:21, Javier Martinez Canillas wrote:
 Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
 Management support v12) added pm support for the pl330 dma driver but
 it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
 during suspend and this clock needs to remain enabled in order to make
 the system resume from a system suspend state.
 
 To make sure that the clock is enabled during suspend, enable it prior
 to entering a suspend state and disable it once the system has resumed.
 
 Thanks to Abhilash Kesavan for figuring out that this was the issue.
 
 Fixes: ae43b32 (ARM: 8202/1: dmaengine: pl330: Add runtime Power Management 
 support v12)
 Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
 ---
  arch/arm/mach-exynos/suspend.c | 15 +++
  1 file changed, 15 insertions(+)
 
 diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
 index 1521eaf99265..6dbc0a6d1bb5 100644
 --- a/arch/arm/mach-exynos/suspend.c
 +++ b/arch/arm/mach-exynos/suspend.c
 @@ -16,6 +16,7 @@
  #include linux/init.h
  #include linux/suspend.h
  #include linux/syscore_ops.h
 +#include linux/clk.h
  #include linux/cpu_pm.h
  #include linux/io.h
  #include linux/irq.h
 @@ -79,6 +80,7 @@ static const struct exynos_pm_data *pm_data;
  
  static int exynos5420_cpu_state;
  static unsigned int exynos_pmu_spare3;
 +static struct clk *clk;
  
  /*
   * GIC wake-up support
 @@ -374,6 +376,16 @@ static void exynos5420_pm_prepare(void)
  {
   unsigned int tmp;
  
 + /*
 +  * Exynos5420 requires the MDMA0 controller clock to be
 +  * ungated on suspend in order to be resumed correctly.
 +  */
 + clk = clk_get(NULL, mdma0);
 + if (IS_ERR(clk))
 + pr_warn(Failed to get mdma0 clk (%ld)\n, PTR_ERR(clk));

I suppose you want this clk_get() call in exynos_pm_init(), now there
is clk_put() missing and this will cause a memory leak.

 + else
 + clk_prepare_enable(clk);
 +
   /* Set wake-up mask registers */
   exynos_pm_set_wakeup_mask();
  
 @@ -516,6 +528,9 @@ static void exynos5420_pm_resume(void)
  {
   unsigned long tmp;
  
 + if (!IS_ERR_OR_NULL(clk))

This should be just IS_ERR().

 + clk_disable_unprepare(clk);
 +
   /* Restore the CPU0 low power state register */
   tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
   pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,

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[GIT PULL] clk: exynos3250 updates for 4.1

[Sylwester Nawrocki]

Hello Mike,

Please pull the following changes, it seems all we have for next release
for clk/samsung.

The following changes since commit 5bc43f9b615f02c57b1ca782128ef5daf055:

  Merge branch 'clk-fixes' into clk-next (2015-03-09 14:23:45 -0700)

are available in the git repository at:


  git://linuxtv.org/snawrocki/samsung.git tags/for-v4.1-exynos-clk

for you to fetch changes up to b5f81840f48ca580774ca6cccb14a254ea35d51e:

  clk: samsung: exynos3250: Add driver for CMU_ISP clock domain (2015-03-18
11:35:51 +0100)


Support for the Image Signal Processor clock management unit
and the CLKOUT block on Exynos3250.


Inha Song (1):
  clk: samsung: Add CLKOUT driver support for Exynos3250 SoC

Tomasz Figa (1):
  clk: samsung: exynos3250: Add driver for CMU_ISP clock domain

 .../devicetree/bindings/clock/exynos3250-clock.txt |8 +
 drivers/clk/samsung/clk-exynos-clkout.c|2 +
 drivers/clk/samsung/clk-exynos3250.c   |  163 
 include/dt-bindings/clock/exynos3250.h |   61 
 4 files changed, 234 insertions(+)

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Re: [alsa-devel] [PATCH RESEND] ARM: dts: Support audio on Exynos5422-odroidxu3 using simple-audio-card

[Sylwester Nawrocki]

On 23/03/15 03:51, Inha Song wrote:
 Add MAX98090 audio codec, I2S interface and the sound nodes to support
 audio on Exynos5422 SoC Based Odroid-XU3 board. Now we can support audio
 in Odroid-XU3 board using simple-audio-card DT binding.
 
 Signed-off-by: Inha Song ideal.s...@samsung.com
 ---
  arch/arm/boot/dts/exynos5420.dtsi  |  9 +
  arch/arm/boot/dts/exynos5422-odroidxu3.dts | 57 
 ++
  2 files changed, 66 insertions(+)
 
 diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
 b/arch/arm/boot/dts/exynos5420.dtsi
 index 4eaeabe..e459c1d 100644
 --- a/arch/arm/boot/dts/exynos5420.dtsi
 +++ b/arch/arm/boot/dts/exynos5420.dtsi
 @@ -415,6 +415,9 @@
   clock_audss EXYNOS_I2S_BUS,
   clock_audss EXYNOS_SCLK_I2S;
   clock-names = iis, i2s_opclk0, i2s_opclk1;
 + #clock-cells = 1;
 + clock-output-names = i2s_cdclk0;
 + #sound-dai-cells = 1;
   samsung,idma-addr = 0x0300;
   pinctrl-names = default;
   pinctrl-0 = i2s0_bus;
 @@ -429,6 +432,9 @@
   dma-names = tx, rx;
   clocks = clock CLK_I2S1, clock CLK_SCLK_I2S1;
   clock-names = iis, i2s_opclk0;
 + #clock-cells = 1;
 + clock-output-names = i2s_cdclk1;
 + #sound-dai-cells = 1;
   pinctrl-names = default;
   pinctrl-0 = i2s1_bus;
   status = disabled;
 @@ -442,6 +448,9 @@
   dma-names = tx, rx;
   clocks = clock CLK_I2S2, clock CLK_SCLK_I2S2;
   clock-names = iis, i2s_opclk0;
 + #clock-cells = 1;
 + clock-output-names = i2s_cdclk2;
 + #sound-dai-cells = 1;
   pinctrl-names = default;
   pinctrl-0 = i2s2_bus;
   status = disabled;
 diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts 
 b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
 index edc25cf..9275ad6 100644
 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
 +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
 @@ -11,6 +11,7 @@
  */
  
  /dts-v1/;
 +#include dt-bindings/sound/samsung-i2s.h
  #include exynos5800.dtsi
  
  / {
 @@ -285,6 +286,62 @@
   rtc@101E {
   status = okay;
   };
 +
 + sound: sound {
 + compatible = simple-audio-card;
 + assigned-clocks = clock_audss EXYNOS_MOUT_AUDSS,
 + clock_audss EXYNOS_MOUT_I2S,
 + clock_audss EXYNOS_DOUT_AUD_BUS;
 + assigned-clock-parents = clock CLK_FIN_PLL,
 + clock_audss EXYNOS_MOUT_AUDSS;
 + assigned-clock-rates = 0,
 + 0,
 + 1920;

The patch looks good, except it would be more appropriate to move the
above properties to clock_audss { }; node in this file.
With that change feel free to add:
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com

As a side note, this is a dts patch and of course Kukjin maintains that.
You would likely get it applied sooner if you would have addressed it
directly to Kukjin, rather than Mark or me.

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Re: [PATCH 1/1] serial: samsung: Clear operation mode on UART shutdown

[Sylwester Nawrocki]

On 13/03/15 12:38, Javier Martinez Canillas wrote:
 Exynos serial ports operate either in a DMA-based or interrupt-based
 modes. In DMA-based mode, the UART generates a transfer data request
 and a Transmission (Tx) interrupt in interrupt-based mode.
 
 The Tx IRQ is only unmasked in interrupt-based mode and it was done
 in s3c24xx_serial_start_tx(). Commit ba019a3e2ad5 (serial: samsung:
 remove redundant interrupt enabling) removed the IRQ enable on that
 function since it is enabled when the mode is set in enable_tx_pio().
 
 The problem is that enable_tx_pio() is only called if the port mode
 has not been set before but the mode was not cleared on .shutdown().
 
 So if the UART was shutdown and then started up again, the mode set
 will remain and the Tx IRQ won't be unmasked.
 
 This caused a hang on at least Exynos5250, Exynos5420 and Exynos5800
 when the system is rebooted or powered off.
 
 Fixes: ba019a3e2ad5 (serial: samsung: remove redundant interrupt enabling)
 Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
 ---
 
 I noticed this issue on an Exynos5250 Snow, Exynos5420 Peach Pit and Exynos
 5800 Peach Pi Chromebooks. This patch fixes the issue on all of them.
 
 The offending commit landed in v4.0-rc1 so this fix is -rc material.
 
  drivers/tty/serial/samsung.c | 1 +
  1 file changed, 1 insertion(+)
 
 diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
 index af821a908720..cf08876922f1 100644
 --- a/drivers/tty/serial/samsung.c
 +++ b/drivers/tty/serial/samsung.c
 @@ -963,6 +963,7 @@ static void s3c24xx_serial_shutdown(struct uart_port 
 *port)
   free_irq(ourport-tx_irq, ourport);
   tx_enabled(port) = 0;
   ourport-tx_claimed = 0;
 + ourport-tx_mode = 0;
   }

The patch looks good to me, Robert could you comment on that?

Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com

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[PATCH] ASoC: samsung: Enable SND_SIMPLE_CARD for Odroid X2/U3

[Sylwester Nawrocki]

Odroid X2/U3 sound support can now be specified in device tree using
the simple card binding, make SND_SOC_ODROIDX2 select SND_SIMPLE_CARD
to ensure there are always required drivers in place.

Reported-by: Tobias Jakobi liquid.a...@gmx.net
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
 sound/soc/samsung/Kconfig |1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index 0632a36..25caadf 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -226,6 +226,7 @@ config SND_SOC_ODROIDX2
depends on SND_SOC_SAMSUNG  I2C
select SND_SOC_MAX98090
select SND_SAMSUNG_I2S
+   select SND_SIMPLE_CARD
help
  Say Y here to enable audio support for the Odroid-X2/U3.
 
-- 
1.7.9.5

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Re: [PATCH v2] clk: samsung: Add CLKOUT driver support for Exynos3250 SoC.

[Sylwester Nawrocki]

On 12/03/15 00:34, Stephen Boyd wrote:
 On 03/01/15 18:15, Inha Song wrote:
  This patch add CLKOUT driver support for Exynos3250 SoC.
 
  Exynos3250 SoC PMU_DEBUG is the same with Exynos4's PMU_DEBUG
  including CLKOUT mux. So, We can use the exynos4's clkout init
  function for Exynos3250 without the need to add new function.
 
  Signed-off-by: Inha Song ideal.s...@samsung.com

 Do you want to take this through some SoC tree? If so:
 
 Acked-by: Stephen Boyd sb...@codeaurora.org

Thanks, I added this patch to my tree.
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Re: [PATCH 1/2] clk: samsung: exynos3250: Add driver for CMU_ISP clock domain

[Sylwester Nawrocki]

On 02/03/15 14:17, Beata Michalska wrote:
 From: Tomasz Figa t.f...@samsung.com
 
 Add clock controller for CMU ISP clock domain on Exynos3250,
 providing clocks for FIMC-IS subsystem.
 
 [b.michalska:use samsung_cmu_register_one to register
  the provider; updated DT binding documentation]

Thanks for moving the initial clocks settings to dts, I've added this
patch to my tree.
In future please don't forget to add version information to subsequent
patch iterations, it helps to ensure the right patch version is being
applied.

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Re: [PATCH 2/2] ARM: dts: exynos3250: Add assigned clock parents to CMU node

[Sylwester Nawrocki]

On 02/03/15 14:17, Beata Michalska wrote:
 Use assigned-clocks/assigned-clock-parents properties for
 CMU clock controller DT node to secure proper clock setup:
 switching the two muxes to root oscillator clock is not only
 required for proper powering down the ISP power domain,
 but it also reduces the risk of accessing the ISP CMU
 registers while the ISP power domain remains turned off
 (i.e. through the common clock framework by clk_summary)
 
 Signed-off-by: Beata Michalska b.michal...@samsung.com
 Acked-by: Kyungmin Park kyungmin.p...@samsung.com

Acked-by: Sylwester Nawrocki s.nawro...@samsung.com

Kukjin, please merge this patch for v4.1. I merged the exynos3250
CMU ISP driver patch and we will have regression if $subject patch
is not applied, i.e. reading /sys/kernel/debug/clk/clk_summary
would cause system hang on exynos3250.

 ---
  arch/arm/boot/dts/exynos3250.dtsi |4 
  1 file changed, 4 insertions(+)
 
 diff --git a/arch/arm/boot/dts/exynos3250.dtsi 
 b/arch/arm/boot/dts/exynos3250.dtsi
 index 277b48b..6d6118e 100644
 --- a/arch/arm/boot/dts/exynos3250.dtsi
 +++ b/arch/arm/boot/dts/exynos3250.dtsi
 @@ -172,6 +172,10 @@
   compatible = samsung,exynos3250-cmu;
   reg = 0x1003 0x2;
   #clock-cells = 1;
 + assigned-clocks = cmu CLK_MOUT_ACLK_400_MCUISP_SUB,
 +   cmu CLK_MOUT_ACLK_266_SUB;
 + assigned-clock-parents = cmu CLK_FIN_PLL,
 +  cmu CLK_FIN_PLL;
   };
  
   cmu_dmc: clock-controller@105C {
 

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Re: [RFC PATCH v2 3/3] ARM: dts: exynos5420: add async-bridge clocks to disp1 power domain

[Sylwester Nawrocki]

On 06/02/15 11:55, Andrzej Hajda wrote:
 FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER),
 therefore their clocks should be enabled during power domain switch.
 
 Signed-off-by: Andrzej Hajda a.ha...@samsung.com
 ---
  arch/arm/boot/dts/exynos5420.dtsi | 6 --
  1 file changed, 4 insertions(+), 2 deletions(-)
 
 diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
 b/arch/arm/boot/dts/exynos5420.dtsi
 index e1fa800..58579f5 100644
 --- a/arch/arm/boot/dts/exynos5420.dtsi
 +++ b/arch/arm/boot/dts/exynos5420.dtsi
 @@ -293,9 +293,11 @@
clock CLK_MOUT_SW_ACLK300,
clock CLK_MOUT_USER_ACLK300_DISP1,
clock CLK_MOUT_SW_ACLK400,
 -  clock CLK_MOUT_USER_ACLK400_DISP1;
 +  clock CLK_MOUT_USER_ACLK400_DISP1,
 +  clock CLK_FIMD1, clock CLK_MIXER;
   clock-names = oscclk, pclk0, clk0,
 -   pclk1, clk1, pclk2, clk2;
 +   pclk1, clk1, pclk2, clk2,
 +   asb0, asb1;
   };

In general I don't like those clock/clock-names properties in the power
domain nodes, since the power domains are not really consumers of those
clocks. However these clocks are essential for the exynos power domains
operation. There are more dependencies between the clocks and the power
domains which adding of those properties does not cover. And we'll need
to address those dependencies somehow.
Anyway, the subject patch looks OK to me, given that support for clocks/
clock-names in the exynos power domain device nodes has been merged
for quite long already.
The entire feature has been merged without PM or clk subsystem
maintainer ACK, I don't see a reason not to merge this small addition
of more clocks, especially that it fixes a real bug.

Please feel free to add:
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com

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Re: [RFC PATCH 2/3] arm/exynos/pm_domains: add support for async-bridge clocks

[Sylwester Nawrocki]

On 05/02/15 13:35, Andrzej Hajda wrote:
 Since Exynos5420 there are async-bridges (ASB) between different IPs. These
 bridges must be operational during power domain on/off, ie. clocks used
 by these bridges should be enabled.
 This patch enabled these clocks during domain on/off.
 
 Signed-off-by: Andrzej Hajda a.ha...@samsung.com

Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com

 ---
  arch/arm/mach-exynos/pm_domains.c | 27 +++
  1 file changed, 23 insertions(+), 4 deletions(-)
 
 diff --git a/arch/arm/mach-exynos/pm_domains.c 
 b/arch/arm/mach-exynos/pm_domains.c
 index 0e2bc36..ecff522 100644
 --- a/arch/arm/mach-exynos/pm_domains.c
 +++ b/arch/arm/mach-exynos/pm_domains.c
 @@ -37,6 +37,7 @@ struct exynos_pm_domain {
   struct clk *oscclk;
   struct clk *clk[MAX_CLK_PER_DOMAIN];
   struct clk *pclk[MAX_CLK_PER_DOMAIN];
 + struct clk *asb_clk[MAX_CLK_PER_DOMAIN];
  };
  
  static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
 @@ -45,14 +46,19 @@ static int exynos_pd_power(struct generic_pm_domain 
 *domain, bool power_on)
   void __iomem *base;
   u32 timeout, pwr;
   char *op;
 + int i;
  
   pd = container_of(domain, struct exynos_pm_domain, pd);
   base = pd-base;
  
 + for (i = 0; i  MAX_CLK_PER_DOMAIN; i++) {
 + if (IS_ERR(pd-asb_clk[i]))
 + break;
 + clk_prepare_enable(pd-asb_clk[i]);
 + }
 +
   /* Set oscclk before powering off a domain*/
   if (!power_on) {
 - int i;
 -
   for (i = 0; i  MAX_CLK_PER_DOMAIN; i++) {
   if (IS_ERR(pd-clk[i]))
   break;
 @@ -81,8 +87,6 @@ static int exynos_pd_power(struct generic_pm_domain 
 *domain, bool power_on)
  
   /* Restore clocks after powering on a domain*/
   if (power_on) {
 - int i;
 -
   for (i = 0; i  MAX_CLK_PER_DOMAIN; i++) {
   if (IS_ERR(pd-clk[i]))
   break;
 @@ -92,6 +96,12 @@ static int exynos_pd_power(struct generic_pm_domain 
 *domain, bool power_on)
   }
   }
  
 + for (i = 0; i  MAX_CLK_PER_DOMAIN; i++) {
 + if (IS_ERR(pd-asb_clk[i]))
 + break;
 + clk_disable_unprepare(pd-asb_clk[i]);
 + }
 +
   return 0;
  }
  
 @@ -137,6 +147,15 @@ static __init int exynos4_pm_init_power_domain(void)
   pd-pd.power_off = exynos_pd_power_off;
   pd-pd.power_on = exynos_pd_power_on;
  
 + for (i = 0; i  MAX_CLK_PER_DOMAIN; i++) {
 + char clk_name[8];
 +
 + snprintf(clk_name, sizeof(clk_name), asb%d, i);
 + pd-asb_clk[i] = clk_get(dev, clk_name);
 + if (IS_ERR(pd-asb_clk[i]))
 + break;
 + }
 +
   pd-oscclk = clk_get(dev, oscclk);
   if (IS_ERR(pd-oscclk))
   goto no_clk;
 


-- 
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Samsung RD Institute Poland
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Re: [PATCH RFT] phy: exynos-mipi-video: Use spin_lock to protct state-regmap rmw operations

[Sylwester Nawrocki]

Hi,

On 04/03/15 13:24, Kishon Vijay Abraham I wrote:
 This patch doesn't apply on 4.0-rc1. Can to refresh it to mainline
 latest?

It depends on Axel's previous patch: phy: exynos-mipi-video: Fixup
the test for state-regmap. Are there any issues even with that patch
applied ?

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Re: [PATCH RFT] phy: exynos-mipi-video: Use spin_lock to protct state-regmap rmw operations

[Sylwester Nawrocki]

On 27/02/15 04:50, Axel Lin wrote:
 he state-regmap is initialized by devm_regmap_init_mmio().
 So it's fine to use spin_lock rather than mutex to protct state-regmap rmw
 operations.
 
 Signed-off-by: Axel Lin axel@ingics.com
 ---
 Hi Sylwester,
 I don't have this hardware handy, so can you test if this patch works.
 This patch is on top of my previous patch (phy: exynos-mipi-video: Fixup 
 the test for state-regmap)

Thanks for the patch, it looks good to me. I somehow missed the syscon
already uses a spinlock for regmap protection.

v4.0-rc1 seems devastated as far as exynos4 is concerned, it may take
some time until I get around and fix all the issues so I tested your
patch on v3.19. It all works well as expected.

Acked-by: Sylwester Nawrocki s.nawro...@samsung.com
Tested-by: Sylwester Nawrocki s.nawro...@samsung.com

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Re: [PATCH] phy: exynos-dp-video: Kill exynos_dp_video_phy_pwr_isol function

[Sylwester Nawrocki]

On 27/02/15 05:34, Axel Lin wrote:
 If IS_ERR(state-regs) the .probe fails.
 So IS_ERR(state-regs) test in exynos_dp_video_phy_pwr_isol() is not 
 necessary.
 exynos_dp_video_phy_pwr_isol() simply does a regmap_update_bits() call now,
 just call regmap_update_bits() instead and return proper return value.
 
 Signed-off-by: Axel Lin axel@ingics.com

Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com

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Re: [PATCH] phy: exynos-mipi-video: Fixup the test for state-regmap

[Sylwester Nawrocki]

On 26/02/15 04:48, Axel Lin wrote:
 syscon_regmap_lookup_by_phandle() returns ERR_PTR on error.
 Thus don't use null test against state-regmap.
 
 Signed-off-by: Axel Lin axel@ingics.com

Thanks for the patch, I had this on my todo list.

Acked-by: Sylwester Nawrocki s.nawro...@samsung.com
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Re: [PATCH] [media] s5p-jpeg: Clear JPEG_CODEC_ON bits in sw reset function

[Sylwester Nawrocki]

Hi,

On 17/12/14 07:22, Tony K Nadackal wrote:
 Bits EXYNOS4_DEC_MODE and EXYNOS4_ENC_MODE do not get cleared
 on software reset. These bits need to be cleared explicitly.
 
 Signed-off-by: Tony K Nadackal tony...@samsung.com
 ---
 This patch is created and tested on top of linux-next-20141210.
 It can be cleanly applied on media-next and kgene/for-next.
 
 
  drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c | 4 
  1 file changed, 4 insertions(+)
 
 diff --git a/drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c 
 b/drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c
 index ab6d6f43..e53f13a 100644
 --- a/drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c
 +++ b/drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c
 @@ -21,6 +21,10 @@ void exynos4_jpeg_sw_reset(void __iomem *base)
   unsigned int reg;
  
   reg = readl(base + EXYNOS4_JPEG_CNTL_REG);
 + writel(reg  ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE),
 + base + EXYNOS4_JPEG_CNTL_REG);
 +
 + reg = readl(base + EXYNOS4_JPEG_CNTL_REG);

Do we really need the second read? Wouldn't it also work as below ?

reg = readl(base + EXYNOS4_JPEG_CNTL_REG);

+   reg = ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE);
+   writel(reg, base + EXYNOS4_JPEG_CNTL_REG);

?
   writel(reg  ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG);
  
   udelay(100);
--
Thanks,
Sylwester
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Re: [PATCH] [media] s5p-jpeg: Fix crash in jpeg isr due to multiple interrupts.

[Sylwester Nawrocki]

On 17/12/14 07:25, Tony K Nadackal wrote:
 In case of corrupt images, multiple interrupts may occur
 due to different error scenarios.
 
 Since we are removing the src and dest buffers in the first
 interrupt itself, crash occurs in the second error interrupts.
 
 Disable the global interrupt before we start processing
 the interrupt avoid the crash.
 
 Disable System interrupt in isr to avoid the crash below.

Rather than disabling all interrupts, is there no way to check
the interrupt reason from some status register and decide
whether we return the buffers or just ignore the interrupt ?

-- 
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Re: [PATCH 1/6] ASoC: max98088: Document DT bindings

[Sylwester Nawrocki]

On 20/02/15 01:36, Andreas Färber wrote:
  So it seems the mclk is not always set up properly by the kernel,
  relying on firmware. Who's in charge of setting that clock up?
  
  Right, it seems audio is only working due the firmware doing some previous
  setup. Probably it works on every boot if you have sound init as a part 
  of
  the u-boot boot commands?

 Indeed it does, 24 MHz without the reparenting patch, and sound working.

You can have parent of the CLKOUT clock set by the clk core if it is
specified in device tree in the PMU (the clkout clock supplier) device
node.

Similarly as we did for the Odroix U3:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/exynos4412-odroid-common.dtsi#n39

Relying on the clk_set_rate() to set the parent clock is not optimal
IMO. Presumably you need to set select stable parent clock for clkout
like XXTI. But I'm not very familiar with exyno5250 and that might be
something different.

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Re: [PATCH 1/1] ARM: dts: Use more descriptive names for Exynos5420 PDs

[Sylwester Nawrocki]

On 10/02/15 13:46, Javier Martinez Canillas wrote:
 This debugfs code iterates over list of generic_pm_domains (gpd_list). I
   cannot find function for translating from genpd to its platform device
   so only genpd-name can be printed.
  
  Then why power domains aren't just named with the platform device 
  names?
  
  Right, the mach-exynos/pm_domains.c set the name equal to OF node name.
  I'll send a patch extending the name.
 
 IIRC the OF core uses the device node unit address and node name to create
 the platform device names so you will have something like 
 10044000.power-domain.
 
 Same if using the node full_name since it will /power-domain@10044000. In both
 cases the DTS should have to be checked to know which power domain really is
 unless someone knows by heart the power domains addresses.
 
 But if using generic names for the power domains as suggested by ePAPR is so
 important then we should change all the other Exynos DTS files which don't do.

Perhaps we could assign OF aliases to the power domain device nodes in DT
and then in the power domains driver map those aliases to more descriptive
names when creating the power domains?

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Re: [PATCH 1/4] drm/exynos: dsim: fix to control mipi phy register

[Sylwester Nawrocki]

On 07/02/15 12:53, Inki Dae wrote:
 This patch fixes the issue that the try to get a phy object is failed
 to enable mipi phy.
 
 System and power management unit registers should be controlled by
 syscon framework. So this patch removes existing phy framework based
 codes and adds syscon support instead. However, we should support
 legacy device tree binding so consider the legacy binding for compatibility.
 
 In addition, we need to remove below device node and relevant properties,
   mipi_phy: video-phy@10020710 {
   compatible = samsung,s5pv210-mipi-video-phy;
   reg = 0x10020710 8;
   #phy-cells = 1;
   };
 
 Now camera device node uses mipi_phy node relevant properties like below,
   camera {
   ...
   csis_0: csis@1188 {
   ...
   phys = mipi_phy 0;
   phy-names = csis;
   ...
   };
   csis_1: csis@1189 {
   ...
   phys = mipi_phy 2;
   phy-names = csis;
   ...
   };
   ...
   };
 
 With above, we will find below message while booting,
  can't request region for resource [mem 0x10020710-0x10020717]

I'm afraid this approach won't work because MIPI DSI Master and MIPI CSI
Slave devices share a control bit in the register and it seems impossible
to ensure proper locking with current regmap/syscon API.

I have submitted patches to fix this issue [1] and they should be already
available in linux-next and can be found on linux-samsung-soc ML:

[PATCH 1/2] phy: exynos-video-mipi: Fix regression by adding support for PMU 
regmap
[PATCH 2/2] ARM: dts: Add syscon phandle to the video-phy node for Exynos4

The other issue with your approach is that we are moving the PMU details
to the MIPI DSIM driver and similar changes would need to be done in
the MIPI CSIS driver.

Instead I just added syscon support to the PHY layer, it's not perfect
but fixes the issue for both DSI and CSI and  doesn't strip the PHY layer
which could potentially be useful.

-- 
Thanks,
Sylwester

[1] https://patchwork.ozlabs.org/patch/429948/
http://www.spinics.net/lists/linux-samsung-soc/msg41210.html
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Re: [PATCH 1/4] drm/exynos: dsim: fix to control mipi phy register

[Sylwester Nawrocki]

On 09/02/15 13:17, Inki Dae wrote:
 Instead I just added syscon support to the PHY layer, it's not perfect
  but fixes the issue for both DSI and CSI and  doesn't strip the PHY layer
  which could potentially be useful.

 Ah, Right. I didn't check your patch set. Your way is a better idea than
 my one. With this, we don't need to change device drivers, MIPI DSI and CSI.
 
 Then, what is the meaning that it's not perfect?

What I didn't like is that there are at least 3 mutexes on the phy_power_on/
phy_power_off path (PHY core, PHY driver, regmap) and there is another level
of indirection after introducing the regmap. I guess it's nothing serious
though. And BTW the syscon could be converted to use spinlock rather than
a mutex, since in our case behind the PMU syscon is always a memory mapped
region.

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Re: [RESEND PATCH V3 15/15] ARM: dts: Fix I2S1, I2S2 compatible for exynos4 SoCs

[Sylwester Nawrocki]

On 05/02/15 20:41, Mark Brown wrote:
 On Tue, Feb 03, 2015 at 03:06:22PM +0100, Sylwester Nawrocki wrote:
 I2S1, I2S2 on Exynos4 SoC series have limited functionality compared
 to I2S0, samsung,s3c6410-i2s compatible should be used for them.
 
 I've applied this even though I really shouldn't in order to get it in.
 Since it's a bug fix for stable it should've been near the head of any
 series it's part of not the very last patch in the series, and since
 it's not really related to the rest of the series except in that it
 relates to the same driver it should probably have been sent by itself
 rather than mixed in with everything else.

Indeed I could sent this one separately to Kukjin, the issue it fixes
was just found in the course of creating remaining part of the series
and I wanted to keep somewhat related changes together.
Thank you for merging it.  I hope you picked up the previous 2 as well,
I couldn't see them in your tree.
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Re: [v3,1/9] clk: samsung: exynos5433: Add clocks for CMU_APOLLO domain

[Sylwester Nawrocki]

On 05/02/15 08:44, Pankaj Dubey wrote:
 +static struct samsung_gate_clock apollo_gate_clks[] __initdata = {

  +
  +  /* ENABLE_PCLK_APOLLO */
  +  GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, pclk_asapbmst_cssys_apollo,
  +  div_pclk_dbg_apollo, ENABLE_PCLK_APOLLO,
  +  2, CLK_IGNORE_UNUSED, 0),
  +  GATE(CLK_PCLK_PMU_APOLLO, pclk_pmu_apollo, div_pclk_apollo,
  +  ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
  +  GATE(CLK_PCLK_SYSREG_APOLLO, pclk_pmu_sysreg_apollo,

 Isn't pclk_pmu_sysreg_apollo be named as pclk_sysreg_apollo to match 
 with UM?

Sounds reasonable, Chanwoo, if you agree I'll squash following change
to this patch before sending upstream:

diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 7a024cd..387e3e3 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -3656,7 +3656,7 @@ static struct samsung_gate_clock apollo_gate_clks[]
__initdata = {
2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PMU_APOLLO, pclk_pmu_apollo, div_pclk_apollo,
ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
-   GATE(CLK_PCLK_SYSREG_APOLLO, pclk_pmu_sysreg_apollo,
+   GATE(CLK_PCLK_SYSREG_APOLLO, pclk_sysreg_apollo,
div_pclk_apollo, ENABLE_PCLK_APOLLO,
0, CLK_IGNORE_UNUSED, 0),
--
Thanks,
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[GIT PULL] clk/samsung: clk support for Exynos 5433 SoC

[Sylwester Nawrocki]

Hi Mike,

This pull request includes driver for clock controller of the Exynos 
5433 SoC.  As the hardware is quite complex, with many peripherals and 
corresponding clock management units the driver is rather huge.  I guess 
it will require a bit more cleanups than last time to balance lines 
introduced in this patch set... Please review and pull if it looks OK.

The following changes since commit e64fb42da4c6c713cfc7cad607e97e0773fa41ff:

  clk: samsung: exynos4: Add divider clock id for memory bus frequency 
(2015-01-28 15:51:17 +0100)

are available in the git repository at:

  git://linuxtv.org/snawrocki/samsung.git tags/v3.20-exynos5433-clk

for you to fetch changes up to b2f0e5f28e0686c0d5db238357a2e32555e97633:

  clk: samsung: exynos5433: Move CLK_SCLK_HDMI_SPDIF_DISP clock to CMU_TOP 
domain (2015-02-05 19:31:09 +0100)


Clock controller driver for Exynos 5433 SoC.


Chanwoo Choi (22):
  clk: samsung: exynos5433: Add binding document for Exynos5433 clock 
domains
  clk: samsung: exynos5433: Add clocks using common clock framework
  clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
  clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
  clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
  clk: samsung: exynos5433: Add clocks for CMU_G2D domain
  clk: samsung: exynos5433: Add clocks for CMU_MIF domain
  clk: samsung: exynos5433: Add clocks for CMU_DISP domain
  clk: samsung: exynos5433: Add clocks for CMU_AUD domain
  clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
  clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
  clk: samsung: exynos5433: Add clocks for CMU_G3D domain
  clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
  clk: samsung: exynos5433: Add clocks for CMU_APOLLO domain
  clk: samsung: exynos5433: Add clocks for CMU_ATLAS domain
  clk: samsung: exynos5433: Add clocks for CMU_MSCL domain
  clk: samsung: exynos5433: Add clocks for CMU_MFC domain
  clk: samsung: exynos5433: Add clocks for CMU_HEVC domain
  clk: samsung: exynos5433: Add clocks for CMU_ISP domain
  clk: samsung: exynos5433: Add clocks for CMU_CAM0 domain
  clk: samsung: exynos5433: Add clocks for CMU_CAM1 domain
  clk: samsung: exynos5433: Move CLK_SCLK_HDMI_SPDIF_DISP clock to CMU_TOP 
domain

Inha Song (1):
  clk: samsung: Add CLKOUT driver support for Exynos5433 SoC

 .../devicetree/bindings/clock/exynos5433-clock.txt |  462 ++
 drivers/clk/samsung/Makefile   |1 +
 drivers/clk/samsung/clk-exynos-clkout.c|2 +
 drivers/clk/samsung/clk-exynos5433.c   | 5423 
 include/dt-bindings/clock/exynos5433.h | 1403 +
 5 files changed, 7291 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt
 create mode 100644 drivers/clk/samsung/clk-exynos5433.c
 create mode 100644 include/dt-bindings/clock/exynos5433.h

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Re: [PATCH v5 02/13] clk: samsung: exynos5433: Add clocks using common clock framework

[Sylwester Nawrocki]

Hi Chanwoo,

On 02/02/15 15:23, Chanwoo Choi wrote:
 +/*
 + * ATLAS_PLL  APOLLO_PLL  MEM0_PLL  MEM1_PLL  BUS_PLL  MFC_PLL
 + *  MPHY_PLL  G3D_PLL  DISP_PLL  ISP_PLL
 + */
 +static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
 + PLL_35XX_RATE(25, 625, 6,  0),
 + PLL_35XX_RATE(24, 500, 5,  0),
 + PLL_35XX_RATE(23, 575, 6,  0),
 + PLL_35XX_RATE(22, 550, 6,  0),
 + PLL_35XX_RATE(21, 350, 4,  0),
 + PLL_35XX_RATE(20, 500, 6,  0),
 + PLL_35XX_RATE(19, 475, 6,  0),
 + PLL_35XX_RATE(18, 375, 5,  0),
 + PLL_35XX_RATE(17, 425, 6,  0),
 + PLL_35XX_RATE(16, 400, 6,  0),
 + PLL_35XX_RATE(15, 250, 4,  0),
 + PLL_35XX_RATE(14, 350, 6,  0),
 + PLL_35XX_RATE(133200, 222, 4,  0),
 + PLL_35XX_RATE(13, 325, 6,  0),
 + PLL_35XX_RATE(12, 500, 5,  1),
 + PLL_35XX_RATE(11, 550, 6,  1),
 + PLL_35XX_RATE(108600, 362, 4,  1),
 + PLL_35XX_RATE(106600, 533, 6,  1),
 + PLL_35XX_RATE(10, 500, 6,  1),
 + PLL_35XX_RATE(93300,  311, 4,  1),
 + PLL_35XX_RATE(92100,  307, 4,  1),
 + PLL_35XX_RATE(9,  375, 5,  1),
 + PLL_35XX_RATE(82500,  275, 4,  1),
 + PLL_35XX_RATE(8,  400, 6,  1),
 + PLL_35XX_RATE(73300,  733, 12, 1),
 + PLL_35XX_RATE(7,  360, 6,  1),
 + PLL_35XX_RATE(66700,  222, 4,  1),
 + PLL_35XX_RATE(63300,  211, 4,  1),
 + PLL_35XX_RATE(6,  500, 5,  2),
 + PLL_35XX_RATE(55200,  460, 5,  2),
 + PLL_35XX_RATE(55000,  550, 6,  2),
 + PLL_35XX_RATE(54300,  362, 4,  2),
 + PLL_35XX_RATE(53300,  533, 6,  2),
 + PLL_35XX_RATE(5,  500, 6,  2),
 + PLL_35XX_RATE(44400,  370, 5,  2),
 + PLL_35XX_RATE(42000,  350, 5,  2),
 + PLL_35XX_RATE(4,  400, 6,  2),
 + PLL_35XX_RATE(35000,  360, 6,  2),
 + PLL_35XX_RATE(33300,  222, 4,  2),
 + PLL_35XX_RATE(3,  500, 5,  3),
 + PLL_35XX_RATE(26600,  532, 6,  3),
 + PLL_35XX_RATE(2,  400, 6,  3),
 + PLL_35XX_RATE(16600,  332, 6,  3),
 + PLL_35XX_RATE(16000,  320, 6,  3),
 + PLL_35XX_RATE(13300,  552, 6,  4),
 + PLL_35XX_RATE(1,  400, 6,  4),
 + { /* sentinel */ }
 +};
 +
 +/* AUD_PLL */
 +static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
 + PLL_36XX_RATE(4, 200, 3, 2,  0),
 + PLL_36XX_RATE(393216000, 197, 3, 2, -25690),
 + PLL_36XX_RATE(38400, 128, 2, 2,  0),
 + PLL_36XX_RATE(36864, 246, 4, 2, -15729),
 + PLL_36XX_RATE(361507200, 181, 3, 2, -16148),
 + PLL_36XX_RATE(338688000, 113, 2, 2,  -6816),
 + PLL_36XX_RATE(294912000,  98, 1, 3,  19923),
 + PLL_36XX_RATE(28800,  96, 1, 3,  0),
 + PLL_36XX_RATE(25200,  84, 1, 3,  0),
 + { /* sentinel */ }
 +};

To avoid issues pointed out by these build warnings:

drivers/clk/samsung/clk-exynos5433.c:726:2: warning: this decimal constant is 
unsigned only in ISO C90 [enabled by default]
drivers/clk/samsung/clk-exynos5433.c:727:2: warning: this decimal constant is 
unsigned only in ISO C90 [enabled by default]
drivers/clk/samsung/clk-exynos5433.c:728:2: warning: this decimal constant is 
unsigned only in ISO C90 [enabled by default]
drivers/clk/samsung/clk-exynos5433.c:729:2: warning: this decimal constant is 
unsigned only in ISO C90 [enabled by default]

I have squashed following change to the $subject patch:

---8---
diff --git a/drivers/clk/samsung/clk-exynos5433.c 
b/drivers/clk/samsung/clk-exynos5433.c
index bdd4113..7a024cd 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -723,66 +723,66 @@ static struct samsung_gate_clock top_gate_clks[] 
__initdata = {
  *  MPHY_PLL  G3D_PLL  DISP_PLL  ISP_PLL
  */
 static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
-   PLL_35XX_RATE(25, 625, 6,  0),
-   PLL_35XX_RATE(24, 500, 5,  0),
-   PLL_35XX_RATE(23, 575, 6,  0),
-   PLL_35XX_RATE(22, 550, 6,  0),
-   PLL_35XX_RATE(21, 350, 4,  0),
-   PLL_35XX_RATE(20, 500, 6,  0),
-   PLL_35XX_RATE(19, 475, 6,  0),
-   PLL_35XX_RATE(18, 375, 5,  0),
-   PLL_35XX_RATE(17, 425, 6,  0),
-   PLL_35XX_RATE(16, 400, 6,  0),
-   PLL_35XX_RATE(15, 250, 4,  0),
-   PLL_35XX_RATE(14, 350, 6,  0),
-   PLL_35XX_RATE(133200, 222, 4,  0),
-   PLL_35XX_RATE(13, 325, 6,  0),
-   PLL_35XX_RATE(12, 500, 5,  1),
-   PLL_35XX_RATE(11, 550, 6,  1),
-   PLL_35XX_RATE(108600, 362, 4,  1),
-   PLL_35XX_RATE(106600, 533, 6,  1),
-   PLL_35XX_RATE(10, 500, 6,  1),
-   PLL_35XX_RATE(93300,  311, 4,  1),
-   PLL_35XX_RATE(92100,  307, 4,  1),
-   

Re: [PATCH v5 10/13] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains

[Sylwester Nawrocki]

Hi Chanwoo,

On 02/02/15 15:24, Chanwoo Choi wrote:
 This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
 which contain global data buses clocked at up the 400MHz. These blocks
 transfer data between DRAM and various sub-blocks. These clock domains
 also contain global peripheral buses clocked at 67/111/200/222/266/333/400
 MHz and used for register accesses.

 +/*
 + * Register offset definitions for CMU_BUS{0|1|2}
 + */
 +#define DIV_BUS  0x0600
 +#define DIV_STAT_BUS 0x0700
 +#define ENABLE_ACLK_BUS  0x0800
 +#define ENABLE_PCLK_BUS  0x0900
 +#define ENABLE_IP_BUS0   0x0b00
 +#define ENABLE_IP_BUS1   0x0b04
 +
 +#define MUX_SEL_BUS2 0x0200  /* Only for CMU_BUS2 */
 +#define MUX_ENABLE_BUS2  0x0300  /* Only for CMU_BUS2 */
 +#define MUX_STAT_BUS20x0400  /* Only for CMU_BUS2 */
 +
 +/* list of all parent clock list */
 +PNAME(mout_aclk_bus2_400_p)  = { oscclk, aclk_bus2_400, };
 +
 +#define CMU_BUS_COMMON_CLK_REGS  \
 + DIV_BUS,\
 + DIV_STAT_BUS,   \
 + ENABLE_ACLK_BUS,\
 + ENABLE_PCLK_BUS,\
 + ENABLE_IP_BUS0, \
 + ENABLE_IP_BUS1
 +
 +static unsigned long bus01_clk_regs[] __initdata = {
 + CMU_BUS_COMMON_CLK_REGS,
 +};
 +
 +static unsigned long bus2_clk_regs[] __initdata = {
 + MUX_SEL_BUS2,
 + MUX_ENABLE_BUS2,
 + MUX_STAT_BUS2,
 + CMU_BUS_COMMON_CLK_REGS,
 +};
 +
 +static struct samsung_div_clock bus0_div_clks[] __initdata = {
 + /* DIV_BUS0 */
 + DIV(CLK_DIV_PCLK_BUS_133, div_pclk_bus0_133, aclk_bus0_400,
 + DIV_BUS, 0, 3),
 +};
 +
 +/* CMU_BUS0 clocks */
 +static struct samsung_gate_clock bus0_gate_clks[] __initdata = {
 + /* ENABLE_ACLK_BUS0 */
 + GATE(CLK_ACLK_AHB2APB_BUSP, aclk_ahb2apb_bus0p, div_pclk_bus0_133,
 + ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
 + GATE(CLK_ACLK_BUSNP_133, aclk_bus0np_133, div_pclk_bus0_133,
 + ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
 + GATE(CLK_ACLK_BUSND_400, aclk_bus0nd_400, aclk_bus0_400,
 + ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
 +
 + /* ENABLE_PCLK_BUS0 */
 + GATE(CLK_PCLK_BUSSRVND_133, pclk_bus0srvnd_133, div_pclk_bus0_133,
 + ENABLE_PCLK_BUS, 2, 0, 0),
 + GATE(CLK_PCLK_PMU_BUS, pclk_pmu_bus0, div_pclk_bus0_133,
 + ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
 + GATE(CLK_PCLK_SYSREG_BUS, pclk_sysreg_bus0, div_pclk_bus0_133,
 + ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
 +};
 +
 +/* CMU_BUS1 clocks */
 +static struct samsung_div_clock bus1_div_clks[] __initdata = {
 + /* DIV_BUS1 */
 + DIV(CLK_DIV_PCLK_BUS_133, div_pclk_bus1_133, aclk_bus1_400,
 + DIV_BUS, 0, 3),
 +};
 +
 +static struct samsung_gate_clock bus1_gate_clks[] __initdata = {
 + /* ENABLE_ACLK_BUS1 */
 + GATE(CLK_ACLK_AHB2APB_BUSP, aclk_ahb2apb_bus1p, div_pclk_bus1_133,
 + ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
 + GATE(CLK_ACLK_BUSNP_133, aclk_bus1np_133, div_pclk_bus1_133,
 + ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
 + GATE(CLK_ACLK_BUSND_400, aclk_bus1nd_400, aclk_bus1_400,
 + ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
 +
 + /* ENABLE_PCLK_BUS1 */
 + GATE(CLK_PCLK_BUSSRVND_133, pclk_bus1srvnd_133, div_pclk_bus1_133,
 + ENABLE_PCLK_BUS, 2, 0, 0),
 + GATE(CLK_PCLK_PMU_BUS, pclk_pmu_bus1, div_pclk_bus1_133,
 + ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
 + GATE(CLK_PCLK_SYSREG_BUS, pclk_sysreg_bus1, div_pclk_bus1_133,
 + ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
 +};
 +
 +/* CMU_BUS2 clocks */
 +static struct samsung_mux_clock bus2_mux_clks[] __initdata = {
 + /* MUX_SEL_BUS2 */
 + MUX(CLK_MOUT_ACLK_BUS2_400_USER, mout_aclk_bus2_400_user,
 + mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
 +};
 +
 +static struct samsung_div_clock bus2_div_clks[] __initdata = {
 + /* DIV_BUS2 */
 + DIV(CLK_DIV_PCLK_BUS_133, div_pclk_bus2_133,
 + mout_aclk_bus2_400_user, DIV_BUS, 0, 3),
 +};
 +
 +static struct samsung_gate_clock bus2_gate_clks[] __initdata = {
 + /* ENABLE_ACLK_BUS2 */
 + GATE(CLK_ACLK_AHB2APB_BUSP, aclk_ahb2apb_bus2p, div_pclk_bus2_133,
 + ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
 + GATE(CLK_ACLK_BUSNP_133, aclk_bus2np_133, div_pclk_bus2_133,
 + ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
 + GATE(CLK_ACLK_BUS2BEND_400, aclk_bus2bend_400,
 + mout_aclk_bus2_400_user, ENABLE_ACLK_BUS,
 + 1, CLK_IGNORE_UNUSED, 0),
 + GATE(CLK_ACLK_BUS2RTND_400, aclk_bus2rtnd_400,
 + 

Re: [PATCH v5 08/13] clk: samsung: exynos5433: Add clocks for CMU_DISP domain

[Sylwester Nawrocki]

Hi Chanwoo,

On 02/02/15 15:24, Chanwoo Choi wrote:
 This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
 includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP 
 clocks
 is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
 related to CMU_DISP should be always on state.

Are you sure we need to add anything to CMU_MIF in this patch ?

 Also, CMU_DISP must need the source clock of 'sclk_hdmi_spdif_disp'
 from CMU_TOP domain. This patch adds the clocks of CMU_TOP related to HDMI.
 
 Cc: Sylwester Nawrocki s.nawro...@samsung.com
 Cc: Tomasz Figa tomasz.f...@gmail.com
 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
 Acked-by: Inki Dae inki@samsung.com
 ---
  drivers/clk/samsung/clk-exynos5433.c   | 437 
 +
  include/dt-bindings/clock/exynos5433.h | 114 -
  2 files changed, 550 insertions(+), 1 deletion(-)
 
 diff --git a/drivers/clk/samsung/clk-exynos5433.c 
 b/drivers/clk/samsung/clk-exynos5433.c
 index 3d6164e..cf3f0ac 100644
 --- a/drivers/clk/samsung/clk-exynos5433.c
 +++ b/drivers/clk/samsung/clk-exynos5433.c
 @@ -245,6 +245,8 @@ PNAME(mout_sclk_audio1_p) = { ioclk_audiocdclk1, 
 oscclk,
  PNAME(mout_sclk_audio0_p)= { ioclk_audiocdclk0, oscclk,
   mout_aud_pll_user_t,};
  
 +PNAME(mout_sclk_hdmi_spdif_p)= { sclk_audio1, 
 ioclk_spdif_extclk, };
 +
  static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata 
 = {
   FFACTOR(0, oscclk_efuse_common, oscclk, 1, 1, 0),
  };
 @@ -395,6 +397,10 @@ static struct samsung_mux_clock top_mux_clks[] 
 __initdata = {
   MUX_SEL_TOP_PERIC1, 4, 2),
   MUX(CLK_MOUT_SCLK_AUDIO0, mout_sclk_audio0, mout_sclk_audio0_p,
   MUX_SEL_TOP_PERIC1, 0, 2),
 +
 + /* MUX_SEL_TOP_DISP */
 + MUX(CLK_MOUT_SCLK_HDMI_SPDIF, mout_sclk_hdmi_spdif,
 + mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
  };
  
  static struct samsung_div_clock top_div_clks[] __initdata = {
 @@ -1360,6 +1366,11 @@ static struct samsung_gate_clock mif_gate_clks[] 
 __initdata = {
   ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
   GATE(CLK_SCLK_BUS_PLL_ATLAS, sclk_bus_pll_atlas, sclk_bus_pll,
   ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
 +
 + /* ENABLE_SCLK_TOP_DISP */
 + GATE(CLK_SCLK_HDMI_SPDIF_DISP, sclk_hdmi_spdif_disp,
 + mout_sclk_hdmi_spdif, ENABLE_SCLK_TOP_DISP, 0,
 + CLK_IGNORE_UNUSED, 0),

I think this clock should be added to top_gate_clks[] table instead, i.e.
it seems to belong to CMU_TOP, not CMU_MIF. Can you double check it ?

If you confirm this I will add following change when applying, no need
to resend again:

8---
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index cf3f0ac..edf9795 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -556,6 +556,11 @@ static struct samsung_gate_clock top_gate_clks[]
__initdata = {
MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
GATE(CLK_SCLK_AUDIO0, sclk_audio0, div_sclk_audio0,
MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
+
+   /* ENABLE_SCLK_TOP_DISP */
+   GATE(CLK_SCLK_HDMI_SPDIF_DISP, sclk_hdmi_spdif_disp,
+   mout_sclk_hdmi_spdif, ENABLE_SCLK_TOP_DISP, 0,
+   CLK_IGNORE_UNUSED, 0),
 };

 /*
@@ -1366,11 +1371,6 @@ static struct samsung_gate_clock mif_gate_clks[]
__initdata = {
ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_BUS_PLL_ATLAS, sclk_bus_pll_atlas, sclk_bus_pll,
ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
-
-   /* ENABLE_SCLK_TOP_DISP */
-   GATE(CLK_SCLK_HDMI_SPDIF_DISP, sclk_hdmi_spdif_disp,
-   mout_sclk_hdmi_spdif, ENABLE_SCLK_TOP_DISP, 0,
-   CLK_IGNORE_UNUSED, 0),
 };
8---

--
Thanks,
Sylwester


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Re: [PATCH V3 13/15] ARM: dts: Exynos4 and Odroid X2/U3 sound device nodes update

[Sylwester Nawrocki]

On 03/02/15 14:11, Mark Brown wrote:
 On Tue, Feb 03, 2015 at 12:04:16PM +0100, Sylwester Nawrocki wrote:
 
   Sorry, I should've said - I applied the ASoC patches, not these.
   Shall I take 13 to 15 DT patches in Samsung tree?
  Patches 13, 14 use macro definitions which are added in patch which is
  already in Mark's sound tree (ASoC: samsung: i2s: Add clk provider DT
  binding documentation) [1]. We would need to consider that to avoid
  build breaks.

 OK, I can apply them if people want but I'd need a resend - I discarded
 them since they'd normally go via the arch tree.

I will resend the last 3 patches then. There also shouldn't be any issues
if 13, 14 are only merged through ASoC tree and patch 15 through Samsung
tree.

--
Thanks,
Sylwester
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[RESEND PATCH V3 13/15] ARM: dts: Exynos4 and Odroid X2/U3 sound device nodes update

[Sylwester Nawrocki]

Clock related properties are added to the Exynos4 I2S device nodes
so they can be referred to as clock providers. Missing i2s_opclk1
clock is added to the I2S0 node and clock properties are added
to the MAX98090 codec node to allow it to control/read frequency
of the MCLK clock directly.

Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
 arch/arm/boot/dts/exynos4.dtsi  |6 ++
 arch/arm/boot/dts/exynos4412-odroid-common.dtsi |8 ++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index b8168f1..38d8f68 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -61,6 +61,8 @@
reg = 0x0383 0x100;
clocks = clock_audss EXYNOS_I2S_BUS;
clock-names = iis;
+   #clock-cells = 1;
+   clock-output-names = i2s_cdclk0;
dmas = pdma0 12, pdma0 11, pdma0 10;
dma-names = tx, rx, tx-sec;
samsung,idma-addr = 0x0300;
@@ -372,6 +374,8 @@
reg = 0x1396 0x100;
clocks = clock CLK_I2S1;
clock-names = iis;
+   #clock-cells = 1;
+   clock-output-names = i2s_cdclk1;
dmas = pdma1 12, pdma1 11;
dma-names = tx, rx;
status = disabled;
@@ -382,6 +386,8 @@
reg = 0x1397 0x100;
clocks = clock CLK_I2S2;
clock-names = iis;
+   #clock-cells = 1;
+   clock-output-names = i2s_cdclk2;
dmas = pdma0 14, pdma0 13;
dma-names = tx, rx;
status = disabled;
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi 
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 3fbf588..c26b9fb 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -7,6 +7,7 @@
  * published by the Free Software Foundation.
 */

+#include dt-bindings/sound/samsung-i2s.h
 #include dt-bindings/input/input.h
 #include exynos4412.dtsi

@@ -37,8 +38,9 @@
pinctrl-names = default;
status = okay;
clocks = clock_audss EXYNOS_I2S_BUS,
-clock_audss EXYNOS_DOUT_AUD_BUS;
-   clock-names = iis, i2s_opclk0;
+clock_audss EXYNOS_DOUT_AUD_BUS,
+clock_audss EXYNOS_SCLK_I2S;
+   clock-names = iis, i2s_opclk0, i2s_opclk1;
};

sound: sound {
@@ -373,6 +375,8 @@
reg = 0x10;
interrupt-parent = gpx0;
interrupts = 0 0;
+   clocks = i2s0 CLK_I2S_CDCLK;
+   clock-names = mclk;
};
};

--
1.7.9.5

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[RESEND PATCH V3 15/15] ARM: dts: Fix I2S1, I2S2 compatible for exynos4 SoCs

[Sylwester Nawrocki]

I2S1, I2S2 on Exynos4 SoC series have limited functionality compared
to I2S0, samsung,s3c6410-i2s compatible should be used for them.

Cc: sta...@vger.kernel.org
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
 arch/arm/boot/dts/exynos4.dtsi |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 0cffe39..cb60010 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -371,7 +371,7 @@
};

i2s1: i2s@1396 {
-   compatible = samsung,s5pv210-i2s;
+   compatible = samsung,s3c6410-i2s;
reg = 0x1396 0x100;
clocks = clock CLK_I2S1;
clock-names = iis;
@@ -384,7 +384,7 @@
};

i2s2: i2s@1397 {
-   compatible = samsung,s5pv210-i2s;
+   compatible = samsung,s3c6410-i2s;
reg = 0x1397 0x100;
clocks = clock CLK_I2S2;
clock-names = iis;
--
1.7.9.5

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[RESEND PATCH V3 14/15] ARM: dts: Switch Odroid X2/U2 to simple-audio-card

[Sylwester Nawrocki]

Now when the CDCLK I2S output clock can be handled through the clock
API the Odroid X2/U3 can be switched to the simple-audio-card DT binding.

Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
 arch/arm/boot/dts/exynos4.dtsi  |3 +++
 arch/arm/boot/dts/exynos4412-odroid-common.dtsi |   19 ---
 arch/arm/boot/dts/exynos4412-odroidu3.dts   |8 +---
 arch/arm/boot/dts/exynos4412-odroidx2.dts   |8 ++--
 4 files changed, 30 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 38d8f68..0cffe39 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -66,6 +66,7 @@
dmas = pdma0 12, pdma0 11, pdma0 10;
dma-names = tx, rx, tx-sec;
samsung,idma-addr = 0x0300;
+   #sound-dai-cells = 1;
status = disabled;
};

@@ -378,6 +379,7 @@
clock-output-names = i2s_cdclk1;
dmas = pdma1 12, pdma1 11;
dma-names = tx, rx;
+   #sound-dai-cells = 1;
status = disabled;
};

@@ -390,6 +392,7 @@
clock-output-names = i2s_cdclk2;
dmas = pdma0 14, pdma0 13;
dma-names = tx, rx;
+   #sound-dai-cells = 1;
status = disabled;
};

diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi 
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index c26b9fb..abd6336 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -44,9 +44,7 @@
};

sound: sound {
-   compatible = samsung,odroidx2-audio;
-   samsung,i2s-controller = i2s0;
-   samsung,audio-codec = max98090;
+   compatible = simple-audio-card;
assigned-clocks = clock_audss EXYNOS_MOUT_AUDSS,
clock_audss EXYNOS_MOUT_I2S,
clock_audss EXYNOS_DOUT_SRP,
@@ -57,6 +55,20 @@
0,
19200,
1920;
+
+   simple-audio-card,format = i2s;
+   simple-audio-card,bitclock-master = link0_codec;
+   simple-audio-card,frame-master = link0_codec;
+
+   simple-audio-card,cpu {
+   sound-dai = i2s0 0;
+   system-clock-frequency = 1920;
+   };
+
+   link0_codec: simple-audio-card,codec {
+   sound-dai = max98090;
+   clocks = i2s0 CLK_I2S_CDCLK;
+   };
};

mmc@1255 {
@@ -377,6 +389,7 @@
interrupts = 0 0;
clocks = i2s0 CLK_I2S_CDCLK;
clock-names = mclk;
+   #sound-dai-cells = 0;
};
};

diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts 
b/arch/arm/boot/dts/exynos4412-odroidu3.dts
index c8a64be..44684e5 100644
--- a/arch/arm/boot/dts/exynos4412-odroidu3.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts
@@ -49,9 +49,11 @@
 };

 sound {
-   compatible = samsung,odroidu3-audio;
-   samsung,model = Odroid-U3;
-   samsung,audio-routing =
+   simple-audio-card,name = Odroid-U3;
+   simple-audio-card,widgets =
+   Headphone, Headphone Jack,
+   Speakers, Speakers;
+   simple-audio-card,routing =
Headphone Jack, HPL,
Headphone Jack, HPR,
Headphone Jack, MICBIAS,
diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts 
b/arch/arm/boot/dts/exynos4412-odroidx2.dts
index 96b43f4..6e33678 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx2.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx2.dts
@@ -23,8 +23,12 @@
 };

 sound {
-   samsung,model = Odroid-X2;
-   samsung,audio-routing =
+   simple-audio-card,name = Odroid-X2;
+   simple-audio-card,widgets =
+   Headphone, Headphone Jack,
+   Microphone, Mic Jack,
+   Microphone, DMIC;
+   simple-audio-card,routing =
Headphone Jack, HPL,
Headphone Jack, HPR,
IN1, Mic Jack,
--
1.7.9.5

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Re: [PATCH V3 13/15] ARM: dts: Exynos4 and Odroid X2/U3 sound device nodes update

[Sylwester Nawrocki]

On 03/02/15 05:27, Kukjin Kim wrote:
 Mark Brown wrote:
 On Wed, Jan 14, 2015 at 07:42:40PM +0100, Sylwester Nawrocki wrote:
 Clock related properties are added to the Exynos4 I2S device nodes
 so they can be referred to as clock providers. Missing i2s_opclk1
 clock is added to the I2S0 node and clock properties are added
 to the MAX98090 codec node to allow it to control/read frequency
 of the MCLK clock directly.

 Sorry, I should've said - I applied the ASoC patches, not these.
 
 Shall I take 13 to 15 DT patches in Samsung tree?

Patches 13, 14 use macro definitions which are added in patch which is
already in Mark's sound tree (ASoC: samsung: i2s: Add clk provider DT
binding documentation) [1]. We would need to consider that to avoid
build breaks.

--
Thanks,
Sylwester

[1]
https://git.kernel.org/cgit/linux/kernel/git/broonie/sound.git/commit/?h=for-nextid=0d40c61279510b8ce2368e1c6adcc2c4dc1af279

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Re: [PATCH v4 01/13] clk: samsung: exynos5433: Add binding document for Exynos5433 clock domains

[Sylwester Nawrocki]

Hi Chanwoo,

On 02/02/15 14:01, Chanwoo Choi wrote:
 This patch adds devicetree binding document for Exynos5433 SoC system clock
 controller.
 
 Cc: Sylwester Nawrocki s.nawro...@samsung.com
 Cc: Tomasz Figa tomasz.f...@gmail.com
 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
 Acked-by: Inki Dae inki@samsung.com
 ---
  .../devicetree/bindings/clock/exynos5433-clock.txt | 258 
 +
  1 file changed, 258 insertions(+)
  create mode 100644 
 Documentation/devicetree/bindings/clock/exynos5433-clock.txt
 
 diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt 
 b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
 new file mode 100644
 index 000..2d7a723
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
 @@ -0,0 +1,258 @@
 +* Samsung Exynos5433 CMU (Clock Management Units)
 +
 +The Exynos5433 clock controller generates and supplies clock to various
 +controllers within the Exynos5433 SoC.
 +
 +Required Properties:
 +
 +- compatible: should be one of the following.
 +  - samsung,exynos5433-cmu-top   - clock controller compatible for CMU_TOP
 +which generates clocks for 
 IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
 +domains and bus clocks.
 +  - samsung,exynos5433-cmu-cpif  - clock controller compatible for CMU_CPIF
 +which generates clocks for LLI (Low Latency Interface) IP.
 +  - samsung,exynos5433-cmu-mif   - clock controller compatible for CMU_MIF
 +which generates clocks for DRAM Memory Controller domain.
 +  - samsung,exynos5433-cmu-peric - clock controller compatible for 
 CMU_PERIC
 +which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
 +  - samsung,exynos5433-cmu-peris - clock controller compatible for 
 CMU_PERIS
 +which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
 +  - samsung,exynos5433-cmu-fsys  - clock controller compatible for CMU_FSYS
 +which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
 +  - samsung,exynos5433-cmu-g2d   - clock controller compatible for CMU_G2D
 +which generates clocks for G2D/MDMA IPs.
 +  - samsung,exynos5433-cmu-disp  - clock controller compatible for CMU_DISP
 +which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
 +  - samsung,exynos5433-cmu-aud   - clock controller compatible for CMU_AUD
 +which generates clocks for Cortex-A5/BUS/AUDIO clocks.
 +  - samsung,exynos5433-cmu-bus0, samsung,exynos5433-cmu-bus1
 +and samsung,exynos5433-cmu-bus2 - clock controller compatible for 
 CMU_BUS
 +which generates global data buses clock and global peripheral buses 
 clock.
 +  - samsung,exynos5433-cmu-g3d  - clock controller compatible for CMU_G3D
 +which generates clocks for 3D Graphics Engine IP.
 +  - samsung,exynos5433-cmu-gscl  - clock controller compatible for CMU_GSCL
 +which generates clocks for GSCALER IPs.
 +
 +- reg: physical base address of the controller and length of memory mapped
 +  region.
 +
 +- #clock-cells: should be 1.

Thanks for addressing my comments! It looks almost good enough, can you
just please also add clocks, clock-names to the list of required properties ?
I guess it's sufficient to mention that these properties should contain
values as listed in the examples below per each CMU.
This also applies to you following series of 9 patches.

 +
 +Each clock is assigned an identifier and client nodes can use this identifier
 +to specify the clock which they consume.
 +
 +All available clocks are defined as preprocessor macros in
 +dt-bindings/clock/exynos5433.h header and can be used in device
 +tree sources.
 +
 +Example 1: Examples of 'oscclk' source clock node are listed below.
 +
 + xxti: xxti {
 + compatible = fixed-clock;
 + clock-output-names = oscclk;
 + #clock-cells = 0;
 + };
 +
 +Example 2: Examples of clock controller nodes are listed below.
 +
 + cmu_top: clock-controller@0x1003 {
 + compatible = samsung,exynos5433-cmu-top;
 + reg = 0x1003 0x0c04;
 + #clock-cells = 1;
 +
 + clock-names = oscclk,
 + sclk_mphy_pll,
 + sclk_mfc_pll,
 + sclk_bus_pll;
 + clocks = xxti,
 +cmu_cpif CLK_SCLK_MPHY_PLL,
 +cmu_mif CLK_SCLK_MFC_PLL,
 +cmu_mif CLK_SCLK_BUS_PLL;
 + };

 + cmu_gscl: clock-controller@0x13cf {
 + compatible = samsung,exynos5433-cmu-gscl;
 + reg = 0x13cf 0x0b10;
 + #clock-cells = 1;
 +
 + clock-names = oscclk,
 + aclk_gscl_111,
 + aclk_gscl_333;
 + clocks = xxti,
 + cmu_top CLK_ACLK_GSCL_111,
 + cmu_top CLK_ACLK_GSCL_333;
 + };
 +
 +Example 3: UART controller node that consumes the clock generated by the 
 clock
 +controller.
 +
 + serial_0: serial

Re: [PATCH 2/2] ARM: dts: Add syscon phandle to the video-phy node for Exynos4

[Sylwester Nawrocki]

Hi Kukjin,

On 16/01/15 18:30, Sylwester Nawrocki wrote:
 This is required to fix regression after introducing the PMU device
 nodes required for the PMU driver modified in commit
 14fc8b93d47323561edf5d482d4a4b3ee1b90286
 (ARM: EXYNOS: Add platform driver support for Exynos PMU).
 This change is needed to make MIPI DSI displays and MIPI CSI-2
 camera sensors working again on Exynos4 boards.
 
 Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
 ---
  arch/arm/boot/dts/exynos4.dtsi |1 +
  1 file changed, 1 insertion(+)
 
 diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
 index b8168f1..250ee50 100644
 --- a/arch/arm/boot/dts/exynos4.dtsi
 +++ b/arch/arm/boot/dts/exynos4.dtsi
 @@ -76,6 +76,7 @@
   compatible = samsung,s5pv210-mipi-video-phy;
   reg = 0x10020710 8;
   #phy-cells = 1;
 + syscon = pmu_system_controller;
   };
  
   pd_mfc: mfc-power-domain@10023C40 {

I'd like to remind you about a few pending dts patches I send to you, except
the above one there are:

[PATCH V3 15/15] ARM: dts: Fix I2S1, I2S2 compatible for exynos4 SoCs
[PATCH] ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for Trats2
[PATCH] ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi
 
and

[PATCH v2 14/16] ARM: dts: Exynos4 and Odroid X2/U3 sound device nodes update

but this one depends on ASoC patch:
[PATCH V3 11/15] ASoC: samsung: i2s: Add clk provider DT binding documentation

hence it could be probably merged only after 3.20-rc1 release. 

--
Thanks,
Sylwester
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Re: [PATCH v4 01/13] clk: samsung: exynos5433: Add binding document for Exynos5433 clock domains

[Sylwester Nawrocki]

On 02/02/15 15:08, Chanwoo Choi wrote:

 OK, I'll add more following information:
 I'll send only patch1 with following information.
 
 + - clocks: list of clock identifiers which are fed as the input to
 +   the given clock controller. Please refer the next section to
 +   find the input clocks for a given controller.
 + - clock-names: list of names of clocks which are fed as the input
 +   to the given clock controller.
 +

Perhaps:

+ - clocks: list of the clock controller input clock identifiers,
from common clock bindings. Please refer the next section
to find the input clocks for a given controller.

+- clock-names: list of the clock controller input clock names,
as described in clock-bindings.txt.

?
It's fine to resend just updated first patch from each series.

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Re: [PATCH v4 01/13] clk: samsung: exynos5433: Add binding document for Exynos5433 clock domains

[Sylwester Nawrocki]

Hi Chanwoo,

On 02/02/15 16:51, Chanwoo Choi wrote:
 On Mon, Feb 2, 2015 at 11:40 PM, Sylwester Nawrocki
 s.nawro...@samsung.com wrote:
  On 02/02/15 15:08, Chanwoo Choi wrote:
 
  OK, I'll add more following information:
  I'll send only patch1 with following information.
 
  + - clocks: list of clock identifiers which are fed as the input to
  +   the given clock controller. Please refer the next section to
  +   find the input clocks for a given controller.
  + - clock-names: list of names of clocks which are fed as the input
  +   to the given clock controller.
  +
 
  Perhaps:
 
  + - clocks: list of the clock controller input clock identifiers,
  from common clock bindings. Please refer the next section
  to find the input clocks for a given controller.
 
  +- clock-names: list of the clock controller input clock names,
  as described in clock-bindings.txt.
 
  ?
  It's fine to resend just updated first patch from each series.
 OK,
 I'll modify the comment of 'clocks' and 'clock-names' and send only first 
 patch.
 
 I have a question. Do you prefer to add the list of input clocks for
 each clock domain as following?
 Or it is not necessary?
 
+   Input clocks for top clock controller:
+   - oscclk
+   - sclk_mphy_pll
+   - sclk_mfc_pll
+   - sclk_bus_pll

We are supposed to document all required input clocks somehow, I would
keep the list in such form. The (example) cmu nodes are also a good
documentation IMHO, they also show clearly which cmu (block) given clock
is sourced from.

--
Thanks,
Sylwester
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Re: [PATCH v3 01/12] clk: samsung: exynos5433: Add clocks using common clock framework

[Sylwester Nawrocki]

Hi Chanwoo,

On 29/01/15 00:38, Chanwoo Choi wrote:
...

 Right. current samsung clock drivers cannot show the hierarchy among clock
 domains in DT.

 IOW, there is currently
 no way to ensure proper registration order of the CMUs (clock domains).
 This may be important in some cases.

 To address this we could either add clocks/clock-names properties in
 respective CMU device nodes, pointing to any clocks in other CMU(s) or
 make a single device node for the whole clock controller, with an
 aggregated reg entry, e.g.

  cmu: clock-controller@0x1003 {
compatible = samsung,exynos5433-cmu;
reg =   0x1003 0x0c04,
0x10fc 0x0c04,
0x105b 0x100c,
0x14c8 0x0b08,
0x1004 0x0b20,
0x156e 0x0b04,
...
reg-names = top, cpif, mif, peric, peris, fsys...
#clock-cells = 1;
  };

 If you make a single device node to support various clock domain,
 How are you indicate the specific clock in some clock domain?

 This might be an issue, we would need to make all the clk indexes a one
 contiguous set.

 Exynos5433 has a whole lot of clocks against Exynos4 series clocks.
 So, if make all the clocks in the same set, I wonder making too huge set.
 It may cause the complicated code to find the proper clock or to analyze
 the clock driver.

 I'm wondering if there is really any use of having such
 information expressed explicitly in DT, or it would just make the DT
 binding closer resembling the SoC's documentation ?

 If we show the hierarchy or dependency between clock domains,
 I think we should modify structure samsung_clk_provider
 to include dependency information between clock domains.
 (It is just my opinion, this opinion could be not proper solution.)

As your patches stand currently there is no need to do anything else
in the driver, since the clock dependencies are specified by static
clock names in each clk domain provider.
We could just leave the multiple nodes, one per each clk domain and if
we specified parent clocks to each clk domain the clk providers would
be registered in proper order, since clk core would take care of it.

 Because when we use the common clk framework without adding
 any dependency information between clock domains, it is well working.

Yes it works currently, but if you try to get/set rate of a clock supplied
by a clk domain A right after this domain is registered, and domain B which
provides clocks to domain A is not yet registered the clk rate will be
incorrect.
We are currently not seeing any issues only because our use cases are
limited.

 Similarly, the clock controller is divided into subdomains in older SoCs,
 like exynos4, yet we do not create separate device nodes for each domain.
 Is reference to each individual clock domain required in any other SoC's
 part in case of exynos5433 ?

 There is a difference between exynos4 cmu and exynos5433 cmu.
 exynos4. As I knew, Exynos4 series have the one more clock domain.
 But, there are not any IPs between clock domains. We can check it as 
 following
 read base address and scope.

 The base address and range of Exynos4412 clock domain :
 - 0x1003_ ~ 0x1003_CA08
 - 0x1004_ ~ 0x1004_8B0C

 But, the clock domain in base address map of exynos5433 is located
 in non-continuous range. Also, there are un-related IPs to clocks.
 (e.g., mct 101c_, gic 1100_1000, serial0 14c1_, pinctrl 1058_ 
 ...)
 If we make the one dt node for clock domains like exynos4,
 I think it may cause the possible issue that clock drivers may access
 the un-related memory-mapped region.

 The base address and range of Exynos5433 clock domain :
 - top domain: 0x1003_ ~ 0x1003_0c04
 - cpif domain   : 0x10fc_ ~ 0x10fc_0x0c04
 - mif domain: 0x105b_ ~ 0x105b_0x100c
 - peric domain : 0x14c8_ ~ 0x14c8_0b08
 - peris domain  : 0x1004_ ~ 0x1004_0x0b20
 - fsys domain   : 0x156e_ ~ 0x156e_0b04

For reason Tomasz mentioned it may be indeed better to model each clk
domain as separate node.  In order to, for example make it easier to
handle dependencies between clk domain and power domain.

The register region specified by reg property of course doesn't have to be
contiguous, each offset/size tuple from reg will be just mapped separately
in the driver.  So there can be gaps (including regions of other IP blocks)
between the clock controller blocks registers memory regions.

 For example,
 The serial dt node in exynos7.dtsi. serial_0 dt node use the uart clocks
 in 'clock_peric0' clock domain and serial_1 dt node use the uart clocks
 in 'clock-peric1' clock domain.

 When using the clock in specific clock domain,
 we need to phandle(e.g., clock_peric0, clock_peric1) of clock domain.

   serial_0: serial@1363 {
   compatible = samsung,exynos4210-uart;
   reg = 0x1363 0x100;
   interrupts = 0 440 0;
   clocks = clock_peric0 

Re: [PATCH v3 01/12] clk: samsung: exynos5433: Add clocks using common clock framework

[Sylwester Nawrocki]

Hi Chanwoo,

On 23/01/15 21:54, Chanwoo Choi wrote:
 On Sat, Jan 24, 2015 at 2:40 AM, Sylwester Nawrocki
 s.nawro...@samsung.com wrote:
 On 21/01/15 07:26, Chanwoo Choi wrote:
 +/* list of all parent clock list */

 +PNAME(mout_bus_pll_user_p)   = { fin_pll, sclk_bus_pll, };
 ...
 +
 +static struct samsung_mux_clock top_mux_clks[] __initdata = {

 + MUX(CLK_MOUT_BUS_PLL_USER, mout_bus_pll_user, mout_bus_pll_user_p,
 + MUX_SEL_TOP1, 0, 1),
 ...
 +};
 +
 +static struct samsung_div_clock top_div_clks[] __initdata = {
 ...
 + /* DIV_TOP3 */
 + DIV(CLK_DIV_ACLK_IMEM_SSSX_266, div_aclk_imem_sssx_266,
 + mout_bus_pll_user, DIV_TOP3, 24, 3),

 Shouldn't fin_pll be renamed to oscclk ? In the documentation
 the root clock (from XXTI input pin) seems to be referred as OSCCLK.
 And I can't see fin_pll clock registered anywhere. Shouldn't there
 be a fixed-rate-clock as a parent of at least CMU_TOP? e.g.
 
 Right,
 I added fin_pll fixed clock in DT as following:
 When I registered fin_pll fixed clock, I could use fin_pll clock
 for exynos5433 cmu without adding additional dt node.
 
 fin_pll: xxti {
 compatible = fixed-clock;
 clock-output-names = fin_pll;
 #clock-cells = 0;
 };
 
 I'll add the example of fin_pll dt node to documentation for exynos5433 cmu.

OK, thanks. But I think it needs to be named oscclk, FIN_PLL is almost
not existent in the SoC's documentation.
I'd suggest to define the root oscillator clock (XXTI/OSCCLK) as oscclk
in DT, rather than registering fin_pll fixed clock in the driver.

 xxti: xxti {
 compatible = fixed-clock;
 #clock-cells = 0;
 clock-output-names = oscclk;
 clock-frequency = 2400;
 };

 cmu_top {
 clocks = xxti;
 };

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Sylwester
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[GIT PULL] clk/samsung updates for v3.20

[Sylwester Nawrocki]

Hi Mike,

The following changes since commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672:

  Linux 3.19-rc1 (2014-12-20 17:08:50 -0800)

are available in the git repository at:

  git://linuxtv.org/snawrocki/samsung.git tags/v3.20-exynos-clk

for you to fetch changes up to e64fb42da4c6c713cfc7cad607e97e0773fa41ff:

  clk: samsung: exynos4: Add divider clock id for memory bus frequency
(2015-01-28 15:51:17 +0100)


Exynos 3250, 4415 drivers cleanup by using common code
and addition of clock definitions for DVFS on Exynos4.



It's just couple mostly cleanup patches this time, we have a clk driver
for exynos5433 pending yet but I'll likely send it after the coming merge
window.

Chanwoo Choi (4):
  clk: samsung: Change the return value of samsung_cmu_register_one()
  clk: samsung: exynos3250: Use samsung_cmu_register_one() to simplify code
  clk: samsung: exynos4415: Use samsung_cmu_register_one() to simplify code
  clk: samsung: exynos4: Add divider clock id for memory bus frequency

 drivers/clk/samsung/clk-exynos3250.c |  217 --
 drivers/clk/samsung/clk-exynos4.c|   10 +-
 drivers/clk/samsung/clk-exynos4415.c |  216 -
 drivers/clk/samsung/clk.c|   13 +-
 drivers/clk/samsung/clk.h|3 +-
 include/dt-bindings/clock/exynos4.h  |7 +-
 6 files changed, 118 insertions(+), 348 deletions(-)

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Sylwester
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Re: [alsa-devel] [PATCH v4 1/3] ASoC: samsung: Add machine driver for Trats2

[Sylwester Nawrocki]

On 23/01/15 06:03, Inha Song wrote:
 +static int trats2_aif1_startup(struct snd_pcm_substream *substream)
 +{
 + struct snd_soc_pcm_runtime *rtd = substream-private_data;
 + struct trats2_machine_priv *priv = snd_soc_card_get_drvdata(rtd-card);
 + int ret;
 +
 + ret = clk_prepare_enable(priv-clk_mclk);
 + if (ret) {
 + dev_err(rtd-card-dev, Failed to enable mclk: %d\n, ret);
 + return ret;
 + }
 +
 + return 0;
 +}
 +
 +static void trats2_aif1_shutdown(struct snd_pcm_substream *substream)
 +{
 + struct snd_soc_pcm_runtime *rtd = substream-private_data;
 + struct trats2_machine_priv *priv = snd_soc_card_get_drvdata(rtd-card);
 +
 + clk_disable_unprepare(priv-clk_mclk);
 +}
 +
 +static const struct snd_soc_ops trats2_aif1_ops = {
 + .startup = trats2_aif1_startup,
 + .shutdown = trats2_aif1_shutdown,
 + .hw_params = trats2_aif1_hw_params,
 +};

 +static int trats2_audio_probe(struct platform_device *pdev)
 +{

 + priv-clk_mclk =  of_clk_get_by_name(codec_node, MCLK1);
 + if (IS_ERR(priv-clk_mclk)) {
 + dev_err(pdev-dev, Failed to get mclk clock\n);
 + of_node_put(codec_node);
 + return PTR_ERR(priv-clk_mclk);
 + }

Wouldn't it also work if we added clock handling into the wm8994 codec
driver instead? Not sure if it is correct to retrieve the codec's clock
in the machine driver like this. Or perhaps the MCLK1 (SoC CLKOUT) clock
should be added to the sound DT node and handled only by the machine
driver, together with the other (MCLK2) clock?

 + of_node_put(codec_node);

--
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Sylwester
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Re: [PATCH v3 01/12] clk: samsung: exynos5433: Add clocks using common clock framework

[Sylwester Nawrocki]

On 21/01/15 07:26, Chanwoo Choi wrote:
 +/* list of all parent clock list */

 +PNAME(mout_bus_pll_user_p)   = { fin_pll, sclk_bus_pll, };
...
 +
 +static struct samsung_mux_clock top_mux_clks[] __initdata = {

 + MUX(CLK_MOUT_BUS_PLL_USER, mout_bus_pll_user, mout_bus_pll_user_p,
 + MUX_SEL_TOP1, 0, 1),
...
 +};
 +
 +static struct samsung_div_clock top_div_clks[] __initdata = {
...
 + /* DIV_TOP3 */
 + DIV(CLK_DIV_ACLK_IMEM_SSSX_266, div_aclk_imem_sssx_266,
 + mout_bus_pll_user, DIV_TOP3, 24, 3),

Shouldn't fin_pll be renamed to oscclk ? In the documentation
the root clock (from XXTI input pin) seems to be referred as OSCCLK.
And I can't see fin_pll clock registered anywhere. Shouldn't there
be a fixed-rate-clock as a parent of at least CMU_TOP? e.g.

xxti: xxti {
compatible = fixed-clock;
#clock-cells = 0;
clock-output-names = oscclk;
clock-frequency = 2400;
};

cmu_top {
clocks = xxti;
};

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Re: [alsa-devel] [PATCH v4 3/3] ARM: dts: Add sound nodes for exynos4412-trats2

[Sylwester Nawrocki]

On 23/01/15 06:03, Inha Song wrote:
 This patch add WM1811 audio codec, I2S interface and the sound
 machine nodes to enable audio on exynos4412-trats2 board.
 
 Signed-off-by: Inha Song ideal.s...@samsung.com

Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com

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Re: [alsa-devel] [PATCH v4 2/3] ASoC: samsung: Document Trats2 audio subsystem bindings

[Sylwester Nawrocki]

On 23/01/15 06:03, Inha Song wrote:
 This patch add Trats2 audio subsystem bindings document.
 
 Signed-off-by: Inha Song ideal.s...@samsung.com

Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com

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Re: [alsa-devel] [PATCH v3 2/4] ASoC: samsung: Document Trats2 audio subsystem bindings

[Sylwester Nawrocki]

On 22/01/15 12:18, Inha Song wrote:
 This patch add Trats2 audio subsystem bindings document.
 
 Signed-off-by: Inha Song ideal.s...@samsung.com

Acked-by: Sylwester Nawrocki s.nawro...@samsung.com
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Re: [alsa-devel] [PATCH v3 3/4] ARM: dts: set clock out parent to XUSBXTI

[Sylwester Nawrocki]

On 22/01/15 12:18, Inha Song wrote:
 This patch set clock out parent to XUSBXTI.
 
 Signed-off-by: Inha Song ideal.s...@samsung.com
 ---
  arch/arm/boot/dts/exynos4.dtsi | 2 ++
  1 file changed, 2 insertions(+)
 
 diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
 index b8168f1..020bbaf 100644
 --- a/arch/arm/boot/dts/exynos4.dtsi
 +++ b/arch/arm/boot/dts/exynos4.dtsi
 @@ -141,6 +141,8 @@
   pmu_system_controller: system-controller@1002 {
   compatible = samsung,exynos4210-pmu, syscon;
   reg = 0x1002 0x4000;
 + assigned-clocks = pmu_system_controller 0;
 + assigned-clock-parents =  clock CLK_XUSBXTI;
   };

Looks good, except it needs to be done only for the Trats2 board, i.e.
the PMU device node including these properties should be added to
exynos4412-trats2.dts.  I think it's fine to make it a one patch including
all dts changes.


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Re: [alsa-devel] [PATCH v3 1/4] ASoC: samsung: Add machine driver for Trats2

[Sylwester Nawrocki]

On 22/01/15 12:17, Inha Song wrote:
 diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
 index fc67f97..8031423 100644
 --- a/sound/soc/samsung/Kconfig
 +++ b/sound/soc/samsung/Kconfig
 @@ -245,3 +245,11 @@ config SND_SOC_ARNDALE_RT5631_ALC5631
  depends on SND_SOC_SAMSUNG
  select SND_SAMSUNG_I2S
  select SND_SOC_RT5631
 +
 +config SND_SOC_SAMSUNG_TRATS2_WM1811
 + tristate SoC I2S Audio support for WM1811 on Tizen Trats2 board
 + depends on SND_SOC_SAMSUNG
 + select SND_SOC_WM8994
 + select SND_SAMSUNG_I2S

Shouldn't you also select the MFD part of WM8994 here ?

 +++ b/sound/soc/samsung/trats2_wm1811.c
 @@ -0,0 +1,218 @@

 +static struct snd_soc_dai_link trats2_dai[] = {
 + {
 + .name   = WM1811 AIF1,
 + .stream_name= Pri_Dai,

Could we have a less cryptic name here, e.g. HiFi Primary ?

 + .codec_dai_name = wm8994-aif1,
 + .codec_name = wm8994-codec,
 + .ops= trats2_aif1_ops,
 + .dai_fmt= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
 +   SND_SOC_DAIFMT_CBM_CFM,
 + },
 +};

 +static int trats2_audio_probe(struct platform_device *pdev)
 +{
 + struct device_node *np = pdev-dev.of_node;
 + struct snd_soc_card *card = trats2_card;
 + struct device_node *codec_node;
 + struct snd_soc_dai_link *dai_link = card-dai_link;
 + struct trats2_machine_priv *priv = snd_soc_card_get_drvdata(card);
 + int ret;
 +
 + if (!np) {
 + dev_err(pdev-dev, of node is missing.\n);
 + return -ENODEV;

I'd say this whole np test could be dropped, we will fail right below
at the snd_soc_of_parse_card_name() function call if np is NULL.
Such a situation seems highly unlikely anyway.

 + }
 +
 + card-dev = pdev-dev;
 +
 + ret = snd_soc_of_parse_card_name(card, samsung,model);
 + if (ret) {
 + dev_err(pdev-dev,
 + Card name is not provided\n);

I guess it would fit in a single line.

 + return ret;
 + }
 +

 +static struct platform_driver trats2_audio_driver = {
 + .driver = {
 + .name   = trats2-audio,
 + .owner  = THIS_MODULE,

You can drop this .owner field assignment, it's also done in
module_platform_driver() macro.

 + .pm = snd_soc_pm_ops,
 + .of_match_table = trats2_audio_of_match,
 + },
 + .probe  = trats2_audio_probe,
 + .remove = trats2_audio_remove,
 +};
 +
 +module_platform_driver(trats2_audio_driver);

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Re: [PATCH v3 01/12] clk: samsung: exynos5433: Add clocks using common clock framework

[Sylwester Nawrocki]

Hi Chanwoo,

On 21/01/15 07:26, Chanwoo Choi wrote:
 This patch adds the support for CMU (Clock Management Units) of Exynos5433
 which is 64bit SoC and has Octa-cores. This patch supports necessary clocks
 (PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation
 for Exynos5433 clock controller.

 diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt 
 b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
 new file mode 100644
 index 000..72cd0ba
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
 @@ -0,0 +1,106 @@
 +* Samsung Exynos5433 CMU (Clock Management Units)
 +
 +The Exynos5433 clock controller generates and supplies clock to various
 +controllers within the Exynos5433 SoC.
 +
 +Required Properties:
 +
 +- compatible: should be one of the following.
 +  - samsung,exynos5433-cmu-top   - clock controller compatible for CMU_TOP
 +which generates clocks for 
 IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
 +domains and bus clocks.
 +  - samsung,exynos5433-cmu-cpif  - clock controller compatible for CMU_CPIF
 +which generates clocks for LLI (Low Latency Interface) IP.
 +  - samsung,exynos5433-cmu-mif   - clock controller compatible for CMU_MIF
 +which generates clocks for DRAM Memory Controller domain.
 +  - samsung,exynos5433-cmu-peric - clock controller compatible for 
 CMU_PERIC
 +which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
 +  - samsung,exynos5433-cmu-peris - clock controller compatible for 
 CMU_PERIS
 +which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
 +  - samsung,exynos5433-cmu-fsys  - clock controller compatible for CMU_FSYS
 +which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
 +
 +- reg: physical base address of the controller and length of memory mapped
 +  region.
 +
 +- #clock-cells: should be 1.
 +
 +Each clock is assigned an identifier and client nodes can use this identifier
 +to specify the clock which they consume.
 +
 +All available clocks are defined as preprocessor macros in
 +dt-bindings/clock/exynos5433.h header and can be used in device
 +tree sources.
 +
 +Example 1: Examples of clock controller nodes are listed below.
 +
 + cmu_top: clock-controller@0x1003 {
 + compatible = samsung,exynos5433-cmu-top;
 + reg = 0x1003 0x0c04;
 + #clock-cells = 1;
 + };
 +
 + cmu_cpif: clock-controller@0x10fc {
 + compatible = samsung,exynos5433-cmu-cpif;
 + reg = 0x10fc 0x0c04;
 + #clock-cells = 1;
 + };
 +
 + cmu_mif: clock-controller@0x105b {
 + compatible = samsung,exynos5433-cmu-mif;
 + reg = 0x105b 0x100c;
 + #clock-cells = 1;
 + };
 +
 + cmu_peric: clock-controller@0x14c8 {
 + compatible = samsung,exynos5433-cmu-peric;
 + reg = 0x14c8 0x0b08;
 + #clock-cells = 1;
 + };
 +
 + cmu_peris: clock-controller@0x1004 {
 + compatible = samsung,exynos5433-cmu-peris;
 + reg = 0x1004 0x0b20;
 + #clock-cells = 1;
 + };
 +
 + cmu_fsys: clock-controller@0x156e {
 + compatible = samsung,exynos5433-cmu-fsys;
 + reg = 0x156e 0x0b04;
 + #clock-cells = 1;
 + };

What are the reasons to split the whole clock controller into separate
device nodes with different compatible strings like this? I doubt drivers
associated with each of those compatible strings could be ever reused on
different Exynos SoCs.

There are hardware dependencies between these clock domains, which are
not currently modelled in DT with your binding. IOW, there is currently
no way to ensure proper registration order of the CMUs (clock domains).
This may be important in some cases.

To address this we could either add clocks/clock-names properties in
respective CMU device nodes, pointing to any clocks in other CMU(s) or
make a single device node for the whole clock controller, with an
aggregated reg entry, e.g.

 cmu: clock-controller@0x1003 {
compatible = samsung,exynos5433-cmu;
reg =   0x1003 0x0c04,
0x10fc 0x0c04,
0x105b 0x100c,
0x14c8 0x0b08,
0x1004 0x0b20,
0x156e 0x0b04,
...
reg-names = top, cpif, mif, peric, peris, fsys...
#clock-cells = 1;
 };

Then we could modify samsung_cmu_register_one() function by adding
the reg entry index or name argument. What do you think ?

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Re: [alsa-devel] [PATCH v2 3/3] ARM: dts: Add sound nodes for exynos4412-trats2

[Sylwester Nawrocki]

Hi,

On 19/01/15 10:48, Inha Song wrote:
 --- a/arch/arm/boot/dts/exynos4412-trats2.dts
 +++ b/arch/arm/boot/dts/exynos4412-trats2.dts

 + sound {
 + compatible = samsung,trats2-audio;

 + assigned-clocks = pmu_system_controller 0;
 + assigned-clock-parents =  clock CLK_XUSBXTI;

How about putting these properties in the pmu_system_controller
node?  After all the mux clock being configured here belongs to
the PMU subsystem. Wouldn't it work that way ?

 + samsung,i2s-controller = i2s0;
 + samsung,model = Trats2;
 + samsung,audio-codec = wm1811;
 + samsung,audio-routing =
 + SPK, SPKOUTLN,
 + SPK, SPKOUTLP,
 + SPK, SPKOUTRN,
 + SPK, SPKOUTRP;
 + };

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Re: [PATCH] ARM: dts: exynos5422-odroidxu3: add sound nodes

[Sylwester Nawrocki]

Hi,

On 21/01/15 06:58, Inha Song wrote:
 Add MAX98090 audio codec, I2S interface and the sound nodes to support
 audio on Odroid-XU3 board.
 
 Signed-off-by: Inha Song ideal.s...@samsung.com
 ---
  arch/arm/boot/dts/exynos5422-odroidxu3.dts | 34 
 ++
  1 file changed, 34 insertions(+)
 
 diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts 
 b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
 index 7874da2..79493d1 100644
 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
 +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
 @@ -310,6 +310,40 @@
   rtc@101E {
   status = okay;
   };
 +
 + sound: sound {
 + compatible = samsung,odroidu3-audio;

How about using simple-card instead ? I've been trying to switch
Odroid X2/U3 to simple card. Here a corresponding dts patch:
http://www.spinics.net/lists/linux-samsung-soc/msg41083.html
For that recent patches for the I2S driver which area already in -next
might be needed.

 + samsung,model = Odroid-XU3;
 + samsung,i2s-controller = i2s0;
 + samsung,audio-codec = max98090;
 + assigned-clocks = clock_audss EXYNOS_MOUT_AUDSS,
 +   clock_audss EXYNOS_MOUT_I2S;
 + assigned-clock-parents = clock CLK_FIN_PLL,
 + clock_audss EXYNOS_MOUT_AUDSS;
 + samsung,audio-routing =
 + Headphone Jack, HPL,
 + Headphone Jack, HPR,
 + Headphone Jack, MICBIAS,
 + IN1, Headphone Jack,
 + Speakers, SPKL,
 + Speakers, SPKR;
 + };
 +};
 +
 +hsi2c_5 {
 + status = okay;
 + max98090: max98090@10 {
 + compatible = maxim,max98090;
 + reg = 0x10;
 + interrupt-parent = gpx3;
 + interrupts = 2 0;
 + clocks = clock_audss EXYNOS_DOUT_AUD_BUS;
 + clock-names = mclk;
 + };
 +};

-- 
Thanks,
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Re: [PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain

[Sylwester Nawrocki]

Hi,

On 20/01/15 11:35, Javier Martinez Canillas wrote:
 When a power domain is powered off on Exynos5420 SoC, the input clocks of
 the devices attached to this power domain are re-parented to oscclk and
 restored to the original parent after powering on the power domain.
 
 So a reference to the input and parent clocks for the devices attached to
 a power domain are needed to be able to do the re-parenting. The DISP1 pd
 includes modules which uses the following clocks:
 
 ACLK_200_DISP1 (MIXER and HDMILINK)
 ACLK_300_DISP1 (FIMD1)
 ACLK_400_DISP1 (Internal Buses)
 
 Each of these clocks are generated as the output of a clock mux so add an
 ID for all of these clock muxes and their parents to be referenced in the
 DISP1 power domain device node.
 
 Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk

The patch looks OK to me, I'm fine with it being merged via Kukjin's tree
due to the dts dependencies (including other pending dts patches touching
the arch/arm/boot/dts/exynos5420.dtsi file).
I think we need also Mike ACK for that, I could also queue the patch for
the clk tree and create a topic branch, but merging both patches via
arm-soc seems a more sane option in this case.

Acked-by: Sylwester Nawrocki s.nawro...@samsung.com

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Re: [PATCH v4 4/9] clk: samsung: exynos4: Add divider clock id for memory bus frequency

[Sylwester Nawrocki]

On 15/01/15 02:50, Chanwoo Choi wrote:
 This patch adds the divider clock id for Exynos4 memory bus frequency.
 The clock id is used fo DVFS (Dynamic Voltage/Frequency Scaling)
 feature of exynos memory bus frequency.
 
 Cc: Sylwester Nawrocki s.nawro...@samsung.com
 Cc: Tomasz Figa tomasz.f...@gmail.com
 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com

I've queued this patch for the clk tree, please let me know if a topic
branch is needed.

--
Thanks,
Sylwester

  drivers/clk/samsung/clk-exynos4.c   | 10 +-
  include/dt-bindings/clock/exynos4.h |  7 ++-
  2 files changed, 11 insertions(+), 6 deletions(-)

 diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
 index 88e8c6b..51462e8 100644
 --- a/drivers/clk/samsung/clk-exynos4.c
 +++ b/drivers/clk/samsung/clk-exynos4.c
 @@ -703,12 +703,12 @@ static struct samsung_mux_clock exynos4x12_mux_clks[]
__initdata = {

  /* list of divider clocks supported in all exynos4 soc's */
  static struct samsung_div_clock exynos4_div_clks[] __initdata = {
 - DIV(0, div_gdl, mout_gdl, DIV_LEFTBUS, 0, 3),
 + DIV(CLK_DIV_GDL, div_gdl, mout_gdl, DIV_LEFTBUS, 0, 3),
   DIV(0, div_gpl, div_gdl, DIV_LEFTBUS, 4, 3),
   DIV(0, div_clkout_leftbus, mout_clkout_leftbus,
   CLKOUT_CMU_LEFTBUS, 8, 6),

 - DIV(0, div_gdr, mout_gdr, DIV_RIGHTBUS, 0, 3),
 + DIV(CLK_DIV_GDR, div_gdr, mout_gdr, DIV_RIGHTBUS, 0, 3),
   DIV(0, div_gpr, div_gdr, DIV_RIGHTBUS, 4, 3),
   DIV(0, div_clkout_rightbus, mout_clkout_rightbus,
   CLKOUT_CMU_RIGHTBUS, 8, 6),
 @@ -781,10 +781,10 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
   CLK_SET_RATE_PARENT, 0),
   DIV(0, div_clkout_top, mout_clkout_top, CLKOUT_CMU_TOP, 8, 6),

 - DIV(0, div_acp, mout_dmc_bus, DIV_DMC0, 0, 3),
 + DIV(CLK_DIV_ACP, div_acp, mout_dmc_bus, DIV_DMC0, 0, 3),
   DIV(0, div_acp_pclk, div_acp, DIV_DMC0, 4, 3),
   DIV(0, div_dphy, mout_dphy, DIV_DMC0, 8, 3),
 - DIV(0, div_dmc, mout_dmc_bus, DIV_DMC0, 12, 3),
 + DIV(CLK_DIV_DMC, div_dmc, mout_dmc_bus, DIV_DMC0, 12, 3),
   DIV(0, div_dmcd, div_dmc, DIV_DMC0, 16, 3),
   DIV(0, div_dmcp, div_dmcd, DIV_DMC0, 20, 3),
   DIV(0, div_pwi, mout_pwi, DIV_DMC1, 8, 4),
 @@ -829,7 +829,7 @@ static struct samsung_div_clock exynos4x12_div_clks[]
__initdata = {
   DIV_F(CLK_DIV_MCUISP1, div_mcuisp1, div_mcuisp0, E4X12_DIV_ISP1,
   8, 3, CLK_GET_RATE_NOCACHE, 0),
   DIV(CLK_SCLK_FIMG2D, sclk_fimg2d, mout_g2d, DIV_DMC1, 0, 4),
 - DIV(0, div_c2c, mout_c2c, DIV_DMC1, 4, 3),
 + DIV(CLK_DIV_C2C, div_c2c, mout_c2c, DIV_DMC1, 4, 3),
   DIV(0, div_c2c_aclk, div_c2c, DIV_DMC1, 12, 3),
  };

 diff --git a/include/dt-bindings/clock/exynos4.h
b/include/dt-bindings/clock/exynos4.h
 index 34fe28c..c4b1676 100644
 --- a/include/dt-bindings/clock/exynos4.h
 +++ b/include/dt-bindings/clock/exynos4.h
 @@ -262,8 +262,13 @@
  #define CLK_DIV_MCUISP1  453 /* Exynos4x12 only */
  #define CLK_DIV_ACLK200  454 /* Exynos4x12 only */
  #define CLK_DIV_ACLK400_MCUISP   455 /* Exynos4x12 only */
 +#define CLK_DIV_ACP  456
 +#define CLK_DIV_DMC  457
 +#define CLK_DIV_C2C  458 /* Exynos4x12 only */
 +#define CLK_DIV_GDL  459
 +#define CLK_DIV_GDR  460

  /* must be greater than maximal clock id */
 -#define CLK_NR_CLKS  456
 +#define CLK_NR_CLKS  461

  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
 -- 1.8.5.5
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Re: [PATCH V3 09/15] ASoC: samsung: i2s: Protect more registers with a spinlock

[Sylwester Nawrocki]

Hi Tuashar,

On 17/01/15 06:21, Tushar Behera wrote:
 On Thu, Jan 15, 2015 at 3:42 AM, Sylwester Nawrocki
 s.nawro...@samsung.com wrote:
 Ensure the I2SMOD, I2SPSR registers, which are also exposed through
 clk API are only accessed with the i2s-spinlock spinlock held.

 Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
 ---
  sound/soc/samsung/i2s.c |   81 
 +--
  1 file changed, 51 insertions(+), 30 deletions(-)

 diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
 index 20cc51f..05fc2f0 100644
 --- a/sound/soc/samsung/i2s.c
 +++ b/sound/soc/samsung/i2s.c
 @@ -472,17 +472,22 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai,
  {
 struct i2s_dai *i2s = to_info(dai);
 struct i2s_dai *other = get_other_dai(i2s);
 -   u32 mod = readl(i2s-addr + I2SMOD);
 const struct samsung_i2s_variant_regs *i2s_regs = i2s-variant_regs;
 unsigned int cdcon_mask = 1  i2s_regs-cdclkcon_off;
 unsigned int rsrc_mask = 1  i2s_regs-rclksrc_off;
 +   u32 mod, mask, val = 0;
 +
 +   spin_lock(i2s-lock);
 +   mod = readl(i2s-addr + I2SMOD);
 +   spin_unlock(i2s-lock);

 
 'mod' is now updated only at the bottom of this function. The above
 readl can be omitted.

mod is used in some of the 'if' statements below, so we must read it
here beforehand.

 switch (clk_id) {
 case SAMSUNG_I2S_OPCLK:
 -   mod = ~MOD_OPCLK_MASK;
 -   mod |= dir;
 +   mask = MOD_OPCLK_MASK;
 +   val = dir;
 break;
 case SAMSUNG_I2S_CDCLK:
 +   mask = 1  i2s_regs-cdclkcon_off;
 
 Use BIT() macro instead?

Yes, it would be a good code cleanup, might be worth to include it in
some future patch series. I'll keep it in mind, since this patch is merged
already.
And the logical bit operations is one of things people make mistakes most
often, so any changes like these would need to be well tested and/or
carefully reviewed.

--
Thanks,
Sylwester
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[GIT PULL] clk: more Exynos7 clock tree definitions

[Sylwester Nawrocki]

Hi Mike,

Please find below a few clk updates for exynos7 SoC. I kept them on
a separate branch as there will likely be depending dts patches.
Please pull for 3.20.

The following changes since commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672:

  Linux 3.19-rc1 (2014-12-20 17:08:50 -0800)

are available in the git repository at:

  git://linuxtv.org/snawrocki/samsung.git tags/for-v3.20-exynos7-clk

for you to fetch changes up to 9f930a39e135d370d17e7a1ab73ddebcfb896f98:

  clk: samsung: exynos7: add clocks for audio block (2015-01-15 15:18:51 +0100)


- Clock definitions for Exynos7 SoC peripheral devices:
  video scaler, USB, DMA, SPI and the audio subsystem.


Padmavathi Venna (3):
  clk: samsung: exynos7: add gate clock for DMA block
  clk: samsung: exynos7: add clocks for SPI block
  clk: samsung: exynos7: add clocks for audio block

Tony K Nadackal (1):
  clk: samsung: exynos7: Add clocks for MSCL block

Vivek Gautam (1):
  clk: samsung: exynos7: Add required clock tree for USB

 .../devicetree/bindings/clock/exynos7-clock.txt|   15 +
 drivers/clk/samsung/clk-exynos7.c  |  408 +++-
 include/dt-bindings/clock/exynos7-clk.h|   88 -
 3 files changed, 505 insertions(+), 6 deletions(-)

Thanks,
Sylwester
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Re: [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block

[Sylwester Nawrocki]

Hi,

On 15/01/15 06:49, Padma Venkat wrote:
 I posted patches after re-basing on your tree and after incorporating
 all comments from Vivek.
 Below is the link
 http://www.spinics.net/lists/linux-samsung-soc/msg40992.html
 
 Can you pick the patches?

Sure, I'm not forgetting it. I've updated the exynos7 branch with your
v2 patches.

Thanks!
Sylwester
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[PATCH V3 01/15] ASoC: samsung: i2s: samsung_i2s_get_driver_data() cleanup

[Sylwester Nawrocki]

Tidy up the samsung_i2s_get_driver_data() function by using
IS_ENABLE() instead of #ifdef and add missing braces for
the 'else' part. Also ensure we are not dereferencing NULL
'match' pointer.

Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
 sound/soc/samsung/i2s.c |9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 86491c9..e5473ee 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -1123,15 +1123,14 @@ static const struct of_device_id exynos_i2s_match[];
 static inline const struct samsung_i2s_dai_data *samsung_i2s_get_driver_data(
struct platform_device *pdev)
 {
-#ifdef CONFIG_OF
-   if (pdev-dev.of_node) {
+   if (IS_ENABLED(CONFIG_OF)  pdev-dev.of_node) {
const struct of_device_id *match;
match = of_match_node(exynos_i2s_match, pdev-dev.of_node);
-   return match-data;
-   } else
-#endif
+   return match ? match-data : NULL;
+   } else {
return (struct samsung_i2s_dai_data *)
platform_get_device_id(pdev)-driver_data;
+   }
 }
 
 #ifdef CONFIG_PM
-- 
1.7.9.5

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[PATCH V3 02/15] ASoC: samsung: i2s: Add return value checks in probe()

[Sylwester Nawrocki]

These functions may fail so let's properly report any errors.

Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
 sound/soc/samsung/i2s.c |   12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index e5473ee..aa52b41 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -1173,11 +1173,13 @@ static int samsung_i2s_probe(struct platform_device 
*pdev)
dev_err(pdev-dev, Unable to get drvdata\n);
return -EFAULT;
}
-   devm_snd_soc_register_component(sec_dai-pdev-dev,
+   ret = devm_snd_soc_register_component(sec_dai-pdev-dev,
samsung_i2s_component,
sec_dai-i2s_dai_drv, 1);
-   samsung_asoc_dma_platform_register(pdev-dev);
-   return 0;
+   if (ret != 0)
+   return ret;
+
+   return samsung_asoc_dma_platform_register(pdev-dev);
}
 
pri_dai = i2s_alloc_dai(pdev, false);
@@ -1290,7 +1292,9 @@ static int samsung_i2s_probe(struct platform_device *pdev)
 
pm_runtime_enable(pdev-dev);
 
-   samsung_asoc_dma_platform_register(pdev-dev);
+   ret = samsung_asoc_dma_platform_register(pdev-dev);
+   if (ret != 0)
+   return ret;
 
return 0;
 err:
-- 
1.7.9.5

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[PATCH V3 03/15] ASoC: samsung: i2s: Request memory region in driver probe()

[Sylwester Nawrocki]

The memory mapped registers region is common for both DAIs so request
it in the I2S platform device driver's probe for the platform device
corresponding to the primary DAI, rather than in the ASoC DAI's probe
callback. While at it switch to devm_ioremap_resource(). This also
drops the hard coded (0x100) register region size in the driver.

Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
 sound/soc/samsung/i2s.c |   45 +++--
 1 file changed, 7 insertions(+), 38 deletions(-)

diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index aa52b41..366b720 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -59,10 +59,8 @@ struct samsung_i2s_dai_data {
 struct i2s_dai {
/* Platform device for this DAI */
struct platform_device *pdev;
-   /* IOREMAP'd SFRs */
+   /* Memory mapped SFR region */
void __iomem*addr;
-   /* Physical base address of SFRs */
-   u32 base;
/* Rate of RCLK source clock */
unsigned long rclk_srcrate;
/* Frame Clock */
@@ -979,16 +977,9 @@ static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
goto probe_exit;
}
 
-   i2s-addr = ioremap(i2s-base, 0x100);
-   if (i2s-addr == NULL) {
-   dev_err(i2s-pdev-dev, cannot ioremap registers\n);
-   return -ENXIO;
-   }
-
i2s-clk = clk_get(i2s-pdev-dev, iis);
if (IS_ERR(i2s-clk)) {
dev_err(i2s-pdev-dev, failed to get i2s_clock\n);
-   iounmap(i2s-addr);
return PTR_ERR(i2s-clk);
}
 
@@ -1001,7 +992,6 @@ static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
samsung_asoc_init_dma_data(dai, i2s-dma_playback, i2s-dma_capture);
 
if (other) {
-   other-addr = i2s-addr;
other-clk = i2s-clk;
}
 
@@ -1043,8 +1033,6 @@ static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
 
clk_disable_unprepare(i2s-clk);
clk_put(i2s-clk);
-
-   iounmap(i2s-addr);
}
 
i2s-clk = NULL;
@@ -1162,7 +1150,6 @@ static int samsung_i2s_probe(struct platform_device *pdev)
u32 regs_base, quirks = 0, idma_addr = 0;
struct device_node *np = pdev-dev.of_node;
const struct samsung_i2s_dai_data *i2s_dai_data;
-   int ret = 0;
 
/* Call during Seconday interface registration */
i2s_dai_data = samsung_i2s_get_driver_data(pdev);
@@ -1229,16 +1216,10 @@ static int samsung_i2s_probe(struct platform_device 
*pdev)
}
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-   if (!res) {
-   dev_err(pdev-dev, Unable to get I2S SFR address\n);
-   return -ENXIO;
-   }
+   pri_dai-addr = devm_ioremap_resource(pdev-dev, res);
+   if (IS_ERR(pri_dai-addr))
+   return PTR_ERR(pri_dai-addr);
 
-   if (!request_mem_region(res-start, resource_size(res),
-   samsung-i2s)) {
-   dev_err(pdev-dev, Unable to request SFR region\n);
-   return -EBUSY;
-   }
regs_base = res-start;
 
pri_dai-dma_playback.dma_addr = regs_base + I2STXD;
@@ -1247,7 +1228,6 @@ static int samsung_i2s_probe(struct platform_device *pdev)
pri_dai-dma_capture.ch_name = rx;
pri_dai-dma_playback.dma_size = 4;
pri_dai-dma_capture.dma_size = 4;
-   pri_dai-base = regs_base;
pri_dai-quirks = quirks;
pri_dai-variant_regs = i2s_dai_data-i2s_variant_regs;
 
@@ -1258,8 +1238,7 @@ static int samsung_i2s_probe(struct platform_device *pdev)
sec_dai = i2s_alloc_dai(pdev, true);
if (!sec_dai) {
dev_err(pdev-dev, Unable to alloc I2S_sec\n);
-   ret = -ENOMEM;
-   goto err;
+   return -ENOMEM;
}
 
sec_dai-variant_regs = pri_dai-variant_regs;
@@ -1273,7 +1252,7 @@ static int samsung_i2s_probe(struct platform_device *pdev)
}
 
sec_dai-dma_playback.dma_size = 4;
-   sec_dai-base = regs_base;
+   sec_dai-addr = pri_dai-addr;
sec_dai-quirks = quirks;
sec_dai-idma_playback.dma_addr = idma_addr;
sec_dai-pri_dai = pri_dai;
@@ -1282,8 +1261,7 @@ static int samsung_i2s_probe(struct platform_device *pdev)
 
if (i2s_pdata  i2s_pdata-cfg_gpio  i2s_pdata-cfg_gpio(pdev)) {
dev_err(pdev-dev, Unable to configure gpio\n);
-   ret = -EINVAL;
-   goto err;
+   return -EINVAL;
}
 
devm_snd_soc_register_component(pri_dai-pdev-dev,
@@ -1297,17 +1275,11 @@ static int samsung_i2s_probe(struct platform_device 
*pdev)
return ret;
 
return 0;
-err:
-   if (res

[PATCH V3 06/15] ASoC: samsung: i2s: Add get_other_dai helper function

[Sylwester Nawrocki]

The code to get pointer to the other DAI is repeated multiple
times. Add a helper function and use it instead.

Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
 sound/soc/samsung/i2s.c |   24 +++-
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index f75c19e..cab2a2a 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -130,10 +130,16 @@ static inline bool tx_active(struct i2s_dai *i2s)
return active ? true : false;
 }
 
+/* Return pointer to the other DAI */
+static inline struct i2s_dai *get_other_dai(struct i2s_dai *i2s)
+{
+   return i2s-pri_dai ? : i2s-sec_dai;
+}
+
 /* If the other interface of the controller is transmitting data */
 static inline bool other_tx_active(struct i2s_dai *i2s)
 {
-   struct i2s_dai *other = i2s-pri_dai ? : i2s-sec_dai;
+   struct i2s_dai *other = get_other_dai(i2s);
 
return tx_active(other);
 }
@@ -160,7 +166,7 @@ static inline bool rx_active(struct i2s_dai *i2s)
 /* If the other interface of the controller is receiving data */
 static inline bool other_rx_active(struct i2s_dai *i2s)
 {
-   struct i2s_dai *other = i2s-pri_dai ? : i2s-sec_dai;
+   struct i2s_dai *other = get_other_dai(i2s);
 
return rx_active(other);
 }
@@ -461,7 +467,7 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai,
  int clk_id, unsigned int rfs, int dir)
 {
struct i2s_dai *i2s = to_info(dai);
-   struct i2s_dai *other = i2s-pri_dai ? : i2s-sec_dai;
+   struct i2s_dai *other = get_other_dai(i2s);
u32 mod = readl(i2s-addr + I2SMOD);
const struct samsung_i2s_variant_regs *i2s_regs = i2s-variant_regs;
unsigned int cdcon_mask = 1  i2s_regs-cdclkcon_off;
@@ -733,7 +739,7 @@ static int i2s_startup(struct snd_pcm_substream *substream,
  struct snd_soc_dai *dai)
 {
struct i2s_dai *i2s = to_info(dai);
-   struct i2s_dai *other = i2s-pri_dai ? : i2s-sec_dai;
+   struct i2s_dai *other = get_other_dai(i2s);
unsigned long flags;
 
spin_lock_irqsave(lock, flags);
@@ -760,7 +766,7 @@ static void i2s_shutdown(struct snd_pcm_substream 
*substream,
struct snd_soc_dai *dai)
 {
struct i2s_dai *i2s = to_info(dai);
-   struct i2s_dai *other = i2s-pri_dai ? : i2s-sec_dai;
+   struct i2s_dai *other = get_other_dai(i2s);
unsigned long flags;
const struct samsung_i2s_variant_regs *i2s_regs = i2s-variant_regs;
 
@@ -791,7 +797,7 @@ static void i2s_shutdown(struct snd_pcm_substream 
*substream,
 
 static int config_setup(struct i2s_dai *i2s)
 {
-   struct i2s_dai *other = i2s-pri_dai ? : i2s-sec_dai;
+   struct i2s_dai *other = get_other_dai(i2s);
unsigned rfs, bfs, blc;
u32 psr;
 
@@ -899,7 +905,7 @@ static int i2s_set_clkdiv(struct snd_soc_dai *dai,
int div_id, int div)
 {
struct i2s_dai *i2s = to_info(dai);
-   struct i2s_dai *other = i2s-pri_dai ? : i2s-sec_dai;
+   struct i2s_dai *other = get_other_dai(i2s);
 
switch (div_id) {
case SAMSUNG_I2S_DIV_BCLK:
@@ -968,7 +974,7 @@ static int i2s_resume(struct snd_soc_dai *dai)
 static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
 {
struct i2s_dai *i2s = to_info(dai);
-   struct i2s_dai *other = i2s-pri_dai ? : i2s-sec_dai;
+   struct i2s_dai *other = get_other_dai(i2s);
 
if (is_secondary(i2s)) { /* If this is probe on the secondary DAI */
samsung_asoc_init_dma_data(dai, other-sec_dai-dma_playback,
@@ -1271,7 +1277,7 @@ static int samsung_i2s_remove(struct platform_device 
*pdev)
struct i2s_dai *i2s, *other;
 
i2s = dev_get_drvdata(pdev-dev);
-   other = i2s-pri_dai ? : i2s-sec_dai;
+   other = get_other_dai(i2s);
 
if (other) {
other-pri_dai = NULL;
-- 
1.7.9.5

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[PATCH V3 05/15] ASoC: samsung: i2s: Move clk enable to the platform driver probe()

[Sylwester Nawrocki]

The clk_prepare_enable() call on the iis clock is moved to happen earlier
in the DAI platform device driver's probe() callback, so the I2S registers
can be safely accessed through the clk API, after the clk supplier is
registered in the platform device probe().

After this patch the iis clock is kept enabled since the (primary) I2S
platform device probe() and until the platform device driver remove() call.
This is similar to gating the clock in the snd_soc_dai probe() and remove()
callbacks.
Normally, in addition to that we should mark the device as PM runtime active,
so if runtime PM is enabled it can idle the device by turning off the clock.
Correcting this issue is left for a separate patch series, as we need to
ensure the BUSCLK clock is always enabled when required.

Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
 sound/soc/samsung/i2s.c |   25 +++--
 1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index a854ffc..f75c19e 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -969,7 +969,6 @@ static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
 {
struct i2s_dai *i2s = to_info(dai);
struct i2s_dai *other = i2s-pri_dai ? : i2s-sec_dai;
-   int ret;
 
if (is_secondary(i2s)) { /* If this is probe on the secondary DAI */
samsung_asoc_init_dma_data(dai, other-sec_dai-dma_playback,
@@ -977,12 +976,6 @@ static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
goto probe_exit;
}
 
-   ret = clk_prepare_enable(i2s-clk);
-   if (ret != 0) {
-   dev_err(i2s-pdev-dev, failed to enable clock: %d\n, ret);
-   return ret;
-   }
-
samsung_asoc_init_dma_data(dai, i2s-dma_playback, i2s-dma_capture);
 
if (i2s-quirks  QUIRK_NEED_RSTCLR)
@@ -1014,18 +1007,12 @@ probe_exit:
 static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
 {
struct i2s_dai *i2s = snd_soc_dai_get_drvdata(dai);
-   struct i2s_dai *other = i2s-pri_dai ? : i2s-sec_dai;
-
-   if (!other || !other-clk) {
 
+   if (!is_secondary(i2s)) {
if (i2s-quirks  QUIRK_NEED_RSTCLR)
writel(0, i2s-addr + I2SCON);
-
-   clk_disable_unprepare(i2s-clk);
}
 
-   i2s-clk = NULL;
-
return 0;
 }
 
@@ -1139,6 +1126,7 @@ static int samsung_i2s_probe(struct platform_device *pdev)
u32 regs_base, quirks = 0, idma_addr = 0;
struct device_node *np = pdev-dev.of_node;
const struct samsung_i2s_dai_data *i2s_dai_data;
+   int ret;
 
/* Call during Seconday interface registration */
i2s_dai_data = samsung_i2s_get_driver_data(pdev);
@@ -1216,6 +1204,12 @@ static int samsung_i2s_probe(struct platform_device 
*pdev)
dev_err(pdev-dev, Failed to get iis clock\n);
return PTR_ERR(pri_dai-clk);
}
+
+   ret = clk_prepare_enable(pri_dai-clk);
+   if (ret != 0) {
+   dev_err(pdev-dev, failed to enable clock: %d\n, ret);
+   return ret;
+   }
pri_dai-dma_playback.dma_addr = regs_base + I2STXD;
pri_dai-dma_capture.dma_addr = regs_base + I2SRXD;
pri_dai-dma_playback.ch_name = tx;
@@ -1286,6 +1280,9 @@ static int samsung_i2s_remove(struct platform_device 
*pdev)
pm_runtime_disable(pdev-dev);
}
 
+   if (!is_secondary(i2s))
+   clk_disable_unprepare(i2s-clk);
+
i2s-pri_dai = NULL;
i2s-sec_dai = NULL;
 
-- 
1.7.9.5

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[PATCH V3 04/15] ASoC: samsung: i2s: Move clk_get() to platform driver probe()

[Sylwester Nawrocki]

Acquire the I2S interface clock in driver probe() callback
as it's a per-device not a per-DAI clock. While at it switch
to the resource managed clk_get().

Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
 sound/soc/samsung/i2s.c |   19 +++
 1 file changed, 7 insertions(+), 12 deletions(-)

diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 366b720..a854ffc 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -971,18 +971,12 @@ static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
struct i2s_dai *other = i2s-pri_dai ? : i2s-sec_dai;
int ret;
 
-   if (other  other-clk) { /* If this is probe on secondary */
+   if (is_secondary(i2s)) { /* If this is probe on the secondary DAI */
samsung_asoc_init_dma_data(dai, other-sec_dai-dma_playback,
   NULL);
goto probe_exit;
}
 
-   i2s-clk = clk_get(i2s-pdev-dev, iis);
-   if (IS_ERR(i2s-clk)) {
-   dev_err(i2s-pdev-dev, failed to get i2s_clock\n);
-   return PTR_ERR(i2s-clk);
-   }
-
ret = clk_prepare_enable(i2s-clk);
if (ret != 0) {
dev_err(i2s-pdev-dev, failed to enable clock: %d\n, ret);
@@ -991,10 +985,6 @@ static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
 
samsung_asoc_init_dma_data(dai, i2s-dma_playback, i2s-dma_capture);
 
-   if (other) {
-   other-clk = i2s-clk;
-   }
-
if (i2s-quirks  QUIRK_NEED_RSTCLR)
writel(CON_RSTCLR, i2s-addr + I2SCON);
 
@@ -1032,7 +1022,6 @@ static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
writel(0, i2s-addr + I2SCON);
 
clk_disable_unprepare(i2s-clk);
-   clk_put(i2s-clk);
}
 
i2s-clk = NULL;
@@ -1222,6 +1211,11 @@ static int samsung_i2s_probe(struct platform_device 
*pdev)
 
regs_base = res-start;
 
+   pri_dai-clk = devm_clk_get(pdev-dev, iis);
+   if (IS_ERR(pri_dai-clk)) {
+   dev_err(pdev-dev, Failed to get iis clock\n);
+   return PTR_ERR(pri_dai-clk);
+   }
pri_dai-dma_playback.dma_addr = regs_base + I2STXD;
pri_dai-dma_capture.dma_addr = regs_base + I2SRXD;
pri_dai-dma_playback.ch_name = tx;
@@ -1253,6 +1247,7 @@ static int samsung_i2s_probe(struct platform_device *pdev)
 
sec_dai-dma_playback.dma_size = 4;
sec_dai-addr = pri_dai-addr;
+   sec_dai-clk = pri_dai-clk;
sec_dai-quirks = quirks;
sec_dai-idma_playback.dma_addr = idma_addr;
sec_dai-pri_dai = pri_dai;
-- 
1.7.9.5

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