On Freitag, 18. Mai 2018 09:14:36 CEST Maxime Ripard wrote:
> On Mon, May 14, 2018 at 10:36:08PM +0200, Paul Kocialkowski wrote:
> > > > + backlight: backlight {
> > > > + compatible = "pwm-backlight";
> > > > + pwms = <&pwm 0 5 PWM_POLARITY_INVERTED>;
> > > >
Hi,
Dne petek, 18. maj 2018 ob 17:26:51 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote:
> > > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
> > > lookup pll-2 either.
> >
> > It is highly unlikely this will be higher than
On Fri, May 18, 2018 at 01:55:31PM +0200, Marek Vasut wrote:
> On 05/18/2018 01:51 PM, Maxime Ripard wrote:
> > On Mon, May 14, 2018 at 11:13:54AM +0200, Marek Vasut wrote:
> >>> And I don't really know what the constraints are on the SPL side, but
> >>> it's really tight on our end. So maybe I'm e
On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote:
> > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
> > lookup pll-2 either.
>
> It is highly unlikely this will be higher than 2, at least for this HDMI PHY,
> since it has only 1 bit reserved for parent select
Hi,
Dne petek, 18. maj 2018 ob 17:09:40 CEST je Sergey Suloev napisal(a):
> Hi, guys,
>
> On 05/18/2018 05:46 PM, Jernej Škrabec wrote:
> > Hi,
> >
> > Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
> >> On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
> >>> Fro
Hi,
Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
> > From: Jernej Skrabec
> >
> > Some SoCs with DW HDMI have multiple possible clock parents, like A64
> > and R40.
> >
> > Expand HDMI PHY clock driver to sup
On Fri, May 18, 2018 at 03:15:26PM +0530, Jagan Teki wrote:
> Allwinner A64 has two clock parents PLL_VIDEO0 and PLL_VIDEO1.
>
> Include these macros on dt-bindings so-that the same can be
> used while defining CCU clock phadles.
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v2:
> - new patc
Hi,
On 18/05/18 11:41, Peter Robinson wrote:
> On Wed, May 16, 2018 at 9:00 AM, Andre Przywara
> wrote:
>> This is an updated version of the series which brings the exact mainline
>> Linux device tree files for various Allwinner boards into U-Boot.
>> Apart from using the usually more correct re
On 05/18/2018 01:51 PM, Maxime Ripard wrote:
> On Mon, May 14, 2018 at 11:13:54AM +0200, Marek Vasut wrote:
>>> And I don't really know what the constraints are on the SPL side, but
>>> it's really tight on our end. So maybe I'm exagerating, but you're
>>> definitely understating it too.
>>
>> You
On Mon, May 14, 2018 at 11:13:54AM +0200, Marek Vasut wrote:
> > And I don't really know what the constraints are on the SPL side, but
> > it's really tight on our end. So maybe I'm exagerating, but you're
> > definitely understating it too.
>
> You can fit into 16k , can you not ?
We have 13k.
Hi again list,
After asking to the freerdp list, this is the answer that they send me:
*Hi Miguel,*
*no, currently there is no (direct) support for libva, but it may be*
*indirectly used with the FFMPEG AVC444 decoder backend.*
*Currently the biggest obstacle there is the custom YUV to RGB filt
Good morning list,
This is my first post to the list, so I don't know very well the rules that
you have about posting (if there is anyone).
I've contacted to Paul to know which was the best way of sending you my
purposal/suggestion, and he told me that sending to this list probably
would be the
On Wed, May 16, 2018 at 9:00 AM, Andre Przywara wrote:
> This is an updated version of the series which brings the exact mainline
> Linux device tree files for various Allwinner boards into U-Boot.
> Apart from using the usually more correct reference DT files, this offers
> the big benefit of bei
On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
> From: Jernej Skrabec
>
> Some SoCs with DW HDMI have multiple possible clock parents, like A64
> and R40.
>
> Expand HDMI PHY clock driver to support second clock parent.
>
> Signed-off-by: Jernej Skrabec
> Signed-off-by: Jagan Teki
On Fri, May 18, 2018 at 03:15:10PM +0530, Jagan Teki wrote:
> Allwinner A64 has display engine pipeline like other Allwinner SOC's
> A83T/H3/H5.
>
> A64 behaviour similar to Allwinner A83T where
> Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI
> Mixer1 => TCON1 => HDMI
> as per Display System Block Diagram
Enable HDMI output on sopine board.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
.../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
b/arch/arm64/boo
Enable HDMI output on a64-olinuxino board.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
.../boot/dts/allwinner/sun50i-a64-olinuxino.dts| 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
b/arch/arm64/boo
Enable HDMI output on Bananpi-m64 board.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/bo
Allwinner SoC like SUN8I and SUN50I are now using DesignWare HDMI
so enable them as default.
Signed-off-by: Jagan Teki
---
Changes for v2:
- Enable for SUN8I
drivers/gpu/drm/sun4i/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/K
From: Jernej Skrabec
PHY is the same as in H3, except it can select between two clock parent.
Signed-off-by: Jernej Skrabec
Signed-off-by: Jagan Teki
---
Changes for v2:
- new patch
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/driver
From: Jernej Skrabec
Some SoCs with DW HDMI have multiple possible clock parents, like A64
and R40.
Expand HDMI PHY clock driver to support second clock parent.
Signed-off-by: Jernej Skrabec
Signed-off-by: Jagan Teki
---
Changes for v2:
- new patch
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
HDMI PHY on Allwinner A64 has similar like H3/H5 but with
two clock parents, so add separate compatible for A64.
Signed-off-by: Jagan Teki
---
Changes for v2:
- Add separate compatible for A64
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
1 file changed, 1 insertion(+)
d
HDMI on Allwinner A64 has similar like H3/H5/A83T.
Add compatible a64 and update A83T compatible as fallback.
Signed-off-by: Jagan Teki
---
Changes for v2:
- Add fallback compatible
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Enable DRM Support for Allwinner Display Engine, built as a module.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index d25121b087bb..d2db76f296cf
From: Jernej Skrabec
When TCON set up TCON TOP, it needs to know mixer index. Here we do that
by setting engine ID to number provided in mixer index quirk.
Signed-off-by: Jernej Skrabec
Signed-off-by: Jagan Teki
---
Changes for v2:
- New patch
drivers/gpu/drm/sun4i/sun8i_mixer.c | 4 ++--
dr
The DE2 on the A64 is mainly composed of the mixers and tcons,
plus various encoders.
This patch add second mixer and tcon which eventually useful
for testing HDMI. the other part of DE2 will add in future.
Signed-off-by: Jagan Teki
---
Changes for v2:
- Change compatibles and other based on pre
Display Engine(DE2) in Allwinner A64 has two mixers and tcons.
The routing for mixer0 is through tcon0 and connected to
LVDS/RGB/MIPI-DSI controller.
The routing for mixer1 is through tcon1 and connected to HDMI.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/gpu/drm/sun4i/sun4i
Allwinner SoC like SUN8I and SUN50I are now using DE2 Mixer
so enable them as default.
Signed-off-by: Jagan Teki
---
Changes for v2:
- Enable for SUN8I
drivers/gpu/drm/sun4i/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/d
According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.
Because of that, set minimal rate to both A64 video PLLs to 192 MHz.
Signed-off-by: Jagan Teki
---
Changes for v2:
- New patch
drivers/clk/sunxi-ng/cc
Allwinner A64 has DE2 pipeline with tcon0 and tcon1 block
which is similar Allwinner A83T.
This patch adds dt-binding documentation for A64 DE2 tcon1 blocks.
Mixer1 has different configuration for A64 so use separate compatible
but tcon1 has similar behaviour with A83T so add fallback compatible.
Mixers in Allwinner have similar capabilities as others SoCs with DE2.
Mixer1 has 1 VI and 1 UI planes and supports HW scaling on all
planes.
Signed-off-by: Jagan Teki
---
Changes for v2:
- New patch
drivers/gpu/drm/sun4i/sun8i_mixer.c | 13 +
1 file changed, 13 insertions(+)
diff
Allwinner SoC like SUN8I and SUN50I has DE2 CCU so enable them
as default.
Signed-off-by: Jagan Teki
---
Changes for v2:
- Enable for MACH_SUN8I
drivers/clk/sunxi-ng/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 8
DE2 CCU in Allwinner A64 has same like H5, so use the
similar dts details for A64 with fallback compatible.
Signed-off-by: Jagan Teki
---
Changes for v2:
- Add h5 compatible first since A64 came first.
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++
1 file changed, 15 insert
Allwinner A64 has DE2 CCU is similar to H3/H5 SoC.
So add compatible for A64 which is fallback compatible
for H5, so update fallback binding.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Changes for v2:
- Add fallback compatible
Documentation/devicetree/bindings/clock/sun8i-de2.txt
Allwinner A64 has display engine pipeline like other Allwinner SOC's A83T/H3/H5.
A64 behaviour similar to Allwinner A83T where
Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI
Mixer1 => TCON1 => HDMI
as per Display System Block DiagramAllwinner_A64_User_Manual_V1.1.pdf
This is second patch-set followed with
On Thu, May 17, 2018 at 10:48:58PM +0800, Hao Zhang wrote:
> 2018-05-15 19:17 GMT+08:00 Maxime Ripard :
> > Hi,
> >
> > On Mon, May 14, 2018 at 10:45:44PM +0800, Hao Zhang wrote:
> >> 2018-02-26 17:00 GMT+08:00 Maxime Ripard :
> >> > Thanks for respinning this serie. It looks mostly good, but you s
On Wed, May 16, 2018 at 02:38:08PM +0300, Stefan Mavrodiev wrote:
> With the new rev.E of A20-SOM-EVB, there is option for 16GB eMMC.
> Currently used card is KLMAG2GEND, wired to MMC2 slot.
>
> Signed-off-by: Stefan Mavrodiev
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin (formerly Free E
On Thu, May 17, 2018 at 10:34:06AM +0300, Stefan Mavrodiev wrote:
> On 05/17/2018 10:25 AM, Stefan Wahren wrote:
> > Hi Stefan,
> >
> > > Stefan Mavrodiev hat am 16. Mai 2018 um 13:38
> > > geschrieben:
> > >
> > >
> > > With the new rev.E of A20-SOM-EVB, there is option for 16GB eMMC.
> > > C
Hi Andre,
On Wed, May 16, 2018 at 09:00:50AM +0100, Andre Przywara wrote:
> The Pine64-LTS board is a new board version of the Pine64, though
> actually it's a non-SoM version of the SoPine and its baseboard.
> In contrast to the original Pine64 it features LPDDR3 DRAM, an eMMC
> socket and a SPI
On Mon, May 14, 2018 at 10:36:08PM +0200, Paul Kocialkowski wrote:
> > > + backlight: backlight {
> > > + compatible = "pwm-backlight";
> > > + pwms = <&pwm 0 5 PWM_POLARITY_INVERTED>;
> > > + brightness-levels = < 0 1 1 1 1 2 2 2
> > > +
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